[llvm] r209746 - InstCombine: Improvement to check if signed addition overflows.

Rafael EspĂ­ndola rafael.espindola at gmail.com
Mon Jun 2 14:56:04 PDT 2014


> I am afraid if this is correct. Its adding 'nsw' to all additions, even
> where it is sure not to add 'nsw'.
>
> ex:-
>
> int foo(short x){
> short v =  (x & ~4) ;
> int u = (int)v + 8;
> return u;
> }
>
> In this example we cannot determine if the addition will overflow of not,
> because, one of the operand (x & ~4) has 0 bit at position 2 from LSB (LSB
> position considered 0) while other operand 8 has 1 bit at position 3, which
> is at higher significant position than position of 0. In this case its
> giving IR as 'add nsw' which it should not.

Sorry, I got confused, but the code is actually correct.

In the above example we know that (int)v will be of the form 00... or
11.... since it is an sext. Now, it is being added to 8, so lets
consider both cases

00...  + 8 -> A carry can change the second 0, but not the sign bit.

11... + 8 -> A negative and a positive number are being added, no overflow.

Cheers,
Rafael



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