[llvm] r209877 - Test cases named with dates is a legacy rule not used now. Rename several test cases.
Hao Liu
Hao.Liu at arm.com
Thu May 29 22:58:19 PDT 2014
Author: haoliu
Date: Fri May 30 00:58:19 2014
New Revision: 209877
URL: http://llvm.org/viewvc/llvm-project?rev=209877&view=rev
Log:
Test cases named with dates is a legacy rule not used now. Rename several test cases.
Added:
llvm/trunk/test/CodeGen/AArch64/arm64-AnInfiniteLoopInDAGCombine.ll
- copied unchanged from r209869, llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll
llvm/trunk/test/CodeGen/AArch64/arm64-EXT-undef-mask.ll
- copied unchanged from r209869, llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll
llvm/trunk/test/CodeGen/AArch64/arm64-shrink-v1i64.ll
- copied unchanged from r209869, llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
llvm/trunk/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll
- copied unchanged from r209869, llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll
Removed:
llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll
llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll
llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll
Removed: llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll?rev=209876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/2014-05-29-shrink-v1i64.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -march=arm64 < %s
-
-; The DAGCombiner tries to do following shrink:
-; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
-; But currently it can't handle vector type and will trigger an assertion failure
-; when it tries to generate an add mixed using vector type and scaler type.
-; This test checks that such assertion failur should not happen.
-define <1 x i64> @dotest(<1 x i64> %in0) {
-entry:
- %0 = add <1 x i64> %in0, %in0
- %vshl_n = shl <1 x i64> %0, <i64 32>
- %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
- ret <1 x i64> %vsra_n
-}
Removed: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll?rev=209876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-16-AnInfiniteLoopInDAGCombine.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc < %s -march=arm64
-
-; This test case tests an infinite loop bug in DAG combiner.
-; It just tries to do the following replacing endlessly:
-; (1) Replacing.3 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
-; With: 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
-;
-; (2) Replacing.2 0x2c4d128: v4i32 = sign_extend 0x2c4cd08 [ORD=4]
-; With: 0x2c509f0: v4i32 = any_extend 0x2c4cd08 [ORD=4]
-; As we think the (2) optimization from SIGN_EXTEND to ANY_EXTEND is
-; an optimization to replace unused bits with undefined bits, we remove
-; the (1) optimization (It doesn't make sense to replace undefined bits
-; with signed bits).
-
-define <4 x i32> @infiniteLoop(<4 x i32> %in0, <4 x i16> %in1) {
-entry:
- %cmp.i = icmp sge <4 x i16> %in1, <i16 32767, i16 32767, i16 -1, i16 -32768>
- %sext.i = sext <4 x i1> %cmp.i to <4 x i32>
- %mul.i = mul <4 x i32> %in0, %sext.i
- %sext = shl <4 x i32> %mul.i, <i32 16, i32 16, i32 16, i32 16>
- %vmovl.i.i = ashr <4 x i32> %sext, <i32 16, i32 16, i32 16, i32 16>
- ret <4 x i32> %vmovl.i.i
-}
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll?rev=209876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-28-sqshl-uqshl-i64Contant.ll (removed)
@@ -1,19 +0,0 @@
-; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
-
-; Check if sqshl/uqshl with constant shift amout can be selected.
-define i64 @test_vqshld_s64_i(i64 %a) {
-; CHECK-LABEL: test_vqshld_s64_i:
-; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
- %1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
- ret i64 %1
-}
-
-define i64 @test_vqshld_u64_i(i64 %a) {
-; CHECK-LABEL: test_vqshld_u64_i:
-; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
- %1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)
- ret i64 %1
-}
-
-declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)
-declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)
Removed: llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll?rev=209876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-2014-04-29-EXT-undef-mask.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc < %s -O0 -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
-
-; The following 2 test cases test shufflevector with beginning UNDEF mask.
-define <8 x i16> @test_vext_undef_traverse(<8 x i16> %in) {
-;CHECK-LABEL: test_vext_undef_traverse:
-;CHECK: {{ext.16b.*v0, #4}}
- %vext = shufflevector <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0>, <8 x i16> %in, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9>
- ret <8 x i16> %vext
-}
-
-define <8 x i16> @test_vext_undef_traverse2(<8 x i16> %in) {
-;CHECK-LABEL: test_vext_undef_traverse2:
-;CHECK: {{ext.16b.*v0, #6}}
- %vext = shufflevector <8 x i16> %in, <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2>
- ret <8 x i16> %vext
-}
-
-define <8 x i8> @test_vext_undef_traverse3(<8 x i8> %in) {
-;CHECK-LABEL: test_vext_undef_traverse3:
-;CHECK: {{ext.8b.*v0, #6}}
- %vext = shufflevector <8 x i8> %in, <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
- ret <8 x i8> %vext
-}
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