[llvm] r209577 - AArch64/ARM64: move ARM64 into AArch64's place
Tim Northover
tnorthover at apple.com
Sat May 24 05:50:31 PDT 2014
Removed: llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll (removed)
@@ -1,532 +0,0 @@
-; RUN: opt -codegenprepare -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
-; RUN: llc < %s -march=arm64 | FileCheck %s
-%struct.X = type { i8, i8, [2 x i8] }
-%struct.Y = type { i32, i8 }
-%struct.Z = type { i8, i8, [2 x i8], i16 }
-%struct.A = type { i64, i8 }
-
-define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp {
-; CHECK-LABEL: foo:
-; CHECK: ubfx
-; CHECK-NOT: and
-; CHECK: ret
-
- %tmp = bitcast %struct.X* %x to i32*
- %tmp1 = load i32* %tmp, align 4
- %b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1
- %bf.clear = lshr i32 %tmp1, 3
- %bf.clear.lobit = and i32 %bf.clear, 1
- %frombool = trunc i32 %bf.clear.lobit to i8
- store i8 %frombool, i8* %b, align 1
- ret void
-}
-
-define i32 @baz(i64 %cav1.coerce) nounwind {
-; CHECK-LABEL: baz:
-; CHECK: sbfx w0, w0, #0, #4
- %tmp = trunc i64 %cav1.coerce to i32
- %tmp1 = shl i32 %tmp, 28
- %bf.val.sext = ashr exact i32 %tmp1, 28
- ret i32 %bf.val.sext
-}
-
-define i32 @bar(i64 %cav1.coerce) nounwind {
-; CHECK-LABEL: bar:
-; CHECK: sbfx w0, w0, #4, #6
- %tmp = trunc i64 %cav1.coerce to i32
- %cav1.sroa.0.1.insert = shl i32 %tmp, 22
- %tmp1 = ashr i32 %cav1.sroa.0.1.insert, 26
- ret i32 %tmp1
-}
-
-define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind optsize ssp {
-; CHECK-LABEL: fct1:
-; CHECK: ubfx
-; CHECK-NOT: and
-; CHECK: ret
-
- %tmp = bitcast %struct.Z* %x to i64*
- %tmp1 = load i64* %tmp, align 4
- %b = getelementptr inbounds %struct.A* %y, i64 0, i32 0
- %bf.clear = lshr i64 %tmp1, 3
- %bf.clear.lobit = and i64 %bf.clear, 1
- store i64 %bf.clear.lobit, i64* %b, align 8
- ret void
-}
-
-define i64 @fct2(i64 %cav1.coerce) nounwind {
-; CHECK-LABEL: fct2:
-; CHECK: sbfx x0, x0, #0, #36
- %tmp = shl i64 %cav1.coerce, 28
- %bf.val.sext = ashr exact i64 %tmp, 28
- ret i64 %bf.val.sext
-}
-
-define i64 @fct3(i64 %cav1.coerce) nounwind {
-; CHECK-LABEL: fct3:
-; CHECK: sbfx x0, x0, #4, #38
- %cav1.sroa.0.1.insert = shl i64 %cav1.coerce, 22
- %tmp1 = ashr i64 %cav1.sroa.0.1.insert, 26
- ret i64 %tmp1
-}
-
-define void @fct4(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct4:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24
-; CHECK-NEXT: str [[REG1]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -16777216
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 16777215
- %or = or i64 %and, %and1
- store i64 %or, i64* %y, align 8
- ret void
-}
-
-define void @fct5(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct5:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
-; CHECK-NEXT: str [[REG1]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -8
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 7
- %or = or i32 %and, %and1
- store i32 %or, i32* %y, align 8
- ret void
-}
-
-; Check if we can still catch bfm instruction when we drop some low bits
-define void @fct6(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct6:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -8
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 7
- %or = or i32 %and, %and1
- %shr1 = lshr i32 %or, 2
- store i32 %shr1, i32* %y, align 8
- ret void
-}
-
-
-; Check if we can still catch bfm instruction when we drop some high bits
-define void @fct7(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct7:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
-; lsl is an alias of ubfm
-; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -8
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 7
- %or = or i32 %and, %and1
- %shl = shl i32 %or, 2
- store i32 %shl, i32* %y, align 8
- ret void
-}
-
-
-; Check if we can still catch bfm instruction when we drop some low bits
-; (i64 version)
-define void @fct8(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct8:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -8
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 7
- %or = or i64 %and, %and1
- %shr1 = lshr i64 %or, 2
- store i64 %shr1, i64* %y, align 8
- ret void
-}
-
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; (i64 version)
-define void @fct9(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct9:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -8
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 7
- %or = or i64 %and, %and1
- %shl = shl i64 %or, 2
- store i64 %shl, i64* %y, align 8
- ret void
-}
-
-; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
-; (i32 version)
-define void @fct10(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct10:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #0, #3
-; lsl is an alias of ubfm
-; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -8
- %and1 = and i32 %x, 7
- %or = or i32 %and, %and1
- %shl = shl i32 %or, 2
- store i32 %shl, i32* %y, align 8
- ret void
-}
-
-; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
-; (i64 version)
-define void @fct11(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct11:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #0, #3
-; lsl is an alias of ubfm
-; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -8
- %and1 = and i64 %x, 7
- %or = or i64 %and, %and1
- %shl = shl i64 %or, 2
- store i64 %shl, i64* %y, align 8
- ret void
-}
-
-define zeroext i1 @fct12bis(i32 %tmp2) unnamed_addr nounwind ssp align 2 {
-; CHECK-LABEL: fct12bis:
-; CHECK-NOT: and
-; CHECK: ubfx w0, w0, #11, #1
- %and.i.i = and i32 %tmp2, 2048
- %tobool.i.i = icmp ne i32 %and.i.i, 0
- ret i1 %tobool.i.i
-}
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits
-define void @fct12(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct12:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -8
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 7
- %or = or i32 %and, %and1
- %shl = shl i32 %or, 2
- %shr2 = lshr i32 %shl, 4
- store i32 %shr2, i32* %y, align 8
- ret void
-}
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits
-; (i64 version)
-define void @fct13(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct13:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60
-; CHECK-NEXT: str [[REG2]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -8
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 7
- %or = or i64 %and, %and1
- %shl = shl i64 %or, 2
- %shr2 = lshr i64 %shl, 4
- store i64 %shr2, i64* %y, align 8
- ret void
-}
-
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits
-define void @fct14(i32* nocapture %y, i32 %x, i32 %x1) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct14:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], w1, #16, #8
-; lsr is an alias of ubfm
-; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #4
-; CHECK-NEXT: bfxil [[REG2]], w2, #5, #3
-; lsl is an alias of ubfm
-; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
-; CHECK-NEXT: str [[REG3]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, -256
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 255
- %or = or i32 %and, %and1
- %shl = lshr i32 %or, 4
- %and2 = and i32 %shl, -8
- %shr1 = lshr i32 %x1, 5
- %and3 = and i32 %shr1, 7
- %or1 = or i32 %and2, %and3
- %shl1 = shl i32 %or1, 2
- store i32 %shl1, i32* %y, align 8
- ret void
-}
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits
-; (i64 version)
-define void @fct15(i64* nocapture %y, i64 %x, i64 %x1) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct15:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; CHECK-NEXT: bfxil [[REG1]], x1, #16, #8
-; lsr is an alias of ubfm
-; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #4
-; CHECK-NEXT: bfxil [[REG2]], x2, #5, #3
-; lsl is an alias of ubfm
-; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2
-; CHECK-NEXT: str [[REG3]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, -256
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 255
- %or = or i64 %and, %and1
- %shl = lshr i64 %or, 4
- %and2 = and i64 %shl, -8
- %shr1 = lshr i64 %x1, 5
- %and3 = and i64 %shr1, 7
- %or1 = or i64 %and2, %and3
- %shl1 = shl i64 %or1, 2
- store i64 %shl1, i64* %y, align 8
- ret void
-}
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits and a masking operation has to be kept
-define void @fct16(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct16:
-; CHECK: ldr [[REG1:w[0-9]+]],
-; Create the constant
-; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16
-; CHECK: movk [[REGCST]], #0x8160
-; Do the masking
-; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
-; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28
-; CHECK-NEXT: str [[REG3]],
-; CHECK-NEXT: ret
- %0 = load i32* %y, align 8
- %and = and i32 %0, 1737056
- %shr = lshr i32 %x, 16
- %and1 = and i32 %shr, 7
- %or = or i32 %and, %and1
- %shl = shl i32 %or, 2
- %shr2 = lshr i32 %shl, 4
- store i32 %shr2, i32* %y, align 8
- ret void
-}
-
-
-; Check if we can still catch bfm instruction when we drop some high bits
-; and some low bits and a masking operation has to be kept
-; (i64 version)
-define void @fct17(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
-entry:
-; CHECK-LABEL: fct17:
-; CHECK: ldr [[REG1:x[0-9]+]],
-; Create the constant
-; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16
-; CHECK: movk w[[REGCST]], #0x8160
-; Do the masking
-; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
-; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3
-; lsr is an alias of ubfm
-; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60
-; CHECK-NEXT: str [[REG3]],
-; CHECK-NEXT: ret
- %0 = load i64* %y, align 8
- %and = and i64 %0, 1737056
- %shr = lshr i64 %x, 16
- %and1 = and i64 %shr, 7
- %or = or i64 %and, %and1
- %shl = shl i64 %or, 2
- %shr2 = lshr i64 %shl, 4
- store i64 %shr2, i64* %y, align 8
- ret void
-}
-
-define i64 @fct18(i32 %xor72) nounwind ssp {
-; CHECK-LABEL: fct18:
-; CHECK: ubfx x0, x0, #9, #8
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %result = and i64 %conv82, 255
- ret i64 %result
-}
-
-; Using the access to the global array to keep the instruction and control flow.
- at first_ones = external global [65536 x i8]
-
-; Function Attrs: nounwind readonly ssp
-define i32 @fct19(i64 %arg1) nounwind readonly ssp {
-; CHECK-LABEL: fct19:
-entry:
- %x.sroa.1.0.extract.shift = lshr i64 %arg1, 16
- %x.sroa.1.0.extract.trunc = trunc i64 %x.sroa.1.0.extract.shift to i16
- %x.sroa.3.0.extract.shift = lshr i64 %arg1, 32
- %x.sroa.5.0.extract.shift = lshr i64 %arg1, 48
- %tobool = icmp eq i64 %x.sroa.5.0.extract.shift, 0
- br i1 %tobool, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- %arrayidx3 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift
- %0 = load i8* %arrayidx3, align 1
- %conv = zext i8 %0 to i32
- br label %return
-
-; OPT-LABEL: if.end
-if.end: ; preds = %entry
-; OPT: lshr
-; CHECK: ubfx [[REG1:x[0-9]+]], [[REG2:x[0-9]+]], #32, #16
- %x.sroa.3.0.extract.trunc = trunc i64 %x.sroa.3.0.extract.shift to i16
- %tobool6 = icmp eq i16 %x.sroa.3.0.extract.trunc, 0
-; CHECK: cbz
- br i1 %tobool6, label %if.end13, label %if.then7
-
-; OPT-LABEL: if.then7
-if.then7: ; preds = %if.end
-; OPT: lshr
-; "and" should be combined to "ubfm" while "ubfm" should be removed by cse.
-; So neither of them should be in the assemble code.
-; CHECK-NOT: and
-; CHECK-NOT: ubfm
- %idxprom10 = and i64 %x.sroa.3.0.extract.shift, 65535
- %arrayidx11 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom10
- %1 = load i8* %arrayidx11, align 1
- %conv12 = zext i8 %1 to i32
- %add = add nsw i32 %conv12, 16
- br label %return
-
-; OPT-LABEL: if.end13
-if.end13: ; preds = %if.end
-; OPT: lshr
-; OPT: trunc
-; CHECK: ubfx [[REG3:x[0-9]+]], [[REG4:x[0-9]+]], #16, #16
- %tobool16 = icmp eq i16 %x.sroa.1.0.extract.trunc, 0
-; CHECK: cbz
- br i1 %tobool16, label %return, label %if.then17
-
-; OPT-LABEL: if.then17
-if.then17: ; preds = %if.end13
-; OPT: lshr
-; "and" should be combined to "ubfm" while "ubfm" should be removed by cse.
-; So neither of them should be in the assemble code.
-; CHECK-NOT: and
-; CHECK-NOT: ubfm
- %idxprom20 = and i64 %x.sroa.1.0.extract.shift, 65535
- %arrayidx21 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom20
- %2 = load i8* %arrayidx21, align 1
- %conv22 = zext i8 %2 to i32
- %add23 = add nsw i32 %conv22, 32
- br label %return
-
-return: ; preds = %if.end13, %if.then17, %if.then7, %if.then
-; CHECK: ret
- %retval.0 = phi i32 [ %conv, %if.then ], [ %add, %if.then7 ], [ %add23, %if.then17 ], [ 64, %if.end13 ]
- ret i32 %retval.0
-}
-
-; Make sure we do not assert if the immediate in and is bigger than i64.
-; PR19503.
-; OPT-LABEL: @fct20
-; OPT: lshr
-; OPT-NOT: lshr
-; OPT: ret
-; CHECK-LABEL: fct20:
-; CHECK: ret
-define i80 @fct20(i128 %a, i128 %b) {
-entry:
- %shr = lshr i128 %a, 18
- %conv = trunc i128 %shr to i80
- %tobool = icmp eq i128 %b, 0
- br i1 %tobool, label %then, label %end
-then:
- %and = and i128 %shr, 483673642326615442599424
- %conv2 = trunc i128 %and to i80
- br label %end
-end:
- %conv3 = phi i80 [%conv, %entry], [%conv2, %then]
- ret i80 %conv3
-}
-
-; Check if we can still catch UBFX when "AND" is used by SHL.
-; CHECK-LABEL: fct21:
-; CHECK: ubfx
- at arr = external global [8 x [64 x i64]]
-define i64 @fct21(i64 %x) {
-entry:
- %shr = lshr i64 %x, 4
- %and = and i64 %shr, 15
- %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and
- %0 = load i64* %arrayidx, align 8
- ret i64 %0
-}
-
-define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
-; CHECK-LABEL: test_ignored_rightbits:
-
- %positioned_field = shl i32 %in, 3
- %positioned_masked_field = and i32 %positioned_field, 120
- %masked_dst = and i32 %dst, 7
- %insertion = or i32 %masked_dst, %positioned_masked_field
-; CHECK: {{bfm|bfi|bfxil}}
-
- %shl16 = shl i32 %insertion, 8
- %or18 = or i32 %shl16, %insertion
- %conv19 = trunc i32 %or18 to i16
-; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #8, #7
-
- ret i16 %conv19
-}
Removed: llvm/trunk/test/CodeGen/ARM64/blockaddress.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/blockaddress.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/blockaddress.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/blockaddress.ll (removed)
@@ -1,30 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
-; RUN: llc < %s -mtriple=arm64-linux-gnu -code-model=large| FileCheck %s --check-prefix=CHECK-LARGE
-
-; rdar://9188695
-
-define i64 @t() nounwind ssp {
-entry:
-; CHECK-LABEL: t:
-; CHECK: adrp [[REG:x[0-9]+]], Ltmp1 at PAGE
-; CHECK: add {{x[0-9]+}}, [[REG]], Ltmp1 at PAGEOFF
-
-; CHECK-LINUX-LABEL: t:
-; CHECK-LINUX: adrp [[REG:x[0-9]+]], .Ltmp1
-; CHECK-LINUX: add {{x[0-9]+}}, [[REG]], :lo12:.Ltmp1
-
-; CHECK-LARGE-LABEL: t:
-; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]]
-; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]]
-
- %recover = alloca i64, align 8
- store volatile i64 ptrtoint (i8* blockaddress(@t, %mylabel) to i64), i64* %recover, align 8
- br label %mylabel
-
-mylabel:
- %tmp = load volatile i64* %recover, align 8
- ret i64 %tmp
-}
Removed: llvm/trunk/test/CodeGen/ARM64/build-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/build-vector.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/build-vector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/build-vector.ll (removed)
@@ -1,35 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-; Check that building up a vector w/ only one non-zero lane initializes
-; intelligently.
-define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {
-; CHECK-LABEL: one_lane:
-; CHECK: dup.16b v[[REG:[0-9]+]], wzr
-; CHECK-NEXT: ins.b v[[REG]][0], w1
-; v and q are aliases, and str is preferred against st.16b when possible
-; rdar://11246289
-; CHECK: str q[[REG]], [x0]
-; CHECK: ret
- %conv = trunc i32 %skip0 to i8
- %vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0
- %tmp = bitcast i32* %out_int to <4 x i32>*
- %tmp1 = bitcast <16 x i8> %vset_lane to <4 x i32>
- store <4 x i32> %tmp1, <4 x i32>* %tmp, align 16
- ret void
-}
-
-; Check that building a vector from floats doesn't insert an unnecessary
-; copy for lane zero.
-define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
-; CHECK-LABEL: foo:
-; CHECK-NOT: ins.s v0[0], v0[0]
-; CHECK: ins.s v0[1], v1[0]
-; CHECK: ins.s v0[2], v2[0]
-; CHECK: ins.s v0[3], v3[0]
-; CHECK: ret
- %1 = insertelement <4 x float> undef, float %a, i32 0
- %2 = insertelement <4 x float> %1, float %b, i32 1
- %3 = insertelement <4 x float> %2, float %c, i32 2
- %4 = insertelement <4 x float> %3, float %d, i32 3
- ret <4 x float> %4
-}
Removed: llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/call-tailcalls.ll (removed)
@@ -1,91 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-
- at t = weak global i32 ()* null
- at x = external global i32, align 4
-
-define void @t2() {
-; CHECK-LABEL: t2:
-; CHECK: adrp x[[GOTADDR:[0-9]+]], _t at GOTPAGE
-; CHECK: ldr x[[ADDR:[0-9]+]], [x[[GOTADDR]], _t at GOTPAGEOFF]
-; CHECK: ldr x[[DEST:[0-9]+]], [x[[ADDR]]]
-; CHECK: br x[[DEST]]
- %tmp = load i32 ()** @t
- %tmp.upgrd.2 = tail call i32 %tmp()
- ret void
-}
-
-define void @t3() {
-; CHECK-LABEL: t3:
-; CHECK: b _t2
- tail call void @t2()
- ret void
-}
-
-define double @t4(double %a) nounwind readonly ssp {
-; CHECK-LABEL: t4:
-; CHECK: b _sin
- %tmp = tail call double @sin(double %a) nounwind readonly
- ret double %tmp
-}
-
-define float @t5(float %a) nounwind readonly ssp {
-; CHECK-LABEL: t5:
-; CHECK: b _sinf
- %tmp = tail call float @sinf(float %a) nounwind readonly
- ret float %tmp
-}
-
-define void @t7() nounwind {
-; CHECK-LABEL: t7:
-; CHECK: b _foo
-; CHECK: b _bar
-
- br i1 undef, label %bb, label %bb1.lr.ph
-
-bb1.lr.ph: ; preds = %entry
- tail call void @bar() nounwind
- ret void
-
-bb: ; preds = %entry
- tail call void @foo() nounwind
- ret void
-}
-
-define i32 @t8(i32 %x) nounwind ssp {
-; CHECK-LABEL: t8:
-; CHECK: b _a
-; CHECK: b _b
-; CHECK: b _c
- %and = and i32 %x, 1
- %tobool = icmp eq i32 %and, 0
- br i1 %tobool, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- %call = tail call i32 @a(i32 %x) nounwind
- br label %return
-
-if.end: ; preds = %entry
- %and1 = and i32 %x, 2
- %tobool2 = icmp eq i32 %and1, 0
- br i1 %tobool2, label %if.end5, label %if.then3
-
-if.then3: ; preds = %if.end
- %call4 = tail call i32 @b(i32 %x) nounwind
- br label %return
-
-if.end5: ; preds = %if.end
- %call6 = tail call i32 @c(i32 %x) nounwind
- br label %return
-
-return: ; preds = %if.end5, %if.then3, %if.then
- %retval.0 = phi i32 [ %call, %if.then ], [ %call4, %if.then3 ], [ %call6, %if.end5 ]
- ret i32 %retval.0
-}
-
-declare float @sinf(float) nounwind readonly
-declare double @sin(double) nounwind readonly
-declare void @bar() nounwind
-declare void @foo() nounwind
-declare i32 @a(i32)
-declare i32 @b(i32)
-declare i32 @c(i32)
Removed: llvm/trunk/test/CodeGen/ARM64/cast-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/cast-opt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/cast-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/cast-opt.ll (removed)
@@ -1,31 +0,0 @@
-; RUN: llc -O3 -march=arm64 -mtriple arm64-apple-ios5.0.0 < %s | FileCheck %s
-; <rdar://problem/15992732>
-; Zero truncation is not necessary when the values are extended properly
-; already.
-
- at block = common global i8* null, align 8
-
-define zeroext i8 @foo(i32 %i1, i32 %i2) {
-; CHECK-LABEL: foo:
-; CHECK: cset
-; CHECK-NOT: and
-entry:
- %idxprom = sext i32 %i1 to i64
- %0 = load i8** @block, align 8
- %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom
- %1 = load i8* %arrayidx, align 1
- %idxprom1 = sext i32 %i2 to i64
- %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1
- %2 = load i8* %arrayidx2, align 1
- %cmp = icmp eq i8 %1, %2
- br i1 %cmp, label %return, label %if.then
-
-if.then: ; preds = %entry
- %cmp7 = icmp ugt i8 %1, %2
- %conv9 = zext i1 %cmp7 to i8
- br label %return
-
-return: ; preds = %entry, %if.then
- %retval.0 = phi i8 [ %conv9, %if.then ], [ 1, %entry ]
- ret i8 %retval.0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ccmp-heuristics.ll (removed)
@@ -1,190 +0,0 @@
-; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -arm64-ccmp | FileCheck %s
-target triple = "arm64-apple-ios7.0.0"
-
- at channelColumns = external global i64
- at channelTracks = external global i64
- at mazeRoute = external hidden unnamed_addr global i8*, align 8
- at TOP = external global i64*
- at BOT = external global i64*
- at netsAssign = external global i64*
-
-; Function from yacr2/maze.c
-; The branch at the end of %if.then is driven by %cmp5 and %cmp6.
-; Isel converts the and i1 into two branches, and arm64-ccmp should not convert
-; it back again. %cmp6 has much higher latency than %cmp5.
-; CHECK: Maze1
-; CHECK: %if.then
-; CHECK: cmp x{{[0-9]+}}, #2
-; CHECK-NEXT b.cc
-; CHECK: %if.then
-; CHECK: cmp x{{[0-9]+}}, #2
-; CHECK-NEXT b.cc
-define i32 @Maze1() nounwind ssp {
-entry:
- %0 = load i64* @channelColumns, align 8, !tbaa !0
- %cmp90 = icmp eq i64 %0, 0
- br i1 %cmp90, label %for.end, label %for.body
-
-for.body: ; preds = %for.inc, %entry
- %1 = phi i64 [ %0, %entry ], [ %37, %for.inc ]
- %i.092 = phi i64 [ 1, %entry ], [ %inc53, %for.inc ]
- %numLeft.091 = phi i32 [ 0, %entry ], [ %numLeft.1, %for.inc ]
- %2 = load i8** @mazeRoute, align 8, !tbaa !3
- %arrayidx = getelementptr inbounds i8* %2, i64 %i.092
- %3 = load i8* %arrayidx, align 1, !tbaa !1
- %tobool = icmp eq i8 %3, 0
- br i1 %tobool, label %for.inc, label %if.then
-
-if.then: ; preds = %for.body
- %4 = load i64** @TOP, align 8, !tbaa !3
- %arrayidx1 = getelementptr inbounds i64* %4, i64 %i.092
- %5 = load i64* %arrayidx1, align 8, !tbaa !0
- %6 = load i64** @netsAssign, align 8, !tbaa !3
- %arrayidx2 = getelementptr inbounds i64* %6, i64 %5
- %7 = load i64* %arrayidx2, align 8, !tbaa !0
- %8 = load i64** @BOT, align 8, !tbaa !3
- %arrayidx3 = getelementptr inbounds i64* %8, i64 %i.092
- %9 = load i64* %arrayidx3, align 8, !tbaa !0
- %arrayidx4 = getelementptr inbounds i64* %6, i64 %9
- %10 = load i64* %arrayidx4, align 8, !tbaa !0
- %cmp5 = icmp ugt i64 %i.092, 1
- %cmp6 = icmp ugt i64 %10, 1
- %or.cond = and i1 %cmp5, %cmp6
- br i1 %or.cond, label %land.lhs.true7, label %if.else
-
-land.lhs.true7: ; preds = %if.then
- %11 = load i64* @channelTracks, align 8, !tbaa !0
- %add = add i64 %11, 1
- %call = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add, i64 %10, i64 0, i64 %7, i32 -1, i32 -1)
- %tobool8 = icmp eq i32 %call, 0
- br i1 %tobool8, label %land.lhs.true7.if.else_crit_edge, label %if.then9
-
-land.lhs.true7.if.else_crit_edge: ; preds = %land.lhs.true7
- %.pre = load i64* @channelColumns, align 8, !tbaa !0
- br label %if.else
-
-if.then9: ; preds = %land.lhs.true7
- %12 = load i8** @mazeRoute, align 8, !tbaa !3
- %arrayidx10 = getelementptr inbounds i8* %12, i64 %i.092
- store i8 0, i8* %arrayidx10, align 1, !tbaa !1
- %13 = load i64** @TOP, align 8, !tbaa !3
- %arrayidx11 = getelementptr inbounds i64* %13, i64 %i.092
- %14 = load i64* %arrayidx11, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %14)
- %15 = load i64** @BOT, align 8, !tbaa !3
- %arrayidx12 = getelementptr inbounds i64* %15, i64 %i.092
- %16 = load i64* %arrayidx12, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %16)
- br label %for.inc
-
-if.else: ; preds = %land.lhs.true7.if.else_crit_edge, %if.then
- %17 = phi i64 [ %.pre, %land.lhs.true7.if.else_crit_edge ], [ %1, %if.then ]
- %cmp13 = icmp ult i64 %i.092, %17
- %or.cond89 = and i1 %cmp13, %cmp6
- br i1 %or.cond89, label %land.lhs.true16, label %if.else24
-
-land.lhs.true16: ; preds = %if.else
- %18 = load i64* @channelTracks, align 8, !tbaa !0
- %add17 = add i64 %18, 1
- %call18 = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add17, i64 %10, i64 0, i64 %7, i32 1, i32 -1)
- %tobool19 = icmp eq i32 %call18, 0
- br i1 %tobool19, label %if.else24, label %if.then20
-
-if.then20: ; preds = %land.lhs.true16
- %19 = load i8** @mazeRoute, align 8, !tbaa !3
- %arrayidx21 = getelementptr inbounds i8* %19, i64 %i.092
- store i8 0, i8* %arrayidx21, align 1, !tbaa !1
- %20 = load i64** @TOP, align 8, !tbaa !3
- %arrayidx22 = getelementptr inbounds i64* %20, i64 %i.092
- %21 = load i64* %arrayidx22, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %21)
- %22 = load i64** @BOT, align 8, !tbaa !3
- %arrayidx23 = getelementptr inbounds i64* %22, i64 %i.092
- %23 = load i64* %arrayidx23, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %23)
- br label %for.inc
-
-if.else24: ; preds = %land.lhs.true16, %if.else
- br i1 %cmp5, label %land.lhs.true26, label %if.else36
-
-land.lhs.true26: ; preds = %if.else24
- %24 = load i64* @channelTracks, align 8, !tbaa !0
- %cmp27 = icmp ult i64 %7, %24
- br i1 %cmp27, label %land.lhs.true28, label %if.else36
-
-land.lhs.true28: ; preds = %land.lhs.true26
- %add29 = add i64 %24, 1
- %call30 = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 0, i64 %7, i64 %add29, i64 %10, i32 -1, i32 1)
- %tobool31 = icmp eq i32 %call30, 0
- br i1 %tobool31, label %if.else36, label %if.then32
-
-if.then32: ; preds = %land.lhs.true28
- %25 = load i8** @mazeRoute, align 8, !tbaa !3
- %arrayidx33 = getelementptr inbounds i8* %25, i64 %i.092
- store i8 0, i8* %arrayidx33, align 1, !tbaa !1
- %26 = load i64** @TOP, align 8, !tbaa !3
- %arrayidx34 = getelementptr inbounds i64* %26, i64 %i.092
- %27 = load i64* %arrayidx34, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %27)
- %28 = load i64** @BOT, align 8, !tbaa !3
- %arrayidx35 = getelementptr inbounds i64* %28, i64 %i.092
- %29 = load i64* %arrayidx35, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %29)
- br label %for.inc
-
-if.else36: ; preds = %land.lhs.true28, %land.lhs.true26, %if.else24
- %30 = load i64* @channelColumns, align 8, !tbaa !0
- %cmp37 = icmp ult i64 %i.092, %30
- br i1 %cmp37, label %land.lhs.true38, label %if.else48
-
-land.lhs.true38: ; preds = %if.else36
- %31 = load i64* @channelTracks, align 8, !tbaa !0
- %cmp39 = icmp ult i64 %7, %31
- br i1 %cmp39, label %land.lhs.true40, label %if.else48
-
-land.lhs.true40: ; preds = %land.lhs.true38
- %add41 = add i64 %31, 1
- %call42 = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 0, i64 %7, i64 %add41, i64 %10, i32 1, i32 1)
- %tobool43 = icmp eq i32 %call42, 0
- br i1 %tobool43, label %if.else48, label %if.then44
-
-if.then44: ; preds = %land.lhs.true40
- %32 = load i8** @mazeRoute, align 8, !tbaa !3
- %arrayidx45 = getelementptr inbounds i8* %32, i64 %i.092
- store i8 0, i8* %arrayidx45, align 1, !tbaa !1
- %33 = load i64** @TOP, align 8, !tbaa !3
- %arrayidx46 = getelementptr inbounds i64* %33, i64 %i.092
- %34 = load i64* %arrayidx46, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %34)
- %35 = load i64** @BOT, align 8, !tbaa !3
- %arrayidx47 = getelementptr inbounds i64* %35, i64 %i.092
- %36 = load i64* %arrayidx47, align 8, !tbaa !0
- tail call fastcc void @CleanNet(i64 %36)
- br label %for.inc
-
-if.else48: ; preds = %land.lhs.true40, %land.lhs.true38, %if.else36
- %inc = add nsw i32 %numLeft.091, 1
- br label %for.inc
-
-for.inc: ; preds = %if.else48, %if.then44, %if.then32, %if.then20, %if.then9, %for.body
- %numLeft.1 = phi i32 [ %numLeft.091, %if.then9 ], [ %numLeft.091, %if.then20 ], [ %numLeft.091, %if.then32 ], [ %numLeft.091, %if.then44 ], [ %inc, %if.else48 ], [ %numLeft.091, %for.body ]
- %inc53 = add i64 %i.092, 1
- %37 = load i64* @channelColumns, align 8, !tbaa !0
- %cmp = icmp ugt i64 %inc53, %37
- br i1 %cmp, label %for.end, label %for.body
-
-for.end: ; preds = %for.inc, %entry
- %numLeft.0.lcssa = phi i32 [ 0, %entry ], [ %numLeft.1, %for.inc ]
- ret i32 %numLeft.0.lcssa
-}
-
-; Materializable
-declare hidden fastcc i32 @Maze1Mech(i64, i64, i64, i64, i64, i32, i32) nounwind ssp
-
-; Materializable
-declare hidden fastcc void @CleanNet(i64) nounwind ssp
-
-!0 = metadata !{metadata !"long", metadata !1}
-!1 = metadata !{metadata !"omnipotent char", metadata !2}
-!2 = metadata !{metadata !"Simple C/C++ TBAA"}
-!3 = metadata !{metadata !"any pointer", metadata !1}
Removed: llvm/trunk/test/CodeGen/ARM64/ccmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ccmp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ccmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ccmp.ll (removed)
@@ -1,289 +0,0 @@
-; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -arm64-ccmp -arm64-stress-ccmp | FileCheck %s
-target triple = "arm64-apple-ios"
-
-; CHECK: single_same
-; CHECK: cmp w0, #5
-; CHECK-NEXT: ccmp w1, #17, #4, ne
-; CHECK-NEXT: b.ne
-; CHECK: %if.then
-; CHECK: bl _foo
-; CHECK: %if.end
-define i32 @single_same(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 5
- %cmp1 = icmp eq i32 %b, 17
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Different condition codes for the two compares.
-; CHECK: single_different
-; CHECK: cmp w0, #6
-; CHECK-NEXT: ccmp w1, #17, #0, ge
-; CHECK-NEXT: b.eq
-; CHECK: %if.then
-; CHECK: bl _foo
-; CHECK: %if.end
-define i32 @single_different(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp sle i32 %a, 5
- %cmp1 = icmp ne i32 %b, 17
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Second block clobbers the flags, can't convert (easily).
-; CHECK: single_flagclobber
-; CHECK: cmp
-; CHECK: b.eq
-; CHECK: cmp
-; CHECK: b.gt
-define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 5
- br i1 %cmp, label %if.then, label %lor.lhs.false
-
-lor.lhs.false: ; preds = %entry
- %cmp1 = icmp slt i32 %b, 7
- %mul = shl nsw i32 %b, 1
- %add = add nsw i32 %b, 1
- %cond = select i1 %cmp1, i32 %mul, i32 %add
- %cmp2 = icmp slt i32 %cond, 17
- br i1 %cmp2, label %if.then, label %if.end
-
-if.then: ; preds = %lor.lhs.false, %entry
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end: ; preds = %if.then, %lor.lhs.false
- ret i32 7
-}
-
-; Second block clobbers the flags and ends with a tbz terminator.
-; CHECK: single_flagclobber_tbz
-; CHECK: cmp
-; CHECK: b.eq
-; CHECK: cmp
-; CHECK: tbz
-define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 5
- br i1 %cmp, label %if.then, label %lor.lhs.false
-
-lor.lhs.false: ; preds = %entry
- %cmp1 = icmp slt i32 %b, 7
- %mul = shl nsw i32 %b, 1
- %add = add nsw i32 %b, 1
- %cond = select i1 %cmp1, i32 %mul, i32 %add
- %and = and i32 %cond, 8
- %cmp2 = icmp ne i32 %and, 0
- br i1 %cmp2, label %if.then, label %if.end
-
-if.then: ; preds = %lor.lhs.false, %entry
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end: ; preds = %if.then, %lor.lhs.false
- ret i32 7
-}
-
-; Speculatively execute division by zero.
-; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
-; safe to speculate.
-; CHECK: speculate_division
-; CHECK-NOT: cmp
-; CHECK: sdiv
-; CHECK: cmp
-; CHECK-NEXT: ccmp
-define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp sgt i32 %a, 0
- br i1 %cmp, label %land.lhs.true, label %if.end
-
-land.lhs.true:
- %div = sdiv i32 %b, %a
- %cmp1 = icmp slt i32 %div, 17
- br i1 %cmp1, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Floating point compare.
-; CHECK: single_fcmp
-; CHECK: cmp
-; CHECK-NOT: b.
-; CHECK: fccmp {{.*}}, #8, ge
-; CHECK: b.lt
-define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {
-entry:
- %cmp = icmp sgt i32 %a, 0
- br i1 %cmp, label %land.lhs.true, label %if.end
-
-land.lhs.true:
- %conv = sitofp i32 %a to float
- %div = fdiv float %b, %conv
- %cmp1 = fcmp oge float %div, 1.700000e+01
- br i1 %cmp1, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Chain multiple compares.
-; CHECK: multi_different
-; CHECK: cmp
-; CHECK: ccmp
-; CHECK: ccmp
-; CHECK: b.
-define void @multi_different(i32 %a, i32 %b, i32 %c) nounwind ssp {
-entry:
- %cmp = icmp sgt i32 %a, %b
- br i1 %cmp, label %land.lhs.true, label %if.end
-
-land.lhs.true:
- %div = sdiv i32 %b, %a
- %cmp1 = icmp eq i32 %div, 5
- %cmp4 = icmp sgt i32 %div, %c
- %or.cond = and i1 %cmp1, %cmp4
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret void
-}
-
-; Convert a cbz in the head block.
-; CHECK: cbz_head
-; CHECK: cmp w0, #0
-; CHECK: ccmp
-define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 0
- %cmp1 = icmp ne i32 %b, 17
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Check that the immediate operand is in range. The ccmp instruction encodes a
-; smaller range of immediates than subs/adds.
-; The ccmp immediates must be in the range 0-31.
-; CHECK: immediate_range
-; CHECK-NOT: ccmp
-define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 5
- %cmp1 = icmp eq i32 %b, 32
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Convert a cbz in the second block.
-; CHECK: cbz_second
-; CHECK: cmp w0, #0
-; CHECK: ccmp w1, #0, #0, ne
-; CHECK: b.eq
-define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 0
- %cmp1 = icmp ne i32 %b, 0
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-
-; Convert a cbnz in the second block.
-; CHECK: cbnz_second
-; CHECK: cmp w0, #0
-; CHECK: ccmp w1, #0, #4, ne
-; CHECK: b.ne
-define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {
-entry:
- %cmp = icmp eq i32 %a, 0
- %cmp1 = icmp eq i32 %b, 0
- %or.cond = or i1 %cmp, %cmp1
- br i1 %or.cond, label %if.then, label %if.end
-
-if.then:
- %call = tail call i32 @foo() nounwind
- br label %if.end
-
-if.end:
- ret i32 7
-}
-declare i32 @foo()
-
-%str1 = type { %str2 }
-%str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* }
-
-; Test case distilled from 126.gcc.
-; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.
-; CHECK: build_modify_expr
-define void @build_modify_expr() nounwind ssp {
-entry:
- switch i32 undef, label %sw.bb.i.i [
- i32 69, label %if.end85
- i32 70, label %if.end85
- i32 71, label %if.end85
- i32 72, label %if.end85
- i32 73, label %if.end85
- i32 105, label %if.end85
- i32 106, label %if.end85
- ]
-
-if.end85:
- ret void
-
-sw.bb.i.i:
- %ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ]
- %operands.i.i = getelementptr inbounds %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
- %arrayidx.i.i = bitcast i32* %operands.i.i to %str1**
- %0 = load %str1** %arrayidx.i.i, align 8
- %code1.i.i.phi.trans.insert = getelementptr inbounds %str1* %0, i64 0, i32 0, i32 0, i64 16
- br label %sw.bb.i.i
-}
Removed: llvm/trunk/test/CodeGen/ARM64/clrsb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/clrsb.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/clrsb.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/clrsb.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios7.0.0"
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.ctlz.i32(i32, i1) #0
-declare i64 @llvm.ctlz.i64(i64, i1) #1
-
-; Function Attrs: nounwind ssp
-define i32 @clrsb32(i32 %x) #2 {
-entry:
- %shr = ashr i32 %x, 31
- %xor = xor i32 %shr, %x
- %mul = shl i32 %xor, 1
- %add = or i32 %mul, 1
- %0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 false)
-
- ret i32 %0
-; CHECK-LABEL: clrsb32
-; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
-}
-
-; Function Attrs: nounwind ssp
-define i64 @clrsb64(i64 %x) #3 {
-entry:
- %shr = ashr i64 %x, 63
- %xor = xor i64 %shr, %x
- %mul = shl nsw i64 %xor, 1
- %add = or i64 %mul, 1
- %0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 false)
-
- ret i64 %0
-; CHECK-LABEL: clrsb64
-; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]]
-}
Removed: llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/coalesce-ext.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc -march=arm64 -mtriple=arm64-apple-darwin < %s | FileCheck %s
-; Check that the peephole optimizer knows about sext and zext instructions.
-; CHECK: test1sext
-define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
- %C = add i64 %A, %B
- ; CHECK: add x[[SUM:[0-9]+]], x0, x1
- %D = trunc i64 %C to i32
- %E = shl i64 %C, 32
- %F = ashr i64 %E, 32
- ; CHECK: sxtw x[[EXT:[0-9]+]], w[[SUM]]
- store volatile i64 %F, i64 *%P2
- ; CHECK: str x[[EXT]]
- store volatile i32 %D, i32* %P
- ; Reuse low bits of extended register, don't extend live range of SUM.
- ; CHECK: str w[[SUM]]
- ret i32 %D
-}
Removed: llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/code-model-large-abs.ll (removed)
@@ -1,72 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large < %s | FileCheck %s
-
- at var8 = global i8 0
- at var16 = global i16 0
- at var32 = global i32 0
- at var64 = global i64 0
-
-define i8* @global_addr() {
-; CHECK-LABEL: global_addr:
- ret i8* @var8
- ; The movz/movk calculation should end up returned directly in x0.
-; CHECK: movz x0, #:abs_g3:var8
-; CHECK: movk x0, #:abs_g2_nc:var8
-; CHECK: movk x0, #:abs_g1_nc:var8
-; CHECK: movk x0, #:abs_g0_nc:var8
-; CHECK-NEXT: ret
-}
-
-define i8 @global_i8() {
-; CHECK-LABEL: global_i8:
- %val = load i8* @var8
- ret i8 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8
-; CHECK: ldrb w0, [x[[ADDR_REG]]]
-}
-
-define i16 @global_i16() {
-; CHECK-LABEL: global_i16:
- %val = load i16* @var16
- ret i16 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
-; CHECK: ldrh w0, [x[[ADDR_REG]]]
-}
-
-define i32 @global_i32() {
-; CHECK-LABEL: global_i32:
- %val = load i32* @var32
- ret i32 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32
-; CHECK: ldr w0, [x[[ADDR_REG]]]
-}
-
-define i64 @global_i64() {
-; CHECK-LABEL: global_i64:
- %val = load i64* @var64
- ret i64 %val
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64
-; CHECK: ldr x0, [x[[ADDR_REG]]]
-}
-
-define <2 x i64> @constpool() {
-; CHECK-LABEL: constpool:
- ret <2 x i64> <i64 123456789, i64 987654321100>
-
-; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:[[CPADDR:.LCPI[0-9]+_[0-9]+]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:[[CPADDR]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:[[CPADDR]]
-; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:[[CPADDR]]
-; CHECK: ldr q0, [x[[ADDR_REG]]]
-}
Removed: llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/collect-loh-garbage-crash.ll (removed)
@@ -1,37 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -O3 -arm64-collect-loh -arm64-collect-loh-bb-only=true -arm64-collect-loh-pre-collect-register=false < %s -o - | FileCheck %s
-; Check that the LOH analysis does not crash when the analysed chained
-; contains instructions that are filtered out.
-;
-; Before the fix for <rdar://problem/16041712>, these cases were removed
-; from the main container. Now, the deterministic container does not allow
-; to remove arbitrary values, so we have to live with garbage values.
-; <rdar://problem/16041712>
-
-%"class.H4ISP::H4ISPDevice" = type { i32 (%"class.H4ISP::H4ISPDevice"*, i32, i8*, i8*)*, i8*, i32*, %"class.H4ISP::H4ISPCameraManager"* }
-
-%"class.H4ISP::H4ISPCameraManager" = type opaque
-
-declare i32 @_ZN5H4ISP11H4ISPDevice32ISP_SelectBestMIPIFrequencyIndexEjPj(%"class.H4ISP::H4ISPDevice"*)
-
- at pH4ISPDevice = hidden global %"class.H4ISP::H4ISPDevice"* null, align 8
-
-; CHECK-LABEL: _foo:
-; CHECK: ret
-; CHECK-NOT: .loh AdrpLdrGotLdr
-define void @foo() {
-entry:
- br label %if.then83
-if.then83: ; preds = %if.end81
- %tmp = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
- %call84 = call i32 @_ZN5H4ISP11H4ISPDevice32ISP_SelectBestMIPIFrequencyIndexEjPj(%"class.H4ISP::H4ISPDevice"* %tmp) #19
- tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27}"()
- %tmp2 = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8
- tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x28}"()
- %pCameraManager.i268 = getelementptr inbounds %"class.H4ISP::H4ISPDevice"* %tmp2, i64 0, i32 3
- %tmp3 = load %"class.H4ISP::H4ISPCameraManager"** %pCameraManager.i268, align 8
- %tobool.i269 = icmp eq %"class.H4ISP::H4ISPCameraManager"* %tmp3, null
- br i1 %tobool.i269, label %if.then83, label %end
-end:
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/collect-loh-str.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s
-; Test case for <rdar://problem/15942912>.
-; AdrpAddStr cannot be used when the store uses same
-; register as address and value. Indeed, the related
-; if applied, may completely remove the definition or
-; at least provide a wrong one (with the offset folded
-; into the definition).
-
-%struct.anon = type { i32*, i32** }
-
- at pptp_wan_head = internal global %struct.anon zeroinitializer, align 8
-
-; CHECK-LABEL: _pptp_wan_init
-; CHECK: ret
-; CHECK-NOT: AdrpAddStr
-define i32 @pptp_wan_init() {
-entry:
- store i32* null, i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), align 8
- store i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), i32*** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 1), align 8
- ret i32 0
-}
-
-
Removed: llvm/trunk/test/CodeGen/ARM64/collect-loh.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/collect-loh.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/collect-loh.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/collect-loh.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -O2 -arm64-collect-loh -arm64-collect-loh-bb-only=false < %s -o - | FileCheck %s --check-prefix=CHECK-ELF
-
-; CHECK-ELF-NOT: .loh
-; CHECK-ELF-NOT: AdrpAdrp
-; CHECK-ELF-NOT: AdrpAdd
-; CHECK-ELF-NOT: AdrpLdrGot
-
- at a = internal unnamed_addr global i32 0, align 4
- at b = external global i32
-
-; Function Attrs: noinline nounwind ssp
-define void @foo(i32 %t) {
-entry:
- %tmp = load i32* @a, align 4
- %add = add nsw i32 %tmp, %t
- store i32 %add, i32* @a, align 4
- ret void
-}
-
-; Function Attrs: nounwind ssp
-; Testcase for <rdar://problem/15438605>, AdrpAdrp reuse is valid only when the first adrp
-; dominates the second.
-; The first adrp comes from the loading of 'a' and the second the loading of 'b'.
-; 'a' is loaded in if.then, 'b' in if.end4, if.then does not dominates if.end4.
-; CHECK-LABEL: _test
-; CHECK: ret
-; CHECK-NOT: .loh AdrpAdrp
-define i32 @test(i32 %t) {
-entry:
- %cmp = icmp sgt i32 %t, 5
- br i1 %cmp, label %if.then, label %if.end4
-
-if.then: ; preds = %entry
- %tmp = load i32* @a, align 4
- %add = add nsw i32 %tmp, %t
- %cmp1 = icmp sgt i32 %add, 12
- br i1 %cmp1, label %if.then2, label %if.end4
-
-if.then2: ; preds = %if.then
- tail call void @foo(i32 %add)
- %tmp1 = load i32* @a, align 4
- br label %if.end4
-
-if.end4: ; preds = %if.then2, %if.then, %entry
- %t.addr.0 = phi i32 [ %tmp1, %if.then2 ], [ %t, %if.then ], [ %t, %entry ]
- %tmp2 = load i32* @b, align 4
- %add5 = add nsw i32 %tmp2, %t.addr.0
- tail call void @foo(i32 %add5)
- %tmp3 = load i32* @b, align 4
- %add6 = add nsw i32 %tmp3, %t.addr.0
- ret i32 %add6
-}
Removed: llvm/trunk/test/CodeGen/ARM64/compact-unwind-unhandled-cfi.S
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/compact-unwind-unhandled-cfi.S?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/compact-unwind-unhandled-cfi.S (original)
+++ llvm/trunk/test/CodeGen/ARM64/compact-unwind-unhandled-cfi.S (removed)
@@ -1,17 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o /dev/null %s
-
- .text
- .globl _foo
- .cfi_startproc
-_foo:
- stp x29, x30, [sp, #-16]!
- .cfi_adjust_cfa_offset 16
-
- ldp x29, x30, [sp], #16
- .cfi_adjust_cfa_offset -16
- .cfi_restore x29
- .cfi_restore x30
-
- ret
-
- .cfi_endproc
Removed: llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/complex-copy-noneon.ll (removed)
@@ -1,21 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=-neon < %s
-
-; The DAG combiner decided to use a vector load/store for this struct copy
-; previously. This probably shouldn't happen without NEON, but the most
-; important thing is that it compiles.
-
-define void @store_combine() nounwind {
- %src = alloca { double, double }, align 8
- %dst = alloca { double, double }, align 8
-
- %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0
- %src.real = load double* %src.realp
- %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1
- %src.imag = load double* %src.imagp
-
- %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0
- %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1
- store double %src.real, double* %dst.realp
- store double %src.imag, double* %dst.imagp
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/complex-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/complex-ret.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/complex-ret.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/complex-ret.ll (removed)
@@ -1,7 +0,0 @@
-; RUN: llc -march=arm64 -o - %s | FileCheck %s
-
-define { i192, i192, i21, i192 } @foo(i192) {
-; CHECK-LABEL: foo:
-; CHECK: stp xzr, xzr, [x8]
- ret { i192, i192, i21, i192 } {i192 0, i192 1, i21 2, i192 3}
-}
Removed: llvm/trunk/test/CodeGen/ARM64/const-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/const-addr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/const-addr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/const-addr.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: llc -mtriple=arm64-darwin-unknown < %s | FileCheck %s
-
-%T = type { i32, i32, i32, i32 }
-
-; Test if the constant base address gets only materialized once.
-define i32 @test1() nounwind {
-; CHECK-LABEL: test1
-; CHECK: movz w8, #0x40f, lsl #16
-; CHECK-NEXT: movk w8, #0xc000
-; CHECK-NEXT: ldp w9, w10, [x8, #4]
-; CHECK: ldr w8, [x8, #12]
- %at = inttoptr i64 68141056 to %T*
- %o1 = getelementptr %T* %at, i32 0, i32 1
- %t1 = load i32* %o1
- %o2 = getelementptr %T* %at, i32 0, i32 2
- %t2 = load i32* %o2
- %a1 = add i32 %t1, %t2
- %o3 = getelementptr %T* %at, i32 0, i32 3
- %t3 = load i32* %o3
- %a2 = add i32 %a1, %t3
- ret i32 %a2
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/convert-v2f64-v2i32.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-; CHECK: fptosi_1
-; CHECK: fcvtzs.2d
-; CHECK: xtn.2s
-; CHECK: ret
-define void @fptosi_1() nounwind noinline ssp {
-entry:
- %0 = fptosi <2 x double> undef to <2 x i32>
- store <2 x i32> %0, <2 x i32>* undef, align 8
- ret void
-}
-
-; CHECK: fptoui_1
-; CHECK: fcvtzu.2d
-; CHECK: xtn.2s
-; CHECK: ret
-define void @fptoui_1() nounwind noinline ssp {
-entry:
- %0 = fptoui <2 x double> undef to <2 x i32>
- store <2 x i32> %0, <2 x i32>* undef, align 8
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/convert-v2i32-v2f64.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <2 x double> @f1(<2 x i32> %v) nounwind readnone {
-; CHECK-LABEL: f1:
-; CHECK: sshll.2d v0, v0, #0
-; CHECK-NEXT: scvtf.2d v0, v0
-; CHECK-NEXT: ret
- %conv = sitofp <2 x i32> %v to <2 x double>
- ret <2 x double> %conv
-}
-define <2 x double> @f2(<2 x i32> %v) nounwind readnone {
-; CHECK-LABEL: f2:
-; CHECK: ushll.2d v0, v0, #0
-; CHECK-NEXT: ucvtf.2d v0, v0
-; CHECK-NEXT: ret
- %conv = uitofp <2 x i32> %v to <2 x double>
- ret <2 x double> %conv
-}
-
-; CHECK: autogen_SD19655
-; CHECK: scvtf
-; CHECK: ret
-define void @autogen_SD19655() {
- %T = load <2 x i64>* undef
- %F = sitofp <2 x i64> undef to <2 x float>
- store <2 x float> %F, <2 x float>* undef
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/copy-tuple.ll (removed)
@@ -1,146 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s
-
-; The main purpose of this test is to find out whether copyPhysReg can deal with
-; the memmove-like situation arising in tuples, where an early copy can clobber
-; the value needed by a later one if the tuples overlap.
-
-; We use dummy inline asm to force LLVM to generate a COPY between the registers
-; we want by clobbering all the others.
-
-define void @test_D1D2_from_D0D1(i8* %addr) #0 {
-; CHECK-LABEL: test_D1D2_from_D0D1:
-; CHECK: mov.8b v2, v1
-; CHECK: mov.8b v1, v0
-entry:
- %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
- %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
- %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
- tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
-
- tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
- ret void
-}
-
-define void @test_D0D1_from_D1D2(i8* %addr) #0 {
-; CHECK-LABEL: test_D0D1_from_D1D2:
-; CHECK: mov.8b v0, v1
-; CHECK: mov.8b v1, v2
-entry:
- %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
- %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
- %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
- tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
-
- tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
- ret void
-}
-
-define void @test_D0D1_from_D31D0(i8* %addr) #0 {
-; CHECK-LABEL: test_D0D1_from_D31D0:
-; CHECK: mov.8b v1, v0
-; CHECK: mov.8b v0, v31
-entry:
- %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
- %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
- %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
- tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
-
- tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
- ret void
-}
-
-define void @test_D31D0_from_D0D1(i8* %addr) #0 {
-; CHECK-LABEL: test_D31D0_from_D0D1:
-; CHECK: mov.8b v31, v0
-; CHECK: mov.8b v0, v1
-entry:
- %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
- %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
- %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
- tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
-
- tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
- tail call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
- ret void
-}
-
-define void @test_D2D3D4_from_D0D1D2(i8* %addr) #0 {
-; CHECK-LABEL: test_D2D3D4_from_D0D1D2:
-; CHECK: mov.8b v4, v2
-; CHECK: mov.8b v3, v1
-; CHECK: mov.8b v2, v0
-entry:
- %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
- %vec = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
- %vec0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 0
- %vec1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 1
- %vec2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 2
-
- tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
-
- tail call void asm sideeffect "", "~{v0},~{v1},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
- ret void
-}
-
-define void @test_Q0Q1Q2_from_Q1Q2Q3(i8* %addr) #0 {
-; CHECK-LABEL: test_Q0Q1Q2_from_Q1Q2Q3:
-; CHECK: mov.16b v0, v1
-; CHECK: mov.16b v1, v2
-; CHECK: mov.16b v2, v3
-entry:
- %addr_v16i8 = bitcast i8* %addr to <16 x i8>*
- %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
- %vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
- %vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
- %vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
- tail call void asm sideeffect "", "~{v0},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
-
- tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
- ret void
-}
-
-define void @test_Q1Q2Q3Q4_from_Q30Q31Q0Q1(i8* %addr) #0 {
-; CHECK-LABEL: test_Q1Q2Q3Q4_from_Q30Q31Q0Q1:
-; CHECK: mov.16b v4, v1
-; CHECK: mov.16b v3, v0
-; CHECK: mov.16b v2, v31
-; CHECK: mov.16b v1, v30
- %addr_v16i8 = bitcast i8* %addr to <16 x i8>*
- %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
- %vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
- %vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
- %vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
- %vec3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 3
-
- tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}"()
- tail call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
-
- tail call void asm sideeffect "", "~{v0},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
- tail call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
- ret void
-}
-
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0v8i8(<8 x i8>*)
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0v8i8(<8 x i8>*)
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0v16i8(<16 x i8>*)
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0v16i8(<16 x i8>*)
-
-declare void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
-declare void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
-declare void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
-declare void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
Removed: llvm/trunk/test/CodeGen/ARM64/crc32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/crc32.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/crc32.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/crc32.ll (removed)
@@ -1,71 +0,0 @@
-; RUN: llc -march=arm64 -mattr=+crc -o - %s | FileCheck %s
-
-define i32 @test_crc32b(i32 %cur, i8 %next) {
-; CHECK-LABEL: test_crc32b:
-; CHECK: crc32b w0, w0, w1
- %bits = zext i8 %next to i32
- %val = call i32 @llvm.arm64.crc32b(i32 %cur, i32 %bits)
- ret i32 %val
-}
-
-define i32 @test_crc32h(i32 %cur, i16 %next) {
-; CHECK-LABEL: test_crc32h:
-; CHECK: crc32h w0, w0, w1
- %bits = zext i16 %next to i32
- %val = call i32 @llvm.arm64.crc32h(i32 %cur, i32 %bits)
- ret i32 %val
-}
-
-define i32 @test_crc32w(i32 %cur, i32 %next) {
-; CHECK-LABEL: test_crc32w:
-; CHECK: crc32w w0, w0, w1
- %val = call i32 @llvm.arm64.crc32w(i32 %cur, i32 %next)
- ret i32 %val
-}
-
-define i32 @test_crc32x(i32 %cur, i64 %next) {
-; CHECK-LABEL: test_crc32x:
-; CHECK: crc32x w0, w0, x1
- %val = call i32 @llvm.arm64.crc32x(i32 %cur, i64 %next)
- ret i32 %val
-}
-
-define i32 @test_crc32cb(i32 %cur, i8 %next) {
-; CHECK-LABEL: test_crc32cb:
-; CHECK: crc32cb w0, w0, w1
- %bits = zext i8 %next to i32
- %val = call i32 @llvm.arm64.crc32cb(i32 %cur, i32 %bits)
- ret i32 %val
-}
-
-define i32 @test_crc32ch(i32 %cur, i16 %next) {
-; CHECK-LABEL: test_crc32ch:
-; CHECK: crc32ch w0, w0, w1
- %bits = zext i16 %next to i32
- %val = call i32 @llvm.arm64.crc32ch(i32 %cur, i32 %bits)
- ret i32 %val
-}
-
-define i32 @test_crc32cw(i32 %cur, i32 %next) {
-; CHECK-LABEL: test_crc32cw:
-; CHECK: crc32cw w0, w0, w1
- %val = call i32 @llvm.arm64.crc32cw(i32 %cur, i32 %next)
- ret i32 %val
-}
-
-define i32 @test_crc32cx(i32 %cur, i64 %next) {
-; CHECK-LABEL: test_crc32cx:
-; CHECK: crc32cx w0, w0, x1
- %val = call i32 @llvm.arm64.crc32cx(i32 %cur, i64 %next)
- ret i32 %val
-}
-
-declare i32 @llvm.arm64.crc32b(i32, i32)
-declare i32 @llvm.arm64.crc32h(i32, i32)
-declare i32 @llvm.arm64.crc32w(i32, i32)
-declare i32 @llvm.arm64.crc32x(i32, i64)
-
-declare i32 @llvm.arm64.crc32cb(i32, i32)
-declare i32 @llvm.arm64.crc32ch(i32, i32)
-declare i32 @llvm.arm64.crc32cw(i32, i32)
-declare i32 @llvm.arm64.crc32cx(i32, i64)
Removed: llvm/trunk/test/CodeGen/ARM64/crypto.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/crypto.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/crypto.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/crypto.ll (removed)
@@ -1,135 +0,0 @@
-; RUN: llc -march=arm64 -mattr=crypto -arm64-neon-syntax=apple -o - %s | FileCheck %s
-
-declare <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
-declare <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
-declare <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
-declare <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
-
-define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
-; CHECK-LABEL: test_aese:
-; CHECK: aese.16b v0, v1
- %res = call <16 x i8> @llvm.arm64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
- ret <16 x i8> %res
-}
-
-define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
-; CHECK-LABEL: test_aesd:
-; CHECK: aesd.16b v0, v1
- %res = call <16 x i8> @llvm.arm64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
- ret <16 x i8> %res
-}
-
-define <16 x i8> @test_aesmc(<16 x i8> %data) {
-; CHECK-LABEL: test_aesmc:
-; CHECK: aesmc.16b v0, v0
- %res = call <16 x i8> @llvm.arm64.crypto.aesmc(<16 x i8> %data)
- ret <16 x i8> %res
-}
-
-define <16 x i8> @test_aesimc(<16 x i8> %data) {
-; CHECK-LABEL: test_aesimc:
-; CHECK: aesimc.16b v0, v0
- %res = call <16 x i8> @llvm.arm64.crypto.aesimc(<16 x i8> %data)
- ret <16 x i8> %res
-}
-
-declare <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
-declare i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
-declare <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
-declare <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
-
-define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha1c:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1c.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
- ret <4 x i32> %res
-}
-
-; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
-define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha1c_in_a_row:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
-; CHECK-NOT: fmov
-; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
- %extract = extractelement <4 x i32> %res, i32 0
- %res2 = call <4 x i32> @llvm.arm64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
- ret <4 x i32> %res2
-}
-
-define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha1p:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1p.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
- ret <4 x i32> %res
-}
-
-define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha1m:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1m.4s q0, [[HASH_E]], v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
- ret <4 x i32> %res
-}
-
-define i32 @test_sha1h(i32 %hash_e) {
-; CHECK-LABEL: test_sha1h:
-; CHECK: fmov [[HASH_E:s[0-9]+]], w0
-; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
-; CHECK: fmov w0, [[RES]]
- %res = call i32 @llvm.arm64.crypto.sha1h(i32 %hash_e)
- ret i32 %res
-}
-
-define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
-; CHECK-LABEL: test_sha1su0:
-; CHECK: sha1su0.4s v0, v1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
- ret <4 x i32> %res
-}
-
-define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
-; CHECK-LABEL: test_sha1su1:
-; CHECK: sha1su1.4s v0, v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
- ret <4 x i32> %res
-}
-
-declare <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
-declare <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
-declare <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
-
-define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha256h:
-; CHECK: sha256h.4s q0, q1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
- ret <4 x i32> %res
-}
-
-define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
-; CHECK-LABEL: test_sha256h2:
-; CHECK: sha256h2.4s q0, q1, v2
-
- %res = call <4 x i32> @llvm.arm64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
- ret <4 x i32> %res
-}
-
-define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
-; CHECK-LABEL: test_sha256su0:
-; CHECK: sha256su0.4s v0, v1
- %res = call <4 x i32> @llvm.arm64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
- ret <4 x i32> %res
-}
-
-define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
-; CHECK-LABEL: test_sha256su1:
-; CHECK: sha256su1.4s v0, v1, v2
- %res = call <4 x i32> @llvm.arm64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
- ret <4 x i32> %res
-}
Removed: llvm/trunk/test/CodeGen/ARM64/cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/cse.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/cse.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/cse.ll (removed)
@@ -1,59 +0,0 @@
-; RUN: llc -O3 < %s | FileCheck %s
-target triple = "arm64-apple-ios"
-
-; rdar://12462006
-; CSE between "icmp reg reg" and "sub reg reg".
-; Both can be in the same basic block or in different basic blocks.
-define i8* @t1(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: subs
-; CHECK-NOT: cmp
-; CHECK-NOT: sub
-; CHECK: b.ge
-; CHECK: sub
-; CHECK: sub
-; CHECK-NOT: sub
-; CHECK: ret
- %0 = load i32* %offset, align 4
- %cmp = icmp slt i32 %0, %size
- %s = sub nsw i32 %0, %size
- br i1 %cmp, label %return, label %if.end
-
-if.end:
- %sub = sub nsw i32 %0, %size
- %s2 = sub nsw i32 %s, %size
- %s3 = sub nsw i32 %sub, %s2
- store i32 %s3, i32* %offset, align 4
- %add.ptr = getelementptr inbounds i8* %base, i32 %sub
- br label %return
-
-return:
- %retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
- ret i8* %retval.0
-}
-
-; CSE between "icmp reg imm" and "sub reg imm".
-define i8* @t2(i8* %base, i32* nocapture %offset) nounwind {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: subs
-; CHECK-NOT: cmp
-; CHECK-NOT: sub
-; CHECK: b.lt
-; CHECK-NOT: sub
-; CHECK: ret
- %0 = load i32* %offset, align 4
- %cmp = icmp slt i32 %0, 1
- br i1 %cmp, label %return, label %if.end
-
-if.end:
- %sub = sub nsw i32 %0, 1
- store i32 %sub, i32* %offset, align 4
- %add.ptr = getelementptr inbounds i8* %base, i32 %sub
- br label %return
-
-return:
- %retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
- ret i8* %retval.0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/csel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/csel.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/csel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/csel.ll (removed)
@@ -1,230 +0,0 @@
-; RUN: llc -O3 < %s | FileCheck %s
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
-target triple = "arm64-unknown-unknown"
-
-; CHECK-LABEL: foo1
-; CHECK: cinc w{{[0-9]+}}, w{{[0-9]+}}, ne
-define i32 @foo1(i32 %b, i32 %c) nounwind readnone ssp {
-entry:
- %not.tobool = icmp ne i32 %c, 0
- %add = zext i1 %not.tobool to i32
- %b.add = add i32 %c, %b
- %add1 = add i32 %b.add, %add
- ret i32 %add1
-}
-
-; CHECK-LABEL: foo2
-; CHECK: cneg w{{[0-9]+}}, w{{[0-9]+}}, ne
-define i32 @foo2(i32 %b, i32 %c) nounwind readnone ssp {
-entry:
- %mul = sub i32 0, %b
- %tobool = icmp eq i32 %c, 0
- %b.mul = select i1 %tobool, i32 %b, i32 %mul
- %add = add nsw i32 %b.mul, %c
- ret i32 %add
-}
-
-; CHECK-LABEL: foo3
-; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
-define i32 @foo3(i32 %b, i32 %c) nounwind readnone ssp {
-entry:
- %not.tobool = icmp ne i32 %c, 0
- %xor = sext i1 %not.tobool to i32
- %b.xor = xor i32 %xor, %b
- %add = add nsw i32 %b.xor, %c
- ret i32 %add
-}
-
-; rdar://11632325
-define i32 at foo4(i32 %a) nounwind ssp {
-; CHECK-LABEL: foo4
-; CHECK: cneg
-; CHECK-NEXT: ret
- %cmp = icmp sgt i32 %a, -1
- %neg = sub nsw i32 0, %a
- %cond = select i1 %cmp, i32 %a, i32 %neg
- ret i32 %cond
-}
-
-define i32 at foo5(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK-LABEL: foo5
-; CHECK: subs
-; CHECK-NEXT: cneg
-; CHECK-NEXT: ret
- %sub = sub nsw i32 %a, %b
- %cmp = icmp sgt i32 %sub, -1
- %sub3 = sub nsw i32 0, %sub
- %cond = select i1 %cmp, i32 %sub, i32 %sub3
- ret i32 %cond
-}
-
-; make sure we can handle branch instruction in optimizeCompare.
-define i32 at foo6(i32 %a, i32 %b) nounwind ssp {
-; CHECK-LABEL: foo6
-; CHECK: b
- %sub = sub nsw i32 %a, %b
- %cmp = icmp sgt i32 %sub, 0
- br i1 %cmp, label %l.if, label %l.else
-
-l.if:
- ret i32 1
-
-l.else:
- ret i32 %sub
-}
-
-; If CPSR is used multiple times and V flag is used, we don't remove cmp.
-define i32 @foo7(i32 %a, i32 %b) nounwind {
-entry:
-; CHECK-LABEL: foo7:
-; CHECK: sub
-; CHECK-next: adds
-; CHECK-next: csneg
-; CHECK-next: b
- %sub = sub nsw i32 %a, %b
- %cmp = icmp sgt i32 %sub, -1
- %sub3 = sub nsw i32 0, %sub
- %cond = select i1 %cmp, i32 %sub, i32 %sub3
- br i1 %cmp, label %if.then, label %if.else
-
-if.then:
- %cmp2 = icmp slt i32 %sub, -1
- %sel = select i1 %cmp2, i32 %cond, i32 %a
- ret i32 %sel
-
-if.else:
- ret i32 %cond
-}
-
-define i32 @foo8(i32 %v, i32 %a, i32 %b) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: foo8:
-; CHECK: cmp w0, #0
-; CHECK: csinv w0, w1, w2, ne
- %tobool = icmp eq i32 %v, 0
- %neg = xor i32 -1, %b
- %cond = select i1 %tobool, i32 %neg, i32 %a
- ret i32 %cond
-}
-
-define i32 @foo9(i32 %v) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo9:
-; CHECK: cmp w0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: cinv w0, w[[REG]], eq
- %tobool = icmp ne i32 %v, 0
- %cond = select i1 %tobool, i32 4, i32 -5
- ret i32 %cond
-}
-
-define i64 @foo10(i64 %v) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo10:
-; CHECK: cmp x0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: cinv x0, x[[REG]], eq
- %tobool = icmp ne i64 %v, 0
- %cond = select i1 %tobool, i64 4, i64 -5
- ret i64 %cond
-}
-
-define i32 @foo11(i32 %v) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo11:
-; CHECK: cmp w0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: cneg w0, w[[REG]], eq
- %tobool = icmp ne i32 %v, 0
- %cond = select i1 %tobool, i32 4, i32 -4
- ret i32 %cond
-}
-
-define i64 @foo12(i64 %v) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo12:
-; CHECK: cmp x0, #0
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
-; CHECK: cneg x0, x[[REG]], eq
- %tobool = icmp ne i64 %v, 0
- %cond = select i1 %tobool, i64 4, i64 -4
- ret i64 %cond
-}
-
-define i32 @foo13(i32 %v, i32 %a, i32 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo13:
-; CHECK: cmp w0, #0
-; CHECK: csneg w0, w1, w2, ne
- %tobool = icmp eq i32 %v, 0
- %sub = sub i32 0, %b
- %cond = select i1 %tobool, i32 %sub, i32 %a
- ret i32 %cond
-}
-
-define i64 @foo14(i64 %v, i64 %a, i64 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo14:
-; CHECK: cmp x0, #0
-; CHECK: csneg x0, x1, x2, ne
- %tobool = icmp eq i64 %v, 0
- %sub = sub i64 0, %b
- %cond = select i1 %tobool, i64 %sub, i64 %a
- ret i64 %cond
-}
-
-define i32 @foo15(i32 %a, i32 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo15:
-; CHECK: cmp w0, w1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: cinc w0, w[[REG]], gt
- %cmp = icmp sgt i32 %a, %b
- %. = select i1 %cmp, i32 2, i32 1
- ret i32 %.
-}
-
-define i32 @foo16(i32 %a, i32 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo16:
-; CHECK: cmp w0, w1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: cinc w0, w[[REG]], le
- %cmp = icmp sgt i32 %a, %b
- %. = select i1 %cmp, i32 1, i32 2
- ret i32 %.
-}
-
-define i64 @foo17(i64 %a, i64 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo17:
-; CHECK: cmp x0, x1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: cinc x0, x[[REG]], gt
- %cmp = icmp sgt i64 %a, %b
- %. = select i1 %cmp, i64 2, i64 1
- ret i64 %.
-}
-
-define i64 @foo18(i64 %a, i64 %b) nounwind readnone optsize ssp {
-entry:
-; CHECK-LABEL: foo18:
-; CHECK: cmp x0, x1
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
-; CHECK: cinc x0, x[[REG]], le
- %cmp = icmp sgt i64 %a, %b
- %. = select i1 %cmp, i64 1, i64 2
- ret i64 %.
-}
-
-define i64 @foo19(i64 %a, i64 %b, i64 %c) {
-entry:
-; CHECK-LABEL: foo19:
-; CHECK: cinc x0, x2
-; CHECK-NOT: add
- %cmp = icmp ult i64 %a, %b
- %inc = zext i1 %cmp to i64
- %inc.c = add i64 %inc, %c
- ret i64 %inc.c
-}
Removed: llvm/trunk/test/CodeGen/ARM64/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/cvt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/cvt.ll (removed)
@@ -1,401 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-;
-; Floating-point scalar convert to signed integer (to nearest with ties to away)
-;
-define i32 @fcvtas_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtas_1w1s:
-;CHECK: fcvtas w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtas_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtas_1x1s:
-;CHECK: fcvtas x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtas_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtas_1w1d:
-;CHECK: fcvtas w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtas.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtas_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtas_1x1d:
-;CHECK: fcvtas x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtas.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtas.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtas.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtas.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtas.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to unsigned integer
-;
-define i32 @fcvtau_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtau_1w1s:
-;CHECK: fcvtau w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtau_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtau_1x1s:
-;CHECK: fcvtau x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtau_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtau_1w1d:
-;CHECK: fcvtau w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtau.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtau_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtau_1x1d:
-;CHECK: fcvtau x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtau.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtau.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtau.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtau.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtau.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to signed integer (toward -Inf)
-;
-define i32 @fcvtms_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtms_1w1s:
-;CHECK: fcvtms w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtms_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtms_1x1s:
-;CHECK: fcvtms x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtms_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtms_1w1d:
-;CHECK: fcvtms w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtms.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtms_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtms_1x1d:
-;CHECK: fcvtms x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtms.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtms.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtms.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtms.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtms.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to unsigned integer (toward -Inf)
-;
-define i32 @fcvtmu_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtmu_1w1s:
-;CHECK: fcvtmu w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtmu_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtmu_1x1s:
-;CHECK: fcvtmu x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtmu_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtmu_1w1d:
-;CHECK: fcvtmu w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtmu.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtmu_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtmu_1x1d:
-;CHECK: fcvtmu x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtmu.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtmu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtmu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtmu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtmu.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to signed integer (to nearest with ties to even)
-;
-define i32 @fcvtns_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtns_1w1s:
-;CHECK: fcvtns w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtns_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtns_1x1s:
-;CHECK: fcvtns x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtns_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtns_1w1d:
-;CHECK: fcvtns w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtns.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtns_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtns_1x1d:
-;CHECK: fcvtns x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtns.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtns.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtns.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtns.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtns.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to unsigned integer (to nearest with ties to even)
-;
-define i32 @fcvtnu_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtnu_1w1s:
-;CHECK: fcvtnu w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtnu_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtnu_1x1s:
-;CHECK: fcvtnu x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtnu_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtnu_1w1d:
-;CHECK: fcvtnu w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtnu.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtnu_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtnu_1x1d:
-;CHECK: fcvtnu x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtnu.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtnu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtnu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtnu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtnu.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to signed integer (toward +Inf)
-;
-define i32 @fcvtps_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtps_1w1s:
-;CHECK: fcvtps w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtps_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtps_1x1s:
-;CHECK: fcvtps x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtps_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtps_1w1d:
-;CHECK: fcvtps w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtps.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtps_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtps_1x1d:
-;CHECK: fcvtps x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtps.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtps.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtps.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtps.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtps.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to unsigned integer (toward +Inf)
-;
-define i32 @fcvtpu_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtpu_1w1s:
-;CHECK: fcvtpu w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtpu_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtpu_1x1s:
-;CHECK: fcvtpu x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtpu_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtpu_1w1d:
-;CHECK: fcvtpu w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtpu.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtpu_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtpu_1x1d:
-;CHECK: fcvtpu x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtpu.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtpu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtpu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtpu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtpu.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to signed integer (toward zero)
-;
-define i32 @fcvtzs_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtzs_1w1s:
-;CHECK: fcvtzs w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtzs_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtzs_1x1s:
-;CHECK: fcvtzs x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtzs_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtzs_1w1d:
-;CHECK: fcvtzs w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzs.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtzs_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtzs_1x1d:
-;CHECK: fcvtzs x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzs.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtzs.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzs.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtzs.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzs.i64.f64(double) nounwind readnone
-
-;
-; Floating-point scalar convert to unsigned integer (toward zero)
-;
-define i32 @fcvtzu_1w1s(float %A) nounwind {
-;CHECK-LABEL: fcvtzu_1w1s:
-;CHECK: fcvtzu w0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f32(float %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtzu_1x1s(float %A) nounwind {
-;CHECK-LABEL: fcvtzu_1x1s:
-;CHECK: fcvtzu x0, s0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f32(float %A)
- ret i64 %tmp3
-}
-
-define i32 @fcvtzu_1w1d(double %A) nounwind {
-;CHECK-LABEL: fcvtzu_1w1d:
-;CHECK: fcvtzu w0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i32 @llvm.arm64.neon.fcvtzu.i32.f64(double %A)
- ret i32 %tmp3
-}
-
-define i64 @fcvtzu_1x1d(double %A) nounwind {
-;CHECK-LABEL: fcvtzu_1x1d:
-;CHECK: fcvtzu x0, d0
-;CHECK-NEXT: ret
- %tmp3 = call i64 @llvm.arm64.neon.fcvtzu.i64.f64(double %A)
- ret i64 %tmp3
-}
-
-declare i32 @llvm.arm64.neon.fcvtzu.i32.f32(float) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzu.i64.f32(float) nounwind readnone
-declare i32 @llvm.arm64.neon.fcvtzu.i32.f64(double) nounwind readnone
-declare i64 @llvm.arm64.neon.fcvtzu.i64.f64(double) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dagcombiner-convergence.ll (removed)
@@ -1,19 +0,0 @@
-; RUN: llc < %s -o /dev/null
-; rdar://10795250
-; DAGCombiner should converge.
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
-target triple = "arm64-apple-macosx10.8.0"
-
-define i64 @foo(i128 %Params.coerce, i128 %SelLocs.coerce) {
-entry:
- %tmp = lshr i128 %Params.coerce, 61
- %.tr38.i = trunc i128 %tmp to i64
- %mul.i = and i64 %.tr38.i, 4294967288
- %tmp1 = lshr i128 %SelLocs.coerce, 62
- %.tr.i = trunc i128 %tmp1 to i64
- %mul7.i = and i64 %.tr.i, 4294967292
- %add.i = add i64 %mul7.i, %mul.i
- %conv.i.i = and i64 %add.i, 4294967292
- ret i64 %conv.i.i
-}
Removed: llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dagcombiner-dead-indexed-load.ll (removed)
@@ -1,29 +0,0 @@
-; RUN: llc -mcpu=cyclone < %s | FileCheck %s
-
-target datalayout = "e-i64:64-n32:64-S128"
-target triple = "arm64-apple-ios"
-
-%"struct.SU" = type { i32, %"struct.SU"*, i32*, i32, i32, %"struct.BO", i32, [5 x i8] }
-%"struct.BO" = type { %"struct.RE" }
-
-%"struct.RE" = type { i32, i32, i32, i32 }
-
-; This is a read-modify-write of some bifields combined into an i48. It gets
-; legalized into i32 and i16 accesses. Only a single store of zero to the low
-; i32 part should be live.
-
-; CHECK-LABEL: test:
-; CHECK-NOT: ldr
-; CHECK: str wzr
-; CHECK-NOT: str
-define void @test(%"struct.SU"* nocapture %su) {
-entry:
- %r1 = getelementptr inbounds %"struct.SU"* %su, i64 1, i32 5
- %r2 = bitcast %"struct.BO"* %r1 to i48*
- %r3 = load i48* %r2, align 8
- %r4 = and i48 %r3, -4294967296
- %r5 = or i48 0, %r4
- store i48 %r5, i48* %r2, align 8
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dagcombiner-indexed-load.ll (removed)
@@ -1,46 +0,0 @@
-; RUN: llc -O3 < %s | FileCheck %s
-; RUN: llc -O3 -addr-sink-using-gep=1 < %s | FileCheck %s
-; Test case for a DAG combiner bug where we combined an indexed load
-; with an extension (sext, zext, or any) into a regular extended load,
-; i.e., dropping the indexed value.
-; <rdar://problem/16389332>
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios"
-
-%class.A = type { i64, i64 }
-%class.C = type { i64 }
-
-; CHECK-LABEL: XX:
-; CHECK: ldr
-define void @XX(%class.A* %K) {
-entry:
- br i1 undef, label %if.then, label %lor.rhs.i
-
-lor.rhs.i: ; preds = %entry
- %tmp = load i32* undef, align 4
- %y.i.i.i = getelementptr inbounds %class.A* %K, i64 0, i32 1
- %tmp1 = load i64* %y.i.i.i, align 8
- %U.sroa.3.8.extract.trunc.i = trunc i64 %tmp1 to i32
- %div11.i = sdiv i32 %U.sroa.3.8.extract.trunc.i, 17
- %add12.i = add nsw i32 0, %div11.i
- %U.sroa.3.12.extract.shift.i = lshr i64 %tmp1, 32
- %U.sroa.3.12.extract.trunc.i = trunc i64 %U.sroa.3.12.extract.shift.i to i32
- %div15.i = sdiv i32 %U.sroa.3.12.extract.trunc.i, 13
- %add16.i = add nsw i32 %add12.i, %div15.i
- %rem.i.i = srem i32 %add16.i, %tmp
- %idxprom = sext i32 %rem.i.i to i64
- %arrayidx = getelementptr inbounds %class.C** undef, i64 %idxprom
- %tobool533 = icmp eq %class.C* undef, null
- br i1 %tobool533, label %while.end, label %while.body
-
-if.then: ; preds = %entry
- unreachable
-
-while.body: ; preds = %lor.rhs.i
- unreachable
-
-while.end: ; preds = %lor.rhs.i
- %tmp3 = load %class.C** %arrayidx, align 8
- unreachable
-}
Removed: llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dagcombiner-load-slicing.ll (removed)
@@ -1,102 +0,0 @@
-; RUN: llc -mtriple arm64-apple-ios -O3 -o - < %s | FileCheck %s
-; <rdar://problem/14477220>
-
-%class.Complex = type { float, float }
-%class.Complex_int = type { i32, i32 }
-%class.Complex_long = type { i64, i64 }
-
-; CHECK-LABEL: @test
-; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3
-; CHECK: ldp [[CPLX1_I:s[0-9]+]], [[CPLX1_R:s[0-9]+]], {{\[}}[[BASE]]]
-; CHECK: ldp [[CPLX2_I:s[0-9]+]], [[CPLX2_R:s[0-9]+]], {{\[}}[[BASE]], #64]
-; CHECK: fadd {{s[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
-; CHECK: fadd {{s[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
-; CHECK: ret
-define void @test(%class.Complex* nocapture %out, i64 %out_start) {
-entry:
- %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start
- %0 = bitcast %class.Complex* %arrayidx to i64*
- %1 = load i64* %0, align 4
- %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
- %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float
- %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
- %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
- %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float
- %add = add i64 %out_start, 8
- %arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add
- %i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0
- %4 = load float* %i.i, align 4
- %add.i = fadd float %4, %2
- %retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0
- %r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1
- %5 = load float* %r.i, align 4
- %add5.i = fadd float %5, %3
- %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1
- %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>*
- store <2 x float> %retval.sroa.0.4.vec.insert.i, <2 x float>* %ref.tmp.sroa.0.0.cast, align 4
- ret void
-}
-
-; CHECK-LABEL: @test_int
-; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #3
-; CHECK: ldp [[CPLX1_I:w[0-9]+]], [[CPLX1_R:w[0-9]+]], {{\[}}[[BASE]]]
-; CHECK: ldp [[CPLX2_I:w[0-9]+]], [[CPLX2_R:w[0-9]+]], {{\[}}[[BASE]], #64]
-; CHECK: add {{w[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
-; CHECK: add {{w[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
-; CHECK: ret
-define void @test_int(%class.Complex_int* nocapture %out, i64 %out_start) {
-entry:
- %arrayidx = getelementptr inbounds %class.Complex_int* %out, i64 %out_start
- %0 = bitcast %class.Complex_int* %arrayidx to i64*
- %1 = load i64* %0, align 4
- %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32
- %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to i32
- %t0.sroa.2.0.extract.shift = lshr i64 %1, 32
- %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32
- %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to i32
- %add = add i64 %out_start, 8
- %arrayidx2 = getelementptr inbounds %class.Complex_int* %out, i64 %add
- %i.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 0
- %4 = load i32* %i.i, align 4
- %add.i = add i32 %4, %2
- %retval.sroa.0.0.vec.insert.i = insertelement <2 x i32> undef, i32 %add.i, i32 0
- %r.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 1
- %5 = load i32* %r.i, align 4
- %add5.i = add i32 %5, %3
- %retval.sroa.0.4.vec.insert.i = insertelement <2 x i32> %retval.sroa.0.0.vec.insert.i, i32 %add5.i, i32 1
- %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_int* %arrayidx to <2 x i32>*
- store <2 x i32> %retval.sroa.0.4.vec.insert.i, <2 x i32>* %ref.tmp.sroa.0.0.cast, align 4
- ret void
-}
-
-; CHECK-LABEL: @test_long
-; CHECK: add [[BASE:x[0-9]+]], x0, x1, lsl #4
-; CHECK: ldp [[CPLX1_I:x[0-9]+]], [[CPLX1_R:x[0-9]+]], {{\[}}[[BASE]]]
-; CHECK: ldp [[CPLX2_I:x[0-9]+]], [[CPLX2_R:x[0-9]+]], {{\[}}[[BASE]], #128]
-; CHECK: add {{x[0-9]+}}, [[CPLX2_I]], [[CPLX1_I]]
-; CHECK: add {{x[0-9]+}}, [[CPLX2_R]], [[CPLX1_R]]
-; CHECK: ret
-define void @test_long(%class.Complex_long* nocapture %out, i64 %out_start) {
-entry:
- %arrayidx = getelementptr inbounds %class.Complex_long* %out, i64 %out_start
- %0 = bitcast %class.Complex_long* %arrayidx to i128*
- %1 = load i128* %0, align 4
- %t0.sroa.0.0.extract.trunc = trunc i128 %1 to i64
- %2 = bitcast i64 %t0.sroa.0.0.extract.trunc to i64
- %t0.sroa.2.0.extract.shift = lshr i128 %1, 64
- %t0.sroa.2.0.extract.trunc = trunc i128 %t0.sroa.2.0.extract.shift to i64
- %3 = bitcast i64 %t0.sroa.2.0.extract.trunc to i64
- %add = add i64 %out_start, 8
- %arrayidx2 = getelementptr inbounds %class.Complex_long* %out, i64 %add
- %i.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 0
- %4 = load i64* %i.i, align 4
- %add.i = add i64 %4, %2
- %retval.sroa.0.0.vec.insert.i = insertelement <2 x i64> undef, i64 %add.i, i32 0
- %r.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 1
- %5 = load i64* %r.i, align 4
- %add5.i = add i64 %5, %3
- %retval.sroa.0.4.vec.insert.i = insertelement <2 x i64> %retval.sroa.0.0.vec.insert.i, i64 %add5.i, i32 1
- %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_long* %arrayidx to <2 x i64>*
- store <2 x i64> %retval.sroa.0.4.vec.insert.i, <2 x i64>* %ref.tmp.sroa.0.0.cast, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dead-def-frame-index.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -march=arm64 < %s | FileCheck %s
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios7.0.0"
-
-; Function Attrs: nounwind ssp uwtable
-define i32 @test1() #0 {
- %tmp1 = alloca i8
- %tmp2 = alloca i32, i32 4096
- %tmp3 = icmp eq i8* %tmp1, null
- %tmp4 = zext i1 %tmp3 to i32
-
- ret i32 %tmp4
-
- ; CHECK-LABEL: test1
- ; CHECK: adds [[TEMP:[a-z0-9]+]], sp, #4, lsl #12
- ; CHECK: adds [[TEMP]], [[TEMP]], #15
-}
Removed: llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dead-register-def-bug.ll (removed)
@@ -1,32 +0,0 @@
-; RUN: llc -mtriple="arm64-apple-ios" < %s | FileCheck %s
-;
-; Check that the dead register definition pass is considering implicit defs.
-; When rematerializing through truncates, the coalescer may produce instructions
-; with dead defs, but live implicit-defs of subregs:
-; E.g. %X1<def, dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32
-; These instructions are live, and their definitions should not be rewritten.
-;
-; <rdar://problem/16492408>
-
-define void @testcase() {
-; CHECK: testcase:
-; CHECK-NOT: orr xzr, xzr, #0x2
-
-bb1:
- %tmp1 = tail call float @ceilf(float 2.000000e+00)
- %tmp2 = fptoui float %tmp1 to i64
- br i1 undef, label %bb2, label %bb3
-
-bb2:
- tail call void @foo()
- br label %bb3
-
-bb3:
- %tmp3 = trunc i64 %tmp2 to i32
- tail call void @bar(i32 %tmp3)
- ret void
-}
-
-declare void @foo()
-declare void @bar(i32)
-declare float @ceilf(float) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/dup.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/dup.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/dup.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/dup.ll (removed)
@@ -1,323 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
-
-define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK-LABEL: v_dup8:
-;CHECK: dup.8b
- %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
- %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
- %tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
- %tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
- %tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4
- %tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5
- %tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6
- %tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7
- ret <8 x i8> %tmp8
-}
-
-define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK-LABEL: v_dup16:
-;CHECK: dup.4h
- %tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
- %tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
- %tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
- %tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3
- ret <4 x i16> %tmp4
-}
-
-define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK-LABEL: v_dup32:
-;CHECK: dup.2s
- %tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
- %tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
- ret <2 x i32> %tmp2
-}
-
-define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK-LABEL: v_dupfloat:
-;CHECK: dup.2s
- %tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
- %tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
- ret <2 x float> %tmp2
-}
-
-define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK-LABEL: v_dupQ8:
-;CHECK: dup.16b
- %tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
- %tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
- %tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
- %tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3
- %tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4
- %tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5
- %tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6
- %tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7
- %tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8
- %tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9
- %tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10
- %tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11
- %tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12
- %tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13
- %tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14
- %tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15
- ret <16 x i8> %tmp16
-}
-
-define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK-LABEL: v_dupQ16:
-;CHECK: dup.8h
- %tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
- %tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
- %tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
- %tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3
- %tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4
- %tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5
- %tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6
- %tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7
- ret <8 x i16> %tmp8
-}
-
-define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK-LABEL: v_dupQ32:
-;CHECK: dup.4s
- %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
- %tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
- %tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
- %tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3
- ret <4 x i32> %tmp4
-}
-
-define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK-LABEL: v_dupQfloat:
-;CHECK: dup.4s
- %tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
- %tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
- %tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
- %tmp4 = insertelement <4 x float> %tmp3, float %A, i32 3
- ret <4 x float> %tmp4
-}
-
-; Check to make sure it works with shuffles, too.
-
-define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK-LABEL: v_shuffledup8:
-;CHECK: dup.8b
- %tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
- ret <8 x i8> %tmp2
-}
-
-define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK-LABEL: v_shuffledup16:
-;CHECK: dup.4h
- %tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
- %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
- ret <4 x i16> %tmp2
-}
-
-define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK-LABEL: v_shuffledup32:
-;CHECK: dup.2s
- %tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
- %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
- ret <2 x i32> %tmp2
-}
-
-define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK-LABEL: v_shuffledupfloat:
-;CHECK: dup.2s
- %tmp1 = insertelement <2 x float> undef, float %A, i32 0
- %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
- ret <2 x float> %tmp2
-}
-
-define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK-LABEL: v_shuffledupQ8:
-;CHECK: dup.16b
- %tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
- %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
- ret <16 x i8> %tmp2
-}
-
-define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK-LABEL: v_shuffledupQ16:
-;CHECK: dup.8h
- %tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
- %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
- ret <8 x i16> %tmp2
-}
-
-define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK-LABEL: v_shuffledupQ32:
-;CHECK: dup.4s
- %tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
- %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
- ret <4 x i32> %tmp2
-}
-
-define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK-LABEL: v_shuffledupQfloat:
-;CHECK: dup.4s
- %tmp1 = insertelement <4 x float> undef, float %A, i32 0
- %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
- ret <4 x float> %tmp2
-}
-
-define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vduplane8:
-;CHECK: dup.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
- ret <8 x i8> %tmp2
-}
-
-define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: vduplane16:
-;CHECK: dup.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
- ret <4 x i16> %tmp2
-}
-
-define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: vduplane32:
-;CHECK: dup.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
- ret <2 x i32> %tmp2
-}
-
-define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK-LABEL: vduplanefloat:
-;CHECK: dup.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
- ret <2 x float> %tmp2
-}
-
-define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: vduplaneQ8:
-;CHECK: dup.16b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
- ret <16 x i8> %tmp2
-}
-
-define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: vduplaneQ16:
-;CHECK: dup.8h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
- ret <8 x i16> %tmp2
-}
-
-define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: vduplaneQ32:
-;CHECK: dup.4s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
- ret <4 x i32> %tmp2
-}
-
-define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK-LABEL: vduplaneQfloat:
-;CHECK: dup.4s
- %tmp1 = load <2 x float>* %A
- %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
- ret <4 x float> %tmp2
-}
-
-define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
-;CHECK-LABEL: foo:
-;CHECK: dup.2d
-entry:
- %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
- ret <2 x i64> %0
-}
-
-define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
-;CHECK-LABEL: bar:
-;CHECK: dup.2d
-entry:
- %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
- ret <2 x i64> %0
-}
-
-define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
-;CHECK-LABEL: baz:
-;CHECK: dup.2d
-entry:
- %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
- ret <2 x double> %0
-}
-
-define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
-;CHECK-LABEL: qux:
-;CHECK: dup.2d
-entry:
- %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
- ret <2 x double> %0
-}
-
-define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {
-; CHECK-LABEL: f:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ins.s v0[1], w1
-; CHECK-NEXT: ret
- %vecinit = insertelement <2 x i32> undef, i32 %a, i32 0
- %vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1
- ret <2 x i32> %vecinit1
-}
-
-define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {
-; CHECK-LABEL: g:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: ins.s v0[1], w1
-; CHECK-NEXT: ins.s v0[2], w1
-; CHECK-NEXT: ins.s v0[3], w0
-; CHECK-NEXT: ret
- %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
- %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
- %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
- %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %a, i32 3
- ret <4 x i32> %vecinit3
-}
-
-define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {
-; CHECK-LABEL: h:
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ins.d v0[1], x1
-; CHECK-NEXT: ret
- %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
- %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
- ret <2 x i64> %vecinit1
-}
-
-; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
-; the single value needed was of the same type as the vector. This is false if
-; the scalar corresponding to the vector type is illegal (e.g. a <4 x i16>
-; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
-; not a simple "dup vD.4h, vN.h[idx]" after all, and we crashed.
-;
-; *However*, it is a dup vD.4h, vN.h[2*idx].
-define <4 x i16> @test_build_illegal(<4 x i32> %in) {
-; CHECK-LABEL: test_build_illegal:
-; CHECK: dup.4h v0, v0[6]
- %val = extractelement <4 x i32> %in, i32 3
- %smallval = trunc i32 %val to i16
- %vec = insertelement <4x i16> undef, i16 %smallval, i32 3
-
- ret <4 x i16> %vec
-}
-
-; We used to inherit an already extract_subvectored v4i16 from
-; SelectionDAGBuilder here. We then added a DUPLANE on top of that, preventing
-; the formation of an indexed-by-7 MLS.
-define <4 x i16> @test_high_splat(<4 x i16> %a, <4 x i16> %b, <8 x i16> %v) #0 {
-; CHECK-LABEL: test_high_splat:
-; CHECK: mls.4h v0, v1, v2[7]
-entry:
- %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
- %mul = mul <4 x i16> %shuffle, %b
- %sub = sub <4 x i16> %a, %mul
- ret <4 x i16> %sub
-}
Removed: llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/early-ifcvt.ll (removed)
@@ -1,423 +0,0 @@
-; RUN: llc < %s -stress-early-ifcvt | FileCheck %s
-target triple = "arm64-apple-macosx"
-
-; CHECK: mm2
-define i32 @mm2(i32* nocapture %p, i32 %n) nounwind uwtable readonly ssp {
-entry:
- br label %do.body
-
-; CHECK: do.body
-; Loop body has no branches before the backedge.
-; CHECK-NOT: LBB
-do.body:
- %max.0 = phi i32 [ 0, %entry ], [ %max.1, %do.cond ]
- %min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ]
- %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ]
- %p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ]
- %incdec.ptr = getelementptr inbounds i32* %p.addr.0, i64 1
- %0 = load i32* %p.addr.0, align 4
- %cmp = icmp sgt i32 %0, %max.0
- br i1 %cmp, label %do.cond, label %if.else
-
-if.else:
- %cmp1 = icmp slt i32 %0, %min.0
- %.min.0 = select i1 %cmp1, i32 %0, i32 %min.0
- br label %do.cond
-
-do.cond:
- %max.1 = phi i32 [ %0, %do.body ], [ %max.0, %if.else ]
- %min.1 = phi i32 [ %min.0, %do.body ], [ %.min.0, %if.else ]
-; CHECK: cbnz
- %dec = add i32 %n.addr.0, -1
- %tobool = icmp eq i32 %dec, 0
- br i1 %tobool, label %do.end, label %do.body
-
-do.end:
- %sub = sub nsw i32 %max.1, %min.1
- ret i32 %sub
-}
-
-; CHECK-LABEL: fold_inc_true_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csinc w0, w1, w0, eq
-; CHECK-NEXT: ret
-define i32 @fold_inc_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %inc = add nsw i32 %x, 1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %y, %eq_bb ], [ %inc, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_inc_true_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csinc x0, x1, x0, eq
-; CHECK-NEXT: ret
-define i64 @fold_inc_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %inc = add nsw i64 %x, 1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %y, %eq_bb ], [ %inc, %entry ]
- ret i64 %cond
-}
-
-; CHECK-LABEL: fold_inc_false_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csinc w0, w1, w0, ne
-; CHECK-NEXT: ret
-define i32 @fold_inc_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %inc = add nsw i32 %x, 1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %inc, %eq_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_inc_false_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csinc x0, x1, x0, ne
-; CHECK-NEXT: ret
-define i64 @fold_inc_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %inc = add nsw i64 %x, 1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %inc, %eq_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK-LABEL: fold_inv_true_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csinv w0, w1, w0, eq
-; CHECK-NEXT: ret
-define i32 @fold_inv_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %inv = xor i32 %x, -1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %y, %eq_bb ], [ %inv, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_inv_true_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csinv x0, x1, x0, eq
-; CHECK-NEXT: ret
-define i64 @fold_inv_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %inv = xor i64 %x, -1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %y, %eq_bb ], [ %inv, %entry ]
- ret i64 %cond
-}
-
-; CHECK-LABEL: fold_inv_false_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csinv w0, w1, w0, ne
-; CHECK-NEXT: ret
-define i32 @fold_inv_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %inv = xor i32 %x, -1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %inv, %eq_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_inv_false_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csinv x0, x1, x0, ne
-; CHECK-NEXT: ret
-define i64 @fold_inv_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %inv = xor i64 %x, -1
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %inv, %eq_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK-LABEL: fold_neg_true_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csneg w0, w1, w0, eq
-; CHECK-NEXT: ret
-define i32 @fold_neg_true_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %neg = sub nsw i32 0, %x
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %y, %eq_bb ], [ %neg, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_neg_true_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csneg x0, x1, x0, eq
-; CHECK-NEXT: ret
-define i64 @fold_neg_true_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %neg = sub nsw i64 0, %x
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %y, %eq_bb ], [ %neg, %entry ]
- ret i64 %cond
-}
-
-; CHECK-LABEL: fold_neg_false_32:
-; CHECK: {{subs.*wzr,|cmp}} w2, #1
-; CHECK-NEXT: csneg w0, w1, w0, ne
-; CHECK-NEXT: ret
-define i32 @fold_neg_false_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 1
- %neg = sub nsw i32 0, %x
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %neg, %eq_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK-LABEL: fold_neg_false_64:
-; CHECK: {{subs.*xzr,|cmp}} x2, #1
-; CHECK-NEXT: csneg x0, x1, x0, ne
-; CHECK-NEXT: ret
-define i64 @fold_neg_false_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 1
- %neg = sub nsw i64 0, %x
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %neg, %eq_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK: cbnz_32
-; CHECK: {{subs.*wzr,|cmp}} w2, #0
-; CHECK-NEXT: csel w0, w1, w0, ne
-; CHECK-NEXT: ret
-define i32 @cbnz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i32 %c, 0
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %x, %eq_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK: cbnz_64
-; CHECK: {{subs.*xzr,|cmp}} x2, #0
-; CHECK-NEXT: csel x0, x1, x0, ne
-; CHECK-NEXT: ret
-define i64 @cbnz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp eq i64 %c, 0
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %x, %eq_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK: cbz_32
-; CHECK: {{subs.*wzr,|cmp}} w2, #0
-; CHECK-NEXT: csel w0, w1, w0, eq
-; CHECK-NEXT: ret
-define i32 @cbz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %tobool = icmp ne i32 %c, 0
- br i1 %tobool, label %ne_bb, label %done
-
-ne_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %x, %ne_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK: cbz_64
-; CHECK: {{subs.*xzr,|cmp}} x2, #0
-; CHECK-NEXT: csel x0, x1, x0, eq
-; CHECK-NEXT: ret
-define i64 @cbz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %tobool = icmp ne i64 %c, 0
- br i1 %tobool, label %ne_bb, label %done
-
-ne_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %x, %ne_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK: tbnz_32
-; CHECK: {{ands.*xzr,|tst}} w2, #0x80
-; CHECK-NEXT: csel w0, w1, w0, ne
-; CHECK-NEXT: ret
-define i32 @tbnz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %mask = and i32 %c, 128
- %tobool = icmp eq i32 %mask, 0
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %x, %eq_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK: tbnz_64
-; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
-; CHECK-NEXT: csel x0, x1, x0, ne
-; CHECK-NEXT: ret
-define i64 @tbnz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %mask = and i64 %c, 9223372036854775808
- %tobool = icmp eq i64 %mask, 0
- br i1 %tobool, label %eq_bb, label %done
-
-eq_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %x, %eq_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; CHECK: tbz_32
-; CHECK: {{ands.*xzr,|tst}} w2, #0x80
-; CHECK-NEXT: csel w0, w1, w0, eq
-; CHECK-NEXT: ret
-define i32 @tbz_32(i32 %x, i32 %y, i32 %c) nounwind ssp {
-entry:
- %mask = and i32 %c, 128
- %tobool = icmp ne i32 %mask, 0
- br i1 %tobool, label %ne_bb, label %done
-
-ne_bb:
- br label %done
-
-done:
- %cond = phi i32 [ %x, %ne_bb ], [ %y, %entry ]
- ret i32 %cond
-}
-
-; CHECK: tbz_64
-; CHECK: {{ands.*xzr,|tst}} x2, #0x8000000000000000
-; CHECK-NEXT: csel x0, x1, x0, eq
-; CHECK-NEXT: ret
-define i64 @tbz_64(i64 %x, i64 %y, i64 %c) nounwind ssp {
-entry:
- %mask = and i64 %c, 9223372036854775808
- %tobool = icmp ne i64 %mask, 0
- br i1 %tobool, label %ne_bb, label %done
-
-ne_bb:
- br label %done
-
-done:
- %cond = phi i64 [ %x, %ne_bb ], [ %y, %entry ]
- ret i64 %cond
-}
-
-; This function from 175.vpr folds an ADDWri into a CSINC.
-; Remember to clear the kill flag on the ADDWri.
-define i32 @get_ytrack_to_xtracks() nounwind ssp {
-entry:
- br label %for.body
-
-for.body:
- %x0 = load i32* undef, align 4
- br i1 undef, label %if.then.i146, label %is_sbox.exit155
-
-if.then.i146:
- %add8.i143 = add nsw i32 0, %x0
- %rem.i144 = srem i32 %add8.i143, %x0
- %add9.i145 = add i32 %rem.i144, 1
- br label %is_sbox.exit155
-
-is_sbox.exit155: ; preds = %if.then.i146, %for.body
- %seg_offset.0.i151 = phi i32 [ %add9.i145, %if.then.i146 ], [ undef, %for.body ]
- %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64
- %arrayidx18.i154 = getelementptr inbounds i32* null, i64 %idxprom15.i152
- %x1 = load i32* %arrayidx18.i154, align 4
- br i1 undef, label %for.body51, label %for.body
-
-for.body51: ; preds = %is_sbox.exit155
- call fastcc void @get_switch_type(i32 %x1, i32 undef, i16 signext undef, i16 signext undef, i16* undef)
- unreachable
-}
-declare fastcc void @get_switch_type(i32, i32, i16 signext, i16 signext, i16* nocapture) nounwind ssp
Removed: llvm/trunk/test/CodeGen/ARM64/elf-calls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/elf-calls.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/elf-calls.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/elf-calls.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
-
-declare void @callee()
-
-define void @caller() {
- call void @callee()
- ret void
-; CHECK-LABEL: caller:
-; CHECK: bl callee
-; CHECK-OBJ: R_AARCH64_CALL26 callee
-}
-
-define void @tail_caller() {
- tail call void @callee()
- ret void
-; CHECK-LABEL: tail_caller:
-; CHECK: b callee
-; CHECK-OBJ: R_AARCH64_JUMP26 callee
-}
Removed: llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/elf-constpool.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -O0 -o - %s | FileCheck %s
-
-; O0 checked for fastisel purposes. It has a separate path which
-; creates a constpool entry for floating values.
-
-define double @needs_const() {
- ret double 3.14159
-; CHECK: .LCPI0_0:
-
-; CHECK: adrp {{x[0-9]+}}, .LCPI0_0
-; CHECK: ldr d0, [{{x[0-9]+}}, :lo12:.LCPI0_0]
-}
Removed: llvm/trunk/test/CodeGen/ARM64/elf-globals.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/elf-globals.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/elf-globals.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/elf-globals.ll (removed)
@@ -1,115 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
-; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC
-; RUN: llc -mtriple=arm64-linux-gnu -O0 -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC
-
- at var8 = external global i8, align 1
- at var16 = external global i16, align 2
- at var32 = external global i32, align 4
- at var64 = external global i64, align 8
-
-define i8 @test_i8(i8 %new) {
- %val = load i8* @var8, align 1
- store i8 %new, i8* @var8
- ret i8 %val
-; CHECK-LABEL: test_i8:
-; CHECK: adrp x[[HIREG:[0-9]+]], var8
-; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
-; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
-
-; CHECK-PIC-LABEL: test_i8:
-; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
-; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
-; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]]
-
-; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8
-; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
-
-; CHECK-FAST-PIC: adrp x[[HIREG:[0-9]+]], :got:var8
-; CHECK-FAST-PIC: ldr x[[VARADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8]
-; CHECK-FAST-PIC: ldr {{w[0-9]+}}, [x[[VARADDR]]]
-}
-
-define i16 @test_i16(i16 %new) {
- %val = load i16* @var16, align 2
- store i16 %new, i16* @var16
- ret i16 %val
-; CHECK-LABEL: test_i16:
-; CHECK: adrp x[[HIREG:[0-9]+]], var16
-; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
-; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
-
-; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
-; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
-}
-
-define i32 @test_i32(i32 %new) {
- %val = load i32* @var32, align 4
- store i32 %new, i32* @var32
- ret i32 %val
-; CHECK-LABEL: test_i32:
-; CHECK: adrp x[[HIREG:[0-9]+]], var32
-; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
-; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
-
-; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32
-; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
-}
-
-define i64 @test_i64(i64 %new) {
- %val = load i64* @var64, align 8
- store i64 %new, i64* @var64
- ret i64 %val
-; CHECK-LABEL: test_i64:
-; CHECK: adrp x[[HIREG:[0-9]+]], var64
-; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
-; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
-
-; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64
-; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64
-}
-
-define i64* @test_addr() {
- ret i64* @var64
-; CHECK-LABEL: test_addr:
-; CHECK: adrp [[HIREG:x[0-9]+]], var64
-; CHECK: add x0, [[HIREG]], :lo12:var64
-
-; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64
-; CHECK-FAST: add x0, [[HIREG]], :lo12:var64
-}
-
- at hiddenvar = hidden global i32 0, align 4
- at protectedvar = protected global i32 0, align 4
-
-define i32 @test_vis() {
- %lhs = load i32* @hiddenvar, align 4
- %rhs = load i32* @protectedvar, align 4
- %ret = add i32 %lhs, %rhs
- ret i32 %ret
-; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar
-; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:hiddenvar]
-; CHECK-PIC: adrp {{x[0-9]+}}, protectedvar
-; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:protectedvar]
-}
-
- at var_default = external global [2 x i32]
-
-define i32 @test_default_align() {
- %addr = getelementptr [2 x i32]* @var_default, i32 0, i32 0
- %val = load i32* %addr
- ret i32 %val
-; CHECK-LABEL: test_default_align:
-; CHECK: adrp x[[HIREG:[0-9]+]], var_default
-; CHECK: ldr w0, [x[[HIREG]], :lo12:var_default]
-}
-
-define i64 @test_default_unaligned() {
- %addr = bitcast [2 x i32]* @var_default to i64*
- %val = load i64* %addr
- ret i64 %val
-; CHECK-LABEL: test_default_unaligned:
-; CHECK: adrp [[HIREG:x[0-9]+]], var_default
-; CHECK: add x[[ADDR:[0-9]+]], [[HIREG]], :lo12:var_default
-; CHECK: ldr x0, [x[[ADDR]]]
-}
Removed: llvm/trunk/test/CodeGen/ARM64/ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ext.ll (removed)
@@ -1,118 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextd:
-;CHECK: {{ext.8b.*#3}}
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
- ret <8 x i8> %tmp3
-}
-
-define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextRd:
-;CHECK: {{ext.8b.*#5}}
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextq:
-;CHECK: {{ext.16b.*3}}
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
- ret <16 x i8> %tmp3
-}
-
-define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextRq:
-;CHECK: {{ext.16b.*7}}
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: test_vextd16:
-;CHECK: {{ext.8b.*#6}}
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- ret <4 x i16> %tmp3
-}
-
-define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: test_vextq32:
-;CHECK: {{ext.16b.*12}}
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
- ret <4 x i32> %tmp3
-}
-
-; Undef shuffle indices should not prevent matching to VEXT:
-
-define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextd_undef:
-;CHECK: {{ext.8b.*}}
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
- ret <8 x i8> %tmp3
-}
-
-define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextd_undef2:
-;CHECK: {{ext.8b.*#6}}
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: test_vextRq_undef:
-;CHECK: {{ext.16b.*#7}}
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
- ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @test_vextRq_undef2(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vextRq_undef2:
-;CHECK: {{ext.16b.*#10}}
- %tmp1 = load <8 x i16>* %A
- %vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
- ret <8 x i16> %vext;
-}
-
-; Tests for ReconstructShuffle function. Indices have to be carefully
-; chosen to reach lowering phase as a BUILD_VECTOR.
-
-; One vector needs vext, the other can be handled by extract_subvector
-; Also checks interleaving of sources is handled correctly.
-; Essence: a vext is used on %A and something saner than stack load/store for final result.
-define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: test_interleaved:
-;CHECK: ext.8b
-;CHECK: zip1.4h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
- ret <4 x i16> %tmp3
-}
-
-; An undef in the shuffle list should still be optimizable
-define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: test_undef:
-;CHECK: zip1.4h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
- ret <4 x i16> %tmp3
-}
Removed: llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extend-int-to-fp.ll (removed)
@@ -1,19 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <4 x float> @foo(<4 x i16> %a) nounwind {
-; CHECK-LABEL: foo:
-; CHECK: ushll.4s v0, v0, #0
-; CHECK-NEXT: ucvtf.4s v0, v0
-; CHECK-NEXT: ret
- %vcvt.i = uitofp <4 x i16> %a to <4 x float>
- ret <4 x float> %vcvt.i
-}
-
-define <4 x float> @bar(<4 x i16> %a) nounwind {
-; CHECK-LABEL: bar:
-; CHECK: sshll.4s v0, v0, #0
-; CHECK-NEXT: scvtf.4s v0, v0
-; CHECK-NEXT: ret
- %vcvt.i = sitofp <4 x i16> %a to <4 x float>
- ret <4 x float> %vcvt.i
-}
Removed: llvm/trunk/test/CodeGen/ARM64/extend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extend.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extend.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extend.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
- at array = external global [0 x i32]
-
-define i64 @foo(i32 %i) {
-; CHECK: foo
-; CHECK: adrp x[[REG:[0-9]+]], _array at GOTPAGE
-; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _array at GOTPAGEOFF]
-; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
-; CHECK: ret
- %idxprom = sext i32 %i to i64
- %arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom
- %tmp1 = load i32* %arrayidx, align 4
- %conv = sext i32 %tmp1 to i64
- ret i64 %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/extern-weak.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extern-weak.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extern-weak.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extern-weak.ll (removed)
@@ -1,51 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -o - < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s
-
-declare extern_weak i32 @var()
-
-define i32()* @foo() {
-; The usual ADRP/ADD pair can't be used for a weak reference because it must
-; evaluate to 0 if the symbol is undefined. We use a litpool entry.
- ret i32()* @var
-
-; CHECK: adrp x[[VAR:[0-9]+]], :got:var
-; CHECK: ldr x0, [x[[VAR]], :got_lo12:var]
-
- ; In the large model, the usual relocations are absolute and can
- ; materialise 0.
-; CHECK-LARGE: movz x0, #:abs_g3:var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:var
-; CHECK-LARGE: movk x0, #:abs_g1_nc:var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:var
-}
-
-
- at arr_var = extern_weak global [10 x i32]
-
-define i32* @bar() {
- %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5
-; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var
-; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var]
-; CHECK: add x0, [[ARR_VAR]], #20
- ret i32* %addr
-
- ; In the large model, the usual relocations are absolute and can
- ; materialise 0.
-; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g2_nc:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g1_nc:arr_var
-; CHECK-LARGE: movk [[ARR_VAR]], #:abs_g0_nc:arr_var
-}
-
- at defined_weak_var = internal unnamed_addr global i32 0
-
-define i32* @wibble() {
- ret i32* @defined_weak_var
-; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
-; CHECK: add x0, [[BASE]], :lo12:defined_weak_var
-
-; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
-; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
-}
Removed: llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extload-knownzero.ll (removed)
@@ -1,28 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-; rdar://12771555
-
-define void @foo(i16* %ptr, i32 %a) nounwind {
-entry:
-; CHECK-LABEL: foo:
- %tmp1 = icmp ult i32 %a, 100
- br i1 %tmp1, label %bb1, label %bb2
-bb1:
-; CHECK: %bb1
-; CHECK: ldrh [[REG:w[0-9]+]]
- %tmp2 = load i16* %ptr, align 2
- br label %bb2
-bb2:
-; CHECK: %bb2
-; CHECK-NOT: and {{w[0-9]+}}, [[REG]], #0xffff
-; CHECK: cmp [[REG]], #23
- %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
- %cmp = icmp ult i16 %tmp3, 24
- br i1 %cmp, label %bb3, label %exit
-bb3:
- call void @bar() nounwind
- br label %exit
-exit:
- ret void
-}
-
-declare void @bar ()
Removed: llvm/trunk/test/CodeGen/ARM64/extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extract.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extract.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extract.ll (removed)
@@ -1,58 +0,0 @@
-; RUN: llc -arm64-extr-generation=true -verify-machineinstrs < %s \
-; RUN: -march=arm64 | FileCheck %s
-
-define i64 @ror_i64(i64 %in) {
-; CHECK-LABEL: ror_i64:
- %left = shl i64 %in, 19
- %right = lshr i64 %in, 45
- %val5 = or i64 %left, %right
-; CHECK: ror {{x[0-9]+}}, x0, #45
- ret i64 %val5
-}
-
-define i32 @ror_i32(i32 %in) {
-; CHECK-LABEL: ror_i32:
- %left = shl i32 %in, 9
- %right = lshr i32 %in, 23
- %val5 = or i32 %left, %right
-; CHECK: ror {{w[0-9]+}}, w0, #23
- ret i32 %val5
-}
-
-define i32 @extr_i32(i32 %lhs, i32 %rhs) {
-; CHECK-LABEL: extr_i32:
- %left = shl i32 %lhs, 6
- %right = lshr i32 %rhs, 26
- %val = or i32 %left, %right
- ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
- ; something other than w0 and w1.
-; CHECK: extr {{w[0-9]+}}, w0, w1, #26
-
- ret i32 %val
-}
-
-define i64 @extr_i64(i64 %lhs, i64 %rhs) {
-; CHECK-LABEL: extr_i64:
- %right = lshr i64 %rhs, 40
- %left = shl i64 %lhs, 24
- %val = or i64 %right, %left
- ; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
- ; something other than w0 and w1.
-; CHECK: extr {{x[0-9]+}}, x0, x1, #40
-
- ret i64 %val
-}
-
-; Regression test: a bad experimental pattern crept into git which optimised
-; this pattern to a single EXTR.
-define i32 @extr_regress(i32 %a, i32 %b) {
-; CHECK-LABEL: extr_regress:
-
- %sh1 = shl i32 %a, 14
- %sh2 = lshr i32 %b, 14
- %val = or i32 %sh2, %sh1
-; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
-
- ret i32 %val
-; CHECK: ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/extract_subvector.ll (removed)
@@ -1,51 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
-
-define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
-; CHECK: v8i8
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <8 x i8> %ret
-}
-
-define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
-; CHECK-LABEL: v4i16:
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- ret <4 x i16> %ret
-}
-
-define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
-; CHECK-LABEL: v2i32:
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
- ret <2 x i32> %ret
-}
-
-define <1 x i64> @v1i64(<2 x i64> %a) nounwind {
-; CHECK-LABEL: v1i64:
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
- ret <1 x i64> %ret
-}
-
-define <2 x float> @v2f32(<4 x float> %a) nounwind {
-; CHECK-LABEL: v2f32:
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
- ret <2 x float> %ret
-}
-
-define <1 x double> @v1f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: v1f64:
-; CHECK: ext.16b v0, v0, v0, #8
-; CHECK: ret
- %ret = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
- ret <1 x double> %ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-addr-offset.ll (removed)
@@ -1,47 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
- at sortlist = common global [5001 x i32] zeroinitializer, align 16
- at sortlist2 = common global [5001 x i64] zeroinitializer, align 16
-
-; Load an address with an offset larget then LDR imm can handle
-define i32 @foo() nounwind {
-entry:
-; CHECK: @foo
-; CHECK: adrp x[[REG:[0-9]+]], _sortlist at GOTPAGE
-; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist at GOTPAGEOFF]
-; CHECK: movz x[[REG2:[0-9]+]], #0x4e20
-; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
-; CHECK: ldr w0, [x[[REG3]]]
-; CHECK: ret
- %0 = load i32* getelementptr inbounds ([5001 x i32]* @sortlist, i32 0, i64 5000), align 4
- ret i32 %0
-}
-
-define i64 @foo2() nounwind {
-entry:
-; CHECK: @foo2
-; CHECK: adrp x[[REG:[0-9]+]], _sortlist2 at GOTPAGE
-; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2 at GOTPAGEOFF]
-; CHECK: movz x[[REG2:[0-9]+]], #0x9c40
-; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
-; CHECK: ldr x0, [x[[REG3]]]
-; CHECK: ret
- %0 = load i64* getelementptr inbounds ([5001 x i64]* @sortlist2, i32 0, i64 5000), align 4
- ret i64 %0
-}
-
-; Load an address with a ridiculously large offset.
-; rdar://12505553
- at pd2 = common global i8* null, align 8
-
-define signext i8 @foo3() nounwind ssp {
-entry:
-; CHECK: @foo3
-; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32
-; CHECK: movk x[[REG]], #0x73ce, lsl #16
-; CHECK: movk x[[REG]], #0x2ff2
- %0 = load i8** @pd2, align 8
- %arrayidx = getelementptr inbounds i8* %0, i64 12345678901234
- %1 = load i8* %arrayidx, align 1
- ret i8 %1
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-alloca.ll (removed)
@@ -1,25 +0,0 @@
-; This test should cause the TargetMaterializeAlloca to be invoked
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-%struct.S1Ty = type { i64 }
-%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
-
-define void @takeS1(%struct.S1Ty* %V) nounwind {
-entry:
- %V.addr = alloca %struct.S1Ty*, align 8
- store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8
- ret void
-}
-
-define void @main() nounwind {
-entry:
-; CHECK: main
-; CHECK: mov x29, sp
-; CHECK: mov x[[REG:[0-9]+]], sp
-; CHECK-NEXT: orr x[[REG1:[0-9]+]], xzr, #0x8
-; CHECK-NEXT: add x0, x[[REG]], x[[REG1]]
- %E = alloca %struct.S2Ty, align 4
- %B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1
- call void @takeS1(%struct.S1Ty* %B)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-br.ll (removed)
@@ -1,155 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
-
-define void @branch1() nounwind uwtable ssp {
- %x = alloca i32, align 4
- store i32 0, i32* %x, align 4
- %1 = load i32* %x, align 4
- %2 = icmp ne i32 %1, 0
- br i1 %2, label %3, label %4
-
-; <label>:3 ; preds = %0
- br label %4
-
-; <label>:4 ; preds = %3, %0
- ret void
-}
-
-define void @branch2() nounwind uwtable ssp {
- %1 = alloca i32, align 4
- %x = alloca i32, align 4
- %y = alloca i32, align 4
- %z = alloca i32, align 4
- store i32 0, i32* %1
- store i32 1, i32* %y, align 4
- store i32 1, i32* %x, align 4
- store i32 0, i32* %z, align 4
- %2 = load i32* %x, align 4
- %3 = icmp ne i32 %2, 0
- br i1 %3, label %4, label %5
-
-; <label>:4 ; preds = %0
- store i32 0, i32* %1
- br label %14
-
-; <label>:5 ; preds = %0
- %6 = load i32* %y, align 4
- %7 = icmp ne i32 %6, 0
- br i1 %7, label %8, label %13
-
-; <label>:8 ; preds = %5
- %9 = load i32* %z, align 4
- %10 = icmp ne i32 %9, 0
- br i1 %10, label %11, label %12
-
-; <label>:11 ; preds = %8
- store i32 1, i32* %1
- br label %14
-
-; <label>:12 ; preds = %8
- store i32 0, i32* %1
- br label %14
-
-; <label>:13 ; preds = %5
- br label %14
-
-; <label>:14 ; preds = %4, %11, %12, %13
- %15 = load i32* %1
- ret void
-}
-
-define void @true_() nounwind uwtable ssp {
-; CHECK: @true_
-; CHECK: b LBB2_1
- br i1 true, label %1, label %2
-
-; <label>:1
-; CHECK: LBB2_1
- br label %2
-
-; <label>:2
- ret void
-}
-
-define void @false_() nounwind uwtable ssp {
-; CHECK: @false_
-; CHECK: b LBB3_2
- br i1 false, label %1, label %2
-
-; <label>:1
- br label %2
-
-; <label>:2
-; CHECK: LBB3_2
- ret void
-}
-
-define zeroext i8 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) {
-entry:
- %a.addr = alloca i8, align 1
- %b.addr = alloca i16, align 2
- %c.addr = alloca i32, align 4
- %d.addr = alloca i64, align 8
- store i8 %a, i8* %a.addr, align 1
- store i16 %b, i16* %b.addr, align 2
- store i32 %c, i32* %c.addr, align 4
- store i64 %d, i64* %d.addr, align 8
- %0 = load i16* %b.addr, align 2
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: b.eq LBB4_2
- %conv = trunc i16 %0 to i1
- br i1 %conv, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @foo1()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %1 = load i32* %c.addr, align 4
-; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1
-; CHECK: subs w{{[0-9]+}}, w[[REG]], #0
-; CHECK: b.eq LBB4_4
- %conv1 = trunc i32 %1 to i1
- br i1 %conv1, label %if.then3, label %if.end4
-
-if.then3: ; preds = %if.end
- call void @foo1()
- br label %if.end4
-
-if.end4: ; preds = %if.then3, %if.end
- %2 = load i64* %d.addr, align 8
-; CHECK: subs w{{[0-9]+}}, w{{[0-9]+}}, #0
-; CHECK: b.eq LBB4_6
- %conv5 = trunc i64 %2 to i1
- br i1 %conv5, label %if.then7, label %if.end8
-
-if.then7: ; preds = %if.end4
- call void @foo1()
- br label %if.end8
-
-if.end8: ; preds = %if.then7, %if.end4
- %3 = load i8* %a.addr, align 1
- ret i8 %3
-}
-
-declare void @foo1()
-
-; rdar://15174028
-define i32 @trunc64(i64 %foo) nounwind {
-; CHECK: trunc64
-; CHECK: orr [[REG:x[0-9]+]], xzr, #0x1
-; CHECK: and [[REG2:x[0-9]+]], x0, [[REG]]
-; CHECK: mov x[[REG3:[0-9]+]], [[REG2]]
-; CHECK: and [[REG4:w[0-9]+]], w[[REG3]], #0x1
-; CHECK: subs {{w[0-9]+}}, [[REG4]], #0
-; CHECK: b.eq LBB5_2
- %a = and i64 %foo, 1
- %b = trunc i64 %a to i1
- br i1 %b, label %if.then, label %if.else
-
-if.then:
- ret i32 1
-
-if.else:
- ret i32 0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-call.ll (removed)
@@ -1,100 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64_be-linux-gnu | FileCheck %s --check-prefix=CHECK-BE
-
-define void @call0() nounwind {
-entry:
- ret void
-}
-
-define void @foo0() nounwind {
-entry:
-; CHECK: foo0
-; CHECK: bl _call0
- call void @call0()
- ret void
-}
-
-define i32 @call1(i32 %a) nounwind {
-entry:
- %a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %tmp = load i32* %a.addr, align 4
- ret i32 %tmp
-}
-
-define i32 @foo1(i32 %a) nounwind {
-entry:
-; CHECK: foo1
-; CHECK: stur w0, [x29, #-4]
-; CHECK-NEXT: ldur w0, [x29, #-4]
-; CHECK-NEXT: bl _call1
- %a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %tmp = load i32* %a.addr, align 4
- %call = call i32 @call1(i32 %tmp)
- ret i32 %call
-}
-
-define i32 @sext_(i8 %a, i16 %b) nounwind {
-entry:
-; CHECK: @sext_
-; CHECK: sxtb w0, w0
-; CHECK: sxth w1, w1
-; CHECK: bl _foo_sext_
- call void @foo_sext_(i8 signext %a, i16 signext %b)
- ret i32 0
-}
-
-declare void @foo_sext_(i8 %a, i16 %b)
-
-define i32 @zext_(i8 %a, i16 %b) nounwind {
-entry:
-; CHECK: @zext_
-; CHECK: uxtb w0, w0
-; CHECK: uxth w1, w1
- call void @foo_zext_(i8 zeroext %a, i16 zeroext %b)
- ret i32 0
-}
-
-declare void @foo_zext_(i8 %a, i16 %b)
-
-define i32 @t1(i32 %argc, i8** nocapture %argv) {
-entry:
-; CHECK: @t1
-; The last parameter will be passed on stack via i8.
-; CHECK: strb w{{[0-9]+}}, [sp]
-; CHECK-NEXT: bl _bar
- %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70, i8 zeroext 28, i8 zeroext 39, i8 zeroext -41)
- ret i32 0
-}
-
-declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext)
-
-; Test materialization of integers. Target-independent selector handles this.
-define i32 @t2() {
-entry:
-; CHECK: @t2
-; CHECK: movz x0, #0
-; CHECK: orr w1, wzr, #0xfffffff8
-; CHECK: orr w[[REG:[0-9]+]], wzr, #0x3ff
-; CHECK: orr w[[REG2:[0-9]+]], wzr, #0x2
-; CHECK: movz w[[REG3:[0-9]+]], #0
-; CHECK: orr w[[REG4:[0-9]+]], wzr, #0x1
-; CHECK: uxth w2, w[[REG]]
-; CHECK: sxtb w3, w[[REG2]]
-; CHECK: and w4, w[[REG3]], #0x1
-; CHECK: and w5, w[[REG4]], #0x1
-; CHECK: bl _func2
- %call = call i32 @func2(i64 zeroext 0, i32 signext -8, i16 zeroext 1023, i8 signext -254, i1 zeroext 0, i1 zeroext 1)
- ret i32 0
-}
-
-declare i32 @func2(i64 zeroext, i32 signext, i16 zeroext, i8 signext, i1 zeroext, i1 zeroext)
-
-declare void @callee_b0f(i8 %bp10, i8 %bp11, i8 %bp12, i8 %bp13, i8 %bp14, i8 %bp15, i8 %bp17, i8 %bp18, i8 %bp19)
-define void @caller_b1f() {
-entry:
- ; CHECK-BE: strb w{{.*}}, [sp, #7]
- call void @callee_b0f(i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 42)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-conversion.ll (removed)
@@ -1,442 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
-
-;; Test various conversions.
-define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
-entry:
-; CHECK: trunc_
-; CHECK: sub sp, sp, #16
-; CHECK: strb w0, [sp, #15]
-; CHECK: strh w1, [sp, #12]
-; CHECK: str w2, [sp, #8]
-; CHECK: str x3, [sp]
-; CHECK: ldr x3, [sp]
-; CHECK: mov x0, x3
-; CHECK: str w0, [sp, #8]
-; CHECK: ldr w0, [sp, #8]
-; CHECK: strh w0, [sp, #12]
-; CHECK: ldrh w0, [sp, #12]
-; CHECK: strb w0, [sp, #15]
-; CHECK: ldrb w0, [sp, #15]
-; CHECK: uxtb w0, w0
-; CHECK: add sp, sp, #16
-; CHECK: ret
- %a.addr = alloca i8, align 1
- %b.addr = alloca i16, align 2
- %c.addr = alloca i32, align 4
- %d.addr = alloca i64, align 8
- store i8 %a, i8* %a.addr, align 1
- store i16 %b, i16* %b.addr, align 2
- store i32 %c, i32* %c.addr, align 4
- store i64 %d, i64* %d.addr, align 8
- %tmp = load i64* %d.addr, align 8
- %conv = trunc i64 %tmp to i32
- store i32 %conv, i32* %c.addr, align 4
- %tmp1 = load i32* %c.addr, align 4
- %conv2 = trunc i32 %tmp1 to i16
- store i16 %conv2, i16* %b.addr, align 2
- %tmp3 = load i16* %b.addr, align 2
- %conv4 = trunc i16 %tmp3 to i8
- store i8 %conv4, i8* %a.addr, align 1
- %tmp5 = load i8* %a.addr, align 1
- %conv6 = zext i8 %tmp5 to i32
- ret i32 %conv6
-}
-
-define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
-entry:
-; CHECK: zext_
-; CHECK: sub sp, sp, #16
-; CHECK: strb w0, [sp, #15]
-; CHECK: strh w1, [sp, #12]
-; CHECK: str w2, [sp, #8]
-; CHECK: str x3, [sp]
-; CHECK: ldrb w0, [sp, #15]
-; CHECK: uxtb w0, w0
-; CHECK: strh w0, [sp, #12]
-; CHECK: ldrh w0, [sp, #12]
-; CHECK: uxth w0, w0
-; CHECK: str w0, [sp, #8]
-; CHECK: ldr w0, [sp, #8]
-; CHECK: mov x3, x0
-; CHECK: ubfx x3, x3, #0, #32
-; CHECK: str x3, [sp]
-; CHECK: ldr x0, [sp]
-; CHECK: ret
- %a.addr = alloca i8, align 1
- %b.addr = alloca i16, align 2
- %c.addr = alloca i32, align 4
- %d.addr = alloca i64, align 8
- store i8 %a, i8* %a.addr, align 1
- store i16 %b, i16* %b.addr, align 2
- store i32 %c, i32* %c.addr, align 4
- store i64 %d, i64* %d.addr, align 8
- %tmp = load i8* %a.addr, align 1
- %conv = zext i8 %tmp to i16
- store i16 %conv, i16* %b.addr, align 2
- %tmp1 = load i16* %b.addr, align 2
- %conv2 = zext i16 %tmp1 to i32
- store i32 %conv2, i32* %c.addr, align 4
- %tmp3 = load i32* %c.addr, align 4
- %conv4 = zext i32 %tmp3 to i64
- store i64 %conv4, i64* %d.addr, align 8
- %tmp5 = load i64* %d.addr, align 8
- ret i64 %tmp5
-}
-
-define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
-entry:
-; CHECK: @zext_i1_i32
-; CHECK: and w0, w0, #0x1
- %conv = zext i1 %a to i32
- ret i32 %conv;
-}
-
-define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
-entry:
-; CHECK: @zext_i1_i64
-; CHECK: and w0, w0, #0x1
- %conv = zext i1 %a to i64
- ret i64 %conv;
-}
-
-define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
-entry:
-; CHECK: sext_
-; CHECK: sub sp, sp, #16
-; CHECK: strb w0, [sp, #15]
-; CHECK: strh w1, [sp, #12]
-; CHECK: str w2, [sp, #8]
-; CHECK: str x3, [sp]
-; CHECK: ldrb w0, [sp, #15]
-; CHECK: sxtb w0, w0
-; CHECK: strh w0, [sp, #12]
-; CHECK: ldrh w0, [sp, #12]
-; CHECK: sxth w0, w0
-; CHECK: str w0, [sp, #8]
-; CHECK: ldr w0, [sp, #8]
-; CHECK: mov x3, x0
-; CHECK: sxtw x3, w3
-; CHECK: str x3, [sp]
-; CHECK: ldr x0, [sp]
-; CHECK: ret
- %a.addr = alloca i8, align 1
- %b.addr = alloca i16, align 2
- %c.addr = alloca i32, align 4
- %d.addr = alloca i64, align 8
- store i8 %a, i8* %a.addr, align 1
- store i16 %b, i16* %b.addr, align 2
- store i32 %c, i32* %c.addr, align 4
- store i64 %d, i64* %d.addr, align 8
- %tmp = load i8* %a.addr, align 1
- %conv = sext i8 %tmp to i16
- store i16 %conv, i16* %b.addr, align 2
- %tmp1 = load i16* %b.addr, align 2
- %conv2 = sext i16 %tmp1 to i32
- store i32 %conv2, i32* %c.addr, align 4
- %tmp3 = load i32* %c.addr, align 4
- %conv4 = sext i32 %tmp3 to i64
- store i64 %conv4, i64* %d.addr, align 8
- %tmp5 = load i64* %d.addr, align 8
- ret i64 %tmp5
-}
-
-; Test sext i8 to i64
-
-define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
-; CHECK-LABEL: sext_i8_i64:
-; CHECK: mov x[[TMP:[0-9]+]], x0
-; CHECK: sxtb x0, w[[TMP]]
- %big = sext i8 %in to i64
- ret i64 %big
-}
-
-define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
-; CHECK-LABEL: sext_i16_i64:
-; CHECK: mov x[[TMP:[0-9]+]], x0
-; CHECK: sxth x0, w[[TMP]]
- %big = sext i16 %in to i64
- ret i64 %big
-}
-
-; Test sext i1 to i32
-define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
-entry:
-; CHECK: sext_i1_i32
-; CHECK: sbfx w0, w0, #0, #1
- %conv = sext i1 %a to i32
- ret i32 %conv
-}
-
-; Test sext i1 to i16
-define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
-entry:
-; CHECK: sext_i1_i16
-; CHECK: sbfx w0, w0, #0, #1
- %conv = sext i1 %a to i16
- ret i16 %conv
-}
-
-; Test sext i1 to i8
-define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
-entry:
-; CHECK: sext_i1_i8
-; CHECK: sbfx w0, w0, #0, #1
- %conv = sext i1 %a to i8
- ret i8 %conv
-}
-
-; Test fpext
-define double @fpext_(float %a) nounwind ssp {
-entry:
-; CHECK: fpext_
-; CHECK: fcvt d0, s0
- %conv = fpext float %a to double
- ret double %conv
-}
-
-; Test fptrunc
-define float @fptrunc_(double %a) nounwind ssp {
-entry:
-; CHECK: fptrunc_
-; CHECK: fcvt s0, d0
- %conv = fptrunc double %a to float
- ret float %conv
-}
-
-; Test fptosi
-define i32 @fptosi_ws(float %a) nounwind ssp {
-entry:
-; CHECK: fptosi_ws
-; CHECK: fcvtzs w0, s0
- %conv = fptosi float %a to i32
- ret i32 %conv
-}
-
-; Test fptosi
-define i32 @fptosi_wd(double %a) nounwind ssp {
-entry:
-; CHECK: fptosi_wd
-; CHECK: fcvtzs w0, d0
- %conv = fptosi double %a to i32
- ret i32 %conv
-}
-
-; Test fptoui
-define i32 @fptoui_ws(float %a) nounwind ssp {
-entry:
-; CHECK: fptoui_ws
-; CHECK: fcvtzu w0, s0
- %conv = fptoui float %a to i32
- ret i32 %conv
-}
-
-; Test fptoui
-define i32 @fptoui_wd(double %a) nounwind ssp {
-entry:
-; CHECK: fptoui_wd
-; CHECK: fcvtzu w0, d0
- %conv = fptoui double %a to i32
- ret i32 %conv
-}
-
-; Test sitofp
-define float @sitofp_sw_i1(i1 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_sw_i1
-; CHECK: sbfx w0, w0, #0, #1
-; CHECK: scvtf s0, w0
- %conv = sitofp i1 %a to float
- ret float %conv
-}
-
-; Test sitofp
-define float @sitofp_sw_i8(i8 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_sw_i8
-; CHECK: sxtb w0, w0
-; CHECK: scvtf s0, w0
- %conv = sitofp i8 %a to float
- ret float %conv
-}
-
-; Test sitofp
-define float @sitofp_sw_i16(i16 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_sw_i16
-; CHECK: sxth w0, w0
-; CHECK: scvtf s0, w0
- %conv = sitofp i16 %a to float
- ret float %conv
-}
-
-; Test sitofp
-define float @sitofp_sw(i32 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_sw
-; CHECK: scvtf s0, w0
- %conv = sitofp i32 %a to float
- ret float %conv
-}
-
-; Test sitofp
-define float @sitofp_sx(i64 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_sx
-; CHECK: scvtf s0, x0
- %conv = sitofp i64 %a to float
- ret float %conv
-}
-
-; Test sitofp
-define double @sitofp_dw(i32 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_dw
-; CHECK: scvtf d0, w0
- %conv = sitofp i32 %a to double
- ret double %conv
-}
-
-; Test sitofp
-define double @sitofp_dx(i64 %a) nounwind ssp {
-entry:
-; CHECK: sitofp_dx
-; CHECK: scvtf d0, x0
- %conv = sitofp i64 %a to double
- ret double %conv
-}
-
-; Test uitofp
-define float @uitofp_sw_i1(i1 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_sw_i1
-; CHECK: and w0, w0, #0x1
-; CHECK: ucvtf s0, w0
- %conv = uitofp i1 %a to float
- ret float %conv
-}
-
-; Test uitofp
-define float @uitofp_sw_i8(i8 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_sw_i8
-; CHECK: uxtb w0, w0
-; CHECK: ucvtf s0, w0
- %conv = uitofp i8 %a to float
- ret float %conv
-}
-
-; Test uitofp
-define float @uitofp_sw_i16(i16 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_sw_i16
-; CHECK: uxth w0, w0
-; CHECK: ucvtf s0, w0
- %conv = uitofp i16 %a to float
- ret float %conv
-}
-
-; Test uitofp
-define float @uitofp_sw(i32 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_sw
-; CHECK: ucvtf s0, w0
- %conv = uitofp i32 %a to float
- ret float %conv
-}
-
-; Test uitofp
-define float @uitofp_sx(i64 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_sx
-; CHECK: ucvtf s0, x0
- %conv = uitofp i64 %a to float
- ret float %conv
-}
-
-; Test uitofp
-define double @uitofp_dw(i32 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_dw
-; CHECK: ucvtf d0, w0
- %conv = uitofp i32 %a to double
- ret double %conv
-}
-
-; Test uitofp
-define double @uitofp_dx(i64 %a) nounwind ssp {
-entry:
-; CHECK: uitofp_dx
-; CHECK: ucvtf d0, x0
- %conv = uitofp i64 %a to double
- ret double %conv
-}
-
-define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
-entry:
-; CHECK: i64_trunc_i32
-; CHECK: mov x1, x0
- %conv = trunc i64 %a to i32
- ret i32 %conv
-}
-
-define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
-entry:
-; CHECK: i64_trunc_i16
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
-; CHECK: uxth w0, [[REG2]]
- %conv = trunc i64 %a to i16
- ret i16 %conv
-}
-
-define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
-entry:
-; CHECK: i64_trunc_i8
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
-; CHECK: uxtb w0, [[REG2]]
- %conv = trunc i64 %a to i8
- ret i8 %conv
-}
-
-define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
-entry:
-; CHECK: i64_trunc_i1
-; CHECK: mov x[[REG:[0-9]+]], x0
-; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
-; CHECK: and w0, [[REG2]], #0x1
- %conv = trunc i64 %a to i1
- ret i1 %conv
-}
-
-; rdar://15101939
-define void @stack_trunc() nounwind {
-; CHECK: stack_trunc
-; CHECK: sub sp, sp, #16
-; CHECK: ldr [[REG:x[0-9]+]], [sp]
-; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
-; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0xff
-; CHECK: strb [[REG3]], [sp, #15]
-; CHECK: add sp, sp, #16
- %a = alloca i8, align 1
- %b = alloca i64, align 8
- %c = load i64* %b, align 8
- %d = trunc i64 %c to i8
- store i8 %d, i8* %a, align 1
- ret void
-}
-
-define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
-; CHECK-LABEL: zext_i8_i64:
-; CHECK: mov x[[TMP:[0-9]+]], x0
-; CHECK: ubfx x0, x[[TMP]], #0, #8
- %big = zext i8 %in to i64
- ret i64 %big
-}
-define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
-; CHECK-LABEL: zext_i16_i64:
-; CHECK: mov x[[TMP:[0-9]+]], x0
-; CHECK: ubfx x0, x[[TMP]], #0, #16
- %big = zext i16 %in to i64
- ret i64 %big
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-fcmp.ll (removed)
@@ -1,146 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin | FileCheck %s
-
-define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_float1
-; CHECK: fcmp s0, #0.0
-; CHECK: cset w{{[0-9]+}}, ne
- %cmp = fcmp une float %a, 0.000000e+00
- ret i1 %cmp
-}
-
-define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_float2
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, ne
- %cmp = fcmp une float %a, %b
- ret i1 %cmp
-}
-
-define zeroext i1 @fcmp_double1(double %a) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_double1
-; CHECK: fcmp d0, #0.0
-; CHECK: cset w{{[0-9]+}}, ne
- %cmp = fcmp une double %a, 0.000000e+00
- ret i1 %cmp
-}
-
-define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_double2
-; CHECK: fcmp d0, d1
-; CHECK: cset w{{[0-9]+}}, ne
- %cmp = fcmp une double %a, %b
- ret i1 %cmp
-}
-
-; Check each fcmp condition
-define float @fcmp_oeq(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_oeq
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, eq
- %cmp = fcmp oeq float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ogt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ogt
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, gt
- %cmp = fcmp ogt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_oge(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_oge
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, ge
- %cmp = fcmp oge float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_olt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_olt
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, mi
- %cmp = fcmp olt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ole(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ole
-; CHECK: fcmp s0, s1
-; CHECK: cset w{{[0-9]+}}, ls
- %cmp = fcmp ole float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ord(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ord
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, vc
- %cmp = fcmp ord float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_uno(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_uno
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, vs
- %cmp = fcmp uno float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ugt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ugt
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, hi
- %cmp = fcmp ugt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_uge(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_uge
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, pl
- %cmp = fcmp uge float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ult(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ult
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, lt
- %cmp = fcmp ult float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ule(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ule
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, le
- %cmp = fcmp ule float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_une(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_une
-; CHECK: fcmp s0, s1
-; CHECK: cset {{w[0-9]+}}, ne
- %cmp = fcmp une float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-gv.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-; Test load/store of global value from global offset table.
- at seed = common global i64 0, align 8
-
-define void @Initrand() nounwind {
-entry:
-; CHECK: @Initrand
-; CHECK: adrp x[[REG:[0-9]+]], _seed at GOTPAGE
-; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed at GOTPAGEOFF]
-; CHECK: str x{{[0-9]+}}, [x[[REG2]]]
- store i64 74755, i64* @seed, align 8
- ret void
-}
-
-define i32 @Rand() nounwind {
-entry:
-; CHECK: @Rand
-; CHECK: adrp x[[REG:[0-9]+]], _seed at GOTPAGE
-; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed at GOTPAGEOFF]
-; CHECK: movz x[[REG3:[0-9]+]], #0x51d
-; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
-; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
-; CHECK: movz x[[REG6:[0-9]+]], #0x3619
-; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
-; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
-; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
-; CHECK: str x[[REG9]], [x[[REG]]]
-; CHECK: ldr x{{[0-9]+}}, [x[[REG]]]
- %0 = load i64* @seed, align 8
- %mul = mul nsw i64 %0, 1309
- %add = add nsw i64 %mul, 13849
- %and = and i64 %add, 65535
- store i64 %and, i64* @seed, align 8
- %1 = load i64* @seed, align 8
- %conv = trunc i64 %1 to i32
- ret i32 %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-icmp.ll (removed)
@@ -1,214 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
-entry:
-; CHECK: icmp_eq_imm
-; CHECK: cmp w0, #31
-; CHECK: cset w0, eq
- %cmp = icmp eq i32 %a, 31
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp {
-entry:
-; CHECK: icmp_eq_neg_imm
-; CHECK: cmn w0, #7
-; CHECK: cset w0, eq
- %cmp = icmp eq i32 %a, -7
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_eq(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_eq
-; CHECK: cmp w0, w1
-; CHECK: cset w0, eq
- %cmp = icmp eq i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_ne
-; CHECK: cmp w0, w1
-; CHECK: cset w0, ne
- %cmp = icmp ne i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_ugt
-; CHECK: cmp w0, w1
-; CHECK: cset w0, hi
- %cmp = icmp ugt i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_uge
-; CHECK: cmp w0, w1
-; CHECK: cset w0, hs
- %cmp = icmp uge i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_ult
-; CHECK: cmp w0, w1
-; CHECK: cset w0, lo
- %cmp = icmp ult i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_ule
-; CHECK: cmp w0, w1
-; CHECK: cset w0, ls
- %cmp = icmp ule i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_sgt
-; CHECK: cmp w0, w1
-; CHECK: cset w0, gt
- %cmp = icmp sgt i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_sge
-; CHECK: cmp w0, w1
-; CHECK: cset w0, ge
- %cmp = icmp sge i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_slt
-; CHECK: cmp w0, w1
-; CHECK: cset w0, lt
- %cmp = icmp slt i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp {
-entry:
-; CHECK: icmp_sle
-; CHECK: cmp w0, w1
-; CHECK: cset w0, le
- %cmp = icmp sle i32 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp {
-entry:
-; CHECK: icmp_i64
-; CHECK: cmp x0, x1
-; CHECK: cset w{{[0-9]+}}, le
- %cmp = icmp sle i64 %a, %b
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp {
-entry:
-; CHECK: icmp_eq_i16
-; CHECK: sxth w0, w0
-; CHECK: sxth w1, w1
-; CHECK: cmp w0, w1
-; CHECK: cset w0, eq
- %cmp = icmp eq i16 %a, %b
- ret i1 %cmp
-}
-
-define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp {
-entry:
-; CHECK: icmp_eq_i8
-; CHECK: sxtb w0, w0
-; CHECK: sxtb w1, w1
-; CHECK: cmp w0, w1
-; CHECK: cset w0, eq
- %cmp = icmp eq i8 %a, %b
- ret i1 %cmp
-}
-
-define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {
-entry:
-; CHECK: icmp_i16_unsigned
-; CHECK: uxth w0, w0
-; CHECK: uxth w1, w1
-; CHECK: cmp w0, w1
-; CHECK: cset w0, lo
- %cmp = icmp ult i16 %a, %b
- %conv2 = zext i1 %cmp to i32
- ret i32 %conv2
-}
-
-define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {
-entry:
-; CHECK: @icmp_i8_signed
-; CHECK: sxtb w0, w0
-; CHECK: sxtb w1, w1
-; CHECK: cmp w0, w1
-; CHECK: cset w0, gt
- %cmp = icmp sgt i8 %a, %b
- %conv2 = zext i1 %cmp to i32
- ret i32 %conv2
-}
-
-
-define i32 @icmp_i16_signed_const(i16 %a) nounwind {
-entry:
-; CHECK: icmp_i16_signed_const
-; CHECK: sxth w0, w0
-; CHECK: cmn w0, #233
-; CHECK: cset w0, lt
-; CHECK: and w0, w0, #0x1
- %cmp = icmp slt i16 %a, -233
- %conv2 = zext i1 %cmp to i32
- ret i32 %conv2
-}
-
-define i32 @icmp_i8_signed_const(i8 %a) nounwind {
-entry:
-; CHECK: icmp_i8_signed_const
-; CHECK: sxtb w0, w0
-; CHECK: cmp w0, #124
-; CHECK: cset w0, gt
-; CHECK: and w0, w0, #0x1
- %cmp = icmp sgt i8 %a, 124
- %conv2 = zext i1 %cmp to i32
- ret i32 %conv2
-}
-
-define i32 @icmp_i1_unsigned_const(i1 %a) nounwind {
-entry:
-; CHECK: icmp_i1_unsigned_const
-; CHECK: and w0, w0, #0x1
-; CHECK: cmp w0, #0
-; CHECK: cset w0, lo
-; CHECK: and w0, w0, #0x1
- %cmp = icmp ult i1 %a, 0
- %conv2 = zext i1 %cmp to i32
- ret i32 %conv2
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-indirectbr.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
- at fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8
-
-define i32 @fn(i32 %target) nounwind {
-entry:
-; CHECK: @fn
- %retval = alloca i32, align 4
- %target.addr = alloca i32, align 4
- store i32 %target, i32* %target.addr, align 4
- %0 = load i32* %target.addr, align 4
- %idxprom = zext i32 %0 to i64
- %arrayidx = getelementptr inbounds [2 x i8*]* @fn.table, i32 0, i64 %idxprom
- %1 = load i8** %arrayidx, align 8
- br label %indirectgoto
-
-ZERO: ; preds = %indirectgoto
-; CHECK: LBB0_1
- store i32 0, i32* %retval
- br label %return
-
-ONE: ; preds = %indirectgoto
-; CHECK: LBB0_2
- store i32 1, i32* %retval
- br label %return
-
-return: ; preds = %ONE, %ZERO
- %2 = load i32* %retval
- ret i32 %2
-
-indirectgoto: ; preds = %entry
-; CHECK: ldr x0, [sp]
-; CHECK: br x0
- %indirect.goto.dest = phi i8* [ %1, %entry ]
- indirectbr i8* %indirect.goto.dest, [label %ZERO, label %ONE]
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-intrinsic.ll (removed)
@@ -1,135 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios | FileCheck %s --check-prefix=ARM64
-
- at message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16
- at temp = common global [80 x i8] zeroinitializer, align 16
-
-define void @t1() {
-; ARM64-LABEL: t1
-; ARM64: adrp x8, _message at PAGE
-; ARM64: add x0, x8, _message at PAGEOFF
-; ARM64: movz w9, #0
-; ARM64: movz x2, #0x50
-; ARM64: uxtb w1, w9
-; ARM64: bl _memset
- call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false)
- ret void
-}
-
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
-
-define void @t2() {
-; ARM64-LABEL: t2
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x0, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x8, _message at PAGE
-; ARM64: add x1, x8, _message at PAGEOFF
-; ARM64: movz x2, #0x50
-; ARM64: bl _memcpy
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false)
- ret void
-}
-
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
-
-define void @t3() {
-; ARM64-LABEL: t3
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x0, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x8, _message at PAGE
-; ARM64: add x1, x8, _message at PAGEOFF
-; ARM64: movz x2, #0x14
-; ARM64: bl _memmove
- call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false)
- ret void
-}
-
-declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
-
-define void @t4() {
-; ARM64-LABEL: t4
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr x10, [x9]
-; ARM64: str x10, [x8]
-; ARM64: ldr x10, [x9, #8]
-; ARM64: str x10, [x8, #8]
-; ARM64: ldrb w11, [x9, #16]
-; ARM64: strb w11, [x8, #16]
-; ARM64: ret
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 16, i1 false)
- ret void
-}
-
-define void @t5() {
-; ARM64-LABEL: t5
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr x10, [x9]
-; ARM64: str x10, [x8]
-; ARM64: ldr x10, [x9, #8]
-; ARM64: str x10, [x8, #8]
-; ARM64: ldrb w11, [x9, #16]
-; ARM64: strb w11, [x8, #16]
-; ARM64: ret
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 8, i1 false)
- ret void
-}
-
-define void @t6() {
-; ARM64-LABEL: t6
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr w10, [x9]
-; ARM64: str w10, [x8]
-; ARM64: ldr w10, [x9, #4]
-; ARM64: str w10, [x8, #4]
-; ARM64: ldrb w10, [x9, #8]
-; ARM64: strb w10, [x8, #8]
-; ARM64: ret
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 9, i32 4, i1 false)
- ret void
-}
-
-define void @t7() {
-; ARM64-LABEL: t7
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldrh w10, [x9]
-; ARM64: strh w10, [x8]
-; ARM64: ldrh w10, [x9, #2]
-; ARM64: strh w10, [x8, #2]
-; ARM64: ldrh w10, [x9, #4]
-; ARM64: strh w10, [x8, #4]
-; ARM64: ldrb w10, [x9, #6]
-; ARM64: strb w10, [x8, #6]
-; ARM64: ret
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 7, i32 2, i1 false)
- ret void
-}
-
-define void @t8() {
-; ARM64-LABEL: t8
-; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldrb w10, [x9]
-; ARM64: strb w10, [x8]
-; ARM64: ldrb w10, [x9, #1]
-; ARM64: strb w10, [x8, #1]
-; ARM64: ldrb w10, [x9, #2]
-; ARM64: strb w10, [x8, #2]
-; ARM64: ldrb w10, [x9, #3]
-; ARM64: strb w10, [x8, #3]
-; ARM64: ret
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 4, i32 1, i1 false)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-materialize.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-; Materialize using fmov
-define void @float_(float* %value) {
-; CHECK: @float_
-; CHECK: fmov s0, #1.25000000
- store float 1.250000e+00, float* %value, align 4
- ret void
-}
-
-define void @double_(double* %value) {
-; CHECK: @double_
-; CHECK: fmov d0, #1.25000000
- store double 1.250000e+00, double* %value, align 8
- ret void
-}
-
-; Materialize from constant pool
-define float @float_cp() {
-; CHECK: @float_cp
- ret float 0x400921FB60000000
-}
-
-define double @double_cp() {
-; CHECK: @double_cp
- ret double 0x400921FB54442D18
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-noconvert.ll (removed)
@@ -1,68 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -O0 %s -o - | FileCheck %s
-
-; Fast-isel can't do vector conversions yet, but it was emitting some highly
-; suspect UCVTFUWDri MachineInstrs.
-define <4 x float> @test_uitofp(<4 x i32> %in) {
-; CHECK-LABEL: test_uitofp:
-; CHECK: ucvtf.4s v0, v0
-
- %res = uitofp <4 x i32> %in to <4 x float>
- ret <4 x float> %res
-}
-
-define <2 x double> @test_sitofp(<2 x i32> %in) {
-; CHECK-LABEL: test_sitofp:
-; CHECK: sshll.2d [[EXT:v[0-9]+]], v0, #0
-; CHECK: scvtf.2d v0, [[EXT]]
-
- %res = sitofp <2 x i32> %in to <2 x double>
- ret <2 x double> %res
-}
-
-define <2 x i32> @test_fptoui(<2 x float> %in) {
-; CHECK-LABEL: test_fptoui:
-; CHECK: fcvtzu.2s v0, v0
-
- %res = fptoui <2 x float> %in to <2 x i32>
- ret <2 x i32> %res
-}
-
-define <2 x i64> @test_fptosi(<2 x double> %in) {
-; CHECK-LABEL: test_fptosi:
-; CHECK: fcvtzs.2d v0, v0
-
- %res = fptosi <2 x double> %in to <2 x i64>
- ret <2 x i64> %res
-}
-
-define fp128 @uitofp_i32_fp128(i32 %a) {
-entry:
-; CHECK-LABEL: uitofp_i32_fp128
-; CHECK: bl ___floatunsitf
- %conv = uitofp i32 %a to fp128
- ret fp128 %conv
-}
-
-define fp128 @uitofp_i64_fp128(i64 %a) {
-entry:
-; CHECK-LABEL: uitofp_i64_fp128
-; CHECK: bl ___floatunditf
- %conv = uitofp i64 %a to fp128
- ret fp128 %conv
-}
-
-define i32 @uitofp_fp128_i32(fp128 %a) {
-entry:
-; CHECK-LABEL: uitofp_fp128_i32
-; CHECK: ___fixunstfsi
- %conv = fptoui fp128 %a to i32
- ret i32 %conv
-}
-
-define i64 @uitofp_fp128_i64(fp128 %a) {
-entry:
-; CHECK-LABEL: uitofp_fp128_i64
-; CHECK: ___fixunstfdi
- %conv = fptoui fp128 %a to i64
- ret i64 %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-rem.ll (removed)
@@ -1,44 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
-; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
-; REQUIRES: asserts
-
-; CHECK-SSA-LABEL: Machine code for function t1
-
-; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
-; CHECK-SSA-NOT: [[QUOTREG]]<def> =
-; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
-
-; CHECK-SSA-LABEL: Machine code for function t2
-
-define i32 @t1(i32 %a, i32 %b) {
-; CHECK: @t1
-; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
-; CHECK: msub w0, [[TMP]], w1, w0
- %1 = srem i32 %a, %b
- ret i32 %1
-}
-
-define i64 @t2(i64 %a, i64 %b) {
-; CHECK: @t2
-; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
-; CHECK: msub x0, [[TMP]], x1, x0
- %1 = srem i64 %a, %b
- ret i64 %1
-}
-
-define i32 @t3(i32 %a, i32 %b) {
-; CHECK: @t3
-; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
-; CHECK: msub w0, [[TMP]], w1, w0
- %1 = urem i32 %a, %b
- ret i32 %1
-}
-
-define i64 @t4(i64 %a, i64 %b) {
-; CHECK: @t4
-; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
-; CHECK: msub x0, [[TMP]], x1, x0
- %1 = urem i64 %a, %b
- ret i64 %1
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-ret.ll (removed)
@@ -1,63 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-;; Test returns.
-define void @t0() nounwind ssp {
-entry:
-; CHECK: t0
-; CHECK: ret
- ret void
-}
-
-define i32 @t1(i32 %a) nounwind ssp {
-entry:
-; CHECK: t1
-; CHECK: str w0, [sp, #12]
-; CHECK-NEXT: ldr w0, [sp, #12]
-; CHECK: ret
- %a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- %tmp = load i32* %a.addr, align 4
- ret i32 %tmp
-}
-
-define i64 @t2(i64 %a) nounwind ssp {
-entry:
-; CHECK: t2
-; CHECK: str x0, [sp, #8]
-; CHECK-NEXT: ldr x0, [sp, #8]
-; CHECK: ret
- %a.addr = alloca i64, align 8
- store i64 %a, i64* %a.addr, align 8
- %tmp = load i64* %a.addr, align 8
- ret i64 %tmp
-}
-
-define signext i16 @ret_i16(i16 signext %a) nounwind {
-entry:
-; CHECK: @ret_i16
-; CHECK: sxth w0, w0
- %a.addr = alloca i16, align 1
- store i16 %a, i16* %a.addr, align 1
- %0 = load i16* %a.addr, align 1
- ret i16 %0
-}
-
-define signext i8 @ret_i8(i8 signext %a) nounwind {
-entry:
-; CHECK: @ret_i8
-; CHECK: sxtb w0, w0
- %a.addr = alloca i8, align 1
- store i8 %a, i8* %a.addr, align 1
- %0 = load i8* %a.addr, align 1
- ret i8 %0
-}
-
-define signext i1 @ret_i1(i1 signext %a) nounwind {
-entry:
-; CHECK: @ret_i1
-; CHECK: and w0, w0, #0x1
- %a.addr = alloca i1, align 1
- store i1 %a, i1* %a.addr, align 1
- %0 = load i1* %a.addr, align 1
- ret i1 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel-select.ll (removed)
@@ -1,63 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-define i32 @t1(i32 %c) nounwind readnone {
-entry:
-; CHECK: @t1
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
- %0 = icmp sgt i32 %c, 1
- %1 = select i1 %0, i32 123, i32 357
- ret i32 %1
-}
-
-define i64 @t2(i32 %c) nounwind readnone {
-entry:
-; CHECK: @t2
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
- %0 = icmp sgt i32 %c, 1
- %1 = select i1 %0, i64 123, i64 357
- ret i64 %1
-}
-
-define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
-entry:
-; CHECK: @t3
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: csel w0, w{{[0-9]+}}, w{{[0-9]+}}, ne
- %0 = select i1 %c, i32 %a, i32 %b
- ret i32 %0
-}
-
-define i64 @t4(i1 %c, i64 %a, i64 %b) nounwind readnone {
-entry:
-; CHECK: @t4
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: csel x0, x{{[0-9]+}}, x{{[0-9]+}}, ne
- %0 = select i1 %c, i64 %a, i64 %b
- ret i64 %0
-}
-
-define float @t5(i1 %c, float %a, float %b) nounwind readnone {
-entry:
-; CHECK: @t5
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: fcsel s0, s0, s1, ne
- %0 = select i1 %c, float %a, float %b
- ret float %0
-}
-
-define double @t6(i1 %c, double %a, double %b) nounwind readnone {
-entry:
-; CHECK: @t6
-; CHECK: and w0, w0, #0x1
-; CHECK: subs w0, w0, #0
-; CHECK: fcsel d0, d0, d1, ne
- %0 = select i1 %c, double %a, double %b
- ret double %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fast-isel.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fast-isel.ll (removed)
@@ -1,95 +0,0 @@
-; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
-
-define void @t0(i32 %a) nounwind {
-entry:
-; CHECK: t0
-; CHECK: str {{w[0-9]+}}, [sp, #12]
-; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
-; CHECK-NEXT: str [[REGISTER]], [sp, #12]
-; CHECK: ret
- %a.addr = alloca i32, align 4
- store i32 %a, i32* %a.addr
- %tmp = load i32* %a.addr
- store i32 %tmp, i32* %a.addr
- ret void
-}
-
-define void @t1(i64 %a) nounwind {
-; CHECK: t1
-; CHECK: str {{x[0-9]+}}, [sp, #8]
-; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
-; CHECK-NEXT: str [[REGISTER]], [sp, #8]
-; CHECK: ret
- %a.addr = alloca i64, align 4
- store i64 %a, i64* %a.addr
- %tmp = load i64* %a.addr
- store i64 %tmp, i64* %a.addr
- ret void
-}
-
-define zeroext i1 @i1(i1 %a) nounwind {
-entry:
-; CHECK: @i1
-; CHECK: and w0, w0, #0x1
-; CHECK: strb w0, [sp, #15]
-; CHECK: ldrb w0, [sp, #15]
-; CHECK: and w0, w0, #0x1
-; CHECK: and w0, w0, #0x1
-; CHECK: add sp, sp, #16
-; CHECK: ret
- %a.addr = alloca i1, align 1
- store i1 %a, i1* %a.addr, align 1
- %0 = load i1* %a.addr, align 1
- ret i1 %0
-}
-
-define i32 @t2(i32 *%ptr) nounwind {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: ldur w0, [x0, #-4]
-; CHECK: ret
- %0 = getelementptr i32 *%ptr, i32 -1
- %1 = load i32* %0, align 4
- ret i32 %1
-}
-
-define i32 @t3(i32 *%ptr) nounwind {
-entry:
-; CHECK-LABEL: t3:
-; CHECK: ldur w0, [x0, #-256]
-; CHECK: ret
- %0 = getelementptr i32 *%ptr, i32 -64
- %1 = load i32* %0, align 4
- ret i32 %1
-}
-
-define void @t4(i32 *%ptr) nounwind {
-entry:
-; CHECK-LABEL: t4:
-; CHECK: movz w8, #0
-; CHECK: stur w8, [x0, #-4]
-; CHECK: ret
- %0 = getelementptr i32 *%ptr, i32 -1
- store i32 0, i32* %0, align 4
- ret void
-}
-
-define void @t5(i32 *%ptr) nounwind {
-entry:
-; CHECK-LABEL: t5:
-; CHECK: movz w8, #0
-; CHECK: stur w8, [x0, #-256]
-; CHECK: ret
- %0 = getelementptr i32 *%ptr, i32 -64
- store i32 0, i32* %0, align 4
- ret void
-}
-
-define void @t6() nounwind {
-; CHECK: t6
-; CHECK: brk #0x1
- tail call void @llvm.trap()
- ret void
-}
-
-declare void @llvm.trap() nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fastcc-tailcall.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define void @caller(i32* nocapture %p, i32 %a, i32 %b) nounwind optsize ssp {
-; CHECK-NOT: stp
-; CHECK: b {{_callee|callee}}
-; CHECK-NOT: ldp
-; CHECK: ret
- %1 = icmp eq i32 %b, 0
- br i1 %1, label %3, label %2
-
- tail call fastcc void @callee(i32* %p, i32 %a) optsize
- br label %3
-
- ret void
-}
-
-define internal fastcc void @callee(i32* nocapture %p, i32 %a) nounwind optsize noinline ssp {
- store volatile i32 %a, i32* %p, align 4, !tbaa !0
- ret void
-}
-
-!0 = metadata !{metadata !"int", metadata !1}
-!1 = metadata !{metadata !"omnipotent char", metadata !2}
-!2 = metadata !{metadata !"Simple C/C++ TBAA"}
Removed: llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fastisel-gep-promote-before-add.ll (removed)
@@ -1,18 +0,0 @@
-; fastisel should not fold add with non-pointer bitwidth
-; sext(a) + sext(b) != sext(a + b)
-; RUN: llc -mtriple=arm64-apple-darwin %s -O0 -o - | FileCheck %s
-
-define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp {
-entry:
- %ptr.addr = alloca i8*, align 8
- %add = add i8 64, 64 ; 0x40 + 0x40
- %0 = load i8** %ptr.addr, align 8
-
- ; CHECK-LABEL: _gep_promotion:
- ; CHECK: ldrb {{[a-z][0-9]+}}, {{\[[a-z][0-9]+\]}}
- %arrayidx = getelementptr inbounds i8* %0, i8 %add
-
- %1 = load i8* %arrayidx, align 1
- ret i8 %1
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fcmp-opt.ll (removed)
@@ -1,204 +0,0 @@
-; RUN: llc < %s -march=arm64 -mcpu=cyclone -arm64-neon-syntax=apple | FileCheck %s
-; rdar://10263824
-
-define i1 @fcmp_float1(float %a) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_float1
-; CHECK: fcmp s0, #0.0
-; CHECK: cset w0, ne
- %cmp = fcmp une float %a, 0.000000e+00
- ret i1 %cmp
-}
-
-define i1 @fcmp_float2(float %a, float %b) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_float2
-; CHECK: fcmp s0, s1
-; CHECK: cset w0, ne
- %cmp = fcmp une float %a, %b
- ret i1 %cmp
-}
-
-define i1 @fcmp_double1(double %a) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_double1
-; CHECK: fcmp d0, #0.0
-; CHECK: cset w0, ne
- %cmp = fcmp une double %a, 0.000000e+00
- ret i1 %cmp
-}
-
-define i1 @fcmp_double2(double %a, double %b) nounwind ssp {
-entry:
-; CHECK-LABEL: @fcmp_double2
-; CHECK: fcmp d0, d1
-; CHECK: cset w0, ne
- %cmp = fcmp une double %a, %b
- ret i1 %cmp
-}
-
-; Check each fcmp condition
-define float @fcmp_oeq(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_oeq
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
-
- %cmp = fcmp oeq float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ogt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ogt
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
-
- %cmp = fcmp ogt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_oge(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_oge
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
-
- %cmp = fcmp oge float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_olt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_olt
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
-
- %cmp = fcmp olt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ole(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ole
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
-
- %cmp = fcmp ole float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ord(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ord
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
- %cmp = fcmp ord float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_uno(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_uno
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
- %cmp = fcmp uno float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ugt(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ugt
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
- %cmp = fcmp ugt float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_uge(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_uge
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
- %cmp = fcmp uge float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ult(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ult
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
- %cmp = fcmp ult float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_ule(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ule
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], le
- %cmp = fcmp ule float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-define float @fcmp_une(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_une
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ne
- %cmp = fcmp une float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-; Possible opportunity for improvement. See comment in
-; ARM64TargetLowering::LowerSETCC()
-define float @fcmp_one(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_one
-; fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], mi
-; CHECK: fcsel s0, s[[ONE]], [[TMP]], gt
- %cmp = fcmp one float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
-
-; Possible opportunity for improvement. See comment in
-; ARM64TargetLowering::LowerSETCC()
-define float @fcmp_ueq(float %a, float %b) nounwind ssp {
-; CHECK-LABEL: @fcmp_ueq
-; CHECK: fcmp s0, s1
-; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
-; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
-; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], eq
-; CHECK: fcsel s0, s[[ONE]], [[TMP]], vs
- %cmp = fcmp ueq float %a, %b
- %conv = uitofp i1 %cmp to float
- ret float %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fcopysign.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fcopysign.ll (removed)
@@ -1,51 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-
-; rdar://9332258
-
-define float @test1(float %x, float %y) nounwind {
-entry:
-; CHECK-LABEL: test1:
-; CHECK: movi.4s v2, #0x80, lsl #24
-; CHECK: bit.16b v0, v1, v2
- %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
- ret float %0
-}
-
-define double @test2(double %x, double %y) nounwind {
-entry:
-; CHECK-LABEL: test2:
-; CHECK: movi.2d v2, #0
-; CHECK: fneg.2d v2, v2
-; CHECK: bit.16b v0, v1, v2
- %0 = tail call double @copysign(double %x, double %y) nounwind readnone
- ret double %0
-}
-
-; rdar://9545768
-define double @test3(double %a, float %b, float %c) nounwind {
-; CHECK-LABEL: test3:
-; CHECK: fcvt d1, s1
-; CHECK: fneg.2d v2, v{{[0-9]+}}
-; CHECK: bit.16b v0, v1, v2
- %tmp1 = fadd float %b, %c
- %tmp2 = fpext float %tmp1 to double
- %tmp = tail call double @copysign( double %a, double %tmp2 ) nounwind readnone
- ret double %tmp
-}
-
-define float @test4() nounwind {
-entry:
-; CHECK-LABEL: test4:
-; CHECK: fcvt s0, d0
-; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24
-; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
- %0 = tail call double (...)* @bar() nounwind
- %1 = fptrunc double %0 to float
- %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
- %3 = fadd float %1, %2
- ret float %3
-}
-
-declare double @bar(...)
-declare double @copysign(double, double) nounwind readnone
-declare float @copysignf(float, float) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fixed-point-scalar-cvt-dagcombine.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-; DAGCombine to transform a conversion of an extract_vector_elt to an
-; extract_vector_elt of a conversion, which saves a round trip of copies
-; of the value to a GPR and back to and FPR.
-; rdar://11855286
-define double @foo0(<2 x i64> %a) nounwind {
-; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9
-; CHECK-NEXT: ins.d v0[0], [[REG]][1]
- %vecext = extractelement <2 x i64> %a, i32 1
- %fcvt_n = tail call double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
- ret double %fcvt_n
-}
-
-declare double @llvm.arm64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/fmadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fmadd.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fmadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fmadd.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc -march=arm64 < %s | FileCheck %s
-
-define float @fma32(float %a, float %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fma32:
-; CHECK: fmadd s0, s0, s1, s2
- %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
- ret float %0
-}
-
-define float @fnma32(float %a, float %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fnma32:
-; CHECK: fnmadd s0, s0, s1, s2
- %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
- %mul = fmul float %0, -1.000000e+00
- ret float %mul
-}
-
-define float @fms32(float %a, float %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fms32:
-; CHECK: fmsub s0, s0, s1, s2
- %mul = fmul float %b, -1.000000e+00
- %0 = tail call float @llvm.fma.f32(float %a, float %mul, float %c)
- ret float %0
-}
-
-define float @fms32_com(float %a, float %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fms32_com:
-; CHECK: fmsub s0, s1, s0, s2
- %mul = fmul float %b, -1.000000e+00
- %0 = tail call float @llvm.fma.f32(float %mul, float %a, float %c)
- ret float %0
-}
-
-define float @fnms32(float %a, float %b, float %c) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: fnms32:
-; CHECK: fnmsub s0, s0, s1, s2
- %mul = fmul float %c, -1.000000e+00
- %0 = tail call float @llvm.fma.f32(float %a, float %b, float %mul)
- ret float %0
-}
-
-define double @fma64(double %a, double %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fma64:
-; CHECK: fmadd d0, d0, d1, d2
-entry:
- %0 = tail call double @llvm.fma.f64(double %a, double %b, double %c)
- ret double %0
-}
-
-define double @fnma64(double %a, double %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fnma64:
-; CHECK: fnmadd d0, d0, d1, d2
-entry:
- %0 = tail call double @llvm.fma.f64(double %a, double %b, double %c)
- %mul = fmul double %0, -1.000000e+00
- ret double %mul
-}
-
-define double @fms64(double %a, double %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fms64:
-; CHECK: fmsub d0, d0, d1, d2
-entry:
- %mul = fmul double %b, -1.000000e+00
- %0 = tail call double @llvm.fma.f64(double %a, double %mul, double %c)
- ret double %0
-}
-
-define double @fms64_com(double %a, double %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fms64_com:
-; CHECK: fmsub d0, d1, d0, d2
-entry:
- %mul = fmul double %b, -1.000000e+00
- %0 = tail call double @llvm.fma.f64(double %mul, double %a, double %c)
- ret double %0
-}
-
-define double @fnms64(double %a, double %b, double %c) nounwind readnone ssp {
-; CHECK-LABEL: fnms64:
-; CHECK: fnmsub d0, d0, d1, d2
-entry:
- %mul = fmul double %c, -1.000000e+00
- %0 = tail call double @llvm.fma.f64(double %a, double %b, double %mul)
- ret double %0
-}
-
-declare float @llvm.fma.f32(float, float, float) nounwind readnone
-declare double @llvm.fma.f64(double, double, double) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/fmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fmax.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fmax.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fmax.ll (removed)
@@ -1,34 +0,0 @@
-; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s
-
-define double @test_direct(float %in) #1 {
-; CHECK-LABEL: test_direct:
- %cmp = fcmp olt float %in, 0.000000e+00
- %longer = fpext float %in to double
- %val = select i1 %cmp, double 0.000000e+00, double %longer
- ret double %val
-
-; CHECK: fmax
-}
-
-define double @test_cross(float %in) #1 {
-; CHECK-LABEL: test_cross:
- %cmp = fcmp olt float %in, 0.000000e+00
- %longer = fpext float %in to double
- %val = select i1 %cmp, double %longer, double 0.000000e+00
- ret double %val
-
-; CHECK: fmin
-}
-
-; This isn't a min or a max, but passes the first condition for swapping the
-; results. Make sure they're put back before we resort to the normal fcsel.
-define float @test_cross_fail(float %lhs, float %rhs) {
-; CHECK-LABEL: test_cross_fail:
- %tst = fcmp une float %lhs, %rhs
- %res = select i1 %tst, float %rhs, float %lhs
- ret float %res
-
- ; The register allocator would have to decide to be deliberately obtuse before
- ; other register were used.
-; CHECK: fcsel s0, s1, s0, ne
-}
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/ARM64/fminv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fminv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fminv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fminv.ll (removed)
@@ -1,101 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-
-define float @test_fminv_v2f32(<2 x float> %in) {
-; CHECK: test_fminv_v2f32:
-; CHECK: fminp s0, v0.2s
- %min = call float @llvm.arm64.neon.fminv.f32.v2f32(<2 x float> %in)
- ret float %min
-}
-
-define float @test_fminv_v4f32(<4 x float> %in) {
-; CHECK: test_fminv_v4f32:
-; CHECK: fminv s0, v0.4s
- %min = call float @llvm.arm64.neon.fminv.f32.v4f32(<4 x float> %in)
- ret float %min
-}
-
-define double @test_fminv_v2f64(<2 x double> %in) {
-; CHECK: test_fminv_v2f64:
-; CHECK: fminp d0, v0.2d
- %min = call double @llvm.arm64.neon.fminv.f64.v2f64(<2 x double> %in)
- ret double %min
-}
-
-declare float @llvm.arm64.neon.fminv.f32.v2f32(<2 x float>)
-declare float @llvm.arm64.neon.fminv.f32.v4f32(<4 x float>)
-declare double @llvm.arm64.neon.fminv.f64.v2f64(<2 x double>)
-
-define float @test_fmaxv_v2f32(<2 x float> %in) {
-; CHECK: test_fmaxv_v2f32:
-; CHECK: fmaxp s0, v0.2s
- %max = call float @llvm.arm64.neon.fmaxv.f32.v2f32(<2 x float> %in)
- ret float %max
-}
-
-define float @test_fmaxv_v4f32(<4 x float> %in) {
-; CHECK: test_fmaxv_v4f32:
-; CHECK: fmaxv s0, v0.4s
- %max = call float @llvm.arm64.neon.fmaxv.f32.v4f32(<4 x float> %in)
- ret float %max
-}
-
-define double @test_fmaxv_v2f64(<2 x double> %in) {
-; CHECK: test_fmaxv_v2f64:
-; CHECK: fmaxp d0, v0.2d
- %max = call double @llvm.arm64.neon.fmaxv.f64.v2f64(<2 x double> %in)
- ret double %max
-}
-
-declare float @llvm.arm64.neon.fmaxv.f32.v2f32(<2 x float>)
-declare float @llvm.arm64.neon.fmaxv.f32.v4f32(<4 x float>)
-declare double @llvm.arm64.neon.fmaxv.f64.v2f64(<2 x double>)
-
-define float @test_fminnmv_v2f32(<2 x float> %in) {
-; CHECK: test_fminnmv_v2f32:
-; CHECK: fminnmp s0, v0.2s
- %minnm = call float @llvm.arm64.neon.fminnmv.f32.v2f32(<2 x float> %in)
- ret float %minnm
-}
-
-define float @test_fminnmv_v4f32(<4 x float> %in) {
-; CHECK: test_fminnmv_v4f32:
-; CHECK: fminnmv s0, v0.4s
- %minnm = call float @llvm.arm64.neon.fminnmv.f32.v4f32(<4 x float> %in)
- ret float %minnm
-}
-
-define double @test_fminnmv_v2f64(<2 x double> %in) {
-; CHECK: test_fminnmv_v2f64:
-; CHECK: fminnmp d0, v0.2d
- %minnm = call double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double> %in)
- ret double %minnm
-}
-
-declare float @llvm.arm64.neon.fminnmv.f32.v2f32(<2 x float>)
-declare float @llvm.arm64.neon.fminnmv.f32.v4f32(<4 x float>)
-declare double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double>)
-
-define float @test_fmaxnmv_v2f32(<2 x float> %in) {
-; CHECK: test_fmaxnmv_v2f32:
-; CHECK: fmaxnmp s0, v0.2s
- %maxnm = call float @llvm.arm64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)
- ret float %maxnm
-}
-
-define float @test_fmaxnmv_v4f32(<4 x float> %in) {
-; CHECK: test_fmaxnmv_v4f32:
-; CHECK: fmaxnmv s0, v0.4s
- %maxnm = call float @llvm.arm64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)
- ret float %maxnm
-}
-
-define double @test_fmaxnmv_v2f64(<2 x double> %in) {
-; CHECK: test_fmaxnmv_v2f64:
-; CHECK: fmaxnmp d0, v0.2d
- %maxnm = call double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
- ret double %maxnm
-}
-
-declare float @llvm.arm64.neon.fmaxnmv.f32.v2f32(<2 x float>)
-declare float @llvm.arm64.neon.fmaxnmv.f32.v4f32(<4 x float>)
-declare double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double>)
Removed: llvm/trunk/test/CodeGen/ARM64/fmuladd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fmuladd.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fmuladd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fmuladd.ll (removed)
@@ -1,88 +0,0 @@
-; RUN: llc -asm-verbose=false < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define float @test_f32(float* %A, float* %B, float* %C) nounwind {
-;CHECK-LABEL: test_f32:
-;CHECK: fmadd
-;CHECK-NOT: fmadd
- %tmp1 = load float* %A
- %tmp2 = load float* %B
- %tmp3 = load float* %C
- %tmp4 = call float @llvm.fmuladd.f32(float %tmp1, float %tmp2, float %tmp3)
- ret float %tmp4
-}
-
-define <2 x float> @test_v2f32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: test_v2f32:
-;CHECK: fmla.2s
-;CHECK-NOT: fmla.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = load <2 x float>* %C
- %tmp4 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3)
- ret <2 x float> %tmp4
-}
-
-define <4 x float> @test_v4f32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: test_v4f32:
-;CHECK: fmla.4s
-;CHECK-NOT: fmla.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = load <4 x float>* %C
- %tmp4 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3)
- ret <4 x float> %tmp4
-}
-
-define <8 x float> @test_v8f32(<8 x float>* %A, <8 x float>* %B, <8 x float>* %C) nounwind {
-;CHECK-LABEL: test_v8f32:
-;CHECK: fmla.4s
-;CHECK: fmla.4s
-;CHECK-NOT: fmla.4s
- %tmp1 = load <8 x float>* %A
- %tmp2 = load <8 x float>* %B
- %tmp3 = load <8 x float>* %C
- %tmp4 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %tmp1, <8 x float> %tmp2, <8 x float> %tmp3)
- ret <8 x float> %tmp4
-}
-
-define double @test_f64(double* %A, double* %B, double* %C) nounwind {
-;CHECK-LABEL: test_f64:
-;CHECK: fmadd
-;CHECK-NOT: fmadd
- %tmp1 = load double* %A
- %tmp2 = load double* %B
- %tmp3 = load double* %C
- %tmp4 = call double @llvm.fmuladd.f64(double %tmp1, double %tmp2, double %tmp3)
- ret double %tmp4
-}
-
-define <2 x double> @test_v2f64(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
-;CHECK-LABEL: test_v2f64:
-;CHECK: fmla.2d
-;CHECK-NOT: fmla.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = load <2 x double>* %C
- %tmp4 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3)
- ret <2 x double> %tmp4
-}
-
-define <4 x double> @test_v4f64(<4 x double>* %A, <4 x double>* %B, <4 x double>* %C) nounwind {
-;CHECK-LABEL: test_v4f64:
-;CHECK: fmla.2d
-;CHECK: fmla.2d
-;CHECK-NOT: fmla.2d
- %tmp1 = load <4 x double>* %A
- %tmp2 = load <4 x double>* %B
- %tmp3 = load <4 x double>* %C
- %tmp4 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %tmp1, <4 x double> %tmp2, <4 x double> %tmp3)
- ret <4 x double> %tmp4
-}
-
-declare float @llvm.fmuladd.f32(float, float, float) nounwind readnone
-declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
-declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
-declare double @llvm.fmuladd.f64(double, double, double) nounwind readnone
-declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
-declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/fold-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fold-address.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fold-address.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fold-address.ll (removed)
@@ -1,79 +0,0 @@
-; RUN: llc < %s -O2 -mtriple=arm64-apple-darwin | FileCheck %s
-
-%0 = type opaque
-%struct.CGRect = type { %struct.CGPoint, %struct.CGSize }
-%struct.CGPoint = type { double, double }
-%struct.CGSize = type { double, double }
-
-@"OBJC_IVAR_$_UIScreen._bounds" = external hidden global i64, section "__DATA, __objc_ivar", align 8
-
-define hidden %struct.CGRect @nofold(%0* nocapture %self, i8* nocapture %_cmd) nounwind readonly optsize ssp {
-entry:
-; CHECK-LABEL: nofold:
-; CHECK: add x[[REG:[0-9]+]], x0, x{{[0-9]+}}
-; CHECK: ldp d0, d1, [x[[REG]]]
-; CHECK: ldp d2, d3, [x[[REG]], #16]
-; CHECK: ret
- %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
- %0 = bitcast %0* %self to i8*
- %add.ptr = getelementptr inbounds i8* %0, i64 %ivar
- %add.ptr10.0 = bitcast i8* %add.ptr to double*
- %tmp11 = load double* %add.ptr10.0, align 8
- %add.ptr.sum = add i64 %ivar, 8
- %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum
- %1 = bitcast i8* %add.ptr10.1 to double*
- %tmp12 = load double* %1, align 8
- %add.ptr.sum17 = add i64 %ivar, 16
- %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum17
- %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double*
- %tmp = load double* %add.ptr4.1.0, align 8
- %add.ptr4.1.sum = add i64 %ivar, 24
- %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %add.ptr4.1.sum
- %2 = bitcast i8* %add.ptr4.1.1 to double*
- %tmp5 = load double* %2, align 8
- %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0
- %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1
- %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0
- %insert7 = insertvalue %struct.CGSize undef, double %tmp, 0
- %insert9 = insertvalue %struct.CGSize %insert7, double %tmp5, 1
- %insert3 = insertvalue %struct.CGRect %insert, %struct.CGSize %insert9, 1
- ret %struct.CGRect %insert3
-}
-
-define hidden %struct.CGRect @fold(%0* nocapture %self, i8* nocapture %_cmd) nounwind readonly optsize ssp {
-entry:
-; CHECK-LABEL: fold:
-; CHECK: ldr d0, [x0, x{{[0-9]+}}]
-; CHECK-NOT: add x0, x0, x1
-; CHECK: ret
- %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4
- %0 = bitcast %0* %self to i8*
- %add.ptr = getelementptr inbounds i8* %0, i64 %ivar
- %add.ptr10.0 = bitcast i8* %add.ptr to double*
- %tmp11 = load double* %add.ptr10.0, align 8
- %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %ivar
- %1 = bitcast i8* %add.ptr10.1 to double*
- %tmp12 = load double* %1, align 8
- %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %ivar
- %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double*
- %tmp = load double* %add.ptr4.1.0, align 8
- %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %ivar
- %2 = bitcast i8* %add.ptr4.1.1 to double*
- %tmp5 = load double* %2, align 8
- %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0
- %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1
- %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0
- %insert7 = insertvalue %struct.CGSize undef, double %tmp, 0
- %insert9 = insertvalue %struct.CGSize %insert7, double %tmp5, 1
- %insert3 = insertvalue %struct.CGRect %insert, %struct.CGSize %insert9, 1
- ret %struct.CGRect %insert3
-}
-
-
-!llvm.module.flags = !{!0, !1, !2, !3}
-
-!0 = metadata !{i32 1, metadata !"Objective-C Version", i32 2}
-!1 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0}
-!2 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"}
-!3 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0}
-!4 = metadata !{}
Removed: llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fold-lsl.ll (removed)
@@ -1,79 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-;
-; <rdar://problem/14486451>
-
-%struct.a = type [256 x i16]
-%struct.b = type [256 x i32]
-%struct.c = type [256 x i64]
-
-define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind {
-; CHECK-LABEL: load_halfword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldrh w0, [x0, [[REG]], lsl #1]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
- %result = load i16* %arrayidx86, align 2
- ret i16 %result
-}
-
-define i32 @load_word(%struct.b* %ctx, i32 %xor72) nounwind {
-; CHECK-LABEL: load_word:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldr w0, [x0, [[REG]], lsl #2]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
- %result = load i32* %arrayidx86, align 4
- ret i32 %result
-}
-
-define i64 @load_doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
-; CHECK-LABEL: load_doubleword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: ldr x0, [x0, [[REG]], lsl #3]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
- %result = load i64* %arrayidx86, align 8
- ret i64 %result
-}
-
-define void @store_halfword(%struct.a* %ctx, i32 %xor72, i16 %val) nounwind {
-; CHECK-LABEL: store_halfword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: strh w2, [x0, [[REG]], lsl #1]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83
- store i16 %val, i16* %arrayidx86, align 8
- ret void
-}
-
-define void @store_word(%struct.b* %ctx, i32 %xor72, i32 %val) nounwind {
-; CHECK-LABEL: store_word:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: str w2, [x0, [[REG]], lsl #2]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83
- store i32 %val, i32* %arrayidx86, align 8
- ret void
-}
-
-define void @store_doubleword(%struct.c* %ctx, i32 %xor72, i64 %val) nounwind {
-; CHECK-LABEL: store_doubleword:
-; CHECK: ubfx [[REG:x[0-9]+]], x1, #9, #8
-; CHECK: str x2, [x0, [[REG]], lsl #3]
- %shr81 = lshr i32 %xor72, 9
- %conv82 = zext i32 %shr81 to i64
- %idxprom83 = and i64 %conv82, 255
- %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83
- store i64 %val, i64* %arrayidx86, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp-contract-zero.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -mtriple=arm64 -fp-contract=fast -o - %s | FileCheck %s
-
-
-; Make sure we don't try to fold an fneg into +0.0, creating an illegal constant
-; -0.0. It's also good, though not essential, that we don't resort to a litpool.
-define double @test_fms_fold(double %a, double %b) {
-; CHECK-LABEL: test_fms_fold:
-; CHECK: fmov {{d[0-9]+}}, xzr
-; CHECK: ret
- %mul = fmul double %a, 0.000000e+00
- %mul1 = fmul double %b, 0.000000e+00
- %sub = fsub double %mul, %mul1
- ret double %sub
-}
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/ARM64/fp-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp-imm.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp-imm.ll (removed)
@@ -1,32 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-
-; CHECK: literal8
-; CHECK: .quad 4614256656552045848
-define double @foo() {
-; CHECK: _foo:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0 at PAGE
-; CHECK: ldr d0, [x[[REG]], lCPI0_0 at PAGEOFF]
-; CHECK-NEXT: ret
- ret double 0x400921FB54442D18
-}
-
-; CHECK: literal4
-; CHECK: .long 1078530011
-define float @bar() {
-; CHECK: _bar:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0 at PAGE
-; CHECK: ldr s0, [x[[REG]], lCPI1_0 at PAGEOFF]
-; CHECK-NEXT: ret
- ret float 0x400921FB60000000
-}
-
-; CHECK: literal16
-; CHECK: .quad 0
-; CHECK: .quad 0
-define fp128 @baz() {
-; CHECK: _baz:
-; CHECK: adrp x[[REG:[0-9]+]], lCPI2_0 at PAGE
-; CHECK: ldr q0, [x[[REG]], lCPI2_0 at PAGEOFF]
-; CHECK-NEXT: ret
- ret fp128 0xL00000000000000000000000000000000
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp.ll (removed)
@@ -1,8 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define float @t1(i1 %a, float %b, float %c) nounwind {
-; CHECK: t1
-; CHECK: fcsel s0, s0, s1, ne
- %sel = select i1 %a, float %b, float %c
- ret float %sel
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp128-folding.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s
-declare void @bar(i8*, i8*, i32*)
-
-; SelectionDAG used to try to fold some fp128 operations using the ppc128 type,
-; which is not supported.
-
-define fp128 @test_folding() {
-; CHECK-LABEL: test_folding:
- %l = alloca i32
- store i32 42, i32* %l
- %val = load i32* %l
- %fpval = sitofp i32 %val to fp128
- ; If the value is loaded from a constant pool into an fp128, it's been folded
- ; successfully.
-; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}},
- ret fp128 %fpval
-}
Removed: llvm/trunk/test/CodeGen/ARM64/fp128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/fp128.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/fp128.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/fp128.ll (removed)
@@ -1,273 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone < %s | FileCheck %s
-
- at lhs = global fp128 zeroinitializer, align 16
- at rhs = global fp128 zeroinitializer, align 16
-
-define fp128 @test_add() {
-; CHECK-LABEL: test_add:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- %val = fadd fp128 %lhs, %rhs
-; CHECK: bl __addtf3
- ret fp128 %val
-}
-
-define fp128 @test_sub() {
-; CHECK-LABEL: test_sub:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- %val = fsub fp128 %lhs, %rhs
-; CHECK: bl __subtf3
- ret fp128 %val
-}
-
-define fp128 @test_mul() {
-; CHECK-LABEL: test_mul:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- %val = fmul fp128 %lhs, %rhs
-; CHECK: bl __multf3
- ret fp128 %val
-}
-
-define fp128 @test_div() {
-; CHECK-LABEL: test_div:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- %val = fdiv fp128 %lhs, %rhs
-; CHECK: bl __divtf3
- ret fp128 %val
-}
-
- at var32 = global i32 0
- at var64 = global i64 0
-
-define void @test_fptosi() {
-; CHECK-LABEL: test_fptosi:
- %val = load fp128* @lhs, align 16
-
- %val32 = fptosi fp128 %val to i32
- store i32 %val32, i32* @var32
-; CHECK: bl __fixtfsi
-
- %val64 = fptosi fp128 %val to i64
- store i64 %val64, i64* @var64
-; CHECK: bl __fixtfdi
-
- ret void
-}
-
-define void @test_fptoui() {
-; CHECK-LABEL: test_fptoui:
- %val = load fp128* @lhs, align 16
-
- %val32 = fptoui fp128 %val to i32
- store i32 %val32, i32* @var32
-; CHECK: bl __fixunstfsi
-
- %val64 = fptoui fp128 %val to i64
- store i64 %val64, i64* @var64
-; CHECK: bl __fixunstfdi
-
- ret void
-}
-
-define void @test_sitofp() {
-; CHECK-LABEL: test_sitofp:
-
- %src32 = load i32* @var32
- %val32 = sitofp i32 %src32 to fp128
- store volatile fp128 %val32, fp128* @lhs
-; CHECK: bl __floatsitf
-
- %src64 = load i64* @var64
- %val64 = sitofp i64 %src64 to fp128
- store volatile fp128 %val64, fp128* @lhs
-; CHECK: bl __floatditf
-
- ret void
-}
-
-define void @test_uitofp() {
-; CHECK-LABEL: test_uitofp:
-
- %src32 = load i32* @var32
- %val32 = uitofp i32 %src32 to fp128
- store volatile fp128 %val32, fp128* @lhs
-; CHECK: bl __floatunsitf
-
- %src64 = load i64* @var64
- %val64 = uitofp i64 %src64 to fp128
- store volatile fp128 %val64, fp128* @lhs
-; CHECK: bl __floatunditf
-
- ret void
-}
-
-define i1 @test_setcc1() {
-; CHECK-LABEL: test_setcc1:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
-; Technically, everything after the call to __letf2 is redundant, but we'll let
-; LLVM have its fun for now.
- %val = fcmp ole fp128 %lhs, %rhs
-; CHECK: bl __letf2
-; CHECK: cmp w0, #0
-; CHECK: cset w0, le
-
- ret i1 %val
-; CHECK: ret
-}
-
-define i1 @test_setcc2() {
-; CHECK-LABEL: test_setcc2:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- %val = fcmp ugt fp128 %lhs, %rhs
-; CHECK: bl __gttf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[GT:w[0-9]+]], gt
-
-; CHECK: bl __unordtf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[UNORDERED:w[0-9]+]], ne
-; CHECK: orr w0, [[UNORDERED]], [[GT]]
-
- ret i1 %val
-; CHECK: ret
-}
-
-define i32 @test_br_cc() {
-; CHECK-LABEL: test_br_cc:
-
- %lhs = load fp128* @lhs, align 16
- %rhs = load fp128* @rhs, align 16
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
-; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
-
- ; olt == !uge, which LLVM unfortunately "optimizes" this to.
- %cond = fcmp olt fp128 %lhs, %rhs
-; CHECK: bl __getf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[OGE:w[0-9]+]], ge
-
-; CHECK: bl __unordtf2
-; CHECK: cmp w0, #0
-; CHECK: cset [[UNORDERED:w[0-9]+]], ne
-
-; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
-; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]
- br i1 %cond, label %iftrue, label %iffalse
-
-iftrue:
- ret i32 42
-; CHECK-NEXT: BB#
-; CHECK-NEXT: movz w0, #0x2a
-; CHECK-NEXT: b [[REALRET:.LBB[0-9]+_[0-9]+]]
-
-iffalse:
- ret i32 29
-; CHECK: [[RET29]]:
-; CHECK-NEXT: movz w0, #0x1d
-; CHECK-NEXT: [[REALRET]]:
-; CHECK: ret
-}
-
-define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
-; CHECK-LABEL: test_select:
-
- %val = select i1 %cond, fp128 %lhs, fp128 %rhs
- store fp128 %val, fp128* @lhs, align 16
-; CHECK: tst w0, #0x1
-; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: BB#
-; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
-; CHECK-NEXT: [[IFFALSE]]:
-; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]
- ret void
-; CHECK: ret
-}
-
- at varfloat = global float 0.0, align 4
- at vardouble = global double 0.0, align 8
-
-define void @test_round() {
-; CHECK-LABEL: test_round:
-
- %val = load fp128* @lhs, align 16
-
- %float = fptrunc fp128 %val to float
- store float %float, float* @varfloat, align 4
-; CHECK: bl __trunctfsf2
-; CHECK: str s0, [{{x[0-9]+}}, :lo12:varfloat]
-
- %double = fptrunc fp128 %val to double
- store double %double, double* @vardouble, align 8
-; CHECK: bl __trunctfdf2
-; CHECK: str d0, [{{x[0-9]+}}, :lo12:vardouble]
-
- ret void
-}
-
-define void @test_extend() {
-; CHECK-LABEL: test_extend:
-
- %val = load fp128* @lhs, align 16
-
- %float = load float* @varfloat
- %fromfloat = fpext float %float to fp128
- store volatile fp128 %fromfloat, fp128* @lhs, align 16
-; CHECK: bl __extendsftf2
-; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
-
- %double = load double* @vardouble
- %fromdouble = fpext double %double to fp128
- store volatile fp128 %fromdouble, fp128* @lhs, align 16
-; CHECK: bl __extenddftf2
-; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
-
- ret void
-; CHECK: ret
-}
-
-define fp128 @test_neg(fp128 %in) {
-; CHECK: [[MINUS0:.LCPI[0-9]+_0]]:
-; Make sure the weird hex constant below *is* -0.0
-; CHECK-NEXT: fp128 -0
-
-; CHECK-LABEL: test_neg:
-
- ; Could in principle be optimized to fneg which we can't select, this makes
- ; sure that doesn't happen.
- %ret = fsub fp128 0xL00000000000000008000000000000000, %in
-; CHECK: mov v1.16b, v0.16b
-; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:[[MINUS0]]]
-; CHECK: bl __subtf3
-
- ret fp128 %ret
-; CHECK: ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/frame-index.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/frame-index.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/frame-index.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/frame-index.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
-; rdar://11935841
-
-define void @t1() nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK-NOT: add x{{[0-9]+}}, sp
-; CHECK: stp x28, x27, [sp, #-16]!
- %v = alloca [288 x i32], align 4
- unreachable
-}
Removed: llvm/trunk/test/CodeGen/ARM64/frameaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/frameaddr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/frameaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/frameaddr.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define i8* @t() nounwind {
-entry:
-; CHECK-LABEL: t:
-; CHECK: stp x29, x30, [sp, #-16]!
-; CHECK: mov x29, sp
-; CHECK: mov x0, x29
-; CHECK: ldp x29, x30, [sp], #16
-; CHECK: ret
- %0 = call i8* @llvm.frameaddress(i32 0)
- ret i8* %0
-}
-
-declare i8* @llvm.frameaddress(i32) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/global-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/global-address.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/global-address.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/global-address.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-; rdar://9618644
-
- at G = external global i32
-
-define i32 @test(i32 %off) nounwind {
-; CHECK-LABEL: test:
-; CHECK: adrp x[[REG:[0-9]+]], _G at GOTPAGE
-; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _G at GOTPAGEOFF]
-; CHECK: add w0, w[[REG2]], w0
- %tmp = ptrtoint i32* @G to i32
- %tmp1 = add i32 %tmp, %off
- ret i32 %tmp1
-}
Removed: llvm/trunk/test/CodeGen/ARM64/hello.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/hello.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/hello.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/hello.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix=CHECK-LINUX
-
-; CHECK-LABEL: main:
-; CHECK: stp x29, x30, [sp, #-16]!
-; CHECK-NEXT: mov x29, sp
-; CHECK-NEXT: sub sp, sp, #16
-; CHECK-NEXT: stur wzr, [x29, #-4]
-; CHECK: adrp x0, L_.str at PAGE
-; CHECK: add x0, x0, L_.str at PAGEOFF
-; CHECK-NEXT: bl _puts
-; CHECK-NEXT: mov sp, x29
-; CHECK-NEXT: ldp x29, x30, [sp], #16
-; CHECK-NEXT: ret
-
-; CHECK-LINUX-LABEL: main:
-; CHECK-LINUX: stp x29, x30, [sp, #-16]!
-; CHECK-LINUX-NEXT: mov x29, sp
-; CHECK-LINUX-NEXT: sub sp, sp, #16
-; CHECK-LINUX-NEXT: stur wzr, [x29, #-4]
-; CHECK-LINUX: adrp x0, .L.str
-; CHECK-LINUX: add x0, x0, :lo12:.L.str
-; CHECK-LINUX-NEXT: bl puts
-; CHECK-LINUX-NEXT: mov sp, x29
-; CHECK-LINUX-NEXT: ldp x29, x30, [sp], #16
-; CHECK-LINUX-NEXT: ret
-
- at .str = private unnamed_addr constant [7 x i8] c"hello\0A\00"
-
-define i32 @main() nounwind ssp {
-entry:
- %retval = alloca i32, align 4
- store i32 0, i32* %retval
- %call = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0))
- ret i32 %call
-}
-
-declare i32 @puts(i8*)
Removed: llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/i16-subreg-extract.ll (removed)
@@ -1,12 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define i32 @foo(<4 x i16>* %__a) nounwind {
-; CHECK-LABEL: foo:
-; CHECK: umov.h w{{[0-9]+}}, v{{[0-9]+}}[0]
- %tmp18 = load <4 x i16>* %__a, align 8
- %vget_lane = extractelement <4 x i16> %tmp18, i32 0
- %conv = zext i16 %vget_lane to i32
- %mul = mul nsw i32 3, %conv
- ret i32 %mul
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/icmp-opt.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-; Optimize (x > -1) to (x >= 0) etc.
-; Optimize (cmp (add / sub), 0): eliminate the subs used to update flag
-; for comparison only
-; rdar://10233472
-
-define i32 @t1(i64 %a) nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK-NOT: movn
-; CHECK: cmp x0, #0
-; CHECK: cset w0, ge
- %cmp = icmp sgt i64 %a, -1
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
Removed: llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/illegal-float-ops.ll (removed)
@@ -1,295 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
-
- at varfloat = global float 0.0
- at vardouble = global double 0.0
- at varfp128 = global fp128 zeroinitializer
-
-declare float @llvm.cos.f32(float)
-declare double @llvm.cos.f64(double)
-declare fp128 @llvm.cos.f128(fp128)
-
-define void @test_cos(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_cos:
-
- %cosfloat = call float @llvm.cos.f32(float %float)
- store float %cosfloat, float* @varfloat
-; CHECK: bl cosf
-
- %cosdouble = call double @llvm.cos.f64(double %double)
- store double %cosdouble, double* @vardouble
-; CHECK: bl cos
-
- %cosfp128 = call fp128 @llvm.cos.f128(fp128 %fp128)
- store fp128 %cosfp128, fp128* @varfp128
-; CHECK: bl cosl
-
- ret void
-}
-
-declare float @llvm.exp.f32(float)
-declare double @llvm.exp.f64(double)
-declare fp128 @llvm.exp.f128(fp128)
-
-define void @test_exp(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_exp:
-
- %expfloat = call float @llvm.exp.f32(float %float)
- store float %expfloat, float* @varfloat
-; CHECK: bl expf
-
- %expdouble = call double @llvm.exp.f64(double %double)
- store double %expdouble, double* @vardouble
-; CHECK: bl exp
-
- %expfp128 = call fp128 @llvm.exp.f128(fp128 %fp128)
- store fp128 %expfp128, fp128* @varfp128
-; CHECK: bl expl
-
- ret void
-}
-
-declare float @llvm.exp2.f32(float)
-declare double @llvm.exp2.f64(double)
-declare fp128 @llvm.exp2.f128(fp128)
-
-define void @test_exp2(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_exp2:
-
- %exp2float = call float @llvm.exp2.f32(float %float)
- store float %exp2float, float* @varfloat
-; CHECK: bl exp2f
-
- %exp2double = call double @llvm.exp2.f64(double %double)
- store double %exp2double, double* @vardouble
-; CHECK: bl exp2
-
- %exp2fp128 = call fp128 @llvm.exp2.f128(fp128 %fp128)
- store fp128 %exp2fp128, fp128* @varfp128
-; CHECK: bl exp2l
- ret void
-
-}
-
-declare float @llvm.log.f32(float)
-declare double @llvm.log.f64(double)
-declare fp128 @llvm.log.f128(fp128)
-
-define void @test_log(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_log:
-
- %logfloat = call float @llvm.log.f32(float %float)
- store float %logfloat, float* @varfloat
-; CHECK: bl logf
-
- %logdouble = call double @llvm.log.f64(double %double)
- store double %logdouble, double* @vardouble
-; CHECK: bl log
-
- %logfp128 = call fp128 @llvm.log.f128(fp128 %fp128)
- store fp128 %logfp128, fp128* @varfp128
-; CHECK: bl logl
-
- ret void
-}
-
-declare float @llvm.log2.f32(float)
-declare double @llvm.log2.f64(double)
-declare fp128 @llvm.log2.f128(fp128)
-
-define void @test_log2(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_log2:
-
- %log2float = call float @llvm.log2.f32(float %float)
- store float %log2float, float* @varfloat
-; CHECK: bl log2f
-
- %log2double = call double @llvm.log2.f64(double %double)
- store double %log2double, double* @vardouble
-; CHECK: bl log2
-
- %log2fp128 = call fp128 @llvm.log2.f128(fp128 %fp128)
- store fp128 %log2fp128, fp128* @varfp128
-; CHECK: bl log2l
- ret void
-
-}
-
-declare float @llvm.log10.f32(float)
-declare double @llvm.log10.f64(double)
-declare fp128 @llvm.log10.f128(fp128)
-
-define void @test_log10(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_log10:
-
- %log10float = call float @llvm.log10.f32(float %float)
- store float %log10float, float* @varfloat
-; CHECK: bl log10f
-
- %log10double = call double @llvm.log10.f64(double %double)
- store double %log10double, double* @vardouble
-; CHECK: bl log10
-
- %log10fp128 = call fp128 @llvm.log10.f128(fp128 %fp128)
- store fp128 %log10fp128, fp128* @varfp128
-; CHECK: bl log10l
-
- ret void
-}
-
-declare float @llvm.sin.f32(float)
-declare double @llvm.sin.f64(double)
-declare fp128 @llvm.sin.f128(fp128)
-
-define void @test_sin(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_sin:
-
- %sinfloat = call float @llvm.sin.f32(float %float)
- store float %sinfloat, float* @varfloat
-; CHECK: bl sinf
-
- %sindouble = call double @llvm.sin.f64(double %double)
- store double %sindouble, double* @vardouble
-; CHECK: bl sin
-
- %sinfp128 = call fp128 @llvm.sin.f128(fp128 %fp128)
- store fp128 %sinfp128, fp128* @varfp128
-; CHECK: bl sinl
- ret void
-
-}
-
-declare float @llvm.pow.f32(float, float)
-declare double @llvm.pow.f64(double, double)
-declare fp128 @llvm.pow.f128(fp128, fp128)
-
-define void @test_pow(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_pow:
-
- %powfloat = call float @llvm.pow.f32(float %float, float %float)
- store float %powfloat, float* @varfloat
-; CHECK: bl powf
-
- %powdouble = call double @llvm.pow.f64(double %double, double %double)
- store double %powdouble, double* @vardouble
-; CHECK: bl pow
-
- %powfp128 = call fp128 @llvm.pow.f128(fp128 %fp128, fp128 %fp128)
- store fp128 %powfp128, fp128* @varfp128
-; CHECK: bl powl
-
- ret void
-}
-
-declare float @llvm.powi.f32(float, i32)
-declare double @llvm.powi.f64(double, i32)
-declare fp128 @llvm.powi.f128(fp128, i32)
-
-define void @test_powi(float %float, double %double, i32 %exponent, fp128 %fp128) {
-; CHECK-LABEL: test_powi:
-
- %powifloat = call float @llvm.powi.f32(float %float, i32 %exponent)
- store float %powifloat, float* @varfloat
-; CHECK: bl __powisf2
-
- %powidouble = call double @llvm.powi.f64(double %double, i32 %exponent)
- store double %powidouble, double* @vardouble
-; CHECK: bl __powidf2
-
- %powifp128 = call fp128 @llvm.powi.f128(fp128 %fp128, i32 %exponent)
- store fp128 %powifp128, fp128* @varfp128
-; CHECK: bl __powitf2
- ret void
-
-}
-
-define void @test_frem(float %float, double %double, fp128 %fp128) {
-; CHECK-LABEL: test_frem:
-
- %fremfloat = frem float %float, %float
- store float %fremfloat, float* @varfloat
-; CHECK: bl fmodf
-
- %fremdouble = frem double %double, %double
- store double %fremdouble, double* @vardouble
-; CHECK: bl fmod
-
- %fremfp128 = frem fp128 %fp128, %fp128
- store fp128 %fremfp128, fp128* @varfp128
-; CHECK: bl fmodl
-
- ret void
-}
-
-declare fp128 @llvm.fma.f128(fp128, fp128, fp128)
-
-define void @test_fma(fp128 %fp128) {
-; CHECK-LABEL: test_fma:
-
- %fmafp128 = call fp128 @llvm.fma.f128(fp128 %fp128, fp128 %fp128, fp128 %fp128)
- store fp128 %fmafp128, fp128* @varfp128
-; CHECK: bl fmal
-
- ret void
-}
-
-declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
-
-define void @test_fmuladd(fp128 %fp128) {
-; CHECK-LABEL: test_fmuladd:
-
- %fmuladdfp128 = call fp128 @llvm.fmuladd.f128(fp128 %fp128, fp128 %fp128, fp128 %fp128)
- store fp128 %fmuladdfp128, fp128* @varfp128
-; CHECK-NOT: bl fmal
-; CHECK: bl __multf3
-; CHECK: bl __addtf3
-
- ret void
-}
-
-define i32 @test_fptosi32(fp128 %a) {
-; CHECK-LABEL: test_fptosi32:
-; CHECK: bl __fixtfsi
- %conv.i = fptosi fp128 %a to i32
- %b = add nsw i32 %conv.i, 48
- ret i32 %b
-}
-
-define i64 @test_fptosi64(fp128 %a) {
-; CHECK-LABEL: test_fptosi64:
-; CHECK: bl __fixtfdi
- %conv.i = fptosi fp128 %a to i64
- %b = add nsw i64 %conv.i, 48
- ret i64 %b
-}
-
-define i128 @test_fptosi128(fp128 %a) {
-; CHECK-LABEL: test_fptosi128:
-; CHECK: bl __fixtfti
- %conv.i = fptosi fp128 %a to i128
- %b = add nsw i128 %conv.i, 48
- ret i128 %b
-}
-
-define i32 @test_fptoui32(fp128 %a) {
-; CHECK-LABEL: test_fptoui32:
-; CHECK: bl __fixunstfsi
- %conv.i = fptoui fp128 %a to i32
- %b = add nsw i32 %conv.i, 48
- ret i32 %b
-}
-
-define i64 @test_fptoui64(fp128 %a) {
-; CHECK-LABEL: test_fptoui64:
-; CHECK: bl __fixunstfdi
- %conv.i = fptoui fp128 %a to i64
- %b = add nsw i64 %conv.i, 48
- ret i64 %b
-}
-
-define i128 @test_fptoui128(fp128 %a) {
-; CHECK-LABEL: test_fptoui128:
-; CHECK: bl __fixunstfti
- %conv.i = fptoui fp128 %a to i128
- %b = add nsw i128 %conv.i, 48
- ret i128 %b
-}
Removed: llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/indexed-memory.ll (removed)
@@ -1,351 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-redzone | FileCheck %s
-
-define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: store64:
-; CHECK: str x{{[0-9+]}}, [x{{[0-9+]}}], #8
-; CHECK: ret
- %tmp = load i64** %out, align 8
- %incdec.ptr = getelementptr inbounds i64* %tmp, i64 1
- store i64 %spacing, i64* %tmp, align 4
- store i64* %incdec.ptr, i64** %out, align 8
- ret void
-}
-
-define void @store32(i32** nocapture %out, i32 %index, i32 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: store32:
-; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4
-; CHECK: ret
- %tmp = load i32** %out, align 8
- %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1
- store i32 %spacing, i32* %tmp, align 4
- store i32* %incdec.ptr, i32** %out, align 8
- ret void
-}
-
-define void @store16(i16** nocapture %out, i16 %index, i16 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: store16:
-; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2
-; CHECK: ret
- %tmp = load i16** %out, align 8
- %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1
- store i16 %spacing, i16* %tmp, align 4
- store i16* %incdec.ptr, i16** %out, align 8
- ret void
-}
-
-define void @store8(i8** nocapture %out, i8 %index, i8 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: store8:
-; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1
-; CHECK: ret
- %tmp = load i8** %out, align 8
- %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1
- store i8 %spacing, i8* %tmp, align 4
- store i8* %incdec.ptr, i8** %out, align 8
- ret void
-}
-
-define void @truncst64to32(i32** nocapture %out, i32 %index, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: truncst64to32:
-; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4
-; CHECK: ret
- %tmp = load i32** %out, align 8
- %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1
- %trunc = trunc i64 %spacing to i32
- store i32 %trunc, i32* %tmp, align 4
- store i32* %incdec.ptr, i32** %out, align 8
- ret void
-}
-
-define void @truncst64to16(i16** nocapture %out, i16 %index, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: truncst64to16:
-; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2
-; CHECK: ret
- %tmp = load i16** %out, align 8
- %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1
- %trunc = trunc i64 %spacing to i16
- store i16 %trunc, i16* %tmp, align 4
- store i16* %incdec.ptr, i16** %out, align 8
- ret void
-}
-
-define void @truncst64to8(i8** nocapture %out, i8 %index, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: truncst64to8:
-; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1
-; CHECK: ret
- %tmp = load i8** %out, align 8
- %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1
- %trunc = trunc i64 %spacing to i8
- store i8 %trunc, i8* %tmp, align 4
- store i8* %incdec.ptr, i8** %out, align 8
- ret void
-}
-
-
-define void @storef32(float** nocapture %out, float %index, float %spacing) nounwind noinline ssp {
-; CHECK-LABEL: storef32:
-; CHECK: str s{{[0-9+]}}, [x{{[0-9+]}}], #4
-; CHECK: ret
- %tmp = load float** %out, align 8
- %incdec.ptr = getelementptr inbounds float* %tmp, i64 1
- store float %spacing, float* %tmp, align 4
- store float* %incdec.ptr, float** %out, align 8
- ret void
-}
-
-define void @storef64(double** nocapture %out, double %index, double %spacing) nounwind noinline ssp {
-; CHECK-LABEL: storef64:
-; CHECK: str d{{[0-9+]}}, [x{{[0-9+]}}], #8
-; CHECK: ret
- %tmp = load double** %out, align 8
- %incdec.ptr = getelementptr inbounds double* %tmp, i64 1
- store double %spacing, double* %tmp, align 4
- store double* %incdec.ptr, double** %out, align 8
- ret void
-}
-
-define double * @pref64(double** nocapture %out, double %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pref64:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: str d0, [x0, #32]!
-; CHECK-NEXT: ret
- %tmp = load double** %out, align 8
- %ptr = getelementptr inbounds double* %tmp, i64 4
- store double %spacing, double* %ptr, align 4
- ret double *%ptr
-}
-
-define float * @pref32(float** nocapture %out, float %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pref32:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: str s0, [x0, #12]!
-; CHECK-NEXT: ret
- %tmp = load float** %out, align 8
- %ptr = getelementptr inbounds float* %tmp, i64 3
- store float %spacing, float* %ptr, align 4
- ret float *%ptr
-}
-
-define i64 * @pre64(i64** nocapture %out, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pre64:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: str x1, [x0, #16]!
-; CHECK-NEXT: ret
- %tmp = load i64** %out, align 8
- %ptr = getelementptr inbounds i64* %tmp, i64 2
- store i64 %spacing, i64* %ptr, align 4
- ret i64 *%ptr
-}
-
-define i32 * @pre32(i32** nocapture %out, i32 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pre32:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: str w1, [x0, #8]!
-; CHECK-NEXT: ret
- %tmp = load i32** %out, align 8
- %ptr = getelementptr inbounds i32* %tmp, i64 2
- store i32 %spacing, i32* %ptr, align 4
- ret i32 *%ptr
-}
-
-define i16 * @pre16(i16** nocapture %out, i16 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pre16:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: strh w1, [x0, #4]!
-; CHECK-NEXT: ret
- %tmp = load i16** %out, align 8
- %ptr = getelementptr inbounds i16* %tmp, i64 2
- store i16 %spacing, i16* %ptr, align 4
- ret i16 *%ptr
-}
-
-define i8 * @pre8(i8** nocapture %out, i8 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pre8:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: strb w1, [x0, #2]!
-; CHECK-NEXT: ret
- %tmp = load i8** %out, align 8
- %ptr = getelementptr inbounds i8* %tmp, i64 2
- store i8 %spacing, i8* %ptr, align 4
- ret i8 *%ptr
-}
-
-define i32 * @pretrunc64to32(i32** nocapture %out, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pretrunc64to32:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: str w1, [x0, #8]!
-; CHECK-NEXT: ret
- %tmp = load i32** %out, align 8
- %ptr = getelementptr inbounds i32* %tmp, i64 2
- %trunc = trunc i64 %spacing to i32
- store i32 %trunc, i32* %ptr, align 4
- ret i32 *%ptr
-}
-
-define i16 * @pretrunc64to16(i16** nocapture %out, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pretrunc64to16:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: strh w1, [x0, #4]!
-; CHECK-NEXT: ret
- %tmp = load i16** %out, align 8
- %ptr = getelementptr inbounds i16* %tmp, i64 2
- %trunc = trunc i64 %spacing to i16
- store i16 %trunc, i16* %ptr, align 4
- ret i16 *%ptr
-}
-
-define i8 * @pretrunc64to8(i8** nocapture %out, i64 %spacing) nounwind noinline ssp {
-; CHECK-LABEL: pretrunc64to8:
-; CHECK: ldr x0, [x0]
-; CHECK-NEXT: strb w1, [x0, #2]!
-; CHECK-NEXT: ret
- %tmp = load i8** %out, align 8
- %ptr = getelementptr inbounds i8* %tmp, i64 2
- %trunc = trunc i64 %spacing to i8
- store i8 %trunc, i8* %ptr, align 4
- ret i8 *%ptr
-}
-
-;-----
-; Pre-indexed loads
-;-----
-define double* @preidxf64(double* %src, double* %out) {
-; CHECK-LABEL: preidxf64:
-; CHECK: ldr d0, [x0, #8]!
-; CHECK: str d0, [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds double* %src, i64 1
- %tmp = load double* %ptr, align 4
- store double %tmp, double* %out, align 4
- ret double* %ptr
-}
-
-define float* @preidxf32(float* %src, float* %out) {
-; CHECK-LABEL: preidxf32:
-; CHECK: ldr s0, [x0, #4]!
-; CHECK: str s0, [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds float* %src, i64 1
- %tmp = load float* %ptr, align 4
- store float %tmp, float* %out, align 4
- ret float* %ptr
-}
-
-define i64* @preidx64(i64* %src, i64* %out) {
-; CHECK-LABEL: preidx64:
-; CHECK: ldr x[[REG:[0-9]+]], [x0, #8]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i64* %src, i64 1
- %tmp = load i64* %ptr, align 4
- store i64 %tmp, i64* %out, align 4
- ret i64* %ptr
-}
-
-define i32* @preidx32(i32* %src, i32* %out) {
-; CHECK: ldr w[[REG:[0-9]+]], [x0, #4]!
-; CHECK: str w[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i32* %src, i64 1
- %tmp = load i32* %ptr, align 4
- store i32 %tmp, i32* %out, align 4
- ret i32* %ptr
-}
-
-define i16* @preidx16zext32(i16* %src, i32* %out) {
-; CHECK: ldrh w[[REG:[0-9]+]], [x0, #2]!
-; CHECK: str w[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i16* %src, i64 1
- %tmp = load i16* %ptr, align 4
- %ext = zext i16 %tmp to i32
- store i32 %ext, i32* %out, align 4
- ret i16* %ptr
-}
-
-define i16* @preidx16zext64(i16* %src, i64* %out) {
-; CHECK: ldrh w[[REG:[0-9]+]], [x0, #2]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i16* %src, i64 1
- %tmp = load i16* %ptr, align 4
- %ext = zext i16 %tmp to i64
- store i64 %ext, i64* %out, align 4
- ret i16* %ptr
-}
-
-define i8* @preidx8zext32(i8* %src, i32* %out) {
-; CHECK: ldrb w[[REG:[0-9]+]], [x0, #1]!
-; CHECK: str w[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i8* %src, i64 1
- %tmp = load i8* %ptr, align 4
- %ext = zext i8 %tmp to i32
- store i32 %ext, i32* %out, align 4
- ret i8* %ptr
-}
-
-define i8* @preidx8zext64(i8* %src, i64* %out) {
-; CHECK: ldrb w[[REG:[0-9]+]], [x0, #1]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i8* %src, i64 1
- %tmp = load i8* %ptr, align 4
- %ext = zext i8 %tmp to i64
- store i64 %ext, i64* %out, align 4
- ret i8* %ptr
-}
-
-define i32* @preidx32sext64(i32* %src, i64* %out) {
-; CHECK: ldrsw x[[REG:[0-9]+]], [x0, #4]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i32* %src, i64 1
- %tmp = load i32* %ptr, align 4
- %ext = sext i32 %tmp to i64
- store i64 %ext, i64* %out, align 8
- ret i32* %ptr
-}
-
-define i16* @preidx16sext32(i16* %src, i32* %out) {
-; CHECK: ldrsh w[[REG:[0-9]+]], [x0, #2]!
-; CHECK: str w[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i16* %src, i64 1
- %tmp = load i16* %ptr, align 4
- %ext = sext i16 %tmp to i32
- store i32 %ext, i32* %out, align 4
- ret i16* %ptr
-}
-
-define i16* @preidx16sext64(i16* %src, i64* %out) {
-; CHECK: ldrsh x[[REG:[0-9]+]], [x0, #2]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i16* %src, i64 1
- %tmp = load i16* %ptr, align 4
- %ext = sext i16 %tmp to i64
- store i64 %ext, i64* %out, align 4
- ret i16* %ptr
-}
-
-define i8* @preidx8sext32(i8* %src, i32* %out) {
-; CHECK: ldrsb w[[REG:[0-9]+]], [x0, #1]!
-; CHECK: str w[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i8* %src, i64 1
- %tmp = load i8* %ptr, align 4
- %ext = sext i8 %tmp to i32
- store i32 %ext, i32* %out, align 4
- ret i8* %ptr
-}
-
-define i8* @preidx8sext64(i8* %src, i64* %out) {
-; CHECK: ldrsb x[[REG:[0-9]+]], [x0, #1]!
-; CHECK: str x[[REG]], [x1]
-; CHECK: ret
- %ptr = getelementptr inbounds i8* %src, i64 1
- %tmp = load i8* %ptr, align 4
- %ext = sext i8 %tmp to i64
- store i64 %ext, i64* %out, align 4
- ret i8* %ptr
-}
Removed: llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst-2.ll (removed)
@@ -1,40 +0,0 @@
-; RUN: llc < %s
-
-; This used to assert with "Overran sorted position" in AssignTopologicalOrder
-; due to a cycle created in performPostLD1Combine.
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios7.0.0"
-
-; Function Attrs: nounwind ssp
-define void @f(double* %P1) #0 {
-entry:
- %arrayidx4 = getelementptr inbounds double* %P1, i64 1
- %0 = load double* %arrayidx4, align 8, !tbaa !1
- %1 = load double* %P1, align 8, !tbaa !1
- %2 = insertelement <2 x double> undef, double %0, i32 0
- %3 = insertelement <2 x double> %2, double %1, i32 1
- %4 = fsub <2 x double> zeroinitializer, %3
- %5 = fmul <2 x double> undef, %4
- %6 = extractelement <2 x double> %5, i32 0
- %cmp168 = fcmp olt double %6, undef
- br i1 %cmp168, label %if.then172, label %return
-
-if.then172: ; preds = %cond.end90
- %7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
- br label %return
-
-return: ; preds = %if.then172, %cond.end90, %entry
- ret void
-}
-
-; Function Attrs: nounwind readnone
-declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
-
-attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind readnone }
-
-!1 = metadata !{metadata !2, metadata !2, i64 0}
-!2 = metadata !{metadata !"double", metadata !3, i64 0}
-!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
-!4 = metadata !{metadata !"Simple C/C++ TBAA"}
Removed: llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/indexed-vector-ldst.ll (removed)
@@ -1,6174 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s
-
- at ptr = global i8* null
-
-define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) {
-; CHECK-LABEL: test_v8i8_pre_load:
-; CHECK: ldr d0, [x0, #40]!
- %newaddr = getelementptr <8 x i8>* %addr, i32 5
- %val = load <8 x i8>* %newaddr, align 8
- store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
- ret <8 x i8> %val
-}
-
-define <8 x i8> @test_v8i8_post_load(<8 x i8>* %addr) {
-; CHECK-LABEL: test_v8i8_post_load:
-; CHECK: ldr d0, [x0], #40
- %newaddr = getelementptr <8 x i8>* %addr, i32 5
- %val = load <8 x i8>* %addr, align 8
- store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
- ret <8 x i8> %val
-}
-
-define void @test_v8i8_pre_store(<8 x i8> %in, <8 x i8>* %addr) {
-; CHECK-LABEL: test_v8i8_pre_store:
-; CHECK: str d0, [x0, #40]!
- %newaddr = getelementptr <8 x i8>* %addr, i32 5
- store <8 x i8> %in, <8 x i8>* %newaddr, align 8
- store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
- ret void
-}
-
-define void @test_v8i8_post_store(<8 x i8> %in, <8 x i8>* %addr) {
-; CHECK-LABEL: test_v8i8_post_store:
-; CHECK: str d0, [x0], #40
- %newaddr = getelementptr <8 x i8>* %addr, i32 5
- store <8 x i8> %in, <8 x i8>* %addr, align 8
- store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**)
- ret void
-}
-
-define <4 x i16> @test_v4i16_pre_load(<4 x i16>* %addr) {
-; CHECK-LABEL: test_v4i16_pre_load:
-; CHECK: ldr d0, [x0, #40]!
- %newaddr = getelementptr <4 x i16>* %addr, i32 5
- %val = load <4 x i16>* %newaddr, align 8
- store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
- ret <4 x i16> %val
-}
-
-define <4 x i16> @test_v4i16_post_load(<4 x i16>* %addr) {
-; CHECK-LABEL: test_v4i16_post_load:
-; CHECK: ldr d0, [x0], #40
- %newaddr = getelementptr <4 x i16>* %addr, i32 5
- %val = load <4 x i16>* %addr, align 8
- store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
- ret <4 x i16> %val
-}
-
-define void @test_v4i16_pre_store(<4 x i16> %in, <4 x i16>* %addr) {
-; CHECK-LABEL: test_v4i16_pre_store:
-; CHECK: str d0, [x0, #40]!
- %newaddr = getelementptr <4 x i16>* %addr, i32 5
- store <4 x i16> %in, <4 x i16>* %newaddr, align 8
- store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
- ret void
-}
-
-define void @test_v4i16_post_store(<4 x i16> %in, <4 x i16>* %addr) {
-; CHECK-LABEL: test_v4i16_post_store:
-; CHECK: str d0, [x0], #40
- %newaddr = getelementptr <4 x i16>* %addr, i32 5
- store <4 x i16> %in, <4 x i16>* %addr, align 8
- store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**)
- ret void
-}
-
-define <2 x i32> @test_v2i32_pre_load(<2 x i32>* %addr) {
-; CHECK-LABEL: test_v2i32_pre_load:
-; CHECK: ldr d0, [x0, #40]!
- %newaddr = getelementptr <2 x i32>* %addr, i32 5
- %val = load <2 x i32>* %newaddr, align 8
- store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
- ret <2 x i32> %val
-}
-
-define <2 x i32> @test_v2i32_post_load(<2 x i32>* %addr) {
-; CHECK-LABEL: test_v2i32_post_load:
-; CHECK: ldr d0, [x0], #40
- %newaddr = getelementptr <2 x i32>* %addr, i32 5
- %val = load <2 x i32>* %addr, align 8
- store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
- ret <2 x i32> %val
-}
-
-define void @test_v2i32_pre_store(<2 x i32> %in, <2 x i32>* %addr) {
-; CHECK-LABEL: test_v2i32_pre_store:
-; CHECK: str d0, [x0, #40]!
- %newaddr = getelementptr <2 x i32>* %addr, i32 5
- store <2 x i32> %in, <2 x i32>* %newaddr, align 8
- store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
- ret void
-}
-
-define void @test_v2i32_post_store(<2 x i32> %in, <2 x i32>* %addr) {
-; CHECK-LABEL: test_v2i32_post_store:
-; CHECK: str d0, [x0], #40
- %newaddr = getelementptr <2 x i32>* %addr, i32 5
- store <2 x i32> %in, <2 x i32>* %addr, align 8
- store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**)
- ret void
-}
-
-define <2 x float> @test_v2f32_pre_load(<2 x float>* %addr) {
-; CHECK-LABEL: test_v2f32_pre_load:
-; CHECK: ldr d0, [x0, #40]!
- %newaddr = getelementptr <2 x float>* %addr, i32 5
- %val = load <2 x float>* %newaddr, align 8
- store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
- ret <2 x float> %val
-}
-
-define <2 x float> @test_v2f32_post_load(<2 x float>* %addr) {
-; CHECK-LABEL: test_v2f32_post_load:
-; CHECK: ldr d0, [x0], #40
- %newaddr = getelementptr <2 x float>* %addr, i32 5
- %val = load <2 x float>* %addr, align 8
- store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
- ret <2 x float> %val
-}
-
-define void @test_v2f32_pre_store(<2 x float> %in, <2 x float>* %addr) {
-; CHECK-LABEL: test_v2f32_pre_store:
-; CHECK: str d0, [x0, #40]!
- %newaddr = getelementptr <2 x float>* %addr, i32 5
- store <2 x float> %in, <2 x float>* %newaddr, align 8
- store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
- ret void
-}
-
-define void @test_v2f32_post_store(<2 x float> %in, <2 x float>* %addr) {
-; CHECK-LABEL: test_v2f32_post_store:
-; CHECK: str d0, [x0], #40
- %newaddr = getelementptr <2 x float>* %addr, i32 5
- store <2 x float> %in, <2 x float>* %addr, align 8
- store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**)
- ret void
-}
-
-define <1 x i64> @test_v1i64_pre_load(<1 x i64>* %addr) {
-; CHECK-LABEL: test_v1i64_pre_load:
-; CHECK: ldr d0, [x0, #40]!
- %newaddr = getelementptr <1 x i64>* %addr, i32 5
- %val = load <1 x i64>* %newaddr, align 8
- store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
- ret <1 x i64> %val
-}
-
-define <1 x i64> @test_v1i64_post_load(<1 x i64>* %addr) {
-; CHECK-LABEL: test_v1i64_post_load:
-; CHECK: ldr d0, [x0], #40
- %newaddr = getelementptr <1 x i64>* %addr, i32 5
- %val = load <1 x i64>* %addr, align 8
- store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
- ret <1 x i64> %val
-}
-
-define void @test_v1i64_pre_store(<1 x i64> %in, <1 x i64>* %addr) {
-; CHECK-LABEL: test_v1i64_pre_store:
-; CHECK: str d0, [x0, #40]!
- %newaddr = getelementptr <1 x i64>* %addr, i32 5
- store <1 x i64> %in, <1 x i64>* %newaddr, align 8
- store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
- ret void
-}
-
-define void @test_v1i64_post_store(<1 x i64> %in, <1 x i64>* %addr) {
-; CHECK-LABEL: test_v1i64_post_store:
-; CHECK: str d0, [x0], #40
- %newaddr = getelementptr <1 x i64>* %addr, i32 5
- store <1 x i64> %in, <1 x i64>* %addr, align 8
- store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**)
- ret void
-}
-
-define <16 x i8> @test_v16i8_pre_load(<16 x i8>* %addr) {
-; CHECK-LABEL: test_v16i8_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <16 x i8>* %addr, i32 5
- %val = load <16 x i8>* %newaddr, align 8
- store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
- ret <16 x i8> %val
-}
-
-define <16 x i8> @test_v16i8_post_load(<16 x i8>* %addr) {
-; CHECK-LABEL: test_v16i8_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <16 x i8>* %addr, i32 5
- %val = load <16 x i8>* %addr, align 8
- store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
- ret <16 x i8> %val
-}
-
-define void @test_v16i8_pre_store(<16 x i8> %in, <16 x i8>* %addr) {
-; CHECK-LABEL: test_v16i8_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <16 x i8>* %addr, i32 5
- store <16 x i8> %in, <16 x i8>* %newaddr, align 8
- store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
- ret void
-}
-
-define void @test_v16i8_post_store(<16 x i8> %in, <16 x i8>* %addr) {
-; CHECK-LABEL: test_v16i8_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <16 x i8>* %addr, i32 5
- store <16 x i8> %in, <16 x i8>* %addr, align 8
- store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**)
- ret void
-}
-
-define <8 x i16> @test_v8i16_pre_load(<8 x i16>* %addr) {
-; CHECK-LABEL: test_v8i16_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <8 x i16>* %addr, i32 5
- %val = load <8 x i16>* %newaddr, align 8
- store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
- ret <8 x i16> %val
-}
-
-define <8 x i16> @test_v8i16_post_load(<8 x i16>* %addr) {
-; CHECK-LABEL: test_v8i16_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <8 x i16>* %addr, i32 5
- %val = load <8 x i16>* %addr, align 8
- store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
- ret <8 x i16> %val
-}
-
-define void @test_v8i16_pre_store(<8 x i16> %in, <8 x i16>* %addr) {
-; CHECK-LABEL: test_v8i16_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <8 x i16>* %addr, i32 5
- store <8 x i16> %in, <8 x i16>* %newaddr, align 8
- store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
- ret void
-}
-
-define void @test_v8i16_post_store(<8 x i16> %in, <8 x i16>* %addr) {
-; CHECK-LABEL: test_v8i16_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <8 x i16>* %addr, i32 5
- store <8 x i16> %in, <8 x i16>* %addr, align 8
- store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**)
- ret void
-}
-
-define <4 x i32> @test_v4i32_pre_load(<4 x i32>* %addr) {
-; CHECK-LABEL: test_v4i32_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <4 x i32>* %addr, i32 5
- %val = load <4 x i32>* %newaddr, align 8
- store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
- ret <4 x i32> %val
-}
-
-define <4 x i32> @test_v4i32_post_load(<4 x i32>* %addr) {
-; CHECK-LABEL: test_v4i32_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <4 x i32>* %addr, i32 5
- %val = load <4 x i32>* %addr, align 8
- store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
- ret <4 x i32> %val
-}
-
-define void @test_v4i32_pre_store(<4 x i32> %in, <4 x i32>* %addr) {
-; CHECK-LABEL: test_v4i32_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <4 x i32>* %addr, i32 5
- store <4 x i32> %in, <4 x i32>* %newaddr, align 8
- store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
- ret void
-}
-
-define void @test_v4i32_post_store(<4 x i32> %in, <4 x i32>* %addr) {
-; CHECK-LABEL: test_v4i32_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <4 x i32>* %addr, i32 5
- store <4 x i32> %in, <4 x i32>* %addr, align 8
- store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**)
- ret void
-}
-
-
-define <4 x float> @test_v4f32_pre_load(<4 x float>* %addr) {
-; CHECK-LABEL: test_v4f32_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <4 x float>* %addr, i32 5
- %val = load <4 x float>* %newaddr, align 8
- store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
- ret <4 x float> %val
-}
-
-define <4 x float> @test_v4f32_post_load(<4 x float>* %addr) {
-; CHECK-LABEL: test_v4f32_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <4 x float>* %addr, i32 5
- %val = load <4 x float>* %addr, align 8
- store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
- ret <4 x float> %val
-}
-
-define void @test_v4f32_pre_store(<4 x float> %in, <4 x float>* %addr) {
-; CHECK-LABEL: test_v4f32_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <4 x float>* %addr, i32 5
- store <4 x float> %in, <4 x float>* %newaddr, align 8
- store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
- ret void
-}
-
-define void @test_v4f32_post_store(<4 x float> %in, <4 x float>* %addr) {
-; CHECK-LABEL: test_v4f32_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <4 x float>* %addr, i32 5
- store <4 x float> %in, <4 x float>* %addr, align 8
- store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**)
- ret void
-}
-
-
-define <2 x i64> @test_v2i64_pre_load(<2 x i64>* %addr) {
-; CHECK-LABEL: test_v2i64_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <2 x i64>* %addr, i32 5
- %val = load <2 x i64>* %newaddr, align 8
- store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
- ret <2 x i64> %val
-}
-
-define <2 x i64> @test_v2i64_post_load(<2 x i64>* %addr) {
-; CHECK-LABEL: test_v2i64_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <2 x i64>* %addr, i32 5
- %val = load <2 x i64>* %addr, align 8
- store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
- ret <2 x i64> %val
-}
-
-define void @test_v2i64_pre_store(<2 x i64> %in, <2 x i64>* %addr) {
-; CHECK-LABEL: test_v2i64_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <2 x i64>* %addr, i32 5
- store <2 x i64> %in, <2 x i64>* %newaddr, align 8
- store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
- ret void
-}
-
-define void @test_v2i64_post_store(<2 x i64> %in, <2 x i64>* %addr) {
-; CHECK-LABEL: test_v2i64_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <2 x i64>* %addr, i32 5
- store <2 x i64> %in, <2 x i64>* %addr, align 8
- store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**)
- ret void
-}
-
-
-define <2 x double> @test_v2f64_pre_load(<2 x double>* %addr) {
-; CHECK-LABEL: test_v2f64_pre_load:
-; CHECK: ldr q0, [x0, #80]!
- %newaddr = getelementptr <2 x double>* %addr, i32 5
- %val = load <2 x double>* %newaddr, align 8
- store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
- ret <2 x double> %val
-}
-
-define <2 x double> @test_v2f64_post_load(<2 x double>* %addr) {
-; CHECK-LABEL: test_v2f64_post_load:
-; CHECK: ldr q0, [x0], #80
- %newaddr = getelementptr <2 x double>* %addr, i32 5
- %val = load <2 x double>* %addr, align 8
- store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
- ret <2 x double> %val
-}
-
-define void @test_v2f64_pre_store(<2 x double> %in, <2 x double>* %addr) {
-; CHECK-LABEL: test_v2f64_pre_store:
-; CHECK: str q0, [x0, #80]!
- %newaddr = getelementptr <2 x double>* %addr, i32 5
- store <2 x double> %in, <2 x double>* %newaddr, align 8
- store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
- ret void
-}
-
-define void @test_v2f64_post_store(<2 x double> %in, <2 x double>* %addr) {
-; CHECK-LABEL: test_v2f64_post_store:
-; CHECK: str q0, [x0], #80
- %newaddr = getelementptr <2 x double>* %addr, i32 5
- store <2 x double> %in, <2 x double>* %addr, align 8
- store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**)
- ret void
-}
-
-define i8* @test_v16i8_post_imm_st1_lane(<16 x i8> %in, i8* %addr) {
-; CHECK-LABEL: test_v16i8_post_imm_st1_lane:
-; CHECK: st1.b { v0 }[3], [x0], #1
- %elt = extractelement <16 x i8> %in, i32 3
- store i8 %elt, i8* %addr
-
- %newaddr = getelementptr i8* %addr, i32 1
- ret i8* %newaddr
-}
-
-define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) {
-; CHECK-LABEL: test_v16i8_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
-; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <16 x i8> %in, i32 3
- store i8 %elt, i8* %addr
-
- %newaddr = getelementptr i8* %addr, i32 2
- ret i8* %newaddr
-}
-
-
-define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) {
-; CHECK-LABEL: test_v8i16_post_imm_st1_lane:
-; CHECK: st1.h { v0 }[3], [x0], #2
- %elt = extractelement <8 x i16> %in, i32 3
- store i16 %elt, i16* %addr
-
- %newaddr = getelementptr i16* %addr, i32 1
- ret i16* %newaddr
-}
-
-define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) {
-; CHECK-LABEL: test_v8i16_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
-; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <8 x i16> %in, i32 3
- store i16 %elt, i16* %addr
-
- %newaddr = getelementptr i16* %addr, i32 2
- ret i16* %newaddr
-}
-
-define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) {
-; CHECK-LABEL: test_v4i32_post_imm_st1_lane:
-; CHECK: st1.s { v0 }[3], [x0], #4
- %elt = extractelement <4 x i32> %in, i32 3
- store i32 %elt, i32* %addr
-
- %newaddr = getelementptr i32* %addr, i32 1
- ret i32* %newaddr
-}
-
-define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) {
-; CHECK-LABEL: test_v4i32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
-; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <4 x i32> %in, i32 3
- store i32 %elt, i32* %addr
-
- %newaddr = getelementptr i32* %addr, i32 2
- ret i32* %newaddr
-}
-
-define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) {
-; CHECK-LABEL: test_v4f32_post_imm_st1_lane:
-; CHECK: st1.s { v0 }[3], [x0], #4
- %elt = extractelement <4 x float> %in, i32 3
- store float %elt, float* %addr
-
- %newaddr = getelementptr float* %addr, i32 1
- ret float* %newaddr
-}
-
-define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) {
-; CHECK-LABEL: test_v4f32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
-; CHECK: st1.s { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <4 x float> %in, i32 3
- store float %elt, float* %addr
-
- %newaddr = getelementptr float* %addr, i32 2
- ret float* %newaddr
-}
-
-define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) {
-; CHECK-LABEL: test_v2i64_post_imm_st1_lane:
-; CHECK: st1.d { v0 }[1], [x0], #8
- %elt = extractelement <2 x i64> %in, i64 1
- store i64 %elt, i64* %addr
-
- %newaddr = getelementptr i64* %addr, i64 1
- ret i64* %newaddr
-}
-
-define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) {
-; CHECK-LABEL: test_v2i64_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
-; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
- %elt = extractelement <2 x i64> %in, i64 1
- store i64 %elt, i64* %addr
-
- %newaddr = getelementptr i64* %addr, i64 2
- ret i64* %newaddr
-}
-
-define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) {
-; CHECK-LABEL: test_v2f64_post_imm_st1_lane:
-; CHECK: st1.d { v0 }[1], [x0], #8
- %elt = extractelement <2 x double> %in, i32 1
- store double %elt, double* %addr
-
- %newaddr = getelementptr double* %addr, i32 1
- ret double* %newaddr
-}
-
-define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) {
-; CHECK-LABEL: test_v2f64_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x10
-; CHECK: st1.d { v0 }[1], [x0], x[[OFFSET]]
- %elt = extractelement <2 x double> %in, i32 1
- store double %elt, double* %addr
-
- %newaddr = getelementptr double* %addr, i32 2
- ret double* %newaddr
-}
-
-define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) {
-; CHECK-LABEL: test_v8i8_post_imm_st1_lane:
-; CHECK: st1.b { v0 }[3], [x0], #1
- %elt = extractelement <8 x i8> %in, i32 3
- store i8 %elt, i8* %addr
-
- %newaddr = getelementptr i8* %addr, i32 1
- ret i8* %newaddr
-}
-
-define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) {
-; CHECK-LABEL: test_v8i8_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x2
-; CHECK: st1.b { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <8 x i8> %in, i32 3
- store i8 %elt, i8* %addr
-
- %newaddr = getelementptr i8* %addr, i32 2
- ret i8* %newaddr
-}
-
-define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) {
-; CHECK-LABEL: test_v4i16_post_imm_st1_lane:
-; CHECK: st1.h { v0 }[3], [x0], #2
- %elt = extractelement <4 x i16> %in, i32 3
- store i16 %elt, i16* %addr
-
- %newaddr = getelementptr i16* %addr, i32 1
- ret i16* %newaddr
-}
-
-define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) {
-; CHECK-LABEL: test_v4i16_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x4
-; CHECK: st1.h { v0 }[3], [x0], x[[OFFSET]]
- %elt = extractelement <4 x i16> %in, i32 3
- store i16 %elt, i16* %addr
-
- %newaddr = getelementptr i16* %addr, i32 2
- ret i16* %newaddr
-}
-
-define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) {
-; CHECK-LABEL: test_v2i32_post_imm_st1_lane:
-; CHECK: st1.s { v0 }[1], [x0], #4
- %elt = extractelement <2 x i32> %in, i32 1
- store i32 %elt, i32* %addr
-
- %newaddr = getelementptr i32* %addr, i32 1
- ret i32* %newaddr
-}
-
-define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) {
-; CHECK-LABEL: test_v2i32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
-; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
- %elt = extractelement <2 x i32> %in, i32 1
- store i32 %elt, i32* %addr
-
- %newaddr = getelementptr i32* %addr, i32 2
- ret i32* %newaddr
-}
-
-define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) {
-; CHECK-LABEL: test_v2f32_post_imm_st1_lane:
-; CHECK: st1.s { v0 }[1], [x0], #4
- %elt = extractelement <2 x float> %in, i32 1
- store float %elt, float* %addr
-
- %newaddr = getelementptr float* %addr, i32 1
- ret float* %newaddr
-}
-
-define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) {
-; CHECK-LABEL: test_v2f32_post_reg_st1_lane:
-; CHECK: orr w[[OFFSET:[0-9]+]], wzr, #0x8
-; CHECK: st1.s { v0 }[1], [x0], x[[OFFSET]]
- %elt = extractelement <2 x float> %in, i32 1
- store float %elt, float* %addr
-
- %newaddr = getelementptr float* %addr, i32 2
- ret float* %newaddr
-}
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld2:
-;CHECK: ld2.16b { v0, v1 }, [x0], #32
- %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld2:
-;CHECK: ld2.16b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld2:
-;CHECK: ld2.8b { v0, v1 }, [x0], #16
- %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 16
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld2:
-;CHECK: ld2.8b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld2:
-;CHECK: ld2.8h { v0, v1 }, [x0], #32
- %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld2:
-;CHECK: ld2.8h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-declare { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld2:
-;CHECK: ld2.4h { v0, v1 }, [x0], #16
- %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 8
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld2:
-;CHECK: ld2.4h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-declare { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld2:
-;CHECK: ld2.4s { v0, v1 }, [x0], #32
- %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld2:
-;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-declare { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld2:
-;CHECK: ld2.2s { v0, v1 }, [x0], #16
- %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld2:
-;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-declare { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld2:
-;CHECK: ld2.2d { v0, v1 }, [x0], #32
- %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld2:
-;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-declare { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld2:
-;CHECK: ld1.1d { v0, v1 }, [x0], #16
- %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld2:
-;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-declare { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld2:
-;CHECK: ld2.4s { v0, v1 }, [x0], #32
- %ld2 = tail call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 8
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld2:
-;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-declare { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld2:
-;CHECK: ld2.2s { v0, v1 }, [x0], #16
- %ld2 = tail call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld2:
-;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-declare { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld2:
-;CHECK: ld2.2d { v0, v1 }, [x0], #32
- %ld2 = tail call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld2:
-;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-declare { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld2:
-;CHECK: ld1.1d { v0, v1 }, [x0], #16
- %ld2 = tail call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld2:
-;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = tail call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-declare { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2.v1f64.p0f64(double*)
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld3:
-;CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 48
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld3:
-;CHECK: ld3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld3:
-;CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 24
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld3:
-;CHECK: ld3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld3:
-;CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 24
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld3:
-;CHECK: ld3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld3:
-;CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 12
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld3:
-;CHECK: ld3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld3:
-;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 12
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld3:
-;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld3:
-;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 6
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld3:
-;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld3:
-;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 6
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld3:
-;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld3:
-;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 12
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld3:
-;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld3:
-;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 6
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld3:
-;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-declare { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld3:
-;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
- %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 6
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld3:
-;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-declare { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
- %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-declare { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3.v1f64.p0f64(double*)
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld4:
-;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 64
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld4:
-;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld4:
-;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld4:
-;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld4:
-;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 32
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld4:
-;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld4:
-;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld4:
-;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld4:
-;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 16
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld4:
-;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld4:
-;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld4:
-;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld4:
-;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 8
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld4:
-;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld4:
-;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 16
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld4:
-;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld4:
-;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 8
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld4:
-;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld4:
-;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
- %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 8
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld4:
-;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4.v1f64.p0f64(double*)
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x2(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld1x2:
-;CHECK: ld1.16b { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x2.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld1x2
-}
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x2(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld1x2:
-;CHECK: ld1.16b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x2.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld1x2
-}
-
-declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x2.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x2(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld1x2:
-;CHECK: ld1.8b { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x2.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 16
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld1x2
-}
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x2(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld1x2:
-;CHECK: ld1.8b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x2.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld1x2
-}
-
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x2.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x2(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld1x2:
-;CHECK: ld1.8h { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x2.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld1x2
-}
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x2(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld1x2:
-;CHECK: ld1.8h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x2.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld1x2
-}
-
-declare { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x2.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x2(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld1x2:
-;CHECK: ld1.4h { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x2.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 8
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld1x2
-}
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x2(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld1x2:
-;CHECK: ld1.4h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x2.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld1x2
-}
-
-declare { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x2.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x2(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld1x2:
-;CHECK: ld1.4s { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x2.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld1x2
-}
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x2(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld1x2:
-;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x2.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld1x2
-}
-
-declare { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x2.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x2(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld1x2:
-;CHECK: ld1.2s { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x2.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld1x2
-}
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x2(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld1x2:
-;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x2.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld1x2
-}
-
-declare { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x2.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x2(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld1x2:
-;CHECK: ld1.2d { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x2.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld1x2
-}
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x2(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld1x2:
-;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x2.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld1x2
-}
-
-declare { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x2.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x2(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld1x2:
-;CHECK: ld1.1d { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x2.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld1x2
-}
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x2(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld1x2:
-;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x2.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld1x2
-}
-
-declare { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x2.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x2(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld1x2:
-;CHECK: ld1.4s { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x2.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 8
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld1x2
-}
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x2(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld1x2:
-;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x2.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld1x2
-}
-
-declare { <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x2.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x2(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld1x2:
-;CHECK: ld1.2s { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x2.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld1x2
-}
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x2(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld1x2:
-;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x2.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld1x2
-}
-
-declare { <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x2.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x2(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld1x2:
-;CHECK: ld1.2d { v0, v1 }, [x0], #32
- %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x2.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld1x2
-}
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x2(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld1x2:
-;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x2.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld1x2
-}
-
-declare { <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x2.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x2(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld1x2:
-;CHECK: ld1.1d { v0, v1 }, [x0], #16
- %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x2.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld1x2
-}
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x2(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld1x2:
-;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x2.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld1x2
-}
-
-declare { <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x2.v1f64.p0f64(double*)
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x3(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld1x3:
-;CHECK: ld1.16b { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x3.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 48
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x3(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld1x3:
-;CHECK: ld1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x3.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x3.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x3(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld1x3:
-;CHECK: ld1.8b { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x3.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 24
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x3(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld1x3:
-;CHECK: ld1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x3.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x3.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x3(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld1x3:
-;CHECK: ld1.8h { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x3.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 24
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x3(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld1x3:
-;CHECK: ld1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x3.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x3.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x3(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld1x3:
-;CHECK: ld1.4h { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x3.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 12
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x3(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld1x3:
-;CHECK: ld1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x3.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x3.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x3(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld1x3:
-;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x3.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 12
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x3(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld1x3:
-;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x3.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x3.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x3(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld1x3:
-;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x3.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 6
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x3(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld1x3:
-;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x3.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x3.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x3(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld1x3:
-;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x3.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 6
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x3(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld1x3:
-;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x3.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x3.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x3(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld1x3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x3.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x3(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld1x3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x3.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x3.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x3(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld1x3:
-;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x3.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 12
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3
-}
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x3(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld1x3:
-;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x3.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3
-}
-
-declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x3.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x3(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld1x3:
-;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x3.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 6
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3
-}
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x3(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld1x3:
-;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x3.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3
-}
-
-declare { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x3.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x3(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld1x3:
-;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48
- %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x3.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 6
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3
-}
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x3(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld1x3:
-;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x3.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3
-}
-
-declare { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x3.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x3(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld1x3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24
- %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x3.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3
-}
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x3(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld1x3:
-;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x3.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3
-}
-
-declare { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x3.v1f64.p0f64(double*)
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v16i8_post_imm_ld1x4:
-;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x4.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 64
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x4(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v16i8_post_reg_ld1x4:
-;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x4.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld1x4.v16i8.p0i8(i8*)
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x4(i8* %A, i8** %ptr) {
-;CHECK-LABEL: test_v8i8_post_imm_ld1x4:
-;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x4.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x4(i8* %A, i8** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i8_post_reg_ld1x4:
-;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x4.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld1x4.v8i8.p0i8(i8*)
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x4(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v8i16_post_imm_ld1x4:
-;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x4.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 32
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x4(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v8i16_post_reg_ld1x4:
-;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x4.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld1x4.v8i16.p0i16(i16*)
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x4(i16* %A, i16** %ptr) {
-;CHECK-LABEL: test_v4i16_post_imm_ld1x4:
-;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x4.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x4(i16* %A, i16** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i16_post_reg_ld1x4:
-;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x4.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld1x4.v4i16.p0i16(i16*)
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x4(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v4i32_post_imm_ld1x4:
-;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x4.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 16
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x4(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4i32_post_reg_ld1x4:
-;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x4.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld1x4.v4i32.p0i32(i32*)
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x4(i32* %A, i32** %ptr) {
-;CHECK-LABEL: test_v2i32_post_imm_ld1x4:
-;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x4.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x4(i32* %A, i32** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i32_post_reg_ld1x4:
-;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x4.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld1x4.v2i32.p0i32(i32*)
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x4(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v2i64_post_imm_ld1x4:
-;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x4.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 8
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x4(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2i64_post_reg_ld1x4:
-;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x4.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld1x4.v2i64.p0i64(i64*)
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x4(i64* %A, i64** %ptr) {
-;CHECK-LABEL: test_v1i64_post_imm_ld1x4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x4.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x4(i64* %A, i64** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1i64_post_reg_ld1x4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x4.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld1x4.v1i64.p0i64(i64*)
-
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x4(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v4f32_post_imm_ld1x4:
-;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x4.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 16
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4
-}
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x4(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v4f32_post_reg_ld1x4:
-;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x4.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4
-}
-
-declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld1x4.v4f32.p0f32(float*)
-
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x4(float* %A, float** %ptr) {
-;CHECK-LABEL: test_v2f32_post_imm_ld1x4:
-;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x4.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 8
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4
-}
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x4(float* %A, float** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f32_post_reg_ld1x4:
-;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x4.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4
-}
-
-declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld1x4.v2f32.p0f32(float*)
-
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x4(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v2f64_post_imm_ld1x4:
-;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64
- %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x4.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 8
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4
-}
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x4(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v2f64_post_reg_ld1x4:
-;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x4.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4
-}
-
-declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld1x4.v2f64.p0f64(double*)
-
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x4(double* %A, double** %ptr) {
-;CHECK-LABEL: test_v1f64_post_imm_ld1x4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32
- %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x4.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4
-}
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x4(double* %A, double** %ptr, i64 %inc) {
-;CHECK-LABEL: test_v1f64_post_reg_ld1x4:
-;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x4.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4
-}
-
-declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld1x4.v1f64.p0f64(double*)
-
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld2r:
-;CHECK: ld2r.16b { v0, v1 }, [x0], #2
- %ld2 = call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld2r:
-;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld2r:
-;CHECK: ld2r.8b { v0, v1 }, [x0], #2
- %ld2 = call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld2r:
-;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld2r:
-;CHECK: ld2r.8h { v0, v1 }, [x0], #4
- %ld2 = call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld2r:
-;CHECK: ld2r.8h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-declare { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2r.v8i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld2r:
-;CHECK: ld2r.4h { v0, v1 }, [x0], #4
- %ld2 = call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld2r:
-;CHECK: ld2r.4h { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-declare { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld2r:
-;CHECK: ld2r.4s { v0, v1 }, [x0], #8
- %ld2 = call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld2r:
-;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-declare { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2r.v4i32.p0i32(i32*) nounwind readonly
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld2r:
-;CHECK: ld2r.2s { v0, v1 }, [x0], #8
- %ld2 = call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld2r:
-;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-declare { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2r.v2i32.p0i32(i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld2r:
-;CHECK: ld2r.2d { v0, v1 }, [x0], #16
- %ld2 = call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld2r:
-;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-declare { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2r.v2i64.p0i64(i64*) nounwind readonly
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld2r:
-;CHECK: ld2r.1d { v0, v1 }, [x0], #16
- %ld2 = call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld2r:
-;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-declare { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2r.v1i64.p0i64(i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld2r:
-;CHECK: ld2r.4s { v0, v1 }, [x0], #8
- %ld2 = call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 2
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld2r:
-;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-declare { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2r.v4f32.p0f32(float*) nounwind readonly
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld2r:
-;CHECK: ld2r.2s { v0, v1 }, [x0], #8
- %ld2 = call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 2
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld2r:
-;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-declare { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2r.v2f32.p0f32(float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld2r:
-;CHECK: ld2r.2d { v0, v1 }, [x0], #16
- %ld2 = call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld2r:
-;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-declare { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2r.v2f64.p0f64(double*) nounwind readonly
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld2r:
-;CHECK: ld2r.1d { v0, v1 }, [x0], #16
- %ld2 = call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld2r:
-;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}}
- %ld2 = call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-declare { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2r.v1f64.p0f64(double*) nounwind readonly
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld3r:
-;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3
- %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld3r:
-;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld3r:
-;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3
- %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld3r:
-;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld3r:
-;CHECK: ld3r.8h { v0, v1, v2 }, [x0], #6
- %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld3r:
-;CHECK: ld3r.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3r.v8i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld3r:
-;CHECK: ld3r.4h { v0, v1, v2 }, [x0], #6
- %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld3r:
-;CHECK: ld3r.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld3r:
-;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12
- %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld3r:
-;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3r.v4i32.p0i32(i32*) nounwind readonly
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld3r:
-;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12
- %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld3r:
-;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3r.v2i32.p0i32(i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld3r:
-;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24
- %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld3r:
-;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3r.v2i64.p0i64(i64*) nounwind readonly
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld3r:
-;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24
- %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld3r:
-;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3r.v1i64.p0i64(i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld3r:
-;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12
- %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 3
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld3r:
-;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3r.v4f32.p0f32(float*) nounwind readonly
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld3r:
-;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12
- %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 3
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld3r:
-;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-declare { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3r.v2f32.p0f32(float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld3r:
-;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24
- %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld3r:
-;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-declare { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3r.v2f64.p0f64(double*) nounwind readonly
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld3r:
-;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24
- %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld3r:
-;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-declare { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3r.v1f64.p0f64(double*) nounwind readonly
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld4r:
-;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], #4
- %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld4r:
-;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4r.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4r.v16i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4r(i8* %A, i8** %ptr) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld4r:
-;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], #4
- %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4r(i8* %A, i8** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld4r:
-;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4r.v8i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4r.v8i8.p0i8(i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld4r:
-;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], #8
- %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld4r:
-;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4r.v8i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4r.v8i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4r(i16* %A, i16** %ptr) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld4r:
-;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], #8
- %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4r(i16* %A, i16** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld4r:
-;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4r.v4i16.p0i16(i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4r.v4i16.p0i16(i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld4r:
-;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16
- %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld4r:
-;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4r.v4i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4r.v4i32.p0i32(i32*) nounwind readonly
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4r(i32* %A, i32** %ptr) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld4r:
-;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16
- %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4r(i32* %A, i32** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld4r:
-;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4r.v2i32.p0i32(i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4r.v2i32.p0i32(i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld4r:
-;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld4r:
-;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4r.v2i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4r.v2i64.p0i64(i64*) nounwind readonly
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4r(i64* %A, i64** %ptr) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld4r:
-;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4r(i64* %A, i64** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld4r:
-;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4r.v1i64.p0i64(i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4r.v1i64.p0i64(i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld4r:
-;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16
- %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld4r:
-;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4r.v4f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4r.v4f32.p0f32(float*) nounwind readonly
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4r(float* %A, float** %ptr) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld4r:
-;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16
- %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4r(float* %A, float** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld4r:
-;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4r.v2f32.p0f32(float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4r.v2f32.p0f32(float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld4r:
-;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld4r:
-;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4r.v2f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4r.v2f64.p0f64(double*) nounwind readonly
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4r(double* %A, double** %ptr) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld4r:
-;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32
- %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4r(double* %A, double** %ptr, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld4r:
-;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4r.v1f64.p0f64(double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4r.v1f64.p0f64(double*) nounwind readonly
-
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld2lane:
-;CHECK: ld2.b { v0, v1 }[0], [x0], #2
- %ld2 = call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2lane(i8* %A, i8** %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld2lane:
-;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2lane.v16i8.p0i8(<16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld2lane:
-;CHECK: ld2.b { v0, v1 }[0], [x0], #2
- %ld2 = call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2lane(i8* %A, i8** %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld2lane:
-;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8> } %ld2
-}
-
-declare { <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld2lane.v8i8.p0i8(<8 x i8>, <8 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld2lane:
-;CHECK: ld2.h { v0, v1 }[0], [x0], #4
- %ld2 = call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2lane(i16* %A, i16** %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld2lane:
-;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16> } %ld2
-}
-
-declare { <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld2lane.v8i16.p0i16(<8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld2lane:
-;CHECK: ld2.h { v0, v1 }[0], [x0], #4
- %ld2 = call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2lane(i16* %A, i16** %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld2lane:
-;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16> } %ld2
-}
-
-declare { <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld2lane.v4i16.p0i16(<4 x i16>, <4 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], #8
- %ld2 = call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2lane(i32* %A, i32** %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32> } %ld2
-}
-
-declare { <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], #8
- %ld2 = call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2lane(i32* %A, i32** %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32> } %ld2
-}
-
-declare { <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld2lane.v2i32.p0i32(<2 x i32>, <2 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], #16
- %ld2 = call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2lane(i64* %A, i64** %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64> } %ld2
-}
-
-declare { <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld2lane.v2i64.p0i64(<2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], #16
- %ld2 = call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 2
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2lane(i64* %A, i64** %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64> } %ld2
-}
-
-declare { <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld2lane.v1i64.p0i64(<1 x i64>, <1 x i64>, i64, i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], #8
- %ld2 = call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 2
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2lane(float* %A, float** %ptr, i64 %inc, <4 x float> %B, <4 x float> %C) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float> } %ld2
-}
-
-declare { <4 x float>, <4 x float> } @llvm.arm64.neon.ld2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], #8
- %ld2 = call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 2
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2lane(float* %A, float** %ptr, i64 %inc, <2 x float> %B, <2 x float> %C) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld2lane:
-;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float> } %ld2
-}
-
-declare { <2 x float>, <2 x float> } @llvm.arm64.neon.ld2lane.v2f32.p0f32(<2 x float>, <2 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], #16
- %ld2 = call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2lane(double* %A, double** %ptr, i64 %inc, <2 x double> %B, <2 x double> %C) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double> } %ld2
-}
-
-declare { <2 x double>, <2 x double> } @llvm.arm64.neon.ld2lane.v2f64.p0f64(<2 x double>, <2 x double>, i64, double*) nounwind readonly
-
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], #16
- %ld2 = call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 2
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2lane(double* %A, double** %ptr, i64 %inc, <1 x double> %B, <1 x double> %C) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld2lane:
-;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- %ld2 = call { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double> } %ld2
-}
-
-declare { <1 x double>, <1 x double> } @llvm.arm64.neon.ld2lane.v1f64.p0f64(<1 x double>, <1 x double>, i64, double*) nounwind readonly
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld3lane:
-;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3
- %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3lane(i8* %A, i8** %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld3lane:
-;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld3lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld3lane:
-;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3
- %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3lane(i8* %A, i8** %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld3lane:
-;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld3lane.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld3lane:
-;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6
- %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3lane(i16* %A, i16** %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld3lane:
-;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld3lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld3lane:
-;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6
- %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3lane(i16* %A, i16** %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld3lane:
-;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld3lane.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
- %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3lane(i32* %A, i32** %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
- %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3lane(i32* %A, i32** %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld3lane.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
- %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3lane(i64* %A, i64** %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld3lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
- %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 3
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3lane(i64* %A, i64** %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld3lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64, i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
- %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 3
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3lane(float* %A, float** %ptr, i64 %inc, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float> } %ld3
-}
-
-declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12
- %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 3
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3lane(float* %A, float** %ptr, i64 %inc, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld3lane:
-;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float> } %ld3
-}
-
-declare { <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld3lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
- %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3lane(double* %A, double** %ptr, i64 %inc, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double> } %ld3
-}
-
-declare { <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld3lane.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, i64, double*) nounwind readonly
-
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24
- %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 3
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3lane(double* %A, double** %ptr, i64 %inc, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld3lane:
-;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double> } %ld3
-}
-
-declare { <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld3lane.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, i64, double*) nounwind readonly
-
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_ld4lane:
-;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4
- %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4lane(i8* %A, i8** %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_ld4lane:
-;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4
-}
-
-declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld4lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_ld4lane:
-;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4
- %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4lane(i8* %A, i8** %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_ld4lane:
-;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- store i8* %tmp, i8** %ptr
- ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4
-}
-
-declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm64.neon.ld4lane.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i64, i8*) nounwind readonly
-
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_ld4lane:
-;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8
- %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4lane(i16* %A, i16** %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_ld4lane:
-;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4
-}
-
-declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm64.neon.ld4lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_ld4lane:
-;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8
- %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4lane(i16* %A, i16** %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_ld4lane:
-;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- store i16* %tmp, i16** %ptr
- ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4
-}
-
-declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm64.neon.ld4lane.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i64, i16*) nounwind readonly
-
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
- %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4lane(i32* %A, i32** %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4
-}
-
-declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
- %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4lane(i32* %A, i32** %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- store i32* %tmp, i32** %ptr
- ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4
-}
-
-declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.arm64.neon.ld4lane.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i64, i32*) nounwind readonly
-
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
- %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4lane(i64* %A, i64** %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4
-}
-
-declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.arm64.neon.ld4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
- %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i32 4
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4lane(i64* %A, i64** %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- store i64* %tmp, i64** %ptr
- ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4
-}
-
-declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.arm64.neon.ld4lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64, i64*) nounwind readonly
-
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
- %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4lane(float* %A, float** %ptr, i64 %inc, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4
-}
-
-declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.arm64.neon.ld4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16
- %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 4
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4lane(float* %A, float** %ptr, i64 %inc, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_ld4lane:
-;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- store float* %tmp, float** %ptr
- ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4
-}
-
-declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.arm64.neon.ld4lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, i64, float*) nounwind readonly
-
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
- %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4lane(double* %A, double** %ptr, i64 %inc, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4
-}
-
-declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.arm64.neon.ld4lane.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, <2 x double>, i64, double*) nounwind readonly
-
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32
- %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i32 4
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4lane(double* %A, double** %ptr, i64 %inc, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_ld4lane:
-;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- store double* %tmp, double** %ptr
- ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4
-}
-
-declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.arm64.neon.ld4lane.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x double>, i64, double*) nounwind readonly
-
-
-define i8* @test_v16i8_post_imm_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st2:
-;CHECK: st2.16b { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st2:
-;CHECK: st2.16b { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v16i8.p0i8(<16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st2:
-;CHECK: st2.8b { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i32 16
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st2:
-;CHECK: st2.8b { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st2:
-;CHECK: st2.8h { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st2:
-;CHECK: st2.8h { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v8i16.p0i16(<8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st2:
-;CHECK: st2.4h { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i32 8
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st2:
-;CHECK: st2.4h { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v4i16.p0i16(<4 x i16>, <4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st2:
-;CHECK: st2.4s { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st2:
-;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st2:
-;CHECK: st2.2s { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st2:
-;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v2i32.p0i32(<2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st2:
-;CHECK: st2.2d { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st2:
-;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v2i64.p0i64(<2 x i64>, <2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st2:
-;CHECK: st1.1d { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 2
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st2:
-;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v1i64.p0i64(<1 x i64>, <1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st2(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st2:
-;CHECK: st2.4s { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i32 8
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st2(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st2:
-;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st2(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st2:
-;CHECK: st2.2s { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i32 4
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st2(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st2:
-;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v2f32.p0f32(<2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st2(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st2:
-;CHECK: st2.2d { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st2(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st2:
-;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v2f64.p0f64(<2 x double>, <2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st2(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st2:
-;CHECK: st1.1d { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 2
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st2(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st2:
-;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st2.v1f64.p0f64(<1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st3:
-;CHECK: st3.16b { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i32 48
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st3:
-;CHECK: st3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st3:
-;CHECK: st3.8b { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i32 24
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st3:
-;CHECK: st3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st3:
-;CHECK: st3.8h { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i32 24
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st3:
-;CHECK: st3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st3:
-;CHECK: st3.4h { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i32 12
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st3:
-;CHECK: st3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st3:
-;CHECK: st3.4s { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i32 12
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st3:
-;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st3:
-;CHECK: st3.2s { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i32 6
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st3:
-;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st3:
-;CHECK: st3.2d { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 6
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st3:
-;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 3
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st3(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st3:
-;CHECK: st3.4s { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i32 12
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st3(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st3:
-;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st3(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st3:
-;CHECK: st3.2s { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i32 6
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st3(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st3:
-;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st3(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st3:
-;CHECK: st3.2d { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 6
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st3(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st3:
-;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st3(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 3
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st3(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st3.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st4:
-;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i32 64
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st4:
-;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st4:
-;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st4:
-;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st4:
-;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i32 32
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st4:
-;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st4:
-;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st4:
-;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>,<4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st4:
-;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i32 16
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st4:
-;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>,<4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st4:
-;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st4:
-;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st4:
-;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 8
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st4:
-;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>,<2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>,<1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st4(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st4:
-;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i32 16
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st4(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st4:
-;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st4(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st4:
-;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i32 8
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st4(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st4:
-;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st4(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st4:
-;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 8
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st4(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st4:
-;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>,<2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st4(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st4(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st4.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st1x2:
-;CHECK: st1.16b { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st1x2:
-;CHECK: st1.16b { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v16i8.p0i8(<16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st1x2:
-;CHECK: st1.8b { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i32 16
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st1x2:
-;CHECK: st1.8b { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st1x2:
-;CHECK: st1.8h { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st1x2:
-;CHECK: st1.8h { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v8i16.p0i16(<8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st1x2:
-;CHECK: st1.4h { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i32 8
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st1x2:
-;CHECK: st1.4h { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v4i16.p0i16(<4 x i16>, <4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st1x2:
-;CHECK: st1.4s { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st1x2:
-;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st1x2:
-;CHECK: st1.2s { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st1x2:
-;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v2i32.p0i32(<2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st1x2:
-;CHECK: st1.2d { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st1x2:
-;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v2i64.p0i64(<2 x i64>, <2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st1x2:
-;CHECK: st1.1d { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 2
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st1x2:
-;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v1i64.p0i64(<1 x i64>, <1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st1x2(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st1x2:
-;CHECK: st1.4s { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i32 8
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st1x2(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st1x2:
-;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st1x2(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st1x2:
-;CHECK: st1.2s { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i32 4
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st1x2(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st1x2:
-;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v2f32.p0f32(<2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st1x2(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st1x2:
-;CHECK: st1.2d { v0, v1 }, [x0], #32
- call void @llvm.arm64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st1x2(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st1x2:
-;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v2f64.p0f64(<2 x double>, <2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st1x2(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st1x2:
-;CHECK: st1.1d { v0, v1 }, [x0], #16
- call void @llvm.arm64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 2
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st1x2(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st1x2:
-;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x2.v1f64.p0f64(<1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st1x3:
-;CHECK: st1.16b { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i32 48
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st1x3:
-;CHECK: st1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st1x3:
-;CHECK: st1.8b { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i32 24
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st1x3:
-;CHECK: st1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st1x3:
-;CHECK: st1.8h { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i32 24
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st1x3:
-;CHECK: st1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st1x3:
-;CHECK: st1.4h { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i32 12
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st1x3:
-;CHECK: st1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st1x3:
-;CHECK: st1.4s { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i32 12
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st1x3:
-;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st1x3:
-;CHECK: st1.2s { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i32 6
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st1x3:
-;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st1x3:
-;CHECK: st1.2d { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 6
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st1x3:
-;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st1x3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 3
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st1x3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st1x3(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st1x3:
-;CHECK: st1.4s { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i32 12
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st1x3(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st1x3:
-;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st1x3(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st1x3:
-;CHECK: st1.2s { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i32 6
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st1x3(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st1x3:
-;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st1x3(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st1x3:
-;CHECK: st1.2d { v0, v1, v2 }, [x0], #48
- call void @llvm.arm64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 6
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st1x3(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st1x3:
-;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st1x3(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st1x3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], #24
- call void @llvm.arm64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 3
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st1x3(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st1x3:
-;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x3.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st1x4:
-;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i32 64
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st1x4:
-;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)
-
-
-define i8* @test_v8i8_post_imm_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st1x4:
-;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st1x4:
-;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*)
-
-
-define i16* @test_v8i16_post_imm_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st1x4:
-;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i32 32
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st1x4:
-;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i16*)
-
-
-define i16* @test_v4i16_post_imm_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st1x4:
-;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i32 16
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st1x4:
-;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>,<4 x i16>, i16*)
-
-
-define i32* @test_v4i32_post_imm_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st1x4:
-;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i32 16
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st1x4:
-;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>,<4 x i32>, i32*)
-
-
-define i32* @test_v2i32_post_imm_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st1x4:
-;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i32 8
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st1x4:
-;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32*)
-
-
-define i64* @test_v2i64_post_imm_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st1x4:
-;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 8
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st1x4:
-;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>,<2 x i64>, i64*)
-
-
-define i64* @test_v1i64_post_imm_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st1x4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st1x4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>,<1 x i64>, i64*)
-
-
-define float* @test_v4f32_post_imm_st1x4(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st1x4:
-;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i32 16
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st1x4(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st1x4:
-;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
-
-
-define float* @test_v2f32_post_imm_st1x4(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st1x4:
-;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i32 8
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st1x4(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st1x4:
-;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, float*)
-
-
-define double* @test_v2f64_post_imm_st1x4(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st1x4:
-;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64
- call void @llvm.arm64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 8
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st1x4(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st1x4:
-;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>,<2 x double>, double*)
-
-
-define double* @test_v1f64_post_imm_st1x4(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st1x4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32
- call void @llvm.arm64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st1x4(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st1x4:
-;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x double>, double*)
-
-
-define i8* @test_v16i8_post_imm_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) {
- call void @llvm.arm64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) {
- call void @llvm.arm64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lanelane.v16i8.p0i8(<16 x i8>, <16 x i8>, i64, i64, i8*) nounwind readnone
-
-
-define i8* @test_v16i8_post_imm_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st2lane:
-;CHECK: st2.b { v0, v1 }[0], [x0], #2
- call void @llvm.arm64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st2lane:
-;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v16i8.p0i8(<16 x i8>, <16 x i8>, i64, i8*)
-
-
-define i8* @test_v8i8_post_imm_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st2lane:
-;CHECK: st2.b { v0, v1 }[0], [x0], #2
- call void @llvm.arm64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 2
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st2lane:
-;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v8i8.p0i8(<8 x i8>, <8 x i8>, i64, i8*)
-
-
-define i16* @test_v8i16_post_imm_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st2lane:
-;CHECK: st2.h { v0, v1 }[0], [x0], #4
- call void @llvm.arm64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st2lane:
-;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v8i16.p0i16(<8 x i16>, <8 x i16>, i64, i16*)
-
-
-define i16* @test_v4i16_post_imm_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st2lane:
-;CHECK: st2.h { v0, v1 }[0], [x0], #4
- call void @llvm.arm64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 2
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st2lane:
-;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v4i16.p0i16(<4 x i16>, <4 x i16>, i64, i16*)
-
-
-define i32* @test_v4i32_post_imm_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], #8
- call void @llvm.arm64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*)
-
-
-define i32* @test_v2i32_post_imm_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], #8
- call void @llvm.arm64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 2
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v2i32.p0i32(<2 x i32>, <2 x i32>, i64, i32*)
-
-
-define i64* @test_v2i64_post_imm_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], #16
- call void @llvm.arm64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 2
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v2i64.p0i64(<2 x i64>, <2 x i64>, i64, i64*)
-
-
-define i64* @test_v1i64_post_imm_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], #16
- call void @llvm.arm64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 2
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v1i64.p0i64(<1 x i64>, <1 x i64>, i64, i64*)
-
-
-define float* @test_v4f32_post_imm_st2lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], #8
- call void @llvm.arm64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 2
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st2lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
-
-
-define float* @test_v2f32_post_imm_st2lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], #8
- call void @llvm.arm64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 2
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st2lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st2lane:
-;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v2f32.p0f32(<2 x float>, <2 x float>, i64, float*)
-
-
-define double* @test_v2f64_post_imm_st2lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], #16
- call void @llvm.arm64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 2
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st2lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v2f64.p0f64(<2 x double>, <2 x double>, i64, double*)
-
-
-define double* @test_v1f64_post_imm_st2lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], #16
- call void @llvm.arm64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 2
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st2lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st2lane:
-;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st2lane.v1f64.p0f64(<1 x double>, <1 x double>, i64, double*)
-
-
-define i8* @test_v16i8_post_imm_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st3lane:
-;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3
- call void @llvm.arm64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st3lane:
-;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i64, i8*)
-
-
-define i8* @test_v8i8_post_imm_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st3lane:
-;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3
- call void @llvm.arm64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 3
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st3lane:
-;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i64, i8*)
-
-
-define i16* @test_v8i16_post_imm_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st3lane:
-;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6
- call void @llvm.arm64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st3lane:
-;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i64, i16*)
-
-
-define i16* @test_v4i16_post_imm_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st3lane:
-;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6
- call void @llvm.arm64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 3
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st3lane:
-;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i64, i16*)
-
-
-define i32* @test_v4i32_post_imm_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
- call void @llvm.arm64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
-
-
-define i32* @test_v2i32_post_imm_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
- call void @llvm.arm64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 3
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i64, i32*)
-
-
-define i64* @test_v2i64_post_imm_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
- call void @llvm.arm64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 3
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64, i64*)
-
-
-define i64* @test_v1i64_post_imm_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
- call void @llvm.arm64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 3
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
-
-
-define float* @test_v4f32_post_imm_st3lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
- call void @llvm.arm64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 3
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st3lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
-
-
-define float* @test_v2f32_post_imm_st3lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12
- call void @llvm.arm64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 3
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st3lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st3lane:
-;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, i64, float*)
-
-
-define double* @test_v2f64_post_imm_st3lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
- call void @llvm.arm64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 3
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st3lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, i64, double*)
-
-
-define double* @test_v1f64_post_imm_st3lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24
- call void @llvm.arm64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 3
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st3lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st3lane:
-;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st3lane.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, i64, double*)
-
-
-define i8* @test_v16i8_post_imm_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind {
-;CHECK-LABEL: test_v16i8_post_imm_st4lane:
-;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4
- call void @llvm.arm64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- ret i8* %tmp
-}
-
-define i8* @test_v16i8_post_reg_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v16i8_post_reg_st4lane:
-;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i64, i8*)
-
-
-define i8* @test_v8i8_post_imm_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind {
-;CHECK-LABEL: test_v8i8_post_imm_st4lane:
-;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4
- call void @llvm.arm64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i32 4
- ret i8* %tmp
-}
-
-define i8* @test_v8i8_post_reg_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i8_post_reg_st4lane:
-;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A)
- %tmp = getelementptr i8* %A, i64 %inc
- ret i8* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i64, i8*)
-
-
-define i16* @test_v8i16_post_imm_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind {
-;CHECK-LABEL: test_v8i16_post_imm_st4lane:
-;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8
- call void @llvm.arm64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- ret i16* %tmp
-}
-
-define i16* @test_v8i16_post_reg_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v8i16_post_reg_st4lane:
-;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i64, i16*)
-
-
-define i16* @test_v4i16_post_imm_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind {
-;CHECK-LABEL: test_v4i16_post_imm_st4lane:
-;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8
- call void @llvm.arm64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i32 4
- ret i16* %tmp
-}
-
-define i16* @test_v4i16_post_reg_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i16_post_reg_st4lane:
-;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A)
- %tmp = getelementptr i16* %A, i64 %inc
- ret i16* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i64, i16*)
-
-
-define i32* @test_v4i32_post_imm_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind {
-;CHECK-LABEL: test_v4i32_post_imm_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
- call void @llvm.arm64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- ret i32* %tmp
-}
-
-define i32* @test_v4i32_post_reg_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4i32_post_reg_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*)
-
-
-define i32* @test_v2i32_post_imm_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind {
-;CHECK-LABEL: test_v2i32_post_imm_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
- call void @llvm.arm64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i32 4
- ret i32* %tmp
-}
-
-define i32* @test_v2i32_post_reg_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i32_post_reg_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A)
- %tmp = getelementptr i32* %A, i64 %inc
- ret i32* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i64, i32*)
-
-
-define i64* @test_v2i64_post_imm_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind {
-;CHECK-LABEL: test_v2i64_post_imm_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
- call void @llvm.arm64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v2i64_post_reg_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2i64_post_reg_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64, i64*)
-
-
-define i64* @test_v1i64_post_imm_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind {
-;CHECK-LABEL: test_v1i64_post_imm_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
- call void @llvm.arm64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 4
- ret i64* %tmp
-}
-
-define i64* @test_v1i64_post_reg_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1i64_post_reg_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A)
- %tmp = getelementptr i64* %A, i64 %inc
- ret i64* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64, i64*)
-
-
-define float* @test_v4f32_post_imm_st4lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind {
-;CHECK-LABEL: test_v4f32_post_imm_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
- call void @llvm.arm64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 4
- ret float* %tmp
-}
-
-define float* @test_v4f32_post_reg_st4lane(float* %A, float** %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v4f32_post_reg_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
-
-
-define float* @test_v2f32_post_imm_st4lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind {
-;CHECK-LABEL: test_v2f32_post_imm_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16
- call void @llvm.arm64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i32 4
- ret float* %tmp
-}
-
-define float* @test_v2f32_post_reg_st4lane(float* %A, float** %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f32_post_reg_st4lane:
-;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A)
- %tmp = getelementptr float* %A, i64 %inc
- ret float* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, i64, float*)
-
-
-define double* @test_v2f64_post_imm_st4lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind {
-;CHECK-LABEL: test_v2f64_post_imm_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
- call void @llvm.arm64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v2f64_post_reg_st4lane(double* %A, double** %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v2f64_post_reg_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, <2 x double>, i64, double*)
-
-
-define double* @test_v1f64_post_imm_st4lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind {
-;CHECK-LABEL: test_v1f64_post_imm_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32
- call void @llvm.arm64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 4
- ret double* %tmp
-}
-
-define double* @test_v1f64_post_reg_st4lane(double* %A, double** %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind {
-;CHECK-LABEL: test_v1f64_post_reg_st4lane:
-;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}}
- call void @llvm.arm64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A)
- %tmp = getelementptr double* %A, i64 %inc
- ret double* %tmp
-}
-
-declare void @llvm.arm64.neon.st4lane.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x double>, i64, double*)
-
-define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
-; CHECK-LABEL: test_v16i8_post_imm_ld1r:
-; CHECK: ld1r.16b { v0 }, [x0], #1
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <16 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <16 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <16 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <16 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <16 x i8> %tmp8, i8 %tmp1, i32 7
- %tmp10 = insertelement <16 x i8> %tmp9, i8 %tmp1, i32 8
- %tmp11 = insertelement <16 x i8> %tmp10, i8 %tmp1, i32 9
- %tmp12 = insertelement <16 x i8> %tmp11, i8 %tmp1, i32 10
- %tmp13 = insertelement <16 x i8> %tmp12, i8 %tmp1, i32 11
- %tmp14 = insertelement <16 x i8> %tmp13, i8 %tmp1, i32 12
- %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13
- %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14
- %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15
- %tmp18 = getelementptr i8* %bar, i64 1
- store i8* %tmp18, i8** %ptr
- ret <16 x i8> %tmp17
-}
-
-define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v16i8_post_reg_ld1r:
-; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <16 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <16 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <16 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <16 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <16 x i8> %tmp8, i8 %tmp1, i32 7
- %tmp10 = insertelement <16 x i8> %tmp9, i8 %tmp1, i32 8
- %tmp11 = insertelement <16 x i8> %tmp10, i8 %tmp1, i32 9
- %tmp12 = insertelement <16 x i8> %tmp11, i8 %tmp1, i32 10
- %tmp13 = insertelement <16 x i8> %tmp12, i8 %tmp1, i32 11
- %tmp14 = insertelement <16 x i8> %tmp13, i8 %tmp1, i32 12
- %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13
- %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14
- %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15
- %tmp18 = getelementptr i8* %bar, i64 %inc
- store i8* %tmp18, i8** %ptr
- ret <16 x i8> %tmp17
-}
-
-define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) {
-; CHECK-LABEL: test_v8i8_post_imm_ld1r:
-; CHECK: ld1r.8b { v0 }, [x0], #1
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <8 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <8 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7
- %tmp10 = getelementptr i8* %bar, i64 1
- store i8* %tmp10, i8** %ptr
- ret <8 x i8> %tmp9
-}
-
-define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v8i8_post_reg_ld1r:
-; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <8 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <8 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7
- %tmp10 = getelementptr i8* %bar, i64 %inc
- store i8* %tmp10, i8** %ptr
- ret <8 x i8> %tmp9
-}
-
-define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
-; CHECK-LABEL: test_v8i16_post_imm_ld1r:
-; CHECK: ld1r.8h { v0 }, [x0], #2
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <8 x i16> %tmp4, i16 %tmp1, i32 3
- %tmp6 = insertelement <8 x i16> %tmp5, i16 %tmp1, i32 4
- %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5
- %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6
- %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7
- %tmp10 = getelementptr i16* %bar, i64 1
- store i16* %tmp10, i16** %ptr
- ret <8 x i16> %tmp9
-}
-
-define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v8i16_post_reg_ld1r:
-; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <8 x i16> %tmp4, i16 %tmp1, i32 3
- %tmp6 = insertelement <8 x i16> %tmp5, i16 %tmp1, i32 4
- %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5
- %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6
- %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7
- %tmp10 = getelementptr i16* %bar, i64 %inc
- store i16* %tmp10, i16** %ptr
- ret <8 x i16> %tmp9
-}
-
-define <4 x i16> @test_v4i16_post_imm_ld1r(i16* %bar, i16** %ptr) {
-; CHECK-LABEL: test_v4i16_post_imm_ld1r:
-; CHECK: ld1r.4h { v0 }, [x0], #2
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3
- %tmp6 = getelementptr i16* %bar, i64 1
- store i16* %tmp6, i16** %ptr
- ret <4 x i16> %tmp5
-}
-
-define <4 x i16> @test_v4i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v4i16_post_reg_ld1r:
-; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3
- %tmp6 = getelementptr i16* %bar, i64 %inc
- store i16* %tmp6, i16** %ptr
- ret <4 x i16> %tmp5
-}
-
-define <4 x i32> @test_v4i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
-; CHECK-LABEL: test_v4i32_post_imm_ld1r:
-; CHECK: ld1r.4s { v0 }, [x0], #4
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
- %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
- %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3
- %tmp6 = getelementptr i32* %bar, i64 1
- store i32* %tmp6, i32** %ptr
- ret <4 x i32> %tmp5
-}
-
-define <4 x i32> @test_v4i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v4i32_post_reg_ld1r:
-; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
- %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
- %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3
- %tmp6 = getelementptr i32* %bar, i64 %inc
- store i32* %tmp6, i32** %ptr
- ret <4 x i32> %tmp5
-}
-
-define <2 x i32> @test_v2i32_post_imm_ld1r(i32* %bar, i32** %ptr) {
-; CHECK-LABEL: test_v2i32_post_imm_ld1r:
-; CHECK: ld1r.2s { v0 }, [x0], #4
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
- %tmp4 = getelementptr i32* %bar, i64 1
- store i32* %tmp4, i32** %ptr
- ret <2 x i32> %tmp3
-}
-
-define <2 x i32> @test_v2i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v2i32_post_reg_ld1r:
-; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
- %tmp4 = getelementptr i32* %bar, i64 %inc
- store i32* %tmp4, i32** %ptr
- ret <2 x i32> %tmp3
-}
-
-define <2 x i64> @test_v2i64_post_imm_ld1r(i64* %bar, i64** %ptr) {
-; CHECK-LABEL: test_v2i64_post_imm_ld1r:
-; CHECK: ld1r.2d { v0 }, [x0], #8
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
- %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
- %tmp4 = getelementptr i64* %bar, i64 1
- store i64* %tmp4, i64** %ptr
- ret <2 x i64> %tmp3
-}
-
-define <2 x i64> @test_v2i64_post_reg_ld1r(i64* %bar, i64** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v2i64_post_reg_ld1r:
-; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
- %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
- %tmp4 = getelementptr i64* %bar, i64 %inc
- store i64* %tmp4, i64** %ptr
- ret <2 x i64> %tmp3
-}
-
-define <4 x float> @test_v4f32_post_imm_ld1r(float* %bar, float** %ptr) {
-; CHECK-LABEL: test_v4f32_post_imm_ld1r:
-; CHECK: ld1r.4s { v0 }, [x0], #4
- %tmp1 = load float* %bar
- %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0
- %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1
- %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2
- %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3
- %tmp6 = getelementptr float* %bar, i64 1
- store float* %tmp6, float** %ptr
- ret <4 x float> %tmp5
-}
-
-define <4 x float> @test_v4f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v4f32_post_reg_ld1r:
-; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load float* %bar
- %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0
- %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1
- %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2
- %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3
- %tmp6 = getelementptr float* %bar, i64 %inc
- store float* %tmp6, float** %ptr
- ret <4 x float> %tmp5
-}
-
-define <2 x float> @test_v2f32_post_imm_ld1r(float* %bar, float** %ptr) {
-; CHECK-LABEL: test_v2f32_post_imm_ld1r:
-; CHECK: ld1r.2s { v0 }, [x0], #4
- %tmp1 = load float* %bar
- %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0
- %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1
- %tmp4 = getelementptr float* %bar, i64 1
- store float* %tmp4, float** %ptr
- ret <2 x float> %tmp3
-}
-
-define <2 x float> @test_v2f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v2f32_post_reg_ld1r:
-; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load float* %bar
- %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0
- %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1
- %tmp4 = getelementptr float* %bar, i64 %inc
- store float* %tmp4, float** %ptr
- ret <2 x float> %tmp3
-}
-
-define <2 x double> @test_v2f64_post_imm_ld1r(double* %bar, double** %ptr) {
-; CHECK-LABEL: test_v2f64_post_imm_ld1r:
-; CHECK: ld1r.2d { v0 }, [x0], #8
- %tmp1 = load double* %bar
- %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0
- %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1
- %tmp4 = getelementptr double* %bar, i64 1
- store double* %tmp4, double** %ptr
- ret <2 x double> %tmp3
-}
-
-define <2 x double> @test_v2f64_post_reg_ld1r(double* %bar, double** %ptr, i64 %inc) {
-; CHECK-LABEL: test_v2f64_post_reg_ld1r:
-; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}}
- %tmp1 = load double* %bar
- %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0
- %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1
- %tmp4 = getelementptr double* %bar, i64 %inc
- store double* %tmp4, double** %ptr
- ret <2 x double> %tmp3
-}
-
-define <16 x i8> @test_v16i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <16 x i8> %A) {
-; CHECK-LABEL: test_v16i8_post_imm_ld1lane:
-; CHECK: ld1.b { v0 }[1], [x0], #1
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1
- %tmp3 = getelementptr i8* %bar, i64 1
- store i8* %tmp3, i8** %ptr
- ret <16 x i8> %tmp2
-}
-
-define <16 x i8> @test_v16i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <16 x i8> %A) {
-; CHECK-LABEL: test_v16i8_post_reg_ld1lane:
-; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1
- %tmp3 = getelementptr i8* %bar, i64 %inc
- store i8* %tmp3, i8** %ptr
- ret <16 x i8> %tmp2
-}
-
-define <8 x i8> @test_v8i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <8 x i8> %A) {
-; CHECK-LABEL: test_v8i8_post_imm_ld1lane:
-; CHECK: ld1.b { v0 }[1], [x0], #1
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1
- %tmp3 = getelementptr i8* %bar, i64 1
- store i8* %tmp3, i8** %ptr
- ret <8 x i8> %tmp2
-}
-
-define <8 x i8> @test_v8i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <8 x i8> %A) {
-; CHECK-LABEL: test_v8i8_post_reg_ld1lane:
-; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1
- %tmp3 = getelementptr i8* %bar, i64 %inc
- store i8* %tmp3, i8** %ptr
- ret <8 x i8> %tmp2
-}
-
-define <8 x i16> @test_v8i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <8 x i16> %A) {
-; CHECK-LABEL: test_v8i16_post_imm_ld1lane:
-; CHECK: ld1.h { v0 }[1], [x0], #2
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1
- %tmp3 = getelementptr i16* %bar, i64 1
- store i16* %tmp3, i16** %ptr
- ret <8 x i16> %tmp2
-}
-
-define <8 x i16> @test_v8i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <8 x i16> %A) {
-; CHECK-LABEL: test_v8i16_post_reg_ld1lane:
-; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1
- %tmp3 = getelementptr i16* %bar, i64 %inc
- store i16* %tmp3, i16** %ptr
- ret <8 x i16> %tmp2
-}
-
-define <4 x i16> @test_v4i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <4 x i16> %A) {
-; CHECK-LABEL: test_v4i16_post_imm_ld1lane:
-; CHECK: ld1.h { v0 }[1], [x0], #2
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1
- %tmp3 = getelementptr i16* %bar, i64 1
- store i16* %tmp3, i16** %ptr
- ret <4 x i16> %tmp2
-}
-
-define <4 x i16> @test_v4i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <4 x i16> %A) {
-; CHECK-LABEL: test_v4i16_post_reg_ld1lane:
-; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1
- %tmp3 = getelementptr i16* %bar, i64 %inc
- store i16* %tmp3, i16** %ptr
- ret <4 x i16> %tmp2
-}
-
-define <4 x i32> @test_v4i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <4 x i32> %A) {
-; CHECK-LABEL: test_v4i32_post_imm_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], #4
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1
- %tmp3 = getelementptr i32* %bar, i64 1
- store i32* %tmp3, i32** %ptr
- ret <4 x i32> %tmp2
-}
-
-define <4 x i32> @test_v4i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <4 x i32> %A) {
-; CHECK-LABEL: test_v4i32_post_reg_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1
- %tmp3 = getelementptr i32* %bar, i64 %inc
- store i32* %tmp3, i32** %ptr
- ret <4 x i32> %tmp2
-}
-
-define <2 x i32> @test_v2i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <2 x i32> %A) {
-; CHECK-LABEL: test_v2i32_post_imm_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], #4
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1
- %tmp3 = getelementptr i32* %bar, i64 1
- store i32* %tmp3, i32** %ptr
- ret <2 x i32> %tmp2
-}
-
-define <2 x i32> @test_v2i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <2 x i32> %A) {
-; CHECK-LABEL: test_v2i32_post_reg_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1
- %tmp3 = getelementptr i32* %bar, i64 %inc
- store i32* %tmp3, i32** %ptr
- ret <2 x i32> %tmp2
-}
-
-define <2 x i64> @test_v2i64_post_imm_ld1lane(i64* %bar, i64** %ptr, <2 x i64> %A) {
-; CHECK-LABEL: test_v2i64_post_imm_ld1lane:
-; CHECK: ld1.d { v0 }[1], [x0], #8
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1
- %tmp3 = getelementptr i64* %bar, i64 1
- store i64* %tmp3, i64** %ptr
- ret <2 x i64> %tmp2
-}
-
-define <2 x i64> @test_v2i64_post_reg_ld1lane(i64* %bar, i64** %ptr, i64 %inc, <2 x i64> %A) {
-; CHECK-LABEL: test_v2i64_post_reg_ld1lane:
-; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1
- %tmp3 = getelementptr i64* %bar, i64 %inc
- store i64* %tmp3, i64** %ptr
- ret <2 x i64> %tmp2
-}
-
-define <4 x float> @test_v4f32_post_imm_ld1lane(float* %bar, float** %ptr, <4 x float> %A) {
-; CHECK-LABEL: test_v4f32_post_imm_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], #4
- %tmp1 = load float* %bar
- %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
- %tmp3 = getelementptr float* %bar, i64 1
- store float* %tmp3, float** %ptr
- ret <4 x float> %tmp2
-}
-
-define <4 x float> @test_v4f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <4 x float> %A) {
-; CHECK-LABEL: test_v4f32_post_reg_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load float* %bar
- %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1
- %tmp3 = getelementptr float* %bar, i64 %inc
- store float* %tmp3, float** %ptr
- ret <4 x float> %tmp2
-}
-
-define <2 x float> @test_v2f32_post_imm_ld1lane(float* %bar, float** %ptr, <2 x float> %A) {
-; CHECK-LABEL: test_v2f32_post_imm_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], #4
- %tmp1 = load float* %bar
- %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1
- %tmp3 = getelementptr float* %bar, i64 1
- store float* %tmp3, float** %ptr
- ret <2 x float> %tmp2
-}
-
-define <2 x float> @test_v2f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <2 x float> %A) {
-; CHECK-LABEL: test_v2f32_post_reg_ld1lane:
-; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load float* %bar
- %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1
- %tmp3 = getelementptr float* %bar, i64 %inc
- store float* %tmp3, float** %ptr
- ret <2 x float> %tmp2
-}
-
-define <2 x double> @test_v2f64_post_imm_ld1lane(double* %bar, double** %ptr, <2 x double> %A) {
-; CHECK-LABEL: test_v2f64_post_imm_ld1lane:
-; CHECK: ld1.d { v0 }[1], [x0], #8
- %tmp1 = load double* %bar
- %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1
- %tmp3 = getelementptr double* %bar, i64 1
- store double* %tmp3, double** %ptr
- ret <2 x double> %tmp2
-}
-
-define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i64 %inc, <2 x double> %A) {
-; CHECK-LABEL: test_v2f64_post_reg_ld1lane:
-; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}}
- %tmp1 = load double* %bar
- %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1
- %tmp3 = getelementptr double* %bar, i64 %inc
- store double* %tmp3, double** %ptr
- ret <2 x double> %tmp2
-}
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-I.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-I.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-I.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-I.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
-
-define i32 @constraint_I(i32 %i, i32 %j) nounwind ssp {
-entry:
- %0 = tail call i32 asm sideeffect "add $0, $1, $2", "=r,r,I"(i32 %i, i32 4097) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-J.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-J.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-J.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-J.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
-
-define i32 @constraint_J(i32 %i, i32 %j) nounwind ssp {
-entry:
- %0 = tail call i32 asm sideeffect "sub $0, $1, $2", "=r,r,J"(i32 %i, i32 2) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-K.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-K.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-K.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-K.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
-
-define i32 @constraint_K(i32 %i, i32 %j) nounwind {
-entry:
- %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,K"(i32 %i, i32 -1) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-L.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-L.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-L.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-L.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
-
-define i32 @constraint_L(i32 %i, i32 %j) nounwind {
-entry:
- %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,L"(i32 %i, i64 -1) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-M.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-M.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-M.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-M.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'M'
-
-define i32 @constraint_M(i32 %i, i32 %j) nounwind {
-entry:
- %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,M"(i32 305418240) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-error-N.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-error-N.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-error-N.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-error-N.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc -march=arm64 < %s 2> %t
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
-
-define i32 @constraint_N(i32 %i, i32 %j) nounwind {
-entry:
- %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,N"(i64 1311761352401879040) nounwind
- ret i32 %0
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm-zero-reg-error.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm-zero-reg-error.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm-zero-reg-error.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm-zero-reg-error.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: not llc < %s -march=arm64 2>&1 | FileCheck %s
-
-
-; The 'z' constraint allocates either xzr or wzr, but obviously an input of 1 is
-; incompatible.
-define void @test_bad_zero_reg() {
- tail call void asm sideeffect "USE($0)", "z"(i32 1) nounwind
-; CHECK: error: invalid operand for inline asm constraint 'z'
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/inline-asm.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/inline-asm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/inline-asm.ll (removed)
@@ -1,230 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -no-integrated-as | FileCheck %s
-
-; rdar://9167275
-
-define i32 @t1() nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: mov {{w[0-9]+}}, 7
- %0 = tail call i32 asm "mov ${0:w}, 7", "=r"() nounwind
- ret i32 %0
-}
-
-define i64 @t2() nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: mov {{x[0-9]+}}, 7
- %0 = tail call i64 asm "mov $0, 7", "=r"() nounwind
- ret i64 %0
-}
-
-define i64 @t3() nounwind ssp {
-entry:
-; CHECK-LABEL: t3:
-; CHECK: mov {{w[0-9]+}}, 7
- %0 = tail call i64 asm "mov ${0:w}, 7", "=r"() nounwind
- ret i64 %0
-}
-
-; rdar://9281206
-
-define void @t4(i64 %op) nounwind {
-entry:
-; CHECK-LABEL: t4:
-; CHECK: mov x0, {{x[0-9]+}}; svc #0
- %0 = tail call i64 asm sideeffect "mov x0, $1; svc #0;", "=r,r,r,~{x0}"(i64 %op, i64 undef) nounwind
- ret void
-}
-
-; rdar://9394290
-
-define float @t5(float %x) nounwind {
-entry:
-; CHECK-LABEL: t5:
-; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
- %0 = tail call float asm "fadd ${0:s}, ${0:s}, ${0:s}", "=w,0"(float %x) nounwind
- ret float %0
-}
-
-; rdar://9553599
-
-define zeroext i8 @t6(i8* %src) nounwind {
-entry:
-; CHECK-LABEL: t6:
-; CHECK: ldtrb {{w[0-9]+}}, [{{x[0-9]+}}]
- %0 = tail call i8 asm "ldtrb ${0:w}, [$1]", "=r,r"(i8* %src) nounwind
- ret i8 %0
-}
-
-define void @t7(i8* %f, i32 %g) nounwind {
-entry:
- %f.addr = alloca i8*, align 8
- store i8* %f, i8** %f.addr, align 8
- ; CHECK-LABEL: t7:
- ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}]
- call void asm "str ${1:w}, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
- ret void
-}
-
-; rdar://10258229
-; ARM64TargetLowering::getRegForInlineAsmConstraint() should recognize 'v'
-; registers.
-define void @t8() nounwind ssp {
-entry:
-; CHECK-LABEL: t8:
-; CHECK: stp {{d[0-9]+}}, {{d[0-9]+}}, [sp, #-16]
- tail call void asm sideeffect "nop", "~{v8}"() nounwind
- ret void
-}
-
-define i32 @constraint_I(i32 %i, i32 %j) nounwind {
-entry:
- ; CHECK-LABEL: constraint_I:
- %0 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 16773120) nounwind
- ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #16773120
- %1 = tail call i32 asm sideeffect "add ${0:w}, ${1:w}, $2", "=r,r,I"(i32 %i, i32 4096) nounwind
- ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4096
- ret i32 %1
-}
-
-define i32 @constraint_J(i32 %i, i32 %j) nounwind {
-entry:
- ; CHECK-LABEL: constraint_J:
- %0 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -16773120) nounwind
- ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4278194176
- %1 = tail call i32 asm sideeffect "sub ${0:w}, ${1:w}, $2", "=r,r,J"(i32 %i, i32 -1) nounwind
- ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4294967295
- ret i32 %1
-}
-
-define i32 @constraint_KL(i32 %i, i32 %j) nounwind {
-entry:
- ; CHECK-LABEL: constraint_KL:
- %0 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,K"(i32 %i, i32 255) nounwind
- ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #255
- %1 = tail call i32 asm sideeffect "eor ${0:w}, ${1:w}, $2", "=r,r,L"(i32 %i, i64 16711680) nounwind
- ; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, #16711680
- ret i32 %1
-}
-
-define i32 @constraint_MN(i32 %i, i32 %j) nounwind {
-entry:
- ; CHECK-LABEL: constraint_MN:
- %0 = tail call i32 asm sideeffect "movk ${0:w}, $1", "=r,M"(i32 65535) nounwind
- ; CHECK: movk {{w[0-9]+}}, #65535
- %1 = tail call i32 asm sideeffect "movz ${0:w}, $1", "=r,N"(i64 0) nounwind
- ; CHECK: movz {{w[0-9]+}}, #0
- ret i32 %1
-}
-
-define void @t9() nounwind {
-entry:
- ; CHECK-LABEL: t9:
- %data = alloca <2 x double>, align 16
- %0 = load <2 x double>* %data, align 16
- call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind
- ; CHECK: mov.2d v4, {{v[0-9]+}}
- ret void
-}
-
-define void @t10() nounwind {
-entry:
- ; CHECK-LABEL: t10:
- %data = alloca <2 x float>, align 8
- %a = alloca [2 x float], align 4
- %arraydecay = getelementptr inbounds [2 x float]* %a, i32 0, i32 0
- %0 = load <2 x float>* %data, align 8
- call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
- ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
- call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
- ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}]
- call void asm sideeffect "ldr ${1:s}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
- ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}]
- call void asm sideeffect "ldr ${1:h}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
- ; CHECK: ldr {{h[0-9]+}}, [{{x[0-9]+}}]
- call void asm sideeffect "ldr ${1:b}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind
- ; CHECK: ldr {{b[0-9]+}}, [{{x[0-9]+}}]
- ret void
-}
-
-define void @t11() nounwind {
-entry:
- ; CHECK-LABEL: t11:
- %a = alloca i32, align 4
- %0 = load i32* %a, align 4
- call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind
- ; CHECK: mov xzr, {{x[0-9]+}}
- %1 = load i32* %a, align 4
- call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind
- ; CHECK: mov wzr, {{w[0-9]+}}
- ret void
-}
-
-define void @t12() nounwind {
-entry:
- ; CHECK-LABEL: t12:
- %data = alloca <4 x float>, align 16
- %0 = load <4 x float>* %data, align 16
- call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind
- ; CHECK mov.2d v4, {{v([0-9])|(1[0-5])}}
- ret void
-}
-
-define void @t13() nounwind {
-entry:
- ; CHECK-LABEL: t13:
- tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 1311673391471656960) nounwind
- ; CHECK: mov x4, #1311673391471656960
- tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 -4662) nounwind
- ; CHECK: mov x4, #-4662
- tail call void asm sideeffect "mov x4, $0\0A", "N"(i64 4660) nounwind
- ; CHECK: mov x4, #4660
- call void asm sideeffect "mov x4, $0\0A", "N"(i64 -71777214294589696) nounwind
- ; CHECK: mov x4, #-71777214294589696
- ret void
-}
-
-define void @t14() nounwind {
-entry:
- ; CHECK-LABEL: t14:
- tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 305397760) nounwind
- ; CHECK: mov w4, #305397760
- tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 -4662) nounwind
- ; CHECK: mov w4, #4294962634
- tail call void asm sideeffect "mov w4, $0\0A", "M"(i32 4660) nounwind
- ; CHECK: mov w4, #4660
- call void asm sideeffect "mov w4, $0\0A", "M"(i32 -16711936) nounwind
- ; CHECK: mov w4, #4278255360
- ret void
-}
-
-define void @t15() nounwind {
-entry:
- %0 = tail call double asm sideeffect "fmov $0, d8", "=r"() nounwind
- ; CHECK: fmov {{x[0-9]+}}, d8
- ret void
-}
-
-; rdar://problem/14285178
-
-define void @test_zero_reg(i32* %addr) {
-; CHECK-LABEL: test_zero_reg:
-
- tail call void asm sideeffect "USE($0)", "z"(i32 0) nounwind
-; CHECK: USE(xzr)
-
- tail call void asm sideeffect "USE(${0:w})", "zr"(i32 0)
-; CHECK: USE(wzr)
-
- tail call void asm sideeffect "USE(${0:w})", "zr"(i32 1)
-; CHECK: orr [[VAL1:w[0-9]+]], wzr, #0x1
-; CHECK: USE([[VAL1]])
-
- tail call void asm sideeffect "USE($0), USE($1)", "z,z"(i32 0, i32 0) nounwind
-; CHECK: USE(xzr), USE(xzr)
-
- tail call void asm sideeffect "USE($0), USE(${1:w})", "z,z"(i32 0, i32 0) nounwind
-; CHECK: USE(xzr), USE(wzr)
-
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/join-reserved.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/join-reserved.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/join-reserved.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/join-reserved.ll (removed)
@@ -1,17 +0,0 @@
-; RUN: llc < %s -verify-machineinstrs | FileCheck %s
-target triple = "arm64-apple-macosx10"
-
-; Make sure that a store to [sp] addresses off sp directly.
-; A move isn't necessary.
-; <rdar://problem/11492712>
-; CHECK-LABEL: g:
-; CHECK: str xzr, [sp]
-; CHECK: bl
-; CHECK: ret
-define void @g() nounwind ssp {
-entry:
- tail call void (i32, ...)* @f(i32 0, i32 0) nounwind
- ret void
-}
-
-declare void @f(i32, ...)
Removed: llvm/trunk/test/CodeGen/ARM64/jumptable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/jumptable.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/jumptable.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/jumptable.ll (removed)
@@ -1,35 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-LINUX
-; <rdar://11417675>
-
-define void @sum(i32* %to) {
-entry:
- switch i32 undef, label %exit [
- i32 1, label %bb1
- i32 2, label %bb2
- i32 3, label %bb3
- i32 4, label %bb4
- ]
-bb1:
- store i32 undef, i32* %to
- br label %exit
-bb2:
- store i32 undef, i32* %to
- br label %exit
-bb3:
- store i32 undef, i32* %to
- br label %exit
-bb4:
- store i32 undef, i32* %to
- br label %exit
-exit:
- ret void
-}
-
-; CHECK-LABEL: sum:
-; CHECK: adrp {{x[0-9]+}}, LJTI0_0 at PAGE
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0 at PAGEOFF
-
-; CHECK-LINUX-LABEL: sum:
-; CHECK-LINUX: adrp {{x[0-9]+}}, .LJTI0_0
-; CHECK-LINUX: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0
Removed: llvm/trunk/test/CodeGen/ARM64/ld1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ld1.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ld1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ld1.ll (removed)
@@ -1,1345 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
-
-%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
-%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
-%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
-
-define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind {
-; CHECK-LABEL: ld2_8b
-; Make sure we are loading into the results defined by the ABI (i.e., v0, v1)
-; and from the argument of the function also defined by ABI (i.e., x0)
-; CHECK ld2.8b { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld2.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x2_t %tmp2
-}
-
-define %struct.__neon_int8x8x3_t @ld3_8b(i8* %A) nounwind {
-; CHECK-LABEL: ld3_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.8b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld3.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x3_t %tmp2
-}
-
-define %struct.__neon_int8x8x4_t @ld4_8b(i8* %A) nounwind {
-; CHECK-LABEL: ld4_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.8b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld4.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x4_t %tmp2
-}
-
-declare %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld2.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld3.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld4.v8i8.p0i8(i8*) nounwind readonly
-
-%struct.__neon_int8x16x2_t = type { <16 x i8>, <16 x i8> }
-%struct.__neon_int8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
-%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> }
-
-define %struct.__neon_int8x16x2_t @ld2_16b(i8* %A) nounwind {
-; CHECK-LABEL: ld2_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.16b { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x2_t %tmp2
-}
-
-define %struct.__neon_int8x16x3_t @ld3_16b(i8* %A) nounwind {
-; CHECK-LABEL: ld3_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.16b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x3_t %tmp2
-}
-
-define %struct.__neon_int8x16x4_t @ld4_16b(i8* %A) nounwind {
-; CHECK-LABEL: ld4_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.16b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x4_t %tmp2
-}
-
-declare %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4.v16i8.p0i8(i8*) nounwind readonly
-
-%struct.__neon_int16x4x2_t = type { <4 x i16>, <4 x i16> }
-%struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> }
-%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
-
-define %struct.__neon_int16x4x2_t @ld2_4h(i16* %A) nounwind {
-; CHECK-LABEL: ld2_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.4h { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld2.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x2_t %tmp2
-}
-
-define %struct.__neon_int16x4x3_t @ld3_4h(i16* %A) nounwind {
-; CHECK-LABEL: ld3_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.4h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld3.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x3_t %tmp2
-}
-
-define %struct.__neon_int16x4x4_t @ld4_4h(i16* %A) nounwind {
-; CHECK-LABEL: ld4_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.4h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld4.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x4_t %tmp2
-}
-
-declare %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld2.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld3.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld4.v4i16.p0i16(i16*) nounwind readonly
-
-%struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> }
-%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
-%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> }
-
-define %struct.__neon_int16x8x2_t @ld2_8h(i16* %A) nounwind {
-; CHECK-LABEL: ld2_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.8h { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x2_t %tmp2
-}
-
-define %struct.__neon_int16x8x3_t @ld3_8h(i16* %A) nounwind {
-; CHECK-LABEL: ld3_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.8h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x3_t %tmp2
-}
-
-define %struct.__neon_int16x8x4_t @ld4_8h(i16* %A) nounwind {
-; CHECK-LABEL: ld4_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.8h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x4_t %tmp2
-}
-
-declare %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4.v8i16.p0i16(i16*) nounwind readonly
-
-%struct.__neon_int32x2x2_t = type { <2 x i32>, <2 x i32> }
-%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
-%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
-
-define %struct.__neon_int32x2x2_t @ld2_2s(i32* %A) nounwind {
-; CHECK-LABEL: ld2_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.2s { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld2.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x2_t %tmp2
-}
-
-define %struct.__neon_int32x2x3_t @ld3_2s(i32* %A) nounwind {
-; CHECK-LABEL: ld3_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.2s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld3.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x3_t %tmp2
-}
-
-define %struct.__neon_int32x2x4_t @ld4_2s(i32* %A) nounwind {
-; CHECK-LABEL: ld4_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.2s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld4.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x4_t %tmp2
-}
-
-declare %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld2.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld3.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld4.v2i32.p0i32(i32*) nounwind readonly
-
-%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
-%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
-%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> }
-
-define %struct.__neon_int32x4x2_t @ld2_4s(i32* %A) nounwind {
-; CHECK-LABEL: ld2_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.4s { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x2_t %tmp2
-}
-
-define %struct.__neon_int32x4x3_t @ld3_4s(i32* %A) nounwind {
-; CHECK-LABEL: ld3_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.4s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x3_t %tmp2
-}
-
-define %struct.__neon_int32x4x4_t @ld4_4s(i32* %A) nounwind {
-; CHECK-LABEL: ld4_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.4s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x4_t %tmp2
-}
-
-declare %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4.v4i32.p0i32(i32*) nounwind readonly
-
-%struct.__neon_int64x2x2_t = type { <2 x i64>, <2 x i64> }
-%struct.__neon_int64x2x3_t = type { <2 x i64>, <2 x i64>, <2 x i64> }
-%struct.__neon_int64x2x4_t = type { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> }
-
-define %struct.__neon_int64x2x2_t @ld2_2d(i64* %A) nounwind {
-; CHECK-LABEL: ld2_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2.2d { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x2_t %tmp2
-}
-
-define %struct.__neon_int64x2x3_t @ld3_2d(i64* %A) nounwind {
-; CHECK-LABEL: ld3_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3.2d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x3_t %tmp2
-}
-
-define %struct.__neon_int64x2x4_t @ld4_2d(i64* %A) nounwind {
-; CHECK-LABEL: ld4_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4.2d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x4_t %tmp2
-}
-
-declare %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4.v2i64.p0i64(i64*) nounwind readonly
-
-%struct.__neon_int64x1x2_t = type { <1 x i64>, <1 x i64> }
-%struct.__neon_int64x1x3_t = type { <1 x i64>, <1 x i64>, <1 x i64> }
-%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
-
-
-define %struct.__neon_int64x1x2_t @ld2_1di64(i64* %A) nounwind {
-; CHECK-LABEL: ld2_1di64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x2_t %tmp2
-}
-
-define %struct.__neon_int64x1x3_t @ld3_1di64(i64* %A) nounwind {
-; CHECK-LABEL: ld3_1di64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x3_t %tmp2
-}
-
-define %struct.__neon_int64x1x4_t @ld4_1di64(i64* %A) nounwind {
-; CHECK-LABEL: ld4_1di64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x4_t %tmp2
-}
-
-
-declare %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4.v1i64.p0i64(i64*) nounwind readonly
-
-%struct.__neon_float64x1x2_t = type { <1 x double>, <1 x double> }
-%struct.__neon_float64x1x3_t = type { <1 x double>, <1 x double>, <1 x double> }
-%struct.__neon_float64x1x4_t = type { <1 x double>, <1 x double>, <1 x double>, <1 x double> }
-
-
-define %struct.__neon_float64x1x2_t @ld2_1df64(double* %A) nounwind {
-; CHECK-LABEL: ld2_1df64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_float64x1x2_t @llvm.arm64.neon.ld2.v1f64.p0f64(double* %A)
- ret %struct.__neon_float64x1x2_t %tmp2
-}
-
-define %struct.__neon_float64x1x3_t @ld3_1df64(double* %A) nounwind {
-; CHECK-LABEL: ld3_1df64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_float64x1x3_t @llvm.arm64.neon.ld3.v1f64.p0f64(double* %A)
- ret %struct.__neon_float64x1x3_t %tmp2
-}
-
-define %struct.__neon_float64x1x4_t @ld4_1df64(double* %A) nounwind {
-; CHECK-LABEL: ld4_1df64
-; Make sure we are using the operands defined by the ABI
-; CHECK ld1.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_float64x1x4_t @llvm.arm64.neon.ld4.v1f64.p0f64(double* %A)
- ret %struct.__neon_float64x1x4_t %tmp2
-}
-
-declare %struct.__neon_float64x1x2_t @llvm.arm64.neon.ld2.v1f64.p0f64(double*) nounwind readonly
-declare %struct.__neon_float64x1x3_t @llvm.arm64.neon.ld3.v1f64.p0f64(double*) nounwind readonly
-declare %struct.__neon_float64x1x4_t @llvm.arm64.neon.ld4.v1f64.p0f64(double*) nounwind readonly
-
-
-define %struct.__neon_int8x16x2_t @ld2lane_16b(<16 x i8> %L1, <16 x i8> %L2, i8* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld2lane_16b
-; CHECK ld2.b { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, i64 1, i8* %A)
- ret %struct.__neon_int8x16x2_t %tmp2
-}
-
-define %struct.__neon_int8x16x3_t @ld3lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i8* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld3lane_16b
-; CHECK ld3.b { v0, v1, v2 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i64 1, i8* %A)
- ret %struct.__neon_int8x16x3_t %tmp2
-}
-
-define %struct.__neon_int8x16x4_t @ld4lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i8* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld4lane_16b
-; CHECK ld4.b { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i64 1, i8* %A)
- ret %struct.__neon_int8x16x4_t %tmp2
-}
-
-declare %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2lane.v16i8.p0i8(<16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-declare %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-declare %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readonly
-
-define %struct.__neon_int16x8x2_t @ld2lane_8h(<8 x i16> %L1, <8 x i16> %L2, i16* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld2lane_8h
-; CHECK ld2.h { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, i64 1, i16* %A)
- ret %struct.__neon_int16x8x2_t %tmp2
-}
-
-define %struct.__neon_int16x8x3_t @ld3lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i16* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld3lane_8h
-; CHECK ld3.h { v0, v1, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i64 1, i16* %A)
- ret %struct.__neon_int16x8x3_t %tmp2
-}
-
-define %struct.__neon_int16x8x4_t @ld4lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i16* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld4lane_8h
-; CHECK ld4.h { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i64 1, i16* %A)
- ret %struct.__neon_int16x8x4_t %tmp2
-}
-
-declare %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2lane.v8i16.p0i16(<8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readonly
-
-define %struct.__neon_int32x4x2_t @ld2lane_4s(<4 x i32> %L1, <4 x i32> %L2, i32* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld2lane_4s
-; CHECK ld2.s { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, i64 1, i32* %A)
- ret %struct.__neon_int32x4x2_t %tmp2
-}
-
-define %struct.__neon_int32x4x3_t @ld3lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i32* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld3lane_4s
-; CHECK ld3.s { v0, v1, v2 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i64 1, i32* %A)
- ret %struct.__neon_int32x4x3_t %tmp2
-}
-
-define %struct.__neon_int32x4x4_t @ld4lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i32* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld4lane_4s
-; CHECK ld4.s { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i64 1, i32* %A)
- ret %struct.__neon_int32x4x4_t %tmp2
-}
-
-declare %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readonly
-
-define %struct.__neon_int64x2x2_t @ld2lane_2d(<2 x i64> %L1, <2 x i64> %L2, i64* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld2lane_2d
-; CHECK ld2.d { v0, v1 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, i64 1, i64* %A)
- ret %struct.__neon_int64x2x2_t %tmp2
-}
-
-define %struct.__neon_int64x2x3_t @ld3lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld3lane_2d
-; CHECK ld3.d { v0, v1, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64 1, i64* %A)
- ret %struct.__neon_int64x2x3_t %tmp2
-}
-
-define %struct.__neon_int64x2x4_t @ld4lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64* %A) nounwind {
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld4lane_2d
-; CHECK ld4.d { v0, v1, v2, v3 }[1], [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64 1, i64* %A)
- ret %struct.__neon_int64x2x4_t %tmp2
-}
-
-declare %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2lane.v2i64.p0i64(<2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-declare %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-declare %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readonly
-
-define <8 x i8> @ld1r_8b(i8* %bar) {
-; CHECK: ld1r_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.8b { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <8 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <8 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7
- ret <8 x i8> %tmp9
-}
-
-define <16 x i8> @ld1r_16b(i8* %bar) {
-; CHECK: ld1r_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.16b { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
- %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1
- %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2
- %tmp5 = insertelement <16 x i8> %tmp4, i8 %tmp1, i32 3
- %tmp6 = insertelement <16 x i8> %tmp5, i8 %tmp1, i32 4
- %tmp7 = insertelement <16 x i8> %tmp6, i8 %tmp1, i32 5
- %tmp8 = insertelement <16 x i8> %tmp7, i8 %tmp1, i32 6
- %tmp9 = insertelement <16 x i8> %tmp8, i8 %tmp1, i32 7
- %tmp10 = insertelement <16 x i8> %tmp9, i8 %tmp1, i32 8
- %tmp11 = insertelement <16 x i8> %tmp10, i8 %tmp1, i32 9
- %tmp12 = insertelement <16 x i8> %tmp11, i8 %tmp1, i32 10
- %tmp13 = insertelement <16 x i8> %tmp12, i8 %tmp1, i32 11
- %tmp14 = insertelement <16 x i8> %tmp13, i8 %tmp1, i32 12
- %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13
- %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14
- %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15
- ret <16 x i8> %tmp17
-}
-
-define <4 x i16> @ld1r_4h(i16* %bar) {
-; CHECK: ld1r_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.4h { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3
- ret <4 x i16> %tmp5
-}
-
-define <8 x i16> @ld1r_8h(i16* %bar) {
-; CHECK: ld1r_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.8h { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0
- %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1
- %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2
- %tmp5 = insertelement <8 x i16> %tmp4, i16 %tmp1, i32 3
- %tmp6 = insertelement <8 x i16> %tmp5, i16 %tmp1, i32 4
- %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5
- %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6
- %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7
- ret <8 x i16> %tmp9
-}
-
-define <2 x i32> @ld1r_2s(i32* %bar) {
-; CHECK: ld1r_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @ld1r_4s(i32* %bar) {
-; CHECK: ld1r_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0
- %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1
- %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2
- %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @ld1r_2d(i64* %bar) {
-; CHECK: ld1r_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0
- %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1
- ret <2 x i64> %tmp3
-}
-
-define %struct.__neon_int8x8x2_t @ld2r_8b(i8* %A) nounwind {
-; CHECK: ld2r_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.8b { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld2r.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x2_t %tmp2
-}
-
-define %struct.__neon_int8x8x3_t @ld3r_8b(i8* %A) nounwind {
-; CHECK: ld3r_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.8b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld3r.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x3_t %tmp2
-}
-
-define %struct.__neon_int8x8x4_t @ld4r_8b(i8* %A) nounwind {
-; CHECK: ld4r_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.8b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld4r.v8i8.p0i8(i8* %A)
- ret %struct.__neon_int8x8x4_t %tmp2
-}
-
-declare %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld2r.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld3r.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld4r.v8i8.p0i8(i8*) nounwind readonly
-
-define %struct.__neon_int8x16x2_t @ld2r_16b(i8* %A) nounwind {
-; CHECK: ld2r_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.16b { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2r.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x2_t %tmp2
-}
-
-define %struct.__neon_int8x16x3_t @ld3r_16b(i8* %A) nounwind {
-; CHECK: ld3r_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.16b { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3r.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x3_t %tmp2
-}
-
-define %struct.__neon_int8x16x4_t @ld4r_16b(i8* %A) nounwind {
-; CHECK: ld4r_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.16b { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4r.v16i8.p0i8(i8* %A)
- ret %struct.__neon_int8x16x4_t %tmp2
-}
-
-declare %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld2r.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld3r.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld4r.v16i8.p0i8(i8*) nounwind readonly
-
-define %struct.__neon_int16x4x2_t @ld2r_4h(i16* %A) nounwind {
-; CHECK: ld2r_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.4h { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld2r.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x2_t %tmp2
-}
-
-define %struct.__neon_int16x4x3_t @ld3r_4h(i16* %A) nounwind {
-; CHECK: ld3r_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.4h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld3r.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x3_t %tmp2
-}
-
-define %struct.__neon_int16x4x4_t @ld4r_4h(i16* %A) nounwind {
-; CHECK: ld4r_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.4h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld4r.v4i16.p0i16(i16* %A)
- ret %struct.__neon_int16x4x4_t %tmp2
-}
-
-declare %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld2r.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld3r.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld4r.v4i16.p0i16(i16*) nounwind readonly
-
-define %struct.__neon_int16x8x2_t @ld2r_8h(i16* %A) nounwind {
-; CHECK: ld2r_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.8h { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2r.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x2_t %tmp2
-}
-
-define %struct.__neon_int16x8x3_t @ld3r_8h(i16* %A) nounwind {
-; CHECK: ld3r_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.8h { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3r.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x3_t %tmp2
-}
-
-define %struct.__neon_int16x8x4_t @ld4r_8h(i16* %A) nounwind {
-; CHECK: ld4r_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.8h { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4r.v8i16.p0i16(i16* %A)
- ret %struct.__neon_int16x8x4_t %tmp2
-}
-
-declare %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld2r.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld3r.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld4r.v8i16.p0i16(i16*) nounwind readonly
-
-define %struct.__neon_int32x2x2_t @ld2r_2s(i32* %A) nounwind {
-; CHECK: ld2r_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.2s { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld2r.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x2_t %tmp2
-}
-
-define %struct.__neon_int32x2x3_t @ld3r_2s(i32* %A) nounwind {
-; CHECK: ld3r_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.2s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld3r.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x3_t %tmp2
-}
-
-define %struct.__neon_int32x2x4_t @ld4r_2s(i32* %A) nounwind {
-; CHECK: ld4r_2s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.2s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld4r.v2i32.p0i32(i32* %A)
- ret %struct.__neon_int32x2x4_t %tmp2
-}
-
-declare %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld2r.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld3r.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld4r.v2i32.p0i32(i32*) nounwind readonly
-
-define %struct.__neon_int32x4x2_t @ld2r_4s(i32* %A) nounwind {
-; CHECK: ld2r_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.4s { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2r.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x2_t %tmp2
-}
-
-define %struct.__neon_int32x4x3_t @ld3r_4s(i32* %A) nounwind {
-; CHECK: ld3r_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.4s { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3r.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x3_t %tmp2
-}
-
-define %struct.__neon_int32x4x4_t @ld4r_4s(i32* %A) nounwind {
-; CHECK: ld4r_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.4s { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4r.v4i32.p0i32(i32* %A)
- ret %struct.__neon_int32x4x4_t %tmp2
-}
-
-declare %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld2r.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld3r.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld4r.v4i32.p0i32(i32*) nounwind readonly
-
-define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind {
-; CHECK: ld2r_1d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.1d { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2r.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x2_t %tmp2
-}
-
-define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind {
-; CHECK: ld3r_1d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.1d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3r.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x3_t %tmp2
-}
-
-define %struct.__neon_int64x1x4_t @ld4r_1d(i64* %A) nounwind {
-; CHECK: ld4r_1d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.1d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4r.v1i64.p0i64(i64* %A)
- ret %struct.__neon_int64x1x4_t %tmp2
-}
-
-declare %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld2r.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld3r.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld4r.v1i64.p0i64(i64*) nounwind readonly
-
-define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind {
-; CHECK: ld2r_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld2r.2d { v0, v1 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2r.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x2_t %tmp2
-}
-
-define %struct.__neon_int64x2x3_t @ld3r_2d(i64* %A) nounwind {
-; CHECK: ld3r_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld3r.2d { v0, v1, v2 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3r.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x3_t %tmp2
-}
-
-define %struct.__neon_int64x2x4_t @ld4r_2d(i64* %A) nounwind {
-; CHECK: ld4r_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK ld4r.2d { v0, v1, v2, v3 }, [x0]
-; CHECK-NEXT ret
- %tmp2 = call %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4r.v2i64.p0i64(i64* %A)
- ret %struct.__neon_int64x2x4_t %tmp2
-}
-
-declare %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld2r.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld3r.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld4r.v2i64.p0i64(i64*) nounwind readonly
-
-define <16 x i8> @ld1_16b(<16 x i8> %V, i8* %bar) {
-; CHECK-LABEL: ld1_16b
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.b { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <16 x i8> %V, i8 %tmp1, i32 0
- ret <16 x i8> %tmp2
-}
-
-define <8 x i16> @ld1_8h(<8 x i16> %V, i16* %bar) {
-; CHECK-LABEL: ld1_8h
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.h { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <8 x i16> %V, i16 %tmp1, i32 0
- ret <8 x i16> %tmp2
-}
-
-define <4 x i32> @ld1_4s(<4 x i32> %V, i32* %bar) {
-; CHECK-LABEL: ld1_4s
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <4 x i32> %V, i32 %tmp1, i32 0
- ret <4 x i32> %tmp2
-}
-
-define <4 x float> @ld1_4s_float(<4 x float> %V, float* %bar) {
-; CHECK-LABEL: ld1_4s_float:
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load float* %bar
- %tmp2 = insertelement <4 x float> %V, float %tmp1, i32 0
- ret <4 x float> %tmp2
-}
-
-define <2 x i64> @ld1_2d(<2 x i64> %V, i64* %bar) {
-; CHECK-LABEL: ld1_2d
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.d { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i64* %bar
- %tmp2 = insertelement <2 x i64> %V, i64 %tmp1, i32 0
- ret <2 x i64> %tmp2
-}
-
-define <2 x double> @ld1_2d_double(<2 x double> %V, double* %bar) {
-; CHECK-LABEL: ld1_2d_double:
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.d { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load double* %bar
- %tmp2 = insertelement <2 x double> %V, double %tmp1, i32 0
- ret <2 x double> %tmp2
-}
-
-define <1 x i64> @ld1_1d(<1 x i64>* %p) {
-; CHECK-LABEL: ld1_1d
-; Make sure we are using the operands defined by the ABI
-; CHECK: ldr [[REG:d[0-9]+]], [x0]
-; CHECK-NEXT: ret
- %tmp = load <1 x i64>* %p, align 8
- ret <1 x i64> %tmp
-}
-
-define <8 x i8> @ld1_8b(<8 x i8> %V, i8* %bar) {
-; CHECK-LABEL: ld1_8b
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.b { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i8* %bar
- %tmp2 = insertelement <8 x i8> %V, i8 %tmp1, i32 0
- ret <8 x i8> %tmp2
-}
-
-define <4 x i16> @ld1_4h(<4 x i16> %V, i16* %bar) {
-; CHECK-LABEL: ld1_4h
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.h { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i16* %bar
- %tmp2 = insertelement <4 x i16> %V, i16 %tmp1, i32 0
- ret <4 x i16> %tmp2
-}
-
-define <2 x i32> @ld1_2s(<2 x i32> %V, i32* %bar) {
-; CHECK-LABEL: ld1_2s:
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load i32* %bar
- %tmp2 = insertelement <2 x i32> %V, i32 %tmp1, i32 0
- ret <2 x i32> %tmp2
-}
-
-define <2 x float> @ld1_2s_float(<2 x float> %V, float* %bar) {
-; CHECK-LABEL: ld1_2s_float:
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1.s { v0 }[0], [x0]
-; CHECK-NEXT ret
- %tmp1 = load float* %bar
- %tmp2 = insertelement <2 x float> %V, float %tmp1, i32 0
- ret <2 x float> %tmp2
-}
-
-
-; Add rdar://13098923 test case: vld1_dup_u32 doesn't generate ld1r.2s
-define void @ld1r_2s_from_dup(i8* nocapture %a, i8* nocapture %b, i16* nocapture %diff) nounwind ssp {
-entry:
-; CHECK: ld1r_2s_from_dup
-; CHECK: ld1r.2s { [[ARG1:v[0-9]+]] }, [x0]
-; CHECK-NEXT: ld1r.2s { [[ARG2:v[0-9]+]] }, [x1]
-; CHECK-NEXT: usubl.8h v[[RESREGNUM:[0-9]+]], [[ARG1]], [[ARG2]]
-; CHECK-NEXT: str d[[RESREGNUM]], [x2]
-; CHECK-NEXT: ret
- %tmp = bitcast i8* %a to i32*
- %tmp1 = load i32* %tmp, align 4
- %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0
- %lane = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer
- %tmp3 = bitcast <2 x i32> %lane to <8 x i8>
- %tmp4 = bitcast i8* %b to i32*
- %tmp5 = load i32* %tmp4, align 4
- %tmp6 = insertelement <2 x i32> undef, i32 %tmp5, i32 0
- %lane1 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> zeroinitializer
- %tmp7 = bitcast <2 x i32> %lane1 to <8 x i8>
- %vmovl.i.i = zext <8 x i8> %tmp3 to <8 x i16>
- %vmovl.i4.i = zext <8 x i8> %tmp7 to <8 x i16>
- %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i4.i
- %tmp8 = bitcast <8 x i16> %sub.i to <2 x i64>
- %shuffle.i = shufflevector <2 x i64> %tmp8, <2 x i64> undef, <1 x i32> zeroinitializer
- %tmp9 = bitcast <1 x i64> %shuffle.i to <4 x i16>
- %tmp10 = bitcast i16* %diff to <4 x i16>*
- store <4 x i16> %tmp9, <4 x i16>* %tmp10, align 8
- ret void
-}
-
-; Tests for rdar://11947069: vld1_dup_* and vld1q_dup_* code gen is suboptimal
-define <4 x float> @ld1r_4s_float(float* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_4s_float
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load float* %x, align 4
- %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0
- %tmp2 = insertelement <4 x float> %tmp1, float %tmp, i32 1
- %tmp3 = insertelement <4 x float> %tmp2, float %tmp, i32 2
- %tmp4 = insertelement <4 x float> %tmp3, float %tmp, i32 3
- ret <4 x float> %tmp4
-}
-
-define <2 x float> @ld1r_2s_float(float* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_2s_float
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load float* %x, align 4
- %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0
- %tmp2 = insertelement <2 x float> %tmp1, float %tmp, i32 1
- ret <2 x float> %tmp2
-}
-
-define <2 x double> @ld1r_2d_double(double* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_2d_double
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load double* %x, align 4
- %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0
- %tmp2 = insertelement <2 x double> %tmp1, double %tmp, i32 1
- ret <2 x double> %tmp2
-}
-
-define <1 x double> @ld1r_1d_double(double* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_1d_double
-; Make sure we are using the operands defined by the ABI
-; CHECK: ldr d0, [x0]
-; CHECK-NEXT ret
- %tmp = load double* %x, align 4
- %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0
- ret <1 x double> %tmp1
-}
-
-define <4 x float> @ld1r_4s_float_shuff(float* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_4s_float_shuff
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.4s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load float* %x, align 4
- %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0
- %lane = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
- ret <4 x float> %lane
-}
-
-define <2 x float> @ld1r_2s_float_shuff(float* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_2s_float_shuff
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2s { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load float* %x, align 4
- %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0
- %lane = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
- ret <2 x float> %lane
-}
-
-define <2 x double> @ld1r_2d_double_shuff(double* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_2d_double_shuff
-; Make sure we are using the operands defined by the ABI
-; CHECK: ld1r.2d { v0 }, [x0]
-; CHECK-NEXT ret
- %tmp = load double* %x, align 4
- %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0
- %lane = shufflevector <2 x double> %tmp1, <2 x double> undef, <2 x i32> zeroinitializer
- ret <2 x double> %lane
-}
-
-define <1 x double> @ld1r_1d_double_shuff(double* nocapture %x) {
-entry:
-; CHECK-LABEL: ld1r_1d_double_shuff
-; Make sure we are using the operands defined by the ABI
-; CHECK: ldr d0, [x0]
-; CHECK-NEXT ret
- %tmp = load double* %x, align 4
- %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0
- %lane = shufflevector <1 x double> %tmp1, <1 x double> undef, <1 x i32> zeroinitializer
- ret <1 x double> %lane
-}
-
-%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
-%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
-%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> }
-
-declare %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld1x2.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld1x2.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld1x2.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x2x2_t @llvm.arm64.neon.ld1x2.v2f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld1x2.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x1x2_t @llvm.arm64.neon.ld1x2.v1f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x8x2_t @ld1_x2_v8i8(i8* %addr) {
-; CHECK-LABEL: ld1_x2_v8i8:
-; CHECK: ld1.8b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x8x2_t @llvm.arm64.neon.ld1x2.v8i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x8x2_t %val
-}
-
-define %struct.__neon_int16x4x2_t @ld1_x2_v4i16(i16* %addr) {
-; CHECK-LABEL: ld1_x2_v4i16:
-; CHECK: ld1.4h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x4x2_t @llvm.arm64.neon.ld1x2.v4i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x4x2_t %val
-}
-
-define %struct.__neon_int32x2x2_t @ld1_x2_v2i32(i32* %addr) {
-; CHECK-LABEL: ld1_x2_v2i32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x2x2_t @llvm.arm64.neon.ld1x2.v2i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x2x2_t %val
-}
-
-define %struct.__neon_float32x2x2_t @ld1_x2_v2f32(float* %addr) {
-; CHECK-LABEL: ld1_x2_v2f32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x2x2_t @llvm.arm64.neon.ld1x2.v2f32.p0f32(float* %addr)
- ret %struct.__neon_float32x2x2_t %val
-}
-
-define %struct.__neon_int64x1x2_t @ld1_x2_v1i64(i64* %addr) {
-; CHECK-LABEL: ld1_x2_v1i64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x1x2_t @llvm.arm64.neon.ld1x2.v1i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x1x2_t %val
-}
-
-define %struct.__neon_float64x1x2_t @ld1_x2_v1f64(double* %addr) {
-; CHECK-LABEL: ld1_x2_v1f64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x1x2_t @llvm.arm64.neon.ld1x2.v1f64.p0f64(double* %addr)
- ret %struct.__neon_float64x1x2_t %val
-}
-
-
-%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
-%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
-%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
-
-%struct.__neon_float64x2x2_t = type { <2 x double>, <2 x double> }
-%struct.__neon_float64x2x3_t = type { <2 x double>, <2 x double>, <2 x double> }
-%struct.__neon_float64x2x4_t = type { <2 x double>, <2 x double>, <2 x double>, <2 x double> }
-
-declare %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld1x2.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld1x2.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld1x2.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x4x2_t @llvm.arm64.neon.ld1x2.v4f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld1x2.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x2x2_t @llvm.arm64.neon.ld1x2.v2f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x16x2_t @ld1_x2_v16i8(i8* %addr) {
-; CHECK-LABEL: ld1_x2_v16i8:
-; CHECK: ld1.16b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x16x2_t @llvm.arm64.neon.ld1x2.v16i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x16x2_t %val
-}
-
-define %struct.__neon_int16x8x2_t @ld1_x2_v8i16(i16* %addr) {
-; CHECK-LABEL: ld1_x2_v8i16:
-; CHECK: ld1.8h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x8x2_t @llvm.arm64.neon.ld1x2.v8i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x8x2_t %val
-}
-
-define %struct.__neon_int32x4x2_t @ld1_x2_v4i32(i32* %addr) {
-; CHECK-LABEL: ld1_x2_v4i32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x4x2_t @llvm.arm64.neon.ld1x2.v4i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x4x2_t %val
-}
-
-define %struct.__neon_float32x4x2_t @ld1_x2_v4f32(float* %addr) {
-; CHECK-LABEL: ld1_x2_v4f32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x4x2_t @llvm.arm64.neon.ld1x2.v4f32.p0f32(float* %addr)
- ret %struct.__neon_float32x4x2_t %val
-}
-
-define %struct.__neon_int64x2x2_t @ld1_x2_v2i64(i64* %addr) {
-; CHECK-LABEL: ld1_x2_v2i64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x2x2_t @llvm.arm64.neon.ld1x2.v2i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x2x2_t %val
-}
-
-define %struct.__neon_float64x2x2_t @ld1_x2_v2f64(double* %addr) {
-; CHECK-LABEL: ld1_x2_v2f64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x2x2_t @llvm.arm64.neon.ld1x2.v2f64.p0f64(double* %addr)
- ret %struct.__neon_float64x2x2_t %val
-}
-
-declare %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld1x3.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld1x3.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld1x3.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x2x3_t @llvm.arm64.neon.ld1x3.v2f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld1x3.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x1x3_t @llvm.arm64.neon.ld1x3.v1f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x8x3_t @ld1_x3_v8i8(i8* %addr) {
-; CHECK-LABEL: ld1_x3_v8i8:
-; CHECK: ld1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x8x3_t @llvm.arm64.neon.ld1x3.v8i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x8x3_t %val
-}
-
-define %struct.__neon_int16x4x3_t @ld1_x3_v4i16(i16* %addr) {
-; CHECK-LABEL: ld1_x3_v4i16:
-; CHECK: ld1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x4x3_t @llvm.arm64.neon.ld1x3.v4i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x4x3_t %val
-}
-
-define %struct.__neon_int32x2x3_t @ld1_x3_v2i32(i32* %addr) {
-; CHECK-LABEL: ld1_x3_v2i32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x2x3_t @llvm.arm64.neon.ld1x3.v2i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x2x3_t %val
-}
-
-define %struct.__neon_float32x2x3_t @ld1_x3_v2f32(float* %addr) {
-; CHECK-LABEL: ld1_x3_v2f32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x2x3_t @llvm.arm64.neon.ld1x3.v2f32.p0f32(float* %addr)
- ret %struct.__neon_float32x2x3_t %val
-}
-
-define %struct.__neon_int64x1x3_t @ld1_x3_v1i64(i64* %addr) {
-; CHECK-LABEL: ld1_x3_v1i64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x1x3_t @llvm.arm64.neon.ld1x3.v1i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x1x3_t %val
-}
-
-define %struct.__neon_float64x1x3_t @ld1_x3_v1f64(double* %addr) {
-; CHECK-LABEL: ld1_x3_v1f64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x1x3_t @llvm.arm64.neon.ld1x3.v1f64.p0f64(double* %addr)
- ret %struct.__neon_float64x1x3_t %val
-}
-
-declare %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld1x3.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld1x3.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld1x3.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x4x3_t @llvm.arm64.neon.ld1x3.v4f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld1x3.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x2x3_t @llvm.arm64.neon.ld1x3.v2f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x16x3_t @ld1_x3_v16i8(i8* %addr) {
-; CHECK-LABEL: ld1_x3_v16i8:
-; CHECK: ld1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x16x3_t @llvm.arm64.neon.ld1x3.v16i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x16x3_t %val
-}
-
-define %struct.__neon_int16x8x3_t @ld1_x3_v8i16(i16* %addr) {
-; CHECK-LABEL: ld1_x3_v8i16:
-; CHECK: ld1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x8x3_t @llvm.arm64.neon.ld1x3.v8i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x8x3_t %val
-}
-
-define %struct.__neon_int32x4x3_t @ld1_x3_v4i32(i32* %addr) {
-; CHECK-LABEL: ld1_x3_v4i32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x4x3_t @llvm.arm64.neon.ld1x3.v4i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x4x3_t %val
-}
-
-define %struct.__neon_float32x4x3_t @ld1_x3_v4f32(float* %addr) {
-; CHECK-LABEL: ld1_x3_v4f32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x4x3_t @llvm.arm64.neon.ld1x3.v4f32.p0f32(float* %addr)
- ret %struct.__neon_float32x4x3_t %val
-}
-
-define %struct.__neon_int64x2x3_t @ld1_x3_v2i64(i64* %addr) {
-; CHECK-LABEL: ld1_x3_v2i64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x2x3_t @llvm.arm64.neon.ld1x3.v2i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x2x3_t %val
-}
-
-define %struct.__neon_float64x2x3_t @ld1_x3_v2f64(double* %addr) {
-; CHECK-LABEL: ld1_x3_v2f64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x2x3_t @llvm.arm64.neon.ld1x3.v2f64.p0f64(double* %addr)
- ret %struct.__neon_float64x2x3_t %val
-}
-
-declare %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld1x4.v8i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld1x4.v4i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld1x4.v2i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x2x4_t @llvm.arm64.neon.ld1x4.v2f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld1x4.v1i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x1x4_t @llvm.arm64.neon.ld1x4.v1f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x8x4_t @ld1_x4_v8i8(i8* %addr) {
-; CHECK-LABEL: ld1_x4_v8i8:
-; CHECK: ld1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x8x4_t @llvm.arm64.neon.ld1x4.v8i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x8x4_t %val
-}
-
-define %struct.__neon_int16x4x4_t @ld1_x4_v4i16(i16* %addr) {
-; CHECK-LABEL: ld1_x4_v4i16:
-; CHECK: ld1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x4x4_t @llvm.arm64.neon.ld1x4.v4i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x4x4_t %val
-}
-
-define %struct.__neon_int32x2x4_t @ld1_x4_v2i32(i32* %addr) {
-; CHECK-LABEL: ld1_x4_v2i32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x2x4_t @llvm.arm64.neon.ld1x4.v2i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x2x4_t %val
-}
-
-define %struct.__neon_float32x2x4_t @ld1_x4_v2f32(float* %addr) {
-; CHECK-LABEL: ld1_x4_v2f32:
-; CHECK: ld1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x2x4_t @llvm.arm64.neon.ld1x4.v2f32.p0f32(float* %addr)
- ret %struct.__neon_float32x2x4_t %val
-}
-
-define %struct.__neon_int64x1x4_t @ld1_x4_v1i64(i64* %addr) {
-; CHECK-LABEL: ld1_x4_v1i64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x1x4_t @llvm.arm64.neon.ld1x4.v1i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x1x4_t %val
-}
-
-define %struct.__neon_float64x1x4_t @ld1_x4_v1f64(double* %addr) {
-; CHECK-LABEL: ld1_x4_v1f64:
-; CHECK: ld1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x1x4_t @llvm.arm64.neon.ld1x4.v1f64.p0f64(double* %addr)
- ret %struct.__neon_float64x1x4_t %val
-}
-
-declare %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld1x4.v16i8.p0i8(i8*) nounwind readonly
-declare %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld1x4.v8i16.p0i16(i16*) nounwind readonly
-declare %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld1x4.v4i32.p0i32(i32*) nounwind readonly
-declare %struct.__neon_float32x4x4_t @llvm.arm64.neon.ld1x4.v4f32.p0f32(float*) nounwind readonly
-declare %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld1x4.v2i64.p0i64(i64*) nounwind readonly
-declare %struct.__neon_float64x2x4_t @llvm.arm64.neon.ld1x4.v2f64.p0f64(double*) nounwind readonly
-
-define %struct.__neon_int8x16x4_t @ld1_x4_v16i8(i8* %addr) {
-; CHECK-LABEL: ld1_x4_v16i8:
-; CHECK: ld1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int8x16x4_t @llvm.arm64.neon.ld1x4.v16i8.p0i8(i8* %addr)
- ret %struct.__neon_int8x16x4_t %val
-}
-
-define %struct.__neon_int16x8x4_t @ld1_x4_v8i16(i16* %addr) {
-; CHECK-LABEL: ld1_x4_v8i16:
-; CHECK: ld1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int16x8x4_t @llvm.arm64.neon.ld1x4.v8i16.p0i16(i16* %addr)
- ret %struct.__neon_int16x8x4_t %val
-}
-
-define %struct.__neon_int32x4x4_t @ld1_x4_v4i32(i32* %addr) {
-; CHECK-LABEL: ld1_x4_v4i32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int32x4x4_t @llvm.arm64.neon.ld1x4.v4i32.p0i32(i32* %addr)
- ret %struct.__neon_int32x4x4_t %val
-}
-
-define %struct.__neon_float32x4x4_t @ld1_x4_v4f32(float* %addr) {
-; CHECK-LABEL: ld1_x4_v4f32:
-; CHECK: ld1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float32x4x4_t @llvm.arm64.neon.ld1x4.v4f32.p0f32(float* %addr)
- ret %struct.__neon_float32x4x4_t %val
-}
-
-define %struct.__neon_int64x2x4_t @ld1_x4_v2i64(i64* %addr) {
-; CHECK-LABEL: ld1_x4_v2i64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_int64x2x4_t @llvm.arm64.neon.ld1x4.v2i64.p0i64(i64* %addr)
- ret %struct.__neon_int64x2x4_t %val
-}
-
-define %struct.__neon_float64x2x4_t @ld1_x4_v2f64(double* %addr) {
-; CHECK-LABEL: ld1_x4_v2f64:
-; CHECK: ld1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- %val = call %struct.__neon_float64x2x4_t @llvm.arm64.neon.ld1x4.v2f64.p0f64(double* %addr)
- ret %struct.__neon_float64x2x4_t %val
-}
Removed: llvm/trunk/test/CodeGen/ARM64/ldp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ldp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ldp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ldp.ll (removed)
@@ -1,149 +0,0 @@
-; RUN: llc < %s -march=arm64 -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -march=arm64 -arm64-unscaled-mem-op=true\
-; RUN: -verify-machineinstrs | FileCheck -check-prefix=LDUR_CHK %s
-
-; CHECK: ldp_int
-; CHECK: ldp
-define i32 @ldp_int(i32* %p) nounwind {
- %tmp = load i32* %p, align 4
- %add.ptr = getelementptr inbounds i32* %p, i64 1
- %tmp1 = load i32* %add.ptr, align 4
- %add = add nsw i32 %tmp1, %tmp
- ret i32 %add
-}
-
-; CHECK: ldp_long
-; CHECK: ldp
-define i64 @ldp_long(i64* %p) nounwind {
- %tmp = load i64* %p, align 8
- %add.ptr = getelementptr inbounds i64* %p, i64 1
- %tmp1 = load i64* %add.ptr, align 8
- %add = add nsw i64 %tmp1, %tmp
- ret i64 %add
-}
-
-; CHECK: ldp_float
-; CHECK: ldp
-define float @ldp_float(float* %p) nounwind {
- %tmp = load float* %p, align 4
- %add.ptr = getelementptr inbounds float* %p, i64 1
- %tmp1 = load float* %add.ptr, align 4
- %add = fadd float %tmp, %tmp1
- ret float %add
-}
-
-; CHECK: ldp_double
-; CHECK: ldp
-define double @ldp_double(double* %p) nounwind {
- %tmp = load double* %p, align 8
- %add.ptr = getelementptr inbounds double* %p, i64 1
- %tmp1 = load double* %add.ptr, align 8
- %add = fadd double %tmp, %tmp1
- ret double %add
-}
-
-; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
-define i32 @ldur_int(i32* %a) nounwind {
-; LDUR_CHK: ldur_int
-; LDUR_CHK: ldp [[DST1:w[0-9]+]], [[DST2:w[0-9]+]], [x0, #-8]
-; LDUR_CHK-NEXT: add w{{[0-9]+}}, [[DST2]], [[DST1]]
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i32* %a, i32 -1
- %tmp1 = load i32* %p1, align 2
- %p2 = getelementptr inbounds i32* %a, i32 -2
- %tmp2 = load i32* %p2, align 2
- %tmp3 = add i32 %tmp1, %tmp2
- ret i32 %tmp3
-}
-
-define i64 @ldur_long(i64* %a) nounwind ssp {
-; LDUR_CHK: ldur_long
-; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16]
-; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]]
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i64* %a, i64 -1
- %tmp1 = load i64* %p1, align 2
- %p2 = getelementptr inbounds i64* %a, i64 -2
- %tmp2 = load i64* %p2, align 2
- %tmp3 = add i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
-
-define float @ldur_float(float* %a) {
-; LDUR_CHK: ldur_float
-; LDUR_CHK: ldp [[DST1:s[0-9]+]], [[DST2:s[0-9]+]], [x0, #-8]
-; LDUR_CHK-NEXT: add s{{[0-9]+}}, [[DST2]], [[DST1]]
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds float* %a, i64 -1
- %tmp1 = load float* %p1, align 2
- %p2 = getelementptr inbounds float* %a, i64 -2
- %tmp2 = load float* %p2, align 2
- %tmp3 = fadd float %tmp1, %tmp2
- ret float %tmp3
-}
-
-define double @ldur_double(double* %a) {
-; LDUR_CHK: ldur_double
-; LDUR_CHK: ldp [[DST1:d[0-9]+]], [[DST2:d[0-9]+]], [x0, #-16]
-; LDUR_CHK-NEXT: add d{{[0-9]+}}, [[DST2]], [[DST1]]
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds double* %a, i64 -1
- %tmp1 = load double* %p1, align 2
- %p2 = getelementptr inbounds double* %a, i64 -2
- %tmp2 = load double* %p2, align 2
- %tmp3 = fadd double %tmp1, %tmp2
- ret double %tmp3
-}
-
-; Now check some boundary conditions
-define i64 @pairUpBarelyIn(i64* %a) nounwind ssp {
-; LDUR_CHK: pairUpBarelyIn
-; LDUR_CHK-NOT: ldur
-; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256]
-; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]]
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i64* %a, i64 -31
- %tmp1 = load i64* %p1, align 2
- %p2 = getelementptr inbounds i64* %a, i64 -32
- %tmp2 = load i64* %p2, align 2
- %tmp3 = add i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
-
-define i64 @pairUpBarelyOut(i64* %a) nounwind ssp {
-; LDUR_CHK: pairUpBarelyOut
-; LDUR_CHK-NOT: ldp
-; Don't be fragile about which loads or manipulations of the base register
-; are used---just check that there isn't an ldp before the add
-; LDUR_CHK: add
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i64* %a, i64 -32
- %tmp1 = load i64* %p1, align 2
- %p2 = getelementptr inbounds i64* %a, i64 -33
- %tmp2 = load i64* %p2, align 2
- %tmp3 = add i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
-
-define i64 @pairUpNotAligned(i64* %a) nounwind ssp {
-; LDUR_CHK: pairUpNotAligned
-; LDUR_CHK-NOT: ldp
-; LDUR_CHK: ldur
-; LDUR_CHK-NEXT: ldur
-; LDUR_CHK-NEXT: add
-; LDUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i64* %a, i64 -18
- %bp1 = bitcast i64* %p1 to i8*
- %bp1p1 = getelementptr inbounds i8* %bp1, i64 1
- %dp1 = bitcast i8* %bp1p1 to i64*
- %tmp1 = load i64* %dp1, align 1
-
- %p2 = getelementptr inbounds i64* %a, i64 -17
- %bp2 = bitcast i64* %p2 to i8*
- %bp2p1 = getelementptr inbounds i8* %bp2, i64 1
- %dp2 = bitcast i8* %bp2p1 to i64*
- %tmp2 = load i64* %dp2, align 1
-
- %tmp3 = add i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
Removed: llvm/trunk/test/CodeGen/ARM64/ldur.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ldur.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ldur.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ldur.ll (removed)
@@ -1,67 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define i64 @_f0(i64* %p) {
-; CHECK: f0:
-; CHECK: ldur x0, [x0, #-8]
-; CHECK-NEXT: ret
- %tmp = getelementptr inbounds i64* %p, i64 -1
- %ret = load i64* %tmp, align 2
- ret i64 %ret
-}
-define i32 @_f1(i32* %p) {
-; CHECK: f1:
-; CHECK: ldur w0, [x0, #-4]
-; CHECK-NEXT: ret
- %tmp = getelementptr inbounds i32* %p, i64 -1
- %ret = load i32* %tmp, align 2
- ret i32 %ret
-}
-define i16 @_f2(i16* %p) {
-; CHECK: f2:
-; CHECK: ldurh w0, [x0, #-2]
-; CHECK-NEXT: ret
- %tmp = getelementptr inbounds i16* %p, i64 -1
- %ret = load i16* %tmp, align 2
- ret i16 %ret
-}
-define i8 @_f3(i8* %p) {
-; CHECK: f3:
-; CHECK: ldurb w0, [x0, #-1]
-; CHECK-NEXT: ret
- %tmp = getelementptr inbounds i8* %p, i64 -1
- %ret = load i8* %tmp, align 2
- ret i8 %ret
-}
-
-define i64 @zext32(i8* %a) nounwind ssp {
-; CHECK-LABEL: zext32:
-; CHECK: ldur w0, [x0, #-12]
-; CHECK-NEXT: ret
- %p = getelementptr inbounds i8* %a, i64 -12
- %tmp1 = bitcast i8* %p to i32*
- %tmp2 = load i32* %tmp1, align 4
- %ret = zext i32 %tmp2 to i64
-
- ret i64 %ret
-}
-define i64 @zext16(i8* %a) nounwind ssp {
-; CHECK-LABEL: zext16:
-; CHECK: ldurh w0, [x0, #-12]
-; CHECK-NEXT: ret
- %p = getelementptr inbounds i8* %a, i64 -12
- %tmp1 = bitcast i8* %p to i16*
- %tmp2 = load i16* %tmp1, align 2
- %ret = zext i16 %tmp2 to i64
-
- ret i64 %ret
-}
-define i64 @zext8(i8* %a) nounwind ssp {
-; CHECK-LABEL: zext8:
-; CHECK: ldurb w0, [x0, #-12]
-; CHECK-NEXT: ret
- %p = getelementptr inbounds i8* %a, i64 -12
- %tmp2 = load i8* %p, align 1
- %ret = zext i8 %tmp2 to i64
-
- ret i64 %ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/ldxr-stxr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/ldxr-stxr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/ldxr-stxr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/ldxr-stxr.ll (removed)
@@ -1,270 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
-
-%0 = type { i64, i64 }
-
-define i128 @f0(i8* %p) nounwind readonly {
-; CHECK-LABEL: f0:
-; CHECK: ldxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
-entry:
- %ldrexd = tail call %0 @llvm.arm64.ldxp(i8* %p)
- %0 = extractvalue %0 %ldrexd, 1
- %1 = extractvalue %0 %ldrexd, 0
- %2 = zext i64 %0 to i128
- %3 = zext i64 %1 to i128
- %shl = shl nuw i128 %2, 64
- %4 = or i128 %shl, %3
- ret i128 %4
-}
-
-define i32 @f1(i8* %ptr, i128 %val) nounwind {
-; CHECK-LABEL: f1:
-; CHECK: stxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
-entry:
- %tmp4 = trunc i128 %val to i64
- %tmp6 = lshr i128 %val, 64
- %tmp7 = trunc i128 %tmp6 to i64
- %strexd = tail call i32 @llvm.arm64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
- ret i32 %strexd
-}
-
-declare %0 @llvm.arm64.ldxp(i8*) nounwind
-declare i32 @llvm.arm64.stxp(i64, i64, i8*) nounwind
-
- at var = global i64 0, align 8
-
-define void @test_load_i8(i8* %addr) {
-; CHECK-LABEL: test_load_i8:
-; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldxr.p0i8(i8* %addr)
- %shortval = trunc i64 %val to i8
- %extval = zext i8 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_i16(i16* %addr) {
-; CHECK-LABEL: test_load_i16:
-; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldxr.p0i16(i16* %addr)
- %shortval = trunc i64 %val to i16
- %extval = zext i16 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_i32(i32* %addr) {
-; CHECK-LABEL: test_load_i32:
-; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldxr.p0i32(i32* %addr)
- %shortval = trunc i64 %val to i32
- %extval = zext i32 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_i64(i64* %addr) {
-; CHECK-LABEL: test_load_i64:
-; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldxr.p0i64(i64* %addr)
- store i64 %val, i64* @var, align 8
- ret void
-}
-
-
-declare i64 @llvm.arm64.ldxr.p0i8(i8*) nounwind
-declare i64 @llvm.arm64.ldxr.p0i16(i16*) nounwind
-declare i64 @llvm.arm64.ldxr.p0i32(i32*) nounwind
-declare i64 @llvm.arm64.ldxr.p0i64(i64*) nounwind
-
-define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
-; CHECK-LABEL: test_store_i8:
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: stxrb w0, w1, [x2]
- %extval = zext i8 %val to i64
- %res = call i32 @llvm.arm64.stxr.p0i8(i64 %extval, i8* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
-; CHECK-LABEL: test_store_i16:
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: stxrh w0, w1, [x2]
- %extval = zext i16 %val to i64
- %res = call i32 @llvm.arm64.stxr.p0i16(i64 %extval, i16* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
-; CHECK-LABEL: test_store_i32:
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: stxr w0, w1, [x2]
- %extval = zext i32 %val to i64
- %res = call i32 @llvm.arm64.stxr.p0i32(i64 %extval, i32* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_i64(i32, i64 %val, i64* %addr) {
-; CHECK-LABEL: test_store_i64:
-; CHECK: stxr w0, x1, [x2]
- %res = call i32 @llvm.arm64.stxr.p0i64(i64 %val, i64* %addr)
- ret i32 %res
-}
-
-declare i32 @llvm.arm64.stxr.p0i8(i64, i8*) nounwind
-declare i32 @llvm.arm64.stxr.p0i16(i64, i16*) nounwind
-declare i32 @llvm.arm64.stxr.p0i32(i64, i32*) nounwind
-declare i32 @llvm.arm64.stxr.p0i64(i64, i64*) nounwind
-
-; CHECK: test_clear:
-; CHECK: clrex
-define void @test_clear() {
- call void @llvm.arm64.clrex()
- ret void
-}
-
-declare void @llvm.arm64.clrex() nounwind
-
-define i128 @test_load_acquire_i128(i8* %p) nounwind readonly {
-; CHECK-LABEL: test_load_acquire_i128:
-; CHECK: ldaxp {{x[0-9]+}}, {{x[0-9]+}}, [x0]
-entry:
- %ldrexd = tail call %0 @llvm.arm64.ldaxp(i8* %p)
- %0 = extractvalue %0 %ldrexd, 1
- %1 = extractvalue %0 %ldrexd, 0
- %2 = zext i64 %0 to i128
- %3 = zext i64 %1 to i128
- %shl = shl nuw i128 %2, 64
- %4 = or i128 %shl, %3
- ret i128 %4
-}
-
-define i32 @test_store_release_i128(i8* %ptr, i128 %val) nounwind {
-; CHECK-LABEL: test_store_release_i128:
-; CHECK: stlxp {{w[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, [x0]
-entry:
- %tmp4 = trunc i128 %val to i64
- %tmp6 = lshr i128 %val, 64
- %tmp7 = trunc i128 %tmp6 to i64
- %strexd = tail call i32 @llvm.arm64.stlxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
- ret i32 %strexd
-}
-
-declare %0 @llvm.arm64.ldaxp(i8*) nounwind
-declare i32 @llvm.arm64.stlxp(i64, i64, i8*) nounwind
-
-define void @test_load_acquire_i8(i8* %addr) {
-; CHECK-LABEL: test_load_acquire_i8:
-; CHECK: ldaxrb w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldaxr.p0i8(i8* %addr)
- %shortval = trunc i64 %val to i8
- %extval = zext i8 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_acquire_i16(i16* %addr) {
-; CHECK-LABEL: test_load_acquire_i16:
-; CHECK: ldaxrh w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldaxr.p0i16(i16* %addr)
- %shortval = trunc i64 %val to i16
- %extval = zext i16 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_acquire_i32(i32* %addr) {
-; CHECK-LABEL: test_load_acquire_i32:
-; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldaxr.p0i32(i32* %addr)
- %shortval = trunc i64 %val to i32
- %extval = zext i32 %shortval to i64
- store i64 %extval, i64* @var, align 8
- ret void
-}
-
-define void @test_load_acquire_i64(i64* %addr) {
-; CHECK-LABEL: test_load_acquire_i64:
-; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
-; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
-
- %val = call i64 @llvm.arm64.ldaxr.p0i64(i64* %addr)
- store i64 %val, i64* @var, align 8
- ret void
-}
-
-
-declare i64 @llvm.arm64.ldaxr.p0i8(i8*) nounwind
-declare i64 @llvm.arm64.ldaxr.p0i16(i16*) nounwind
-declare i64 @llvm.arm64.ldaxr.p0i32(i32*) nounwind
-declare i64 @llvm.arm64.ldaxr.p0i64(i64*) nounwind
-
-define i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
-; CHECK-LABEL: test_store_release_i8:
-; CHECK-NOT: uxtb
-; CHECK-NOT: and
-; CHECK: stlxrb w0, w1, [x2]
- %extval = zext i8 %val to i64
- %res = call i32 @llvm.arm64.stlxr.p0i8(i64 %extval, i8* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
-; CHECK-LABEL: test_store_release_i16:
-; CHECK-NOT: uxth
-; CHECK-NOT: and
-; CHECK: stlxrh w0, w1, [x2]
- %extval = zext i16 %val to i64
- %res = call i32 @llvm.arm64.stlxr.p0i16(i64 %extval, i16* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_release_i32(i32, i32 %val, i32* %addr) {
-; CHECK-LABEL: test_store_release_i32:
-; CHECK-NOT: uxtw
-; CHECK-NOT: and
-; CHECK: stlxr w0, w1, [x2]
- %extval = zext i32 %val to i64
- %res = call i32 @llvm.arm64.stlxr.p0i32(i64 %extval, i32* %addr)
- ret i32 %res
-}
-
-define i32 @test_store_release_i64(i32, i64 %val, i64* %addr) {
-; CHECK-LABEL: test_store_release_i64:
-; CHECK: stlxr w0, x1, [x2]
- %res = call i32 @llvm.arm64.stlxr.p0i64(i64 %val, i64* %addr)
- ret i32 %res
-}
-
-declare i32 @llvm.arm64.stlxr.p0i8(i64, i8*) nounwind
-declare i32 @llvm.arm64.stlxr.p0i16(i64, i16*) nounwind
-declare i32 @llvm.arm64.stlxr.p0i32(i64, i32*) nounwind
-declare i32 @llvm.arm64.stlxr.p0i64(i64, i64*) nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/leaf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/leaf.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/leaf.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/leaf.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
-; rdar://12829704
-
-define void @t8() nounwind ssp {
-; CHECK-LABEL: t8:
-; CHECK-NOT: stp fp, lr, [sp, #-16]!
-; CHECK-NOT: mov fp, sp
-; CHECK: nop
-; CHECK-NOT: mov sp, fp
-; CHECK-NOT: ldp fp, lr, [sp], #16
- tail call void asm sideeffect "nop", "~{v8}"() nounwind
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/CodeGen/ARM64/lit.local.cfg (removed)
@@ -1,11 +0,0 @@
-import re
-
-config.suffixes = ['.ll']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
-# For now we don't test arm64-win32.
-if re.search(r'cygwin|mingw32|win32', config.target_triple):
- config.unsupported = True
Removed: llvm/trunk/test/CodeGen/ARM64/long-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/long-shift.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/long-shift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/long-shift.ll (removed)
@@ -1,59 +0,0 @@
-; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
-
-define i128 @shl(i128 %r, i128 %s) nounwind readnone {
-; CHECK-LABEL: shl:
-; CHECK: lsl [[XREG_0:x[0-9]+]], x1, x2
-; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lsr [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
-; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
-; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
-; CHECK-NEXT: lsl [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
-; CHECK-NEXT: cmp [[XREG_4]], #0
-; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge
-; CHECK-NEXT: lsl [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
-; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge
-; CHECK-NEXT: ret
-
- %shl = shl i128 %r, %s
- ret i128 %shl
-}
-
-define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
-; CHECK-LABEL: ashr:
-; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
-; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
-; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
-; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: asr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
-; CHECK-NEXT: cmp [[XREG_5]], #0
-; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: asr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
-; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
-; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
-; CHECK-NEXT: ret
-
- %shr = ashr i128 %r, %s
- ret i128 %shr
-}
-
-define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
-; CHECK-LABEL: lshr:
-; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
-; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
-; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
-; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
-; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
-; CHECK-NEXT: lsr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
-; CHECK-NEXT: cmp [[XREG_5]], #0
-; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
-; CHECK-NEXT: lsr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
-; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
-; CHECK-NEXT: ret
-
- %shr = lshr i128 %r, %s
- ret i128 %shr
-}
Removed: llvm/trunk/test/CodeGen/ARM64/memcpy-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/memcpy-inline.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/memcpy-inline.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/memcpy-inline.ll (removed)
@@ -1,112 +0,0 @@
-; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
-
-%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
-
- at src = external global %struct.x
- at dst = external global %struct.x
-
- at .str1 = private unnamed_addr constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 1
- at .str2 = private unnamed_addr constant [36 x i8] c"DHRYSTONE PROGRAM, SOME STRING BLAH\00", align 1
- at .str3 = private unnamed_addr constant [24 x i8] c"DHRYSTONE PROGRAM, SOME\00", align 1
- at .str4 = private unnamed_addr constant [18 x i8] c"DHRYSTONE PROGR \00", align 1
- at .str5 = private unnamed_addr constant [7 x i8] c"DHRYST\00", align 1
- at .str6 = private unnamed_addr constant [14 x i8] c"/tmp/rmXXXXXX\00", align 1
- at spool.splbuf = internal global [512 x i8] zeroinitializer, align 16
-
-define i32 @t0() {
-entry:
-; CHECK-LABEL: t0:
-; CHECK: ldrb [[REG0:w[0-9]+]], [x[[BASEREG:[0-9]+]], #10]
-; CHECK: strb [[REG0]], [x[[BASEREG2:[0-9]+]], #10]
-; CHECK: ldrh [[REG1:w[0-9]+]], [x[[BASEREG]], #8]
-; CHECK: strh [[REG1]], [x[[BASEREG2]], #8]
-; CHECK: ldr [[REG2:x[0-9]+]],
-; CHECK: str [[REG2]],
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
- ret i32 0
-}
-
-define void @t1(i8* nocapture %C) nounwind {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: ldur [[DEST:q[0-9]+]], [x[[BASEREG:[0-9]+]], #15]
-; CHECK: stur [[DEST]], [x0, #15]
-; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
-; CHECK: str [[DEST]], [x0]
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false)
- ret void
-}
-
-define void @t2(i8* nocapture %C) nounwind {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: movz [[REG3:w[0-9]+]]
-; CHECK: movk [[REG3]],
-; CHECK: str [[REG3]], [x0, #32]
-; CHECK: ldp [[DEST1:q[0-9]+]], [[DEST2:q[0-9]+]], [x{{[0-9]+}}]
-; CHECK: stp [[DEST1]], [[DEST2]], [x0]
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false)
- ret void
-}
-
-define void @t3(i8* nocapture %C) nounwind {
-entry:
-; CHECK-LABEL: t3:
-; CHECK: ldr [[REG4:x[0-9]+]], [x[[BASEREG:[0-9]+]], #16]
-; CHECK: str [[REG4]], [x0, #16]
-; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]
-; CHECK: str [[DEST]], [x0]
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false)
- ret void
-}
-
-define void @t4(i8* nocapture %C) nounwind {
-entry:
-; CHECK-LABEL: t4:
-; CHECK: orr [[REG5:w[0-9]+]], wzr, #0x20
-; CHECK: strh [[REG5]], [x0, #16]
-; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}]
-; CHECK: str [[REG6]], [x0]
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
- ret void
-}
-
-define void @t5(i8* nocapture %C) nounwind {
-entry:
-; CHECK-LABEL: t5:
-; CHECK: strb wzr, [x0, #6]
-; CHECK: movz [[REG7:w[0-9]+]], #0x5453
-; CHECK: strh [[REG7]], [x0, #4]
-; CHECK: movz [[REG8:w[0-9]+]],
-; CHECK: movk [[REG8]],
-; CHECK: str [[REG8]], [x0]
- tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false)
- ret void
-}
-
-define void @t6() nounwind {
-entry:
-; CHECK-LABEL: t6:
-; CHECK: ldur [[REG9:x[0-9]+]], [x{{[0-9]+}}, #6]
-; CHECK: stur [[REG9]], [x{{[0-9]+}}, #6]
-; CHECK: ldr
-; CHECK: str
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false)
- ret void
-}
-
-%struct.Foo = type { i32, i32, i32, i32 }
-
-define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
-entry:
-; CHECK: t7
-; CHECK: ldr [[REG10:q[0-9]+]], [x1]
-; CHECK: str [[REG10]], [x0]
- %0 = bitcast %struct.Foo* %a to i8*
- %1 = bitcast %struct.Foo* %b to i8*
- tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* %1, i32 16, i32 4, i1 false)
- ret void
-}
-
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/memset-inline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/memset-inline.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/memset-inline.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/memset-inline.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define void @t1(i8* nocapture %c) nounwind optsize {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: str wzr, [x0, #8]
-; CHECK: str xzr, [x0]
- call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
- ret void
-}
-
-define void @t2() nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: strh wzr, [sp, #32]
-; CHECK: stp xzr, xzr, [sp, #16]
-; CHECK: str xzr, [sp, #8]
- %buf = alloca [26 x i8], align 1
- %0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0
- call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
- call void @something(i8* %0) nounwind
- ret void
-}
-
-declare void @something(i8*) nounwind
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/memset-to-bzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/memset-to-bzero.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/memset-to-bzero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/memset-to-bzero.ll (removed)
@@ -1,108 +0,0 @@
-; RUN: llc %s -mtriple=arm64-apple-darwin -o - | \
-; RUN: FileCheck --check-prefix=CHECK-DARWIN --check-prefix=CHECK %s
-; RUN: llc %s -mtriple=arm64-linux-gnu -o - | \
-; RUN: FileCheck --check-prefix=CHECK-LINUX --check-prefix=CHECK %s
-; <rdar://problem/14199482> ARM64: Calls to bzero() replaced with calls to memset()
-
-; CHECK: @fct1
-; For small size (<= 256), we do not change memset to bzero.
-; CHECK: memset
-define void @fct1(i8* nocapture %ptr) {
-entry:
- tail call void @llvm.memset.p0i8.i64(i8* %ptr, i8 0, i64 256, i32 1, i1 false)
- ret void
-}
-
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)
-
-; CHECK: @fct2
-; When the size is bigger than 256, change into bzero.
-; CHECK-DARWIN: bzero
-; CHECK-LINUX: memset
-define void @fct2(i8* nocapture %ptr) {
-entry:
- tail call void @llvm.memset.p0i8.i64(i8* %ptr, i8 0, i64 257, i32 1, i1 false)
- ret void
-}
-
-; CHECK: @fct3
-; For unknown size, change to bzero.
-; CHECK-DARWIN: bzero
-; CHECK-LINUX: memset
-define void @fct3(i8* nocapture %ptr, i32 %unknown) {
-entry:
- %conv = sext i32 %unknown to i64
- tail call void @llvm.memset.p0i8.i64(i8* %ptr, i8 0, i64 %conv, i32 1, i1 false)
- ret void
-}
-
-; CHECK: @fct4
-; Size <= 256, no change.
-; CHECK: memset
-define void @fct4(i8* %ptr) {
-entry:
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 0, i64 256, i64 %tmp)
- ret void
-}
-
-declare i8* @__memset_chk(i8*, i32, i64, i64)
-
-declare i64 @llvm.objectsize.i64(i8*, i1)
-
-; CHECK: @fct5
-; Size > 256, change.
-; CHECK-DARWIN: bzero
-; CHECK-LINUX: memset
-define void @fct5(i8* %ptr) {
-entry:
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 0, i64 257, i64 %tmp)
- ret void
-}
-
-; CHECK: @fct6
-; Size = unknown, change.
-; CHECK-DARWIN: bzero
-; CHECK-LINUX: memset
-define void @fct6(i8* %ptr, i32 %unknown) {
-entry:
- %conv = sext i32 %unknown to i64
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 0, i64 %conv, i64 %tmp)
- ret void
-}
-
-; Next functions check that memset is not turned into bzero
-; when the set constant is non-zero, whatever the given size.
-
-; CHECK: @fct7
-; memset with something that is not a zero, no change.
-; CHECK: memset
-define void @fct7(i8* %ptr) {
-entry:
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 1, i64 256, i64 %tmp)
- ret void
-}
-
-; CHECK: @fct8
-; memset with something that is not a zero, no change.
-; CHECK: memset
-define void @fct8(i8* %ptr) {
-entry:
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 1, i64 257, i64 %tmp)
- ret void
-}
-
-; CHECK: @fct9
-; memset with something that is not a zero, no change.
-; CHECK: memset
-define void @fct9(i8* %ptr, i32 %unknown) {
-entry:
- %conv = sext i32 %unknown to i64
- %tmp = tail call i64 @llvm.objectsize.i64(i8* %ptr, i1 false)
- %call = tail call i8* @__memset_chk(i8* %ptr, i32 1, i64 %conv, i64 %tmp)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/misched-basic-A53.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/misched-basic-A53.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/misched-basic-A53.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/misched-basic-A53.ll (removed)
@@ -1,124 +0,0 @@
-; REQUIRES: asserts
-; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
-;
-; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
-; much higher than the ADD instructions in order to hide latency. When not
-; specifying a subtarget, the MADD will remain near the end of the block.
-;
-; CHECK: ********** MI Scheduling **********
-; CHECK: main
-; CHECK: *** Final schedule for BB#2 ***
-; CHECK: MADDWrrr
-; CHECK: ADDWri
-; CHECK: ********** INTERVALS **********
- at main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
- at main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
-
-; Function Attrs: nounwind
-define i32 @main() #0 {
-entry:
- %retval = alloca i32, align 4
- %x = alloca [8 x i32], align 4
- %y = alloca [8 x i32], align 4
- %i = alloca i32, align 4
- %xx = alloca i32, align 4
- %yy = alloca i32, align 4
- store i32 0, i32* %retval
- %0 = bitcast [8 x i32]* %x to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
- %1 = bitcast [8 x i32]* %y to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
- store i32 0, i32* %xx, align 4
- store i32 0, i32* %yy, align 4
- store i32 0, i32* %i, align 4
- br label %for.cond
-
-for.cond: ; preds = %for.inc, %entry
- %2 = load i32* %i, align 4
- %cmp = icmp slt i32 %2, 8
- br i1 %cmp, label %for.body, label %for.end
-
-for.body: ; preds = %for.cond
- %3 = load i32* %i, align 4
- %idxprom = sext i32 %3 to i64
- %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
- %4 = load i32* %arrayidx, align 4
- %add = add nsw i32 %4, 1
- store i32 %add, i32* %xx, align 4
- %5 = load i32* %xx, align 4
- %add1 = add nsw i32 %5, 12
- store i32 %add1, i32* %xx, align 4
- %6 = load i32* %xx, align 4
- %add2 = add nsw i32 %6, 23
- store i32 %add2, i32* %xx, align 4
- %7 = load i32* %xx, align 4
- %add3 = add nsw i32 %7, 34
- store i32 %add3, i32* %xx, align 4
- %8 = load i32* %i, align 4
- %idxprom4 = sext i32 %8 to i64
- %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
- %9 = load i32* %arrayidx5, align 4
- %10 = load i32* %yy, align 4
- %mul = mul nsw i32 %10, %9
- store i32 %mul, i32* %yy, align 4
- br label %for.inc
-
-for.inc: ; preds = %for.body
- %11 = load i32* %i, align 4
- %inc = add nsw i32 %11, 1
- store i32 %inc, i32* %i, align 4
- br label %for.cond
-
-for.end: ; preds = %for.cond
- %12 = load i32* %xx, align 4
- %13 = load i32* %yy, align 4
- %add6 = add nsw i32 %12, %13
- ret i32 %add6
-}
-
-
-; The Cortex-A53 machine model will cause the FDIVvvv_42 to be raised to
-; hide latency. Whereas normally there would only be a single FADDvvv_4s
-; after it, this test checks to make sure there are more than one.
-;
-; CHECK: ********** MI Scheduling **********
-; CHECK: neon4xfloat:BB#0
-; CHECK: *** Final schedule for BB#0 ***
-; CHECK: FDIVv4f32
-; CHECK: FADDv4f32
-; CHECK: FADDv4f32
-; CHECK: ********** INTERVALS **********
-define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
- %tmp1 = fadd <4 x float> %A, %B;
- %tmp2 = fadd <4 x float> %A, %tmp1;
- %tmp3 = fadd <4 x float> %A, %tmp2;
- %tmp4 = fadd <4 x float> %A, %tmp3;
- %tmp5 = fadd <4 x float> %A, %tmp4;
- %tmp6 = fadd <4 x float> %A, %tmp5;
- %tmp7 = fadd <4 x float> %A, %tmp6;
- %tmp8 = fadd <4 x float> %A, %tmp7;
- %tmp9 = fdiv <4 x float> %A, %B;
- %tmp10 = fadd <4 x float> %tmp8, %tmp9;
-
- ret <4 x float> %tmp10
-}
-
-; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
-
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind }
-
-
-; Regression Test for PR19761
-; [ARM64] Cortex-a53 schedule mode can't handle NEON post-increment load
-;
-; Nothing explicit to check other than llc not crashing.
-define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
- %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8* %A)
- %tmp = getelementptr i8* %A, i32 32
- store i8* %tmp, i8** %ptr
- ret { <16 x i8>, <16 x i8> } %ld2
-}
-
-declare { <16 x i8>, <16 x i8> } @llvm.arm64.neon.ld2.v16i8.p0i8(i8*)
Removed: llvm/trunk/test/CodeGen/ARM64/misched-forwarding-A53.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/misched-forwarding-A53.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/misched-forwarding-A53.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/misched-forwarding-A53.ll (removed)
@@ -1,21 +0,0 @@
-; REQUIRES: asserts
-; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
-;
-; For Cortex-A53, shiftable operands that are not actually shifted
-; are not needed for an additional two cycles.
-;
-; CHECK: ********** MI Scheduling **********
-; CHECK: shiftable
-; CHECK: *** Final schedule for BB#0 ***
-; CHECK: ADDXrr %vreg0, %vreg2
-; CHECK: ADDXrs %vreg0, %vreg2, 5
-; CHECK: ********** INTERVALS **********
-define i64 @shiftable(i64 %A, i64 %B) {
- %tmp0 = sub i64 %B, 20
- %tmp1 = shl i64 %tmp0, 5;
- %tmp2 = add i64 %A, %tmp1;
- %tmp3 = add i64 %A, %tmp0
- %tmp4 = mul i64 %tmp2, %tmp3
-
- ret i64 %tmp4
-}
Removed: llvm/trunk/test/CodeGen/ARM64/movi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/movi.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/movi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/movi.ll (removed)
@@ -1,202 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-;==--------------------------------------------------------------------------==
-; Tests for MOV-immediate implemented with ORR-immediate.
-;==--------------------------------------------------------------------------==
-
-; 64-bit immed with 32-bit pattern size, rotated by 0.
-define i64 @test64_32_rot0() nounwind {
-; CHECK-LABEL: test64_32_rot0:
-; CHECK: orr x0, xzr, #0x700000007
- ret i64 30064771079
-}
-
-; 64-bit immed with 32-bit pattern size, rotated by 2.
-define i64 @test64_32_rot2() nounwind {
-; CHECK-LABEL: test64_32_rot2:
-; CHECK: orr x0, xzr, #0xc0000003c0000003
- ret i64 13835058071388291075
-}
-
-; 64-bit immed with 4-bit pattern size, rotated by 3.
-define i64 @test64_4_rot3() nounwind {
-; CHECK-LABEL: test64_4_rot3:
-; CHECK: orr x0, xzr, #0xeeeeeeeeeeeeeeee
- ret i64 17216961135462248174
-}
-
-; 32-bit immed with 32-bit pattern size, rotated by 16.
-define i32 @test32_32_rot16() nounwind {
-; CHECK-LABEL: test32_32_rot16:
-; CHECK: orr w0, wzr, #0xff0000
- ret i32 16711680
-}
-
-; 32-bit immed with 2-bit pattern size, rotated by 1.
-define i32 @test32_2_rot1() nounwind {
-; CHECK-LABEL: test32_2_rot1:
-; CHECK: orr w0, wzr, #0xaaaaaaaa
- ret i32 2863311530
-}
-
-;==--------------------------------------------------------------------------==
-; Tests for MOVZ with MOVK.
-;==--------------------------------------------------------------------------==
-
-define i32 @movz() nounwind {
-; CHECK-LABEL: movz:
-; CHECK: movz w0, #0x5
- ret i32 5
-}
-
-define i64 @movz_3movk() nounwind {
-; CHECK-LABEL: movz_3movk:
-; CHECK: movz x0, #0x5, lsl #48
-; CHECK-NEXT: movk x0, #0x1234, lsl #32
-; CHECK-NEXT: movk x0, #0xabcd, lsl #16
-; CHECK-NEXT: movk x0, #0x5678
- ret i64 1427392313513592
-}
-
-define i64 @movz_movk_skip1() nounwind {
-; CHECK-LABEL: movz_movk_skip1:
-; CHECK: movz x0, #0x5, lsl #32
-; CHECK-NEXT: movk x0, #0x4321, lsl #16
- ret i64 22601072640
-}
-
-define i64 @movz_skip1_movk() nounwind {
-; CHECK-LABEL: movz_skip1_movk:
-; CHECK: movz x0, #0x8654, lsl #32
-; CHECK-NEXT: movk x0, #0x1234
- ret i64 147695335379508
-}
-
-;==--------------------------------------------------------------------------==
-; Tests for MOVN with MOVK.
-;==--------------------------------------------------------------------------==
-
-define i64 @movn() nounwind {
-; CHECK-LABEL: movn:
-; CHECK: movn x0, #0x29
- ret i64 -42
-}
-
-define i64 @movn_skip1_movk() nounwind {
-; CHECK-LABEL: movn_skip1_movk:
-; CHECK: movn x0, #0x29, lsl #32
-; CHECK-NEXT: movk x0, #0x1234
- ret i64 -176093720012
-}
-
-;==--------------------------------------------------------------------------==
-; Tests for ORR with MOVK.
-;==--------------------------------------------------------------------------==
-; rdar://14987673
-
-define i64 @orr_movk1() nounwind {
-; CHECK-LABEL: orr_movk1:
-; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #0xdead, lsl #16
- ret i64 72056498262245120
-}
-
-define i64 @orr_movk2() nounwind {
-; CHECK-LABEL: orr_movk2:
-; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #0xdead, lsl #48
- ret i64 -2400982650836746496
-}
-
-define i64 @orr_movk3() nounwind {
-; CHECK-LABEL: orr_movk3:
-; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #0xdead, lsl #32
- ret i64 72020953688702720
-}
-
-define i64 @orr_movk4() nounwind {
-; CHECK-LABEL: orr_movk4:
-; CHECK: orr x0, xzr, #0xffff0000ffff0
-; CHECK: movk x0, #0xdead
- ret i64 72056494543068845
-}
-
-; rdar://14987618
-define i64 @orr_movk5() nounwind {
-; CHECK-LABEL: orr_movk5:
-; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #0xdead, lsl #16
- ret i64 -71777214836900096
-}
-
-define i64 @orr_movk6() nounwind {
-; CHECK-LABEL: orr_movk6:
-; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #0xdead, lsl #16
-; CHECK: movk x0, #0xdead, lsl #48
- ret i64 -2400982647117578496
-}
-
-define i64 @orr_movk7() nounwind {
-; CHECK-LABEL: orr_movk7:
-; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #0xdead, lsl #48
- ret i64 -2400982646575268096
-}
-
-define i64 @orr_movk8() nounwind {
-; CHECK-LABEL: orr_movk8:
-; CHECK: orr x0, xzr, #0xff00ff00ff00ff00
-; CHECK: movk x0, #0xdead
-; CHECK: movk x0, #0xdead, lsl #48
- ret i64 -2400982646575276371
-}
-
-; rdar://14987715
-define i64 @orr_movk9() nounwind {
-; CHECK-LABEL: orr_movk9:
-; CHECK: orr x0, xzr, #0xffffff000000000
-; CHECK: movk x0, #0xff00
-; CHECK: movk x0, #0xdead, lsl #16
- ret i64 1152921439623315200
-}
-
-define i64 @orr_movk10() nounwind {
-; CHECK-LABEL: orr_movk10:
-; CHECK: orr x0, xzr, #0xfffffffffffff00
-; CHECK: movk x0, #0xdead, lsl #16
- ret i64 1152921504047824640
-}
-
-define i64 @orr_movk11() nounwind {
-; CHECK-LABEL: orr_movk11:
-; CHECK: orr x0, xzr, #0xfff00000000000ff
-; CHECK: movk x0, #0xdead, lsl #16
-; CHECK: movk x0, #0xffff, lsl #32
- ret i64 -4222125209747201
-}
-
-define i64 @orr_movk12() nounwind {
-; CHECK-LABEL: orr_movk12:
-; CHECK: orr x0, xzr, #0xfff00000000000ff
-; CHECK: movk x0, #0xdead, lsl #32
- ret i64 -4258765016661761
-}
-
-define i64 @orr_movk13() nounwind {
-; CHECK-LABEL: orr_movk13:
-; CHECK: orr x0, xzr, #0xfffff000000
-; CHECK: movk x0, #0xdead
-; CHECK: movk x0, #0xdead, lsl #48
- ret i64 -2401245434149282131
-}
-
-; rdar://13944082
-define i64 @g() nounwind {
-; CHECK-LABEL: g:
-; CHECK: movz x0, #0xffff, lsl #48
-; CHECK: movk x0, #0x2
-entry:
- ret i64 -281474976710654
-}
Removed: llvm/trunk/test/CodeGen/ARM64/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/mul.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/mul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/mul.ll (removed)
@@ -1,90 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-; rdar://9296808
-; rdar://9349137
-
-define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK: umulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
- %tmp1 = zext i64 %a to i128
- %tmp2 = zext i64 %b to i128
- %tmp3 = mul i128 %tmp1, %tmp2
- ret i128 %tmp3
-}
-
-define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK: smulh {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
- %tmp1 = sext i64 %a to i128
- %tmp2 = sext i64 %b to i128
- %tmp3 = mul i128 %tmp1, %tmp2
- ret i128 %tmp3
-}
-
-define i64 @t3(i32 %a, i32 %b) nounwind {
-entry:
-; CHECK-LABEL: t3:
-; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
- %tmp1 = zext i32 %a to i64
- %tmp2 = zext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
-
-define i64 @t4(i32 %a, i32 %b) nounwind {
-entry:
-; CHECK-LABEL: t4:
-; CHECK: smull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
- %tmp1 = sext i32 %a to i64
- %tmp2 = sext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- ret i64 %tmp3
-}
-
-define i64 @t5(i32 %a, i32 %b, i64 %c) nounwind {
-entry:
-; CHECK-LABEL: t5:
-; CHECK: umaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
- %tmp1 = zext i32 %a to i64
- %tmp2 = zext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- %tmp4 = add i64 %c, %tmp3
- ret i64 %tmp4
-}
-
-define i64 @t6(i32 %a, i32 %b, i64 %c) nounwind {
-entry:
-; CHECK-LABEL: t6:
-; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
- %tmp1 = sext i32 %a to i64
- %tmp2 = sext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- %tmp4 = sub i64 %c, %tmp3
- ret i64 %tmp4
-}
-
-define i64 @t7(i32 %a, i32 %b) nounwind {
-entry:
-; CHECK-LABEL: t7:
-; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
- %tmp1 = zext i32 %a to i64
- %tmp2 = zext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- %tmp4 = sub i64 0, %tmp3
- ret i64 %tmp4
-}
-
-define i64 @t8(i32 %a, i32 %b) nounwind {
-entry:
-; CHECK-LABEL: t8:
-; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
- %tmp1 = sext i32 %a to i64
- %tmp2 = sext i32 %b to i64
- %tmp3 = mul i64 %tmp1, %tmp2
- %tmp4 = sub i64 0, %tmp3
- ret i64 %tmp4
-}
Removed: llvm/trunk/test/CodeGen/ARM64/named-reg-alloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/named-reg-alloc.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/named-reg-alloc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/named-reg-alloc.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
-
-define i32 @get_stack() nounwind {
-entry:
-; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name global variable
- %sp = call i32 @llvm.read_register.i32(metadata !0)
- ret i32 %sp
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-
-!0 = metadata !{metadata !"x5\00"}
Removed: llvm/trunk/test/CodeGen/ARM64/named-reg-notareg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/named-reg-notareg.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/named-reg-notareg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/named-reg-notareg.ll (removed)
@@ -1,13 +0,0 @@
-; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
-; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
-
-define i32 @get_stack() nounwind {
-entry:
-; CHECK: Invalid register name global variable
- %sp = call i32 @llvm.read_register.i32(metadata !0)
- ret i32 %sp
-}
-
-declare i32 @llvm.read_register.i32(metadata) nounwind
-
-!0 = metadata !{metadata !"notareg\00"}
Removed: llvm/trunk/test/CodeGen/ARM64/neg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/neg.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/neg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/neg.ll (removed)
@@ -1,71 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-
-define i32 @test_neg_i32(i32 %in) {
-; CHECK-LABEL: test_neg_i32:
-; CHECK: neg w0, w0
- %res = sub i32 0, %in
- ret i32 %res
-}
-
-define i64 @test_neg_i64(i64 %in) {
-; CHECK-LABEL: test_neg_i64:
-; CHECK: neg x0, x0
- %res = sub i64 0, %in
- ret i64 %res
-}
-
-define <8 x i8> @test_neg_v8i8(<8 x i8> %in) {
-; CHECK-LABEL: test_neg_v8i8:
-; CHECK: neg v0.8b, v0.8b
- %res = sub <8 x i8> zeroinitializer, %in
- ret <8 x i8> %res
-}
-
-define <4 x i16> @test_neg_v4i16(<4 x i16> %in) {
-; CHECK-LABEL: test_neg_v4i16:
-; CHECK: neg v0.4h, v0.4h
- %res = sub <4 x i16> zeroinitializer, %in
- ret <4 x i16> %res
-}
-
-define <2 x i32> @test_neg_v2i32(<2 x i32> %in) {
-; CHECK-LABEL: test_neg_v2i32:
-; CHECK: neg v0.2s, v0.2s
- %res = sub <2 x i32> zeroinitializer, %in
- ret <2 x i32> %res
-}
-
-define <16 x i8> @test_neg_v16i8(<16 x i8> %in) {
-; CHECK-LABEL: test_neg_v16i8:
-; CHECK: neg v0.16b, v0.16b
- %res = sub <16 x i8> zeroinitializer, %in
- ret <16 x i8> %res
-}
-
-define <8 x i16> @test_neg_v8i16(<8 x i16> %in) {
-; CHECK-LABEL: test_neg_v8i16:
-; CHECK: neg v0.8h, v0.8h
- %res = sub <8 x i16> zeroinitializer, %in
- ret <8 x i16> %res
-}
-
-define <4 x i32> @test_neg_v4i32(<4 x i32> %in) {
-; CHECK-LABEL: test_neg_v4i32:
-; CHECK: neg v0.4s, v0.4s
- %res = sub <4 x i32> zeroinitializer, %in
- ret <4 x i32> %res
-}
-
-define <2 x i64> @test_neg_v2i64(<2 x i64> %in) {
-; CHECK-LABEL: test_neg_v2i64:
-; CHECK: neg v0.2d, v0.2d
- %res = sub <2 x i64> zeroinitializer, %in
- ret <2 x i64> %res
-}
-
-define <1 x i64> @test_neg_v1i64(<1 x i64> %in) {
-; CHECK-LABEL: test_neg_v1i64:
-; CHECK: neg d0, d0
- %res = sub <1 x i64> zeroinitializer, %in
- ret <1 x i64> %res
-}
Removed: llvm/trunk/test/CodeGen/ARM64/neon-compare-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/neon-compare-instructions.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/neon-compare-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/neon-compare-instructions.ll (removed)
@@ -1,1191 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu < %s | FileCheck %s
-
-define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp eq <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp eq <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
- %tmp3 = icmp eq <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
- %tmp3 = icmp eq <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
- %tmp3 = icmp eq <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
- %tmp3 = icmp eq <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
- %tmp3 = icmp eq <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp sgt <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp sgt <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
- %tmp3 = icmp sgt <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
- %tmp3 = icmp sgt <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
- %tmp3 = icmp sgt <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
- %tmp3 = icmp sgt <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
- %tmp3 = icmp sgt <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b
- %tmp3 = icmp slt <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b
- %tmp3 = icmp slt <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h
- %tmp3 = icmp slt <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h
- %tmp3 = icmp slt <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
- %tmp3 = icmp slt <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
- %tmp3 = icmp slt <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LT implemented as GT, so check reversed operands.
-;CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
- %tmp3 = icmp slt <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp sge <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp sge <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
- %tmp3 = icmp sge <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
- %tmp3 = icmp sge <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
- %tmp3 = icmp sge <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
- %tmp3 = icmp sge <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
- %tmp3 = icmp sge <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b
- %tmp3 = icmp sle <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b
- %tmp3 = icmp sle <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h
- %tmp3 = icmp sle <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h
- %tmp3 = icmp sle <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s
- %tmp3 = icmp sle <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s
- %tmp3 = icmp sle <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LE implemented as GE, so check reversed operands.
-;CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d
- %tmp3 = icmp sle <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ugt <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ugt <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
- %tmp3 = icmp ugt <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
- %tmp3 = icmp ugt <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
- %tmp3 = icmp ugt <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
- %tmp3 = icmp ugt <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
- %tmp3 = icmp ugt <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b
- %tmp3 = icmp ult <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
- %tmp3 = icmp ult <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
- %tmp3 = icmp ult <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
- %tmp3 = icmp ult <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
- %tmp3 = icmp ult <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
- %tmp3 = icmp ult <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
- %tmp3 = icmp ult <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
-;CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp uge <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
-;CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp uge <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
-;CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
- %tmp3 = icmp uge <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
-;CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
- %tmp3 = icmp uge <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
-;CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
- %tmp3 = icmp uge <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
-;CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
- %tmp3 = icmp uge <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
-;CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
- %tmp3 = icmp uge <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
- %tmp3 = icmp ule <8 x i8> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
- %tmp3 = icmp ule <16 x i8> %A, %B;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
- %tmp3 = icmp ule <4 x i16> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
- %tmp3 = icmp ule <8 x i16> %A, %B;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
- %tmp3 = icmp ule <2 x i32> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
- %tmp3 = icmp ule <4 x i32> %A, %B;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
- %tmp3 = icmp ule <2 x i64> %A, %B;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-
-define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
-;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
- %tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
-;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
- %tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
-;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
- %tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
-;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
- %tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
-;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
- %tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
-;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
- %tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
-;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
- %tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-
-define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
-;CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
- %tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
-;CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
- %tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
-;CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
- %tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
-;CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
- %tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
-;CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
- %tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
-;CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
- %tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
-;CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
- %tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-
-define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
-;CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
- %tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
-;CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
- %tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
-;CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
- %tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
-;CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
- %tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
-;CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
- %tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
-;CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
- %tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
-;CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
- %tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
-;CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
- %tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
-;CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
- %tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
-;CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
- %tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
-;CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
- %tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
-;CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
- %tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
-;CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
- %tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
-;CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
- %tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
-;CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
- %tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
-;CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
- %tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
-;CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
- %tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
-;CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
- %tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
-;CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
- %tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
-;CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
- %tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
-;CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
- %tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
-;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
-;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
-;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
-;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
-;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
-;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
-;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0
-;CHECK-NEXT: mvn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, v[[ZERO]].8b
- %tmp3 = icmp uge <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, v[[ZERO]].16b
- %tmp3 = icmp uge <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v[[ZERO]].4h
- %tmp3 = icmp uge <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v[[ZERO]].8h
- %tmp3 = icmp uge <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, v[[ZERO]].2s
- %tmp3 = icmp uge <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, v[[ZERO]].4s
- %tmp3 = icmp uge <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
- %tmp3 = icmp uge <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-
-define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, v[[ZERO]].8b
- %tmp3 = icmp ugt <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, v[[ZERO]].16b
- %tmp3 = icmp ugt <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v[[ZERO]].4h
- %tmp3 = icmp ugt <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v[[ZERO]].8h
- %tmp3 = icmp ugt <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, v[[ZERO]].2s
- %tmp3 = icmp ugt <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, v[[ZERO]].4s
- %tmp3 = icmp ugt <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, v[[ZERO]].2d
- %tmp3 = icmp ugt <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v[[ZERO]].8b, v0.8b
- %tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v[[ZERO]].16b, v0.16b
- %tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v[[ZERO]].4h, v0.4h
- %tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v[[ZERO]].8h, v0.8h
- %tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v[[ZERO]].2s, v0.2s
- %tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v[[ZERO]].4s, v0.4s
- %tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LS implemented as HS, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v[[ZERO]].2d, v0.2d
- %tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v[[ZERO]].8b, {{v[0-9]+}}.8b
- %tmp3 = icmp ult <8 x i8> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
- ret <8 x i8> %tmp4
-}
-
-define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v[[ZERO]].16b, v0.16b
- %tmp3 = icmp ult <16 x i8> %A, zeroinitializer;
- %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
- ret <16 x i8> %tmp4
-}
-
-define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v[[ZERO]].4h, v0.4h
- %tmp3 = icmp ult <4 x i16> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
- ret <4 x i16> %tmp4
-}
-
-define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v[[ZERO]].8h, v0.8h
- %tmp3 = icmp ult <8 x i16> %A, zeroinitializer;
- %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi d[[ZERO:[0-9]+]], #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v[[ZERO]].2s, v0.2s
- %tmp3 = icmp ult <2 x i32> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
- ret <2 x i32> %tmp4
-}
-
-define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v[[ZERO]].4s, v0.4s
- %tmp3 = icmp ult <4 x i32> %A, zeroinitializer;
- %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
-; Using registers other than v0, v1 are possible, but would be odd.
-; LO implemented as HI, so check reversed operands.
-;CHECK: movi v[[ZERO:[0-9]+]].2d, #0
-;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v[[ZERO]].2d, v0.2d
- %tmp3 = icmp ult <2 x i64> %A, zeroinitializer;
- %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <1 x i64> @cmeqz_v1i64(<1 x i64> %A) {
-; CHECK-LABEL: cmeqz_v1i64:
-; CHECK: cmeq d0, d0, #0
- %tst = icmp eq <1 x i64> %A, <i64 0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @cmgez_v1i64(<1 x i64> %A) {
-; CHECK-LABEL: cmgez_v1i64:
-; CHECK: cmge d0, d0, #0
- %tst = icmp sge <1 x i64> %A, <i64 0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @cmgtz_v1i64(<1 x i64> %A) {
-; CHECK-LABEL: cmgtz_v1i64:
-; CHECK: cmgt d0, d0, #0
- %tst = icmp sgt <1 x i64> %A, <i64 0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @cmlez_v1i64(<1 x i64> %A) {
-; CHECK-LABEL: cmlez_v1i64:
-; CHECK: cmle d0, d0, #0
- %tst = icmp sle <1 x i64> %A, <i64 0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @cmltz_v1i64(<1 x i64> %A) {
-; CHECK-LABEL: cmltz_v1i64:
-; CHECK: cmlt d0, d0, #0
- %tst = icmp slt <1 x i64> %A, <i64 0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmeqz_v1f64(<1 x double> %A) {
-; CHECK-LABEL: fcmeqz_v1f64:
-; CHECK: fcmeq d0, d0, #0
- %tst = fcmp oeq <1 x double> %A, <double 0.0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmgez_v1f64(<1 x double> %A) {
-; CHECK-LABEL: fcmgez_v1f64:
-; CHECK: fcmge d0, d0, #0
- %tst = fcmp oge <1 x double> %A, <double 0.0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmgtz_v1f64(<1 x double> %A) {
-; CHECK-LABEL: fcmgtz_v1f64:
-; CHECK: fcmgt d0, d0, #0
- %tst = fcmp ogt <1 x double> %A, <double 0.0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmlez_v1f64(<1 x double> %A) {
-; CHECK-LABEL: fcmlez_v1f64:
-; CHECK: fcmle d0, d0, #0
- %tst = fcmp ole <1 x double> %A, <double 0.0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
-
-define <1 x i64> @fcmltz_v1f64(<1 x double> %A) {
-; CHECK-LABEL: fcmltz_v1f64:
-; CHECK: fcmlt d0, d0, #0
- %tst = fcmp olt <1 x double> %A, <double 0.0>
- %mask = sext <1 x i1> %tst to <1 x i64>
- ret <1 x i64> %mask
-}
Removed: llvm/trunk/test/CodeGen/ARM64/neon-v1i1-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/neon-v1i1-setcc.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/neon-v1i1-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/neon-v1i1-setcc.ll (removed)
@@ -1,74 +0,0 @@
-; RUN: llc %s -o - -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s
-
-; This is the analogue of AArch64's file of the same name. It's mostly testing
-; some form of correct lowering occurs, the tests are a little artificial but I
-; strongly suspect there's room for improved CodeGen (FIXME).
-
-define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
-; CHECK-LABEL: test_sext_extr_cmp_0:
-; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
-; CHECK: cset
- %1 = icmp sge <1 x i64> %v1, %v2
- %2 = extractelement <1 x i1> %1, i32 0
- %vget_lane = sext i1 %2 to i64
- ret i64 %vget_lane
-}
-
-define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) {
-; CHECK-LABEL: test_sext_extr_cmp_1:
-; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
- %1 = fcmp oeq <1 x double> %v1, %v2
- %2 = extractelement <1 x i1> %1, i32 0
- %vget_lane = sext i1 %2 to i64
- ret i64 %vget_lane
-}
-
-define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
-; CHECK-LABEL: test_select_v1i1_0:
-; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
- %1 = icmp eq <1 x i64> %v1, %v2
- %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
- ret <1 x i64> %res
-}
-
-define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) {
-; CHECK-LABEL: test_select_v1i1_1:
-; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
- %1 = fcmp oeq <1 x double> %v1, %v2
- %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
- ret <1 x i64> %res
-}
-
-define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) {
-; CHECK-LABEL: test_select_v1i1_2:
-; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
- %1 = icmp eq <1 x i64> %v1, %v2
- %res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3
- ret <1 x double> %res
-}
-
-define <1 x i64> @test_select_v1i1_3(i64 %lhs, i64 %rhs, <1 x i64> %v3) {
-; CHECK-LABEL: test_select_v1i1_3:
-; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
- %tst = icmp eq i64 %lhs, %rhs
- %evil = insertelement <1 x i1> undef, i1 %tst, i32 0
- %res = select <1 x i1> %evil, <1 x i64> zeroinitializer, <1 x i64> %v3
- ret <1 x i64> %res
-}
-
-define i32 @test_br_extr_cmp(<1 x i64> %v1, <1 x i64> %v2) {
-; CHECK-LABEL: test_br_extr_cmp:
-; CHECK: cmp x{{[0-9]+}}, x{{[0-9]+}}
- %1 = icmp eq <1 x i64> %v1, %v2
- %2 = extractelement <1 x i1> %1, i32 0
- br i1 %2, label %if.end, label %if.then
-
-if.then:
- ret i32 0;
-
-if.end:
- ret i32 1;
-}
Removed: llvm/trunk/test/CodeGen/ARM64/patchpoint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/patchpoint.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/patchpoint.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/patchpoint.ll (removed)
@@ -1,163 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone | FileCheck %s
-
-; Trivial patchpoint codegen
-;
-define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-; CHECK-LABEL: trivial_patchpoint_codegen:
-; CHECK: movz x16, #0xdead, lsl #32
-; CHECK-NEXT: movk x16, #0xbeef, lsl #16
-; CHECK-NEXT: movk x16, #0xcafe
-; CHECK-NEXT: blr x16
-; CHECK: movz x16, #0xdead, lsl #32
-; CHECK-NEXT: movk x16, #0xbeef, lsl #16
-; CHECK-NEXT: movk x16, #0xcaff
-; CHECK-NEXT: blr x16
-; CHECK: ret
- %resolveCall2 = inttoptr i64 244837814094590 to i8*
- %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
- %resolveCall3 = inttoptr i64 244837814094591 to i8*
- tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
- ret i64 %result
-}
-
-; Caller frame metadata with stackmaps. This should not be optimized
-; as a leaf function.
-;
-; CHECK-LABEL: caller_meta_leaf
-; CHECK: mov x29, sp
-; CHECK-NEXT: sub sp, sp, #32
-; CHECK: Ltmp
-; CHECK: mov sp, x29
-; CHECK: ret
-
-define void @caller_meta_leaf() {
-entry:
- %metadata = alloca i64, i32 3, align 8
- store i64 11, i64* %metadata
- store i64 12, i64* %metadata
- store i64 13, i64* %metadata
- call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
- ret void
-}
-
-; Test the webkit_jscc calling convention.
-; One argument will be passed in register, the other will be pushed on the stack.
-; Return value in x0.
-define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-; CHECK-LABEL: jscall_patchpoint_codegen:
-; CHECK: Ltmp
-; CHECK: str x{{.+}}, [sp]
-; CHECK-NEXT: mov x0, x{{.+}}
-; CHECK: Ltmp
-; CHECK-NEXT: movz x16, #0xffff, lsl #32
-; CHECK-NEXT: movk x16, #0xdead, lsl #16
-; CHECK-NEXT: movk x16, #0xbeef
-; CHECK-NEXT: blr x16
- %resolveCall2 = inttoptr i64 281474417671919 to i8*
- %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
- %resolveCall3 = inttoptr i64 244837814038255 to i8*
- tail call webkit_jscc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result)
- ret void
-}
-
-; Test if the arguments are properly aligned and that we don't store undef arguments.
-define i64 @jscall_patchpoint_codegen2(i64 %callee) {
-entry:
-; CHECK-LABEL: jscall_patchpoint_codegen2:
-; CHECK: Ltmp
-; CHECK: orr w{{.+}}, wzr, #0x6
-; CHECK-NEXT: str x{{.+}}, [sp, #24]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
-; CHECK-NEXT: str w{{.+}}, [sp, #16]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
-; CHECK-NEXT: str x{{.+}}, [sp]
-; CHECK: Ltmp
-; CHECK-NEXT: movz x16, #0xffff, lsl #32
-; CHECK-NEXT: movk x16, #0xdead, lsl #16
-; CHECK-NEXT: movk x16, #0xbeef
-; CHECK-NEXT: blr x16
- %call = inttoptr i64 281474417671919 to i8*
- %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6)
- ret i64 %result
-}
-
-; Test if the arguments are properly aligned and that we don't store undef arguments.
-define i64 @jscall_patchpoint_codegen3(i64 %callee) {
-entry:
-; CHECK-LABEL: jscall_patchpoint_codegen3:
-; CHECK: Ltmp
-; CHECK: movz w{{.+}}, #0xa
-; CHECK-NEXT: str x{{.+}}, [sp, #48]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x8
-; CHECK-NEXT: str w{{.+}}, [sp, #36]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x6
-; CHECK-NEXT: str x{{.+}}, [sp, #24]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
-; CHECK-NEXT: str w{{.+}}, [sp, #16]
-; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
-; CHECK-NEXT: str x{{.+}}, [sp]
-; CHECK: Ltmp
-; CHECK-NEXT: movz x16, #0xffff, lsl #32
-; CHECK-NEXT: movk x16, #0xdead, lsl #16
-; CHECK-NEXT: movk x16, #0xbeef
-; CHECK-NEXT: blr x16
- %call = inttoptr i64 281474417671919 to i8*
- %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10)
- ret i64 %result
-}
-
-; Test patchpoints reusing the same TargetConstant.
-; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4)
-; There is no way to verify this, since it depends on memory allocation.
-; But I think it's useful to include as a working example.
-define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) {
-entry:
- %tmp80 = add i64 %tmp79, -16
- %tmp81 = inttoptr i64 %tmp80 to i64*
- %tmp82 = load i64* %tmp81, align 8
- tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82)
- tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82)
- %tmp83 = load i64* %tmp33, align 8
- %tmp84 = add i64 %tmp83, -24
- %tmp85 = inttoptr i64 %tmp84 to i64*
- %tmp86 = load i64* %tmp85, align 8
- tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86)
- tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86)
- ret i64 10
-}
-
-; Test small patchpoints that don't emit calls.
-define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
-entry:
-; CHECK-LABEL: small_patchpoint_codegen:
-; CHECK: Ltmp
-; CHECK: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: ldp
-; CHECK-NEXT: ret
- %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2)
- ret void
-}
-
-; Test that scratch registers are spilled around patchpoints
-; CHECK: InlineAsm End
-; CHECK-NEXT: mov x{{[0-9]+}}, x16
-; CHECK-NEXT: mov x{{[0-9]+}}, x17
-; CHECK-NEXT: Ltmp
-; CHECK-NEXT: nop
-define void @clobberScratch(i32* %p) {
- %v = load i32* %p
- tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
- tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v)
- store i32 %v, i32* %p
- ret void
-}
-
-declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
Removed: llvm/trunk/test/CodeGen/ARM64/pic-local-symbol.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/pic-local-symbol.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/pic-local-symbol.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/pic-local-symbol.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc -mtriple=arm64-unknown-linux-gnu -relocation-model=pic < %s | FileCheck %s
-
- at a = internal unnamed_addr global i32 0, align 4
- at .str = private unnamed_addr constant [6 x i8] c"test\0A\00", align 1
-
-define i32 @get() {
-; CHECK: get:
-; CHECK: adrp x{{[0-9]+}}, a
-; CHECK-NEXT: ldr w{{[0-9]+}}, [x{{[0-9]}}, :lo12:a]
- %res = load i32* @a, align 4
- ret i32 %res
-}
-
-define void @foo() nounwind {
-; CHECK: foo:
-; CHECK: adrp x{{[0-9]}}, .L.str
-; CHECK-NEXT: add x{{[0-9]}}, x{{[0-9]}}, :lo12:.L.str
- tail call void @bar(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0))
- ret void
-}
-
-declare void @bar(i8*)
Removed: llvm/trunk/test/CodeGen/ARM64/platform-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/platform-reg.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/platform-reg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/platform-reg.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-DARWIN
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
-
-; x18 is reserved as a platform register on Darwin but not on other
-; systems. Create loads of register pressure and make sure this is respected.
-
-; Also, fp must always refer to a valid frame record, even if it's not the one
-; of the current function, so it shouldn't be used either.
-
- at var = global [30 x i64] zeroinitializer
-
-define void @keep_live() {
- %val = load volatile [30 x i64]* @var
- store volatile [30 x i64] %val, [30 x i64]* @var
-
-; CHECK: ldr x18
-; CHECK: str x18
-
-; CHECK-DARWIN-NOT: ldr fp
-; CHECK-DARWIN-NOT: ldr x18
-; CHECK-DARWIN: Spill
-; CHECK-DARWIN-NOT: ldr fp
-; CHECK-DARWIN-NOT: ldr x18
-; CHECK-DARWIN: ret
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/popcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/popcnt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/popcnt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/popcnt.ll (removed)
@@ -1,43 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
- %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
- ret i32 %cnt
-; CHECK: fmov s0, w0
-; CHECK: cnt.8b v0, v0
-; CHECK: uaddlv.8b h0, v0
-; CHECK: fmov w0, s0
-; CHECK: ret
-}
-
-define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
- %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
- ret i64 %cnt
-; CHECK: fmov d0, x0
-; CHECK: cnt.8b v0, v0
-; CHECK: uaddlv.8b h0, v0
-; CHECK: fmov w0, s0
-; CHECK: ret
-}
-
-; Do not use AdvSIMD when -mno-implicit-float is specified.
-; rdar://9473858
-
-define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat {
- %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
- ret i32 %cnt
-; CHECK-LABEL: cnt32:
-; CHECK-NOT 16b
-; CHECK: ret
-}
-
-define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat {
- %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
- ret i64 %cnt
-; CHECK-LABEL: cnt64:
-; CHECK-NOT 16b
-; CHECK: ret
-}
-
-declare i32 @llvm.ctpop.i32(i32) nounwind readnone
-declare i64 @llvm.ctpop.i64(i64) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/prefetch.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/prefetch.ll (removed)
@@ -1,88 +0,0 @@
-; RUN: llc %s -march arm64 -o - | FileCheck %s
-
- at a = common global i32* null, align 8
-
-define void @test(i32 %i, i32 %j) nounwind ssp {
-entry:
- ; CHECK: @test
- %j.addr = alloca i32, align 4
- store i32 %j, i32* %j.addr, align 4, !tbaa !0
- %tmp = bitcast i32* %j.addr to i8*
- ; CHECK: prfum pldl1strm
- call void @llvm.prefetch(i8* %tmp, i32 0, i32 0, i32 1)
- ; CHECK: prfum pldl3keep
- call void @llvm.prefetch(i8* %tmp, i32 0, i32 1, i32 1)
- ; CHECK: prfum pldl2keep
- call void @llvm.prefetch(i8* %tmp, i32 0, i32 2, i32 1)
- ; CHECK: prfum pldl1keep
- call void @llvm.prefetch(i8* %tmp, i32 0, i32 3, i32 1)
-
- ; CHECK: prfum pstl1strm
- call void @llvm.prefetch(i8* %tmp, i32 1, i32 0, i32 1)
- ; CHECK: prfum pstl3keep
- call void @llvm.prefetch(i8* %tmp, i32 1, i32 1, i32 1)
- ; CHECK: prfum pstl2keep
- call void @llvm.prefetch(i8* %tmp, i32 1, i32 2, i32 1)
- ; CHECK: prfum pstl1keep
- call void @llvm.prefetch(i8* %tmp, i32 1, i32 3, i32 1)
-
- %tmp1 = load i32* %j.addr, align 4, !tbaa !0
- %add = add nsw i32 %tmp1, %i
- %idxprom = sext i32 %add to i64
- %tmp2 = load i32** @a, align 8, !tbaa !3
- %arrayidx = getelementptr inbounds i32* %tmp2, i64 %idxprom
- %tmp3 = bitcast i32* %arrayidx to i8*
-
- ; CHECK: prfm pldl1strm
- call void @llvm.prefetch(i8* %tmp3, i32 0, i32 0, i32 1)
- %tmp4 = load i32** @a, align 8, !tbaa !3
- %arrayidx3 = getelementptr inbounds i32* %tmp4, i64 %idxprom
- %tmp5 = bitcast i32* %arrayidx3 to i8*
-
- ; CHECK: prfm pldl3keep
- call void @llvm.prefetch(i8* %tmp5, i32 0, i32 1, i32 1)
- %tmp6 = load i32** @a, align 8, !tbaa !3
- %arrayidx6 = getelementptr inbounds i32* %tmp6, i64 %idxprom
- %tmp7 = bitcast i32* %arrayidx6 to i8*
-
- ; CHECK: prfm pldl2keep
- call void @llvm.prefetch(i8* %tmp7, i32 0, i32 2, i32 1)
- %tmp8 = load i32** @a, align 8, !tbaa !3
- %arrayidx9 = getelementptr inbounds i32* %tmp8, i64 %idxprom
- %tmp9 = bitcast i32* %arrayidx9 to i8*
-
- ; CHECK: prfm pldl1keep
- call void @llvm.prefetch(i8* %tmp9, i32 0, i32 3, i32 1)
- %tmp10 = load i32** @a, align 8, !tbaa !3
- %arrayidx12 = getelementptr inbounds i32* %tmp10, i64 %idxprom
- %tmp11 = bitcast i32* %arrayidx12 to i8*
-
- ; CHECK: prfm pstl1strm
- call void @llvm.prefetch(i8* %tmp11, i32 1, i32 0, i32 1)
- %tmp12 = load i32** @a, align 8, !tbaa !3
- %arrayidx15 = getelementptr inbounds i32* %tmp12, i64 %idxprom
- %tmp13 = bitcast i32* %arrayidx15 to i8*
-
- ; CHECK: prfm pstl3keep
- call void @llvm.prefetch(i8* %tmp13, i32 1, i32 1, i32 1)
- %tmp14 = load i32** @a, align 8, !tbaa !3
- %arrayidx18 = getelementptr inbounds i32* %tmp14, i64 %idxprom
- %tmp15 = bitcast i32* %arrayidx18 to i8*
-
- ; CHECK: prfm pstl2keep
- call void @llvm.prefetch(i8* %tmp15, i32 1, i32 2, i32 1)
- %tmp16 = load i32** @a, align 8, !tbaa !3
- %arrayidx21 = getelementptr inbounds i32* %tmp16, i64 %idxprom
- %tmp17 = bitcast i32* %arrayidx21 to i8*
-
- ; CHECK: prfm pstl1keep
- call void @llvm.prefetch(i8* %tmp17, i32 1, i32 3, i32 1)
- ret void
-}
-
-declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind
-
-!0 = metadata !{metadata !"int", metadata !1}
-!1 = metadata !{metadata !"omnipotent char", metadata !2}
-!2 = metadata !{metadata !"Simple C/C++ TBAA"}
-!3 = metadata !{metadata !"any pointer", metadata !1}
Removed: llvm/trunk/test/CodeGen/ARM64/promote-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/promote-const.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/promote-const.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/promote-const.ll (removed)
@@ -1,255 +0,0 @@
-; Disable machine cse to stress the different path of the algorithm.
-; Otherwise, we always fall in the simple case, i.e., only one definition.
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -arm64-stress-promote-const -mcpu=cyclone | FileCheck -check-prefix=PROMOTED %s
-; The REGULAR run just checks that the inputs passed to promote const expose
-; the appropriate patterns.
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-machine-cse -arm64-promote-const=false -mcpu=cyclone | FileCheck -check-prefix=REGULAR %s
-
-%struct.uint8x16x4_t = type { [4 x <16 x i8>] }
-
-; Constant is a structure
-define %struct.uint8x16x4_t @test1() {
-; PROMOTED-LABEL: test1:
-; Promote constant has created a big constant for the whole structure
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], __PromotedConst at PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], __PromotedConst at PAGEOFF
-; Destination registers are defined by the ABI
-; PROMOTED-NEXT: ldp q0, q1, {{\[}}[[BASEADDR]]]
-; PROMOTED-NEXT: ldp q2, q3, {{\[}}[[BASEADDR]], #32]
-; PROMOTED-NEXT: ret
-
-; REGULAR-LABEL: test1:
-; Regular access is quite bad, it performs 4 loads, one for each chunk of
-; the structure
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; Destination registers are defined by the ABI
-; REGULAR: ldr q0, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR: ldr q1, {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; REGULAR: adrp [[PAGEADDR2:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
-; REGULAR: ldr q2, {{\[}}[[PAGEADDR2]], [[CSTLABEL2]]@PAGEOFF]
-; REGULAR: adrp [[PAGEADDR3:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
-; REGULAR: ldr q3, {{\[}}[[PAGEADDR3]], [[CSTLABEL3]]@PAGEOFF]
-; REGULAR-NEXT: ret
-entry:
- ret %struct.uint8x16x4_t { [4 x <16 x i8>] [<16 x i8> <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, <16 x i8> <i8 32, i8 124, i8 121, i8 120, i8 8, i8 117, i8 -56, i8 113, i8 -76, i8 110, i8 -53, i8 107, i8 7, i8 105, i8 103, i8 102>, <16 x i8> <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>, <16 x i8> <i8 -104, i8 83, i8 -20, i8 81, i8 81, i8 80, i8 -59, i8 78, i8 73, i8 77, i8 -37, i8 75, i8 122, i8 74, i8 37, i8 73>] }
-}
-
-; Two different uses of the same constant in the same basic block
-define <16 x i8> @test2(<16 x i8> %arg) {
-entry:
-; PROMOTED-LABEL: test2:
-; In stress mode, constant vector are promoted
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
-; Destination register is defined by ABI
-; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: ret
-
-; REGULAR-LABEL: test2:
-; Regular access is strickly the same as promoted access.
-; The difference is that the address (and thus the space in memory) is not
-; shared between constants
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: mla.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: ret
- %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- %add.i9 = add <16 x i8> %add.i, %mul.i
- ret <16 x i8> %add.i9
-}
-
-; Two different uses of the sane constant in two different basic blocks,
-; one dominates the other
-define <16 x i8> @test3(<16 x i8> %arg, i32 %path) {
-; PROMOTED-LABEL: test3:
-; In stress mode, constant vector are promoted
-; Since, the constant is the same as the previous function,
-; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
-; Destination register is defined by ABI
-; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV2]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[BASEADDR]]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; PROMOTED-NEXT: add.16b v0, v0, [[DESTV]]
-; PROMOTED-NEXT: ret
-
-; REGULAR-LABEL: test3:
-; Regular mode does not elimitate common sub expression by its own.
-; In other words, the same loads appears several times.
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: cbz w0, [[LABELelse:LBB.*]]
-; Next BB
-; Redundant load
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF]
-; REGULAR-NEXT: b [[LABELend:LBB.*]]
-; Next BB
-; REGULAR-NEXT: [[LABELelse]]
-; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL2]]@PAGEOFF]
-; Next BB
-; REGULAR-NEXT: [[LABELend]]:
-; REGULAR-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; REGULAR-NEXT: add.16b v0, v0, [[DESTV]]
-; REGULAR-NEXT: ret
-entry:
- %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- %tobool = icmp eq i32 %path, 0
- br i1 %tobool, label %if.else, label %if.then
-
-if.then: ; preds = %entry
- %mul.i13 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- br label %if.end
-
-if.else: ; preds = %entry
- %mul.i = mul <16 x i8> %add.i, <i8 -24, i8 99, i8 -121, i8 97, i8 66, i8 95, i8 24, i8 93, i8 6, i8 91, i8 12, i8 89, i8 39, i8 87, i8 86, i8 85>
- br label %if.end
-
-if.end: ; preds = %if.else, %if.then
- %ret2.0 = phi <16 x i8> [ %mul.i13, %if.then ], [ %mul.i, %if.else ]
- %add.i12 = add <16 x i8> %add.i, %ret2.0
- ret <16 x i8> %add.i12
-}
-
-; Two different uses of the sane constant in two different basic blocks,
-; none dominates the other
-define <16 x i8> @test4(<16 x i8> %arg, i32 %path) {
-; PROMOTED-LABEL: test4:
-; In stress mode, constant vector are promoted
-; Since, the constant is the same as the previous function,
-; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
-; Destination register is defined by ABI
-; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
-; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: mul.16b v0, v0, v[[REGNUM]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: ret
-
-
-; REGULAR-LABEL: test4:
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]]
-; REGULAR-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; Redundant expression
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF]
-; Destination register is defined by ABI
-; REGULAR-NEXT: mul.16b v0, v0, v[[REGNUM]]
-; Next BB
-; REGULAR-NEXT: [[LABEL]]:
-; REGULAR-NEXT: ret
-entry:
- %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- %tobool = icmp eq i32 %path, 0
- br i1 %tobool, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- %mul.i = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- br label %if.end
-
-if.end: ; preds = %entry, %if.then
- %ret.0 = phi <16 x i8> [ %mul.i, %if.then ], [ %add.i, %entry ]
- ret <16 x i8> %ret.0
-}
-
-; Two different uses of the sane constant in two different basic blocks,
-; one is in a phi.
-define <16 x i8> @test5(<16 x i8> %arg, i32 %path) {
-; PROMOTED-LABEL: test5:
-; In stress mode, constant vector are promoted
-; Since, the constant is the same as the previous function,
-; the same address must be used
-; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
-; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
-; Next BB
-; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]]
-; Next BB
-; PROMOTED-NEXT: [[LABEL]]:
-; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]]
-; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; PROMOTED-NEXT: ret
-
-; REGULAR-LABEL: test5:
-; REGULAR: cbz w0, [[LABELelse:LBB.*]]
-; Next BB
-; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
-; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]]
-; REGULAR-NEXT: b [[LABELend:LBB.*]]
-; Next BB
-; REGULAR-NEXT: [[LABELelse]]
-; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE
-; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF]
-; Next BB
-; REGULAR-NEXT: [[LABELend]]:
-; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]]
-; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]]
-; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]]
-; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]]
-; REGULAR-NEXT: ret
-entry:
- %tobool = icmp eq i32 %path, 0
- br i1 %tobool, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- %add.i = add <16 x i8> %arg, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- %mul.i26 = mul <16 x i8> %add.i, <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>
- br label %if.end
-
-if.end: ; preds = %entry, %if.then
- %ret.0 = phi <16 x i8> [ %mul.i26, %if.then ], [ <i8 -40, i8 -93, i8 -118, i8 -99, i8 -75, i8 -105, i8 74, i8 -110, i8 62, i8 -115, i8 -119, i8 -120, i8 34, i8 -124, i8 0, i8 -128>, %entry ]
- %mul.i25 = mul <16 x i8> %ret.0, %ret.0
- %mul.i24 = mul <16 x i8> %mul.i25, %mul.i25
- %mul.i23 = mul <16 x i8> %mul.i24, %mul.i24
- %mul.i = mul <16 x i8> %mul.i23, %mul.i23
- ret <16 x i8> %mul.i
-}
-
-define void @accessBig(i64* %storage) {
-; PROMOTED-LABEL: accessBig:
-; PROMOTED: adrp
-; PROMOTED: ret
- %addr = bitcast i64* %storage to <1 x i80>*
- store <1 x i80> <i80 483673642326615442599424>, <1 x i80>* %addr
- ret void
-}
-
-define void @asmStatement() {
-; PROMOTED-LABEL: asmStatement:
-; PROMOTED-NOT: adrp
-; PROMOTED: ret
- call void asm sideeffect "bfxil w0, w0, $0, $1", "i,i"(i32 28, i32 4)
- ret void
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/redzone.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/redzone.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/redzone.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/redzone.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-redzone | FileCheck %s
-
-define i32 @foo(i32 %a, i32 %b) nounwind ssp {
-; CHECK-LABEL: foo:
-; CHECK-NOT: sub sp, sp
-; CHECK: ret
- %a.addr = alloca i32, align 4
- %b.addr = alloca i32, align 4
- %x = alloca i32, align 4
- store i32 %a, i32* %a.addr, align 4
- store i32 %b, i32* %b.addr, align 4
- %tmp = load i32* %a.addr, align 4
- %tmp1 = load i32* %b.addr, align 4
- %add = add nsw i32 %tmp, %tmp1
- store i32 %add, i32* %x, align 4
- %tmp2 = load i32* %x, align 4
- ret i32 %tmp2
-}
Removed: llvm/trunk/test/CodeGen/ARM64/reg-copy-noneon.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/reg-copy-noneon.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/reg-copy-noneon.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/reg-copy-noneon.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=-neon < %s | FileCheck %s
-
-define float @copy_FPR32(float %a, float %b) {
-;CHECK-LABEL: copy_FPR32:
-;CHECK: fmov s0, s1
- ret float %b;
-}
-
-define double @copy_FPR64(double %a, double %b) {
-;CHECK-LABEL: copy_FPR64:
-;CHECK: fmov d0, d1
- ret double %b;
-}
-
-define fp128 @copy_FPR128(fp128 %a, fp128 %b) {
-;CHECK-LABEL: copy_FPR128:
-;CHECK: str q1, [sp, #-16]!
-;CHECK-NEXT: ldr q0, [sp, #16]!
- ret fp128 %b;
-}
Removed: llvm/trunk/test/CodeGen/ARM64/register-offset-addressing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/register-offset-addressing.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/register-offset-addressing.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/register-offset-addressing.ll (removed)
@@ -1,145 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-
-define i8 @test_64bit_add(i16* %a, i64 %b) {
-; CHECK-LABEL: test_64bit_add:
-; CHECK: lsl [[REG:x[0-9]+]], x1, #1
-; CHECK: ldrb w0, [x0, [[REG]]]
-; CHECK: ret
- %tmp1 = getelementptr inbounds i16* %a, i64 %b
- %tmp2 = load i16* %tmp1
- %tmp3 = trunc i16 %tmp2 to i8
- ret i8 %tmp3
-}
-
-; These tests are trying to form SEXT and ZEXT operations that never leave i64
-; space, to make sure LLVM can adapt the offset register correctly.
-define void @ldst_8bit(i8* %base, i64 %offset) minsize {
-; CHECK-LABEL: ldst_8bit:
-
- %off32.sext.tmp = shl i64 %offset, 32
- %off32.sext = ashr i64 %off32.sext.tmp, 32
- %addr8_sxtw = getelementptr i8* %base, i64 %off32.sext
- %val8_sxtw = load volatile i8* %addr8_sxtw
- %val32_signed = sext i8 %val8_sxtw to i32
- store volatile i32 %val32_signed, i32* @var_32bit
-; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
-
- %addrint_uxtw = ptrtoint i8* %base to i64
- %offset_uxtw = and i64 %offset, 4294967295
- %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
- %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8*
- %val8_uxtw = load volatile i8* %addr_uxtw
- %newval8 = add i8 %val8_uxtw, 1
- store volatile i8 %newval8, i8* @var_8bit
-; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
-
- ret void
-}
-
-
-define void @ldst_16bit(i16* %base, i64 %offset) minsize {
-; CHECK-LABEL: ldst_16bit:
-
- %addrint_uxtw = ptrtoint i16* %base to i64
- %offset_uxtw = and i64 %offset, 4294967295
- %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
- %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16*
- %val8_uxtw = load volatile i16* %addr_uxtw
- %newval8 = add i16 %val8_uxtw, 1
- store volatile i16 %newval8, i16* @var_16bit
-; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
-
- %base_sxtw = ptrtoint i16* %base to i64
- %offset_sxtw.tmp = shl i64 %offset, 32
- %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
- %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
- %addr_sxtw = inttoptr i64 %addrint_sxtw to i16*
- %val16_sxtw = load volatile i16* %addr_sxtw
- %val64_signed = sext i16 %val16_sxtw to i64
- store volatile i64 %val64_signed, i64* @var_64bit
-; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
-
-
- %base_uxtwN = ptrtoint i16* %base to i64
- %offset_uxtwN = and i64 %offset, 4294967295
- %offset2_uxtwN = shl i64 %offset_uxtwN, 1
- %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
- %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16*
- %val32 = load volatile i32* @var_32bit
- %val16_trunc32 = trunc i32 %val32 to i16
- store volatile i16 %val16_trunc32, i16* %addr_uxtwN
-; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1]
- ret void
-}
-
-define void @ldst_32bit(i32* %base, i64 %offset) minsize {
-; CHECK-LABEL: ldst_32bit:
-
- %addrint_uxtw = ptrtoint i32* %base to i64
- %offset_uxtw = and i64 %offset, 4294967295
- %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
- %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32*
- %val32_uxtw = load volatile i32* %addr_uxtw
- %newval32 = add i32 %val32_uxtw, 1
- store volatile i32 %newval32, i32* @var_32bit
-; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
-
- %base_sxtw = ptrtoint i32* %base to i64
- %offset_sxtw.tmp = shl i64 %offset, 32
- %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
- %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
- %addr_sxtw = inttoptr i64 %addrint_sxtw to i32*
- %val32_sxtw = load volatile i32* %addr_sxtw
- %val64_signed = sext i32 %val32_sxtw to i64
- store volatile i64 %val64_signed, i64* @var_64bit
-; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
-
-
- %base_uxtwN = ptrtoint i32* %base to i64
- %offset_uxtwN = and i64 %offset, 4294967295
- %offset2_uxtwN = shl i64 %offset_uxtwN, 2
- %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
- %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32*
- %val32 = load volatile i32* @var_32bit
- store volatile i32 %val32, i32* %addr_uxtwN
-; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2]
- ret void
-}
-
-define void @ldst_64bit(i64* %base, i64 %offset) minsize {
-; CHECK-LABEL: ldst_64bit:
-
- %addrint_uxtw = ptrtoint i64* %base to i64
- %offset_uxtw = and i64 %offset, 4294967295
- %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw
- %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64*
- %val64_uxtw = load volatile i64* %addr_uxtw
- %newval8 = add i64 %val64_uxtw, 1
- store volatile i64 %newval8, i64* @var_64bit
-; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw]
-
- %base_sxtw = ptrtoint i64* %base to i64
- %offset_sxtw.tmp = shl i64 %offset, 32
- %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32
- %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw
- %addr_sxtw = inttoptr i64 %addrint_sxtw to i64*
- %val64_sxtw = load volatile i64* %addr_sxtw
- store volatile i64 %val64_sxtw, i64* @var_64bit
-; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
-
-
- %base_uxtwN = ptrtoint i64* %base to i64
- %offset_uxtwN = and i64 %offset, 4294967295
- %offset2_uxtwN = shl i64 %offset_uxtwN, 3
- %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN
- %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64*
- %val64 = load volatile i64* @var_64bit
- store volatile i64 %val64, i64* %addr_uxtwN
-; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3]
- ret void
-}
-
- at var_8bit = global i8 0
- at var_16bit = global i16 0
- at var_32bit = global i32 0
- at var_64bit = global i64 0
Removed: llvm/trunk/test/CodeGen/ARM64/register-pairing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/register-pairing.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/register-pairing.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/register-pairing.ll (removed)
@@ -1,53 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s
-;
-; rdar://14075006
-
-define void @odd() nounwind {
-; CHECK-LABEL: odd:
-; CHECK: stp d15, d14, [sp, #-144]!
-; CHECK: stp d13, d12, [sp, #16]
-; CHECK: stp d11, d10, [sp, #32]
-; CHECK: stp d9, d8, [sp, #48]
-; CHECK: stp x28, x27, [sp, #64]
-; CHECK: stp x26, x25, [sp, #80]
-; CHECK: stp x24, x23, [sp, #96]
-; CHECK: stp x22, x21, [sp, #112]
-; CHECK: stp x20, x19, [sp, #128]
-; CHECK: movz x0, #0x2a
-; CHECK: ldp x20, x19, [sp, #128]
-; CHECK: ldp x22, x21, [sp, #112]
-; CHECK: ldp x24, x23, [sp, #96]
-; CHECK: ldp x26, x25, [sp, #80]
-; CHECK: ldp x28, x27, [sp, #64]
-; CHECK: ldp d9, d8, [sp, #48]
-; CHECK: ldp d11, d10, [sp, #32]
-; CHECK: ldp d13, d12, [sp, #16]
-; CHECK: ldp d15, d14, [sp], #144
- call void asm sideeffect "mov x0, #42", "~{x0},~{x19},~{x21},~{x23},~{x25},~{x27},~{d8},~{d10},~{d12},~{d14}"() nounwind
- ret void
-}
-
-define void @even() nounwind {
-; CHECK-LABEL: even:
-; CHECK: stp d15, d14, [sp, #-144]!
-; CHECK: stp d13, d12, [sp, #16]
-; CHECK: stp d11, d10, [sp, #32]
-; CHECK: stp d9, d8, [sp, #48]
-; CHECK: stp x28, x27, [sp, #64]
-; CHECK: stp x26, x25, [sp, #80]
-; CHECK: stp x24, x23, [sp, #96]
-; CHECK: stp x22, x21, [sp, #112]
-; CHECK: stp x20, x19, [sp, #128]
-; CHECK: movz x0, #0x2a
-; CHECK: ldp x20, x19, [sp, #128]
-; CHECK: ldp x22, x21, [sp, #112]
-; CHECK: ldp x24, x23, [sp, #96]
-; CHECK: ldp x26, x25, [sp, #80]
-; CHECK: ldp x28, x27, [sp, #64]
-; CHECK: ldp d9, d8, [sp, #48]
-; CHECK: ldp d11, d10, [sp, #32]
-; CHECK: ldp d13, d12, [sp, #16]
-; CHECK: ldp d15, d14, [sp], #144
- call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d13},~{d15}"() nounwind
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/regress-f128csel-flags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/regress-f128csel-flags.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/regress-f128csel-flags.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/regress-f128csel-flags.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: llc -march=arm64 -verify-machineinstrs < %s | FileCheck %s
-
-; We used to not mark NZCV as being used in the continuation basic-block
-; when lowering a 128-bit "select" to branches. This meant a subsequent use
-; of the same flags gave an internal fault here.
-
-declare void @foo(fp128)
-
-define double @test_f128csel_flags(i32 %lhs, fp128 %a, fp128 %b, double %l, double %r) nounwind {
-; CHECK: test_f128csel_flags
-
- %tst = icmp ne i32 %lhs, 42
- %val = select i1 %tst, fp128 %a, fp128 %b
-; CHECK: cmp w0, #42
-; CHECK: b.eq {{.?LBB0}}
-
- call void @foo(fp128 %val)
- %retval = select i1 %tst, double %l, double %r
-
- ; It's also reasonably important that the actual fcsel comes before the
- ; function call since bl may corrupt NZCV. We were doing the right thing anyway,
- ; but just as well test it while we're here.
-; CHECK: fcsel {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, ne
-; CHECK: bl {{_?foo}}
-
- ret double %retval
-}
Removed: llvm/trunk/test/CodeGen/ARM64/regress-interphase-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/regress-interphase-shift.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/regress-interphase-shift.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/regress-interphase-shift.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc -march=arm64 -o - %s | FileCheck %s
-
-; This is mostly a "don't assert" test. The type of the RHS of a shift depended
-; on the phase of legalization, which led to the creation of an unexpected and
-; unselectable "rotr" node: (i32 (rotr i32, i64)).
-
-; FIXME: This test is xfailed because it relies on an optimization that has
-; been reverted (see PR17975).
-; XFAIL: *
-
-define void @foo(i64* nocapture %d) {
-; CHECK-LABEL: foo:
-; CHECK: rorv
- %tmp = load i64* undef, align 8
- %sub397 = sub i64 0, %tmp
- %and398 = and i64 %sub397, 4294967295
- %shr404 = lshr i64 %and398, 0
- %or405 = or i64 0, %shr404
- %xor406 = xor i64 %or405, 0
- %xor417 = xor i64 0, %xor406
- %xor428 = xor i64 0, %xor417
- %sub430 = sub i64 %xor417, 0
- %and431 = and i64 %sub430, 4294967295
- %and432 = and i64 %xor428, 31
- %sub433 = sub i64 32, %and432
- %shl434 = shl i64 %and431, %sub433
- %shr437 = lshr i64 %and431, %and432
- %or438 = or i64 %shl434, %shr437
- %xor439 = xor i64 %or438, %xor428
- %sub441 = sub i64 %xor439, 0
- store i64 %sub441, i64* %d, align 8
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/return-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/return-vector.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/return-vector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/return-vector.ll (removed)
@@ -1,11 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-; 2x64 vector should be returned in Q0.
-
-define <2 x double> @test(<2 x double>* %p) nounwind {
-; CHECK: test
-; CHECK: ldr q0, [x0]
-; CHECK: ret
- %tmp1 = load <2 x double>* %p, align 16
- ret <2 x double> %tmp1
-}
Removed: llvm/trunk/test/CodeGen/ARM64/returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/returnaddr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/returnaddr.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-define i8* @rt0(i32 %x) nounwind readnone {
-entry:
-; CHECK-LABEL: rt0:
-; CHECK: mov x0, x30
-; CHECK: ret
- %0 = tail call i8* @llvm.returnaddress(i32 0)
- ret i8* %0
-}
-
-define i8* @rt2() nounwind readnone {
-entry:
-; CHECK-LABEL: rt2:
-; CHECK: stp x29, x30, [sp, #-16]!
-; CHECK: mov x29, sp
-; CHECK: ldr x[[REG:[0-9]+]], [x29]
-; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]]]
-; CHECK: ldr x0, [x[[REG2]], #8]
-; CHECK: ldp x29, x30, [sp], #16
-; CHECK: ret
- %0 = tail call i8* @llvm.returnaddress(i32 2)
- ret i8* %0
-}
-
-declare i8* @llvm.returnaddress(i32) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/rev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/rev.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/rev.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/rev.ll (removed)
@@ -1,235 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define i32 @test_rev_w(i32 %a) nounwind {
-entry:
-; CHECK-LABEL: test_rev_w:
-; CHECK: rev w0, w0
- %0 = tail call i32 @llvm.bswap.i32(i32 %a)
- ret i32 %0
-}
-
-define i64 @test_rev_x(i64 %a) nounwind {
-entry:
-; CHECK-LABEL: test_rev_x:
-; CHECK: rev x0, x0
- %0 = tail call i64 @llvm.bswap.i64(i64 %a)
- ret i64 %0
-}
-
-declare i32 @llvm.bswap.i32(i32) nounwind readnone
-declare i64 @llvm.bswap.i64(i64) nounwind readnone
-
-define i32 @test_rev16_w(i32 %X) nounwind {
-entry:
-; CHECK-LABEL: test_rev16_w:
-; CHECK: rev16 w0, w0
- %tmp1 = lshr i32 %X, 8
- %X15 = bitcast i32 %X to i32
- %tmp4 = shl i32 %X15, 8
- %tmp2 = and i32 %tmp1, 16711680
- %tmp5 = and i32 %tmp4, -16777216
- %tmp9 = and i32 %tmp1, 255
- %tmp13 = and i32 %tmp4, 65280
- %tmp6 = or i32 %tmp5, %tmp2
- %tmp10 = or i32 %tmp6, %tmp13
- %tmp14 = or i32 %tmp10, %tmp9
- ret i32 %tmp14
-}
-
-; 64-bit REV16 is *not* a swap then a 16-bit rotation:
-; 01234567 ->(bswap) 76543210 ->(rotr) 10765432
-; 01234567 ->(rev16) 10325476
-define i64 @test_rev16_x(i64 %a) nounwind {
-entry:
-; CHECK-LABEL: test_rev16_x:
-; CHECK-NOT: rev16 x0, x0
- %0 = tail call i64 @llvm.bswap.i64(i64 %a)
- %1 = lshr i64 %0, 16
- %2 = shl i64 %0, 48
- %3 = or i64 %1, %2
- ret i64 %3
-}
-
-define i64 @test_rev32_x(i64 %a) nounwind {
-entry:
-; CHECK-LABEL: test_rev32_x:
-; CHECK: rev32 x0, x0
- %0 = tail call i64 @llvm.bswap.i64(i64 %a)
- %1 = lshr i64 %0, 32
- %2 = shl i64 %0, 32
- %3 = or i64 %1, %2
- ret i64 %3
-}
-
-define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D8:
-;CHECK: rev64.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i8> %tmp2
-}
-
-define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D16:
-;CHECK: rev64.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
- ret <4 x i16> %tmp2
-}
-
-define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D32:
-;CHECK: rev64.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x i32> %tmp2
-}
-
-define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Df:
-;CHECK: rev64.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
- ret <2 x float> %tmp2
-}
-
-define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q8:
-;CHECK: rev64.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
- ret <16 x i8> %tmp2
-}
-
-define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q16:
-;CHECK: rev64.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
- ret <8 x i16> %tmp2
-}
-
-define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Q32:
-;CHECK: rev64.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
- ret <4 x i32> %tmp2
-}
-
-define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK-LABEL: test_vrev64Qf:
-;CHECK: rev64.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
- ret <4 x float> %tmp2
-}
-
-define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev32D8:
-;CHECK: rev32.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
- ret <8 x i8> %tmp2
-}
-
-define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32D16:
-;CHECK: rev32.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
- ret <4 x i16> %tmp2
-}
-
-define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q8:
-;CHECK: rev32.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
- ret <16 x i8> %tmp2
-}
-
-define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q16:
-;CHECK: rev32.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
- ret <8 x i16> %tmp2
-}
-
-define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev16D8:
-;CHECK: rev16.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
- ret <8 x i8> %tmp2
-}
-
-define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev16Q8:
-;CHECK: rev16.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
- ret <16 x i8> %tmp2
-}
-
-; Undef shuffle indices should not prevent matching to VREV:
-
-define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: test_vrev64D8_undef:
-;CHECK: rev64.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
- ret <8 x i8> %tmp2
-}
-
-define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: test_vrev32Q16_undef:
-;CHECK: rev32.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
- ret <8 x i16> %tmp2
-}
-
-; vrev <4 x i16> should use REV32 and not REV64
-define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK-LABEL: test_vrev64:
-; CHECK: ldr [[DEST:q[0-9]+]],
-; CHECK: st1.h
-; CHECK: st1.h
-entry:
- %0 = bitcast <4 x i16>* %source to <8 x i16>*
- %tmp2 = load <8 x i16>* %0, align 4
- %tmp3 = extractelement <8 x i16> %tmp2, i32 6
- %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0
- %tmp9 = extractelement <8 x i16> %tmp2, i32 5
- %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1
- store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
- ret void
-}
-
-; Test vrev of float4
-define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
-; CHECK: float_vrev64
-; CHECK: ldr [[DEST:q[0-9]+]],
-; CHECK: rev64.4s
-entry:
- %0 = bitcast float* %source to <4 x float>*
- %tmp2 = load <4 x float>* %0, align 4
- %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
- %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
- store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
- ret void
-}
-
-
-define <4 x i32> @test_vrev32_bswap(<4 x i32> %source) nounwind {
-; CHECK-LABEL: test_vrev32_bswap:
-; CHECK: rev32.16b
-; CHECK-NOT: rev
-; CHECK: ret
- %bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %source)
- ret <4 x i32> %bswap
-}
-
-declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/rounding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/rounding.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/rounding.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/rounding.ll (removed)
@@ -1,208 +0,0 @@
-; RUN: llc -O3 < %s -mcpu=cyclone | FileCheck %s
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
-target triple = "arm64-apple-ios6.0.0"
-
-; CHECK: test1
-; CHECK: frintx
-; CHECK: frintm
-define float @test1(float %a) #0 {
-entry:
- %call = tail call float @floorf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @floorf(float) nounwind readnone
-
-; CHECK: test2
-; CHECK: frintx
-; CHECK: frintm
-define double @test2(double %a) #0 {
-entry:
- %call = tail call double @floor(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @floor(double) nounwind readnone
-
-; CHECK: test3
-; CHECK: frinti
-define float @test3(float %a) #0 {
-entry:
- %call = tail call float @nearbyintf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @nearbyintf(float) nounwind readnone
-
-; CHECK: test4
-; CHECK: frinti
-define double @test4(double %a) #0 {
-entry:
- %call = tail call double @nearbyint(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @nearbyint(double) nounwind readnone
-
-; CHECK: test5
-; CHECK: frintx
-; CHECK: frintp
-define float @test5(float %a) #0 {
-entry:
- %call = tail call float @ceilf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @ceilf(float) nounwind readnone
-
-; CHECK: test6
-; CHECK: frintx
-; CHECK: frintp
-define double @test6(double %a) #0 {
-entry:
- %call = tail call double @ceil(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @ceil(double) nounwind readnone
-
-; CHECK: test7
-; CHECK: frintx
-define float @test7(float %a) #0 {
-entry:
- %call = tail call float @rintf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @rintf(float) nounwind readnone
-
-; CHECK: test8
-; CHECK: frintx
-define double @test8(double %a) #0 {
-entry:
- %call = tail call double @rint(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @rint(double) nounwind readnone
-
-; CHECK: test9
-; CHECK: frintx
-; CHECK: frintz
-define float @test9(float %a) #0 {
-entry:
- %call = tail call float @truncf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @truncf(float) nounwind readnone
-
-; CHECK: test10
-; CHECK: frintx
-; CHECK: frintz
-define double @test10(double %a) #0 {
-entry:
- %call = tail call double @trunc(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @trunc(double) nounwind readnone
-
-; CHECK: test11
-; CHECK: frintx
-; CHECK: frinta
-define float @test11(float %a) #0 {
-entry:
- %call = tail call float @roundf(float %a) nounwind readnone
- ret float %call
-}
-
-declare float @roundf(float %a) nounwind readnone
-
-; CHECK: test12
-; CHECK: frintx
-; CHECK: frinta
-define double @test12(double %a) #0 {
-entry:
- %call = tail call double @round(double %a) nounwind readnone
- ret double %call
-}
-
-declare double @round(double %a) nounwind readnone
-
-; CHECK: test13
-; CHECK-NOT: frintx
-; CHECK: frintm
-define float @test13(float %a) #1 {
-entry:
- %call = tail call float @floorf(float %a) nounwind readnone
- ret float %call
-}
-
-; CHECK: test14
-; CHECK-NOT: frintx
-; CHECK: frintm
-define double @test14(double %a) #1 {
-entry:
- %call = tail call double @floor(double %a) nounwind readnone
- ret double %call
-}
-
-; CHECK: test15
-; CHECK-NOT: frintx
-; CHECK: frintp
-define float @test15(float %a) #1 {
-entry:
- %call = tail call float @ceilf(float %a) nounwind readnone
- ret float %call
-}
-
-; CHECK: test16
-; CHECK-NOT: frintx
-; CHECK: frintp
-define double @test16(double %a) #1 {
-entry:
- %call = tail call double @ceil(double %a) nounwind readnone
- ret double %call
-}
-
-; CHECK: test17
-; CHECK-NOT: frintx
-; CHECK: frintz
-define float @test17(float %a) #1 {
-entry:
- %call = tail call float @truncf(float %a) nounwind readnone
- ret float %call
-}
-
-; CHECK: test18
-; CHECK-NOT: frintx
-; CHECK: frintz
-define double @test18(double %a) #1 {
-entry:
- %call = tail call double @trunc(double %a) nounwind readnone
- ret double %call
-}
-
-; CHECK: test19
-; CHECK-NOT: frintx
-; CHECK: frinta
-define float @test19(float %a) #1 {
-entry:
- %call = tail call float @roundf(float %a) nounwind readnone
- ret float %call
-}
-
-; CHECK: test20
-; CHECK-NOT: frintx
-; CHECK: frinta
-define double @test20(double %a) #1 {
-entry:
- %call = tail call double @round(double %a) nounwind readnone
- ret double %call
-}
-
-
-
-attributes #0 = { nounwind }
-attributes #1 = { nounwind "unsafe-fp-math"="true" }
Removed: llvm/trunk/test/CodeGen/ARM64/scaled_iv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/scaled_iv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/scaled_iv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/scaled_iv.ll (removed)
@@ -1,38 +0,0 @@
-; RUN: opt -S -loop-reduce < %s | FileCheck %s
-; Scaling factor in addressing mode are costly.
-; Make loop-reduce prefer unscaled accesses.
-; <rdar://problem/13806271>
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-target triple = "arm64-apple-ios7.0.0"
-
-; Function Attrs: nounwind ssp
-define void @mulDouble(double* nocapture %a, double* nocapture %b, double* nocapture %c) {
-; CHECK: @mulDouble
-entry:
- br label %for.body
-
-for.body: ; preds = %for.body, %entry
-; CHECK: [[IV:%[^ ]+]] = phi i64 [ [[IVNEXT:%[^,]+]], %for.body ], [ 0, %entry ]
-; Only one induction variable should have been generated.
-; CHECK-NOT: phi
- %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ]
- %tmp = add nsw i64 %indvars.iv, -1
- %arrayidx = getelementptr inbounds double* %b, i64 %tmp
- %tmp1 = load double* %arrayidx, align 8
-; The induction variable should carry the scaling factor: 1 * 8 = 8.
-; CHECK: [[IVNEXT]] = add nuw nsw i64 [[IV]], 8
- %indvars.iv.next = add i64 %indvars.iv, 1
- %arrayidx2 = getelementptr inbounds double* %c, i64 %indvars.iv.next
- %tmp2 = load double* %arrayidx2, align 8
- %mul = fmul double %tmp1, %tmp2
- %arrayidx4 = getelementptr inbounds double* %a, i64 %indvars.iv
- store double %mul, double* %arrayidx4, align 8
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
-; Comparison should be 19 * 8 = 152.
-; CHECK: icmp eq i32 {{%[^,]+}}, 152
- %exitcond = icmp eq i32 %lftr.wideiv, 20
- br i1 %exitcond, label %for.end, label %for.body
-
-for.end: ; preds = %for.body
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/scvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/scvt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/scvt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/scvt.ll (removed)
@@ -1,830 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-; rdar://13082402
-
-define float @t1(i32* nocapture %src) nounwind ssp {
-entry:
-; CHECK-LABEL: t1:
-; CHECK: ldr s0, [x0]
-; CHECK: scvtf s0, s0
- %tmp1 = load i32* %src, align 4
- %tmp2 = sitofp i32 %tmp1 to float
- ret float %tmp2
-}
-
-define float @t2(i32* nocapture %src) nounwind ssp {
-entry:
-; CHECK-LABEL: t2:
-; CHECK: ldr s0, [x0]
-; CHECK: ucvtf s0, s0
- %tmp1 = load i32* %src, align 4
- %tmp2 = uitofp i32 %tmp1 to float
- ret float %tmp2
-}
-
-define double @t3(i64* nocapture %src) nounwind ssp {
-entry:
-; CHECK-LABEL: t3:
-; CHECK: ldr d0, [x0]
-; CHECK: scvtf d0, d0
- %tmp1 = load i64* %src, align 4
- %tmp2 = sitofp i64 %tmp1 to double
- ret double %tmp2
-}
-
-define double @t4(i64* nocapture %src) nounwind ssp {
-entry:
-; CHECK-LABEL: t4:
-; CHECK: ldr d0, [x0]
-; CHECK: ucvtf d0, d0
- %tmp1 = load i64* %src, align 4
- %tmp2 = uitofp i64 %tmp1 to double
- ret double %tmp2
-}
-
-; rdar://13136456
-define double @t5(i32* nocapture %src) nounwind ssp optsize {
-entry:
-; CHECK-LABEL: t5:
-; CHECK: ldr [[REG:w[0-9]+]], [x0]
-; CHECK: scvtf d0, [[REG]]
- %tmp1 = load i32* %src, align 4
- %tmp2 = sitofp i32 %tmp1 to double
- ret double %tmp2
-}
-
-; Check that we load in FP register when we want to convert into
-; floating point value.
-; This is much faster than loading on GPR and making the conversion
-; GPR -> FPR.
-; <rdar://problem/14599607>
-;
-; Check the flollowing patterns for signed/unsigned:
-; 1. load with scaled imm to float.
-; 2. load with scaled register to float.
-; 3. load with scaled imm to double.
-; 4. load with scaled register to double.
-; 5. load with unscaled imm to float.
-; 6. load with unscaled imm to double.
-; With loading size: 8, 16, 32, and 64-bits.
-
-; ********* 1. load with scaled imm to float. *********
-define float @fct1(i8* nocapture %sp0) {
-; CHECK-LABEL: fct1:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct2(i16* nocapture %sp0) {
-; CHECK-LABEL: fct2:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct3(i32* nocapture %sp0) {
-; CHECK-LABEL: fct3:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @fct4(i64* nocapture %sp0) {
-; CHECK-LABEL: fct4:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; ********* 2. load with scaled register to float. *********
-define float @fct5(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct5:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct6(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct6:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct7(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct7:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @fct8(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct8:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-
-; ********* 3. load with scaled imm to double. *********
-define double @fct9(i8* nocapture %sp0) {
-; CHECK-LABEL: fct9:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct10(i16* nocapture %sp0) {
-; CHECK-LABEL: fct10:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct11(i32* nocapture %sp0) {
-; CHECK-LABEL: fct11:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct12(i64* nocapture %sp0) {
-; CHECK-LABEL: fct12:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-; ********* 4. load with scaled register to double. *********
-define double @fct13(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct13:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct14(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct14:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct15(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct15:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct16(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: fct16:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-; ********* 5. load with unscaled imm to float. *********
-define float @fct17(i8* nocapture %sp0) {
-entry:
-; CHECK-LABEL: fct17:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i8* %sp0 to i64
- %add = add i64 %bitcast, -1
- %addr = inttoptr i64 %add to i8*
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct18(i16* nocapture %sp0) {
-; CHECK-LABEL: fct18:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i16* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i16*
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @fct19(i32* nocapture %sp0) {
-; CHECK-LABEL: fct19:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i32* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i32*
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @fct20(i64* nocapture %sp0) {
-; CHECK-LABEL: fct20:
-; CHECK: ldur x[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i64* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i64*
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-
-}
-
-; ********* 6. load with unscaled imm to double. *********
-define double @fct21(i8* nocapture %sp0) {
-entry:
-; CHECK-LABEL: fct21:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i8* %sp0 to i64
- %add = add i64 %bitcast, -1
- %addr = inttoptr i64 %add to i8*
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = uitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct22(i16* nocapture %sp0) {
-; CHECK-LABEL: fct22:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i16* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i16*
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = uitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct23(i32* nocapture %sp0) {
-; CHECK-LABEL: fct23:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i32* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i32*
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = uitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @fct24(i64* nocapture %sp0) {
-; CHECK-LABEL: fct24:
-; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i64* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i64*
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = uitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-
-}
-
-; ********* 1s. load with scaled imm to float. *********
-define float @sfct1(i8* nocapture %sp0) {
-; CHECK-LABEL: sfct1:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct2(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct2:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct3(i32* nocapture %sp0) {
-; CHECK-LABEL: sfct3:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @sfct4(i64* nocapture %sp0) {
-; CHECK-LABEL: sfct4:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; ********* 2s. load with scaled register to float. *********
-define float @sfct5(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct5:
-; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct6(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct6:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct7(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct7:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @sfct8(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct8:
-; CHECK: ldr x[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; ********* 3s. load with scaled imm to double. *********
-define double @sfct9(i8* nocapture %sp0) {
-; CHECK-LABEL: sfct9:
-; CHECK: ldrsb w[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 1
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct10(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct10:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 1
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct11(i32* nocapture %sp0) {
-; CHECK-LABEL: sfct11:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct12(i64* nocapture %sp0) {
-; CHECK-LABEL: sfct12:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 1
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-; ********* 4s. load with scaled register to double. *********
-define double @sfct13(i8* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct13:
-; CHECK: ldrsb w[[REGNUM:[0-9]+]], [x0, x1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i8* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct14(i16* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct14:
-; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i16* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct15(i32* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct15:
-; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct16(i64* nocapture %sp0, i64 %offset) {
-; CHECK-LABEL: sfct16:
-; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, x1, lsl #3]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i64* %sp0, i64 %offset
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-; ********* 5s. load with unscaled imm to float. *********
-define float @sfct17(i8* nocapture %sp0) {
-entry:
-; CHECK-LABEL: sfct17:
-; CHECK: ldur b[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: sshll.8h [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i8* %sp0 to i64
- %add = add i64 %bitcast, -1
- %addr = inttoptr i64 %add to i8*
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct18(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct18:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i16* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i16*
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define float @sfct19(i32* nocapture %sp0) {
-; CHECK-LABEL: sfct19:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i32* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i32*
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-; i64 -> f32 is not supported on floating point unit.
-define float @sfct20(i64* nocapture %sp0) {
-; CHECK-LABEL: sfct20:
-; CHECK: ldur x[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i64* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i64*
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-
-}
-
-; ********* 6s. load with unscaled imm to double. *********
-define double @sfct21(i8* nocapture %sp0) {
-entry:
-; CHECK-LABEL: sfct21:
-; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i8* %sp0 to i64
- %add = add i64 %bitcast, -1
- %addr = inttoptr i64 %add to i8*
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct22(i16* nocapture %sp0) {
-; CHECK-LABEL: sfct22:
-; CHECK: ldur h[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.4s [[SEXTREG1:v[0-9]+]], v[[REGNUM]], #0
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], [[SEXTREG1]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i16* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i16*
- %pix_sp0.0.copyload = load i16* %addr, align 1
- %val = sitofp i16 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct23(i32* nocapture %sp0) {
-; CHECK-LABEL: sfct23:
-; CHECK: ldur s[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: sshll.2d v[[SEXTREG:[0-9]+]], v[[REGNUM]], #0
-; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i32* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i32*
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-define double @sfct24(i64* nocapture %sp0) {
-; CHECK-LABEL: sfct24:
-; CHECK: ldur d[[REGNUM:[0-9]+]], [x0, #1]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
- %bitcast = ptrtoint i64* %sp0 to i64
- %add = add i64 %bitcast, 1
- %addr = inttoptr i64 %add to i64*
- %pix_sp0.0.copyload = load i64* %addr, align 1
- %val = sitofp i64 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-
-}
-
-; Check that we do not use SSHLL code sequence when code size is a concern.
-define float @codesize_sfct17(i8* nocapture %sp0) optsize {
-entry:
-; CHECK-LABEL: codesize_sfct17:
-; CHECK: ldursb w[[REGNUM:[0-9]+]], [x0, #-1]
-; CHECK-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul s0, [[REG]], [[REG]]
- %bitcast = ptrtoint i8* %sp0 to i64
- %add = add i64 %bitcast, -1
- %addr = inttoptr i64 %add to i8*
- %pix_sp0.0.copyload = load i8* %addr, align 1
- %val = sitofp i8 %pix_sp0.0.copyload to float
- %vmull.i = fmul float %val, %val
- ret float %vmull.i
-}
-
-define double @codesize_sfct11(i32* nocapture %sp0) minsize {
-; CHECK-LABEL: sfct11:
-; CHECK: ldr w[[REGNUM:[0-9]+]], [x0, #4]
-; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]]
-; CHECK-NEXT: fmul d0, [[REG]], [[REG]]
-entry:
- %addr = getelementptr i32* %sp0, i64 1
- %pix_sp0.0.copyload = load i32* %addr, align 1
- %val = sitofp i32 %pix_sp0.0.copyload to double
- %vmull.i = fmul double %val, %val
- ret double %vmull.i
-}
-
-; Adding fp128 custom lowering makes these a little fragile since we have to
-; return the correct mix of Legal/Expand from the custom method.
-;
-; rdar://problem/14991489
-
-define float @float_from_i128(i128 %in) {
-; CHECK-LABEL: float_from_i128:
-; CHECK: bl {{_?__floatuntisf}}
- %conv = uitofp i128 %in to float
- ret float %conv
-}
-
-define double @double_from_i128(i128 %in) {
-; CHECK-LABEL: double_from_i128:
-; CHECK: bl {{_?__floattidf}}
- %conv = sitofp i128 %in to double
- ret double %conv
-}
-
-define fp128 @fp128_from_i128(i128 %in) {
-; CHECK-LABEL: fp128_from_i128:
-; CHECK: bl {{_?__floatuntitf}}
- %conv = uitofp i128 %in to fp128
- ret fp128 %conv
-}
-
-define i128 @i128_from_float(float %in) {
-; CHECK-LABEL: i128_from_float
-; CHECK: bl {{_?__fixsfti}}
- %conv = fptosi float %in to i128
- ret i128 %conv
-}
-
-define i128 @i128_from_double(double %in) {
-; CHECK-LABEL: i128_from_double
-; CHECK: bl {{_?__fixunsdfti}}
- %conv = fptoui double %in to i128
- ret i128 %conv
-}
-
-define i128 @i128_from_fp128(fp128 %in) {
-; CHECK-LABEL: i128_from_fp128
-; CHECK: bl {{_?__fixtfti}}
- %conv = fptosi fp128 %in to i128
- ret i128 %conv
-}
-
Removed: llvm/trunk/test/CodeGen/ARM64/shifted-sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/shifted-sext.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/shifted-sext.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/shifted-sext.ll (removed)
@@ -1,277 +0,0 @@
-; RUN: llc -march=arm64 -mtriple=arm64-apple-ios < %s | FileCheck %s
-;
-; <rdar://problem/13820218>
-
-define signext i16 @extendedLeftShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharToshortBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #8
- %inc = add i8 %a, 1
- %conv1 = sext i8 %inc to i32
- %shl = shl nsw i32 %conv1, 4
- %conv2 = trunc i32 %shl to i16
- ret i16 %conv2
-}
-
-define signext i16 @extendedRightShiftcharToshortBy4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharToshortBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #4
- %inc = add i8 %a, 1
- %conv1 = sext i8 %inc to i32
- %shr4 = lshr i32 %conv1, 4
- %conv2 = trunc i32 %shr4 to i16
- ret i16 %conv2
-}
-
-define signext i16 @extendedLeftShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharToshortBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #8, #8
- %inc = add i8 %a, 1
- %conv1 = sext i8 %inc to i32
- %shl = shl nsw i32 %conv1, 8
- %conv2 = trunc i32 %shl to i16
- ret i16 %conv2
-}
-
-define signext i16 @extendedRightShiftcharToshortBy8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharToshortBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxtb [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #8
- %inc = add i8 %a, 1
- %conv1 = sext i8 %inc to i32
- %shr4 = lshr i32 %conv1, 8
- %conv2 = trunc i32 %shr4 to i16
- ret i16 %conv2
-}
-
-define i32 @extendedLeftShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i32
- %shl = shl nsw i32 %conv, 4
- ret i32 %shl
-}
-
-define i32 @extendedRightShiftcharTointBy4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #4
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i32
- %shr = ashr i32 %conv, 4
- ret i32 %shr
-}
-
-define i32 @extendedLeftShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharTointBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #8, #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i32
- %shl = shl nsw i32 %conv, 8
- ret i32 %shl
-}
-
-define i32 @extendedRightShiftcharTointBy8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharTointBy8:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxtb [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i32
- %shr = ashr i32 %conv, 8
- ret i32 %shr
-}
-
-define i64 @extendedLeftShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i64
- %shl = shl nsw i64 %conv, 4
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftcharToint64By4(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #4
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i64
- %shr = ashr i64 %conv, 4
- ret i64 %shr
-}
-
-define i64 @extendedLeftShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftcharToint64By8:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #8, #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i64
- %shl = shl nsw i64 %conv, 8
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftcharToint64By8(i8 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftcharToint64By8:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtb x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #8
- %inc = add i8 %a, 1
- %conv = sext i8 %inc to i64
- %shr = ashr i64 %conv, 8
- ret i64 %shr
-}
-
-define i32 @extendedLeftShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftshortTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfiz w0, [[REG]], #4, #16
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i32
- %shl = shl nsw i32 %conv, 4
- ret i32 %shl
-}
-
-define i32 @extendedRightShiftshortTointBy4(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftshortTointBy4:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sbfx w0, [[REG]], #4, #12
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i32
- %shr = ashr i32 %conv, 4
- ret i32 %shr
-}
-
-define i32 @extendedLeftShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftshortTointBy16:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: lsl w0, [[REG]], #16
- %inc = add i16 %a, 1
- %conv2 = zext i16 %inc to i32
- %shl = shl nuw i32 %conv2, 16
- ret i32 %shl
-}
-
-define i32 @extendedRightShiftshortTointBy16(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftshortTointBy16:
-; CHECK: add [[REG:w[0-9]+]], w0, #1
-; CHECK: sxth [[REG]], [[REG]]
-; CHECK: asr w0, [[REG]], #16
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i32
- %shr = ashr i32 %conv, 16
- ret i32 %shr
-}
-
-define i64 @extendedLeftShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftshortToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #16
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i64
- %shl = shl nsw i64 %conv, 4
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftshortToint64By4(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftshortToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #12
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i64
- %shr = ashr i64 %conv, 4
- ret i64 %shr
-}
-
-define i64 @extendedLeftShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftshortToint64By16:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #16, #16
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i64
- %shl = shl nsw i64 %conv, 16
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftshortToint64By16(i16 signext %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftshortToint64By16:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxth x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #16
- %inc = add i16 %a, 1
- %conv = sext i16 %inc to i64
- %shr = ashr i64 %conv, 16
- ret i64 %shr
-}
-
-define i64 @extendedLeftShiftintToint64By4(i32 %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftintToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfiz x0, x[[REG]], #4, #32
- %inc = add nsw i32 %a, 1
- %conv = sext i32 %inc to i64
- %shl = shl nsw i64 %conv, 4
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftintToint64By4(i32 %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftintToint64By4:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sbfx x0, x[[REG]], #4, #28
- %inc = add nsw i32 %a, 1
- %conv = sext i32 %inc to i64
- %shr = ashr i64 %conv, 4
- ret i64 %shr
-}
-
-define i64 @extendedLeftShiftintToint64By32(i32 %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedLeftShiftintToint64By32:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: lsl x0, x[[REG]], #32
- %inc = add nsw i32 %a, 1
- %conv2 = zext i32 %inc to i64
- %shl = shl nuw i64 %conv2, 32
- ret i64 %shl
-}
-
-define i64 @extendedRightShiftintToint64By32(i32 %a) nounwind readnone ssp {
-entry:
-; CHECK-LABEL: extendedRightShiftintToint64By32:
-; CHECK: add w[[REG:[0-9]+]], w0, #1
-; CHECK: sxtw x[[REG]], w[[REG]]
-; CHECK: asr x0, x[[REG]], #32
- %inc = add nsw i32 %a, 1
- %conv = sext i32 %inc to i64
- %shr = ashr i64 %conv, 32
- ret i64 %shr
-}
Removed: llvm/trunk/test/CodeGen/ARM64/simd-scalar-to-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/simd-scalar-to-vector.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/simd-scalar-to-vector.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/simd-scalar-to-vector.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -O0 -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST
-
-define <16 x i8> @foo(<16 x i8> %a) nounwind optsize readnone ssp {
-; CHECK: uaddlv.16b h0, v0
-; CHECK: rshrn.8b v0, v0, #4
-; CHECK: dup.16b v0, v0[0]
-; CHECK: ret
-
-; CHECK-FAST: uaddlv.16b
-; CHECK-FAST: rshrn.8b
-; CHECK-FAST: dup.16b
- %tmp = tail call i32 @llvm.arm64.neon.uaddlv.i32.v16i8(<16 x i8> %a) nounwind
- %tmp1 = trunc i32 %tmp to i16
- %tmp2 = insertelement <8 x i16> undef, i16 %tmp1, i32 0
- %tmp3 = tail call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %tmp2, i32 4)
- %tmp4 = shufflevector <8 x i8> %tmp3, <8 x i8> undef, <16 x i32> zeroinitializer
- ret <16 x i8> %tmp4
-}
-
-declare <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
-declare i32 @llvm.arm64.neon.uaddlv.i32.v16i8(<16 x i8>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/simplest-elf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/simplest-elf.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/simplest-elf.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/simplest-elf.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -mtriple=arm64-linux-gnu < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump - -r -d --triple=arm64-linux-gnu | FileCheck --check-prefix=CHECK-ELF %s
-
-define void @foo() nounwind {
- ret void
-}
-
- ; Check source looks ELF-like: no leading underscore, comments with //
-; CHECK: foo: // @foo
-; CHECK: ret
-
- ; Similarly make sure ELF output works and is vaguely sane: aarch64 target
- ; machine with correct section & symbol names.
-; CHECK-ELF: file format ELF64-aarch64
-
-; CHECK-ELF: Disassembly of section .text
-; CHECK-ELF-LABEL: foo:
-; CHECK-ELF: ret
Removed: llvm/trunk/test/CodeGen/ARM64/sincos.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/sincos.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/sincos.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/sincos.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7 | FileCheck %s --check-prefix CHECK-IOS
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix CHECK-LINUX
-
-; Combine sin / cos into a single call.
-; rdar://12856873
-
-define float @test1(float %x) nounwind {
-entry:
-; CHECK-IOS-LABEL: test1:
-; CHECK-IOS: bl ___sincosf_stret
-; CHECK-IOS: fadd s0, s0, s1
-
-; CHECK-LINUX-LABEL: test1:
-; CHECK-LINUX: bl sinf
-; CHECK-LINUX: bl cosf
-
- %call = tail call float @sinf(float %x) nounwind readnone
- %call1 = tail call float @cosf(float %x) nounwind readnone
- %add = fadd float %call, %call1
- ret float %add
-}
-
-define double @test2(double %x) nounwind {
-entry:
-; CHECK-IOS-LABEL: test2:
-; CHECK-IOS: bl ___sincos_stret
-; CHECK-IOS: fadd d0, d0, d1
-
-; CHECK-LINUX-LABEL: test2:
-; CHECK-LINUX: bl sin
-; CHECK-LINUX: bl cos
-
- %call = tail call double @sin(double %x) nounwind readnone
- %call1 = tail call double @cos(double %x) nounwind readnone
- %add = fadd double %call, %call1
- ret double %add
-}
-
-declare float @sinf(float) readonly
-declare double @sin(double) readonly
-declare float @cosf(float) readonly
-declare double @cos(double) readonly
Removed: llvm/trunk/test/CodeGen/ARM64/sitofp-combine-chains.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/sitofp-combine-chains.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/sitofp-combine-chains.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/sitofp-combine-chains.ll (removed)
@@ -1,22 +0,0 @@
-; RUN: llc -march=arm64 -o - %s | FileCheck %s
-
-; ARM64ISelLowering.cpp was creating a new (floating-point) load for efficiency
-; but not updating chain-successors of the old one. As a result, the two memory
-; operations in this function both ended up direct successors to the EntryToken
-; and could be reordered.
-
- at var = global i32 0, align 4
-
-define float @foo() {
-; CHECK-LABEL: foo:
- ; Load must come before we clobber @var
-; CHECK: adrp x[[VARBASE:[0-9]+]], {{_?var}}
-; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]],
-; CHECK: str wzr, [x[[VARBASE]],
-
- %val = load i32* @var, align 4
- store i32 0, i32* @var, align 4
-
- %fltval = sitofp i32 %val to float
- ret float %fltval
-}
Removed: llvm/trunk/test/CodeGen/ARM64/sli-sri-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/sli-sri-opt.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/sli-sri-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/sli-sri-opt.ll (removed)
@@ -1,41 +0,0 @@
-; RUN: llc -arm64-shift-insert-generation=true -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
-; CHECK-LABEL: testLeftGood:
-; CHECK: sli.16b v0, v1, #3
- %and.i = and <16 x i8> %src1, <i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252>
- %vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
- %result = or <16 x i8> %and.i, %vshl_n
- store <16 x i8> %result, <16 x i8>* %dest, align 16
- ret void
-}
-
-define void @testLeftBad(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
-; CHECK-LABEL: testLeftBad:
-; CHECK-NOT: sli
- %and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
- %vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %result = or <16 x i8> %and.i, %vshl_n
- store <16 x i8> %result, <16 x i8>* %dest, align 16
- ret void
-}
-
-define void @testRightGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
-; CHECK-LABEL: testRightGood:
-; CHECK: sri.16b v0, v1, #3
- %and.i = and <16 x i8> %src1, <i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252>
- %vshl_n = lshr <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
- %result = or <16 x i8> %and.i, %vshl_n
- store <16 x i8> %result, <16 x i8>* %dest, align 16
- ret void
-}
-
-define void @testRightBad(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
-; CHECK-LABEL: testRightBad:
-; CHECK-NOT: sri
- %and.i = and <16 x i8> %src1, <i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165, i8 165>
- %vshl_n = lshr <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
- %result = or <16 x i8> %and.i, %vshl_n
- store <16 x i8> %result, <16 x i8>* %dest, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/smaxv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/smaxv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/smaxv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/smaxv.ll (removed)
@@ -1,74 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define signext i8 @test_vmaxv_s8(<8 x i8> %a1) {
-; CHECK: test_vmaxv_s8
-; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v8i8(<8 x i8> %a1)
- %0 = trunc i32 %vmaxv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vmaxv_s16(<4 x i16> %a1) {
-; CHECK: test_vmaxv_s16
-; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v4i16(<4 x i16> %a1)
- %0 = trunc i32 %vmaxv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vmaxv_s32(<2 x i32> %a1) {
-; CHECK: test_vmaxv_s32
-; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v2i32(<2 x i32> %a1)
- ret i32 %vmaxv.i
-}
-
-define signext i8 @test_vmaxvq_s8(<16 x i8> %a1) {
-; CHECK: test_vmaxvq_s8
-; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v16i8(<16 x i8> %a1)
- %0 = trunc i32 %vmaxv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vmaxvq_s16(<8 x i16> %a1) {
-; CHECK: test_vmaxvq_s16
-; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v8i16(<8 x i16> %a1)
- %0 = trunc i32 %vmaxv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vmaxvq_s32(<4 x i32> %a1) {
-; CHECK: test_vmaxvq_s32
-; CHECK: smaxv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.smaxv.i32.v4i32(<4 x i32> %a1)
- ret i32 %vmaxv.i
-}
-
-declare i32 @llvm.arm64.neon.smaxv.i32.v4i32(<4 x i32>)
-declare i32 @llvm.arm64.neon.smaxv.i32.v8i16(<8 x i16>)
-declare i32 @llvm.arm64.neon.smaxv.i32.v16i8(<16 x i8>)
-declare i32 @llvm.arm64.neon.smaxv.i32.v2i32(<2 x i32>)
-declare i32 @llvm.arm64.neon.smaxv.i32.v4i16(<4 x i16>)
-declare i32 @llvm.arm64.neon.smaxv.i32.v8i8(<8 x i8>)
-
Removed: llvm/trunk/test/CodeGen/ARM64/sminv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/sminv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/sminv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/sminv.ll (removed)
@@ -1,74 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define signext i8 @test_vminv_s8(<8 x i8> %a1) {
-; CHECK: test_vminv_s8
-; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v8i8(<8 x i8> %a1)
- %0 = trunc i32 %vminv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vminv_s16(<4 x i16> %a1) {
-; CHECK: test_vminv_s16
-; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v4i16(<4 x i16> %a1)
- %0 = trunc i32 %vminv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vminv_s32(<2 x i32> %a1) {
-; CHECK: test_vminv_s32
-; 2 x i32 is not supported by the ISA, thus, this is a special case
-; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v0, v0
-; CHECK-NEXT: fmov w0, s[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v2i32(<2 x i32> %a1)
- ret i32 %vminv.i
-}
-
-define signext i8 @test_vminvq_s8(<16 x i8> %a1) {
-; CHECK: test_vminvq_s8
-; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v16i8(<16 x i8> %a1)
- %0 = trunc i32 %vminv.i to i8
- ret i8 %0
-}
-
-define signext i16 @test_vminvq_s16(<8 x i16> %a1) {
-; CHECK: test_vminvq_s16
-; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v0
-; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v8i16(<8 x i16> %a1)
- %0 = trunc i32 %vminv.i to i16
- ret i16 %0
-}
-
-define i32 @test_vminvq_s32(<4 x i32> %a1) {
-; CHECK: test_vminvq_s32
-; CHECK: sminv.4s [[REGNUM:s[0-9]+]], v0
-; CHECK-NEXT: fmov w0, [[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.sminv.i32.v4i32(<4 x i32> %a1)
- ret i32 %vminv.i
-}
-
-declare i32 @llvm.arm64.neon.sminv.i32.v4i32(<4 x i32>)
-declare i32 @llvm.arm64.neon.sminv.i32.v8i16(<8 x i16>)
-declare i32 @llvm.arm64.neon.sminv.i32.v16i8(<16 x i8>)
-declare i32 @llvm.arm64.neon.sminv.i32.v2i32(<2 x i32>)
-declare i32 @llvm.arm64.neon.sminv.i32.v4i16(<4 x i16>)
-declare i32 @llvm.arm64.neon.sminv.i32.v8i8(<8 x i8>)
-
Removed: llvm/trunk/test/CodeGen/ARM64/spill-lr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/spill-lr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/spill-lr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/spill-lr.ll (removed)
@@ -1,74 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios < %s
- at bar = common global i32 0, align 4
-
-; Leaf function which uses all callee-saved registers and allocates >= 256 bytes on the stack
-; this will cause processFunctionBeforeCalleeSavedScan() to spill LR as an additional scratch
-; register.
-;
-; This is a crash-only regression test for rdar://15124582.
-define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) nounwind {
-entry:
- %stack = alloca [128 x i32], align 4
- %0 = bitcast [128 x i32]* %stack to i8*
- %idxprom = sext i32 %a to i64
- %arrayidx = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom
- store i32 %b, i32* %arrayidx, align 4
- %1 = load volatile i32* @bar, align 4
- %2 = load volatile i32* @bar, align 4
- %3 = load volatile i32* @bar, align 4
- %4 = load volatile i32* @bar, align 4
- %5 = load volatile i32* @bar, align 4
- %6 = load volatile i32* @bar, align 4
- %7 = load volatile i32* @bar, align 4
- %8 = load volatile i32* @bar, align 4
- %9 = load volatile i32* @bar, align 4
- %10 = load volatile i32* @bar, align 4
- %11 = load volatile i32* @bar, align 4
- %12 = load volatile i32* @bar, align 4
- %13 = load volatile i32* @bar, align 4
- %14 = load volatile i32* @bar, align 4
- %15 = load volatile i32* @bar, align 4
- %16 = load volatile i32* @bar, align 4
- %17 = load volatile i32* @bar, align 4
- %18 = load volatile i32* @bar, align 4
- %19 = load volatile i32* @bar, align 4
- %20 = load volatile i32* @bar, align 4
- %idxprom1 = sext i32 %c to i64
- %arrayidx2 = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom1
- %21 = load i32* %arrayidx2, align 4
- %factor = mul i32 %h, -2
- %factor67 = mul i32 %g, -2
- %factor68 = mul i32 %f, -2
- %factor69 = mul i32 %e, -2
- %factor70 = mul i32 %d, -2
- %factor71 = mul i32 %c, -2
- %factor72 = mul i32 %b, -2
- %sum = add i32 %2, %1
- %sum73 = add i32 %sum, %3
- %sum74 = add i32 %sum73, %4
- %sum75 = add i32 %sum74, %5
- %sum76 = add i32 %sum75, %6
- %sum77 = add i32 %sum76, %7
- %sum78 = add i32 %sum77, %8
- %sum79 = add i32 %sum78, %9
- %sum80 = add i32 %sum79, %10
- %sum81 = add i32 %sum80, %11
- %sum82 = add i32 %sum81, %12
- %sum83 = add i32 %sum82, %13
- %sum84 = add i32 %sum83, %14
- %sum85 = add i32 %sum84, %15
- %sum86 = add i32 %sum85, %16
- %sum87 = add i32 %sum86, %17
- %sum88 = add i32 %sum87, %18
- %sum89 = add i32 %sum88, %19
- %sum90 = add i32 %sum89, %20
- %sub15 = sub i32 %21, %sum90
- %sub16 = add i32 %sub15, %factor
- %sub17 = add i32 %sub16, %factor67
- %sub18 = add i32 %sub17, %factor68
- %sub19 = add i32 %sub18, %factor69
- %sub20 = add i32 %sub19, %factor70
- %sub21 = add i32 %sub20, %factor71
- %add = add i32 %sub21, %factor72
- ret i32 %add
-}
Removed: llvm/trunk/test/CodeGen/ARM64/spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/spill.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/spill.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/spill.ll (removed)
@@ -1,15 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -arm64-neon-syntax=apple -verify-machineinstrs
-
-; CHECK: fpr128
-; CHECK: ld1.2d
-; CHECK: str q
-; CHECK: inlineasm
-; CHECK: ldr q
-; CHECK: st1.2d
-define void @fpr128(<4 x float>* %p) nounwind ssp {
-entry:
- %x = load <4 x float>* %p, align 16
- call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
- store <4 x float> %x, <4 x float>* %p, align 16
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/st1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/st1.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/st1.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/st1.ll (removed)
@@ -1,676 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
-
-define void @st1lane_16b(<16 x i8> %A, i8* %D) {
-; CHECK-LABEL: st1lane_16b
-; CHECK: st1.b
- %tmp = extractelement <16 x i8> %A, i32 1
- store i8 %tmp, i8* %D
- ret void
-}
-
-define void @st1lane_8h(<8 x i16> %A, i16* %D) {
-; CHECK-LABEL: st1lane_8h
-; CHECK: st1.h
- %tmp = extractelement <8 x i16> %A, i32 1
- store i16 %tmp, i16* %D
- ret void
-}
-
-define void @st1lane_4s(<4 x i32> %A, i32* %D) {
-; CHECK-LABEL: st1lane_4s
-; CHECK: st1.s
- %tmp = extractelement <4 x i32> %A, i32 1
- store i32 %tmp, i32* %D
- ret void
-}
-
-define void @st1lane_4s_float(<4 x float> %A, float* %D) {
-; CHECK-LABEL: st1lane_4s_float
-; CHECK: st1.s
- %tmp = extractelement <4 x float> %A, i32 1
- store float %tmp, float* %D
- ret void
-}
-
-define void @st1lane_2d(<2 x i64> %A, i64* %D) {
-; CHECK-LABEL: st1lane_2d
-; CHECK: st1.d
- %tmp = extractelement <2 x i64> %A, i32 1
- store i64 %tmp, i64* %D
- ret void
-}
-
-define void @st1lane_2d_double(<2 x double> %A, double* %D) {
-; CHECK-LABEL: st1lane_2d_double
-; CHECK: st1.d
- %tmp = extractelement <2 x double> %A, i32 1
- store double %tmp, double* %D
- ret void
-}
-
-define void @st1lane_8b(<8 x i8> %A, i8* %D) {
-; CHECK-LABEL: st1lane_8b
-; CHECK: st1.b
- %tmp = extractelement <8 x i8> %A, i32 1
- store i8 %tmp, i8* %D
- ret void
-}
-
-define void @st1lane_4h(<4 x i16> %A, i16* %D) {
-; CHECK-LABEL: st1lane_4h
-; CHECK: st1.h
- %tmp = extractelement <4 x i16> %A, i32 1
- store i16 %tmp, i16* %D
- ret void
-}
-
-define void @st1lane_2s(<2 x i32> %A, i32* %D) {
-; CHECK-LABEL: st1lane_2s
-; CHECK: st1.s
- %tmp = extractelement <2 x i32> %A, i32 1
- store i32 %tmp, i32* %D
- ret void
-}
-
-define void @st1lane_2s_float(<2 x float> %A, float* %D) {
-; CHECK-LABEL: st1lane_2s_float
-; CHECK: st1.s
- %tmp = extractelement <2 x float> %A, i32 1
- store float %tmp, float* %D
- ret void
-}
-
-define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, i8* %D) {
-; CHECK-LABEL: st2lane_16b
-; CHECK: st2.b
- call void @llvm.arm64.neon.st2lane.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i64 1, i8* %D)
- ret void
-}
-
-define void @st2lane_8h(<8 x i16> %A, <8 x i16> %B, i16* %D) {
-; CHECK-LABEL: st2lane_8h
-; CHECK: st2.h
- call void @llvm.arm64.neon.st2lane.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i64 1, i16* %D)
- ret void
-}
-
-define void @st2lane_4s(<4 x i32> %A, <4 x i32> %B, i32* %D) {
-; CHECK-LABEL: st2lane_4s
-; CHECK: st2.s
- call void @llvm.arm64.neon.st2lane.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i64 1, i32* %D)
- ret void
-}
-
-define void @st2lane_2d(<2 x i64> %A, <2 x i64> %B, i64* %D) {
-; CHECK-LABEL: st2lane_2d
-; CHECK: st2.d
- call void @llvm.arm64.neon.st2lane.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64 1, i64* %D)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2lane.v16i8.p0i8(<16 x i8>, <16 x i8>, i64, i8*) nounwind readnone
-declare void @llvm.arm64.neon.st2lane.v8i16.p0i16(<8 x i16>, <8 x i16>, i64, i16*) nounwind readnone
-declare void @llvm.arm64.neon.st2lane.v4i32.p0i32(<4 x i32>, <4 x i32>, i64, i32*) nounwind readnone
-declare void @llvm.arm64.neon.st2lane.v2i64.p0i64(<2 x i64>, <2 x i64>, i64, i64*) nounwind readnone
-
-define void @st3lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %D) {
-; CHECK-LABEL: st3lane_16b
-; CHECK: st3.b
- call void @llvm.arm64.neon.st3lane.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i64 1, i8* %D)
- ret void
-}
-
-define void @st3lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %D) {
-; CHECK-LABEL: st3lane_8h
-; CHECK: st3.h
- call void @llvm.arm64.neon.st3lane.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i64 1, i16* %D)
- ret void
-}
-
-define void @st3lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %D) {
-; CHECK-LABEL: st3lane_4s
-; CHECK: st3.s
- call void @llvm.arm64.neon.st3lane.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i64 1, i32* %D)
- ret void
-}
-
-define void @st3lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %D) {
-; CHECK-LABEL: st3lane_2d
-; CHECK: st3.d
- call void @llvm.arm64.neon.st3lane.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64 1, i64* %D)
- ret void
-}
-
-declare void @llvm.arm64.neon.st3lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readnone
-declare void @llvm.arm64.neon.st3lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readnone
-declare void @llvm.arm64.neon.st3lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readnone
-declare void @llvm.arm64.neon.st3lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readnone
-
-define void @st4lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %E) {
-; CHECK-LABEL: st4lane_16b
-; CHECK: st4.b
- call void @llvm.arm64.neon.st4lane.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 1, i8* %E)
- ret void
-}
-
-define void @st4lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %E) {
-; CHECK-LABEL: st4lane_8h
-; CHECK: st4.h
- call void @llvm.arm64.neon.st4lane.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 1, i16* %E)
- ret void
-}
-
-define void @st4lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %E) {
-; CHECK-LABEL: st4lane_4s
-; CHECK: st4.s
- call void @llvm.arm64.neon.st4lane.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 1, i32* %E)
- ret void
-}
-
-define void @st4lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %E) {
-; CHECK-LABEL: st4lane_2d
-; CHECK: st4.d
- call void @llvm.arm64.neon.st4lane.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 1, i64* %E)
- ret void
-}
-
-declare void @llvm.arm64.neon.st4lane.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i64, i8*) nounwind readnone
-declare void @llvm.arm64.neon.st4lane.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i64, i16*) nounwind readnone
-declare void @llvm.arm64.neon.st4lane.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i64, i32*) nounwind readnone
-declare void @llvm.arm64.neon.st4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64, i64*) nounwind readnone
-
-
-define void @st2_8b(<8 x i8> %A, <8 x i8> %B, i8* %P) nounwind {
-; CHECK-LABEL: st2_8b
-; CHECK st2.8b
- call void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, i8* %P)
- ret void
-}
-
-define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) nounwind {
-; CHECK-LABEL: st3_8b
-; CHECK st3.8b
- call void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P)
- ret void
-}
-
-define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P) nounwind {
-; CHECK-LABEL: st4_8b
-; CHECK st4.8b
- call void @llvm.arm64.neon.st4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind readonly
-
-define void @st2_16b(<16 x i8> %A, <16 x i8> %B, i8* %P) nounwind {
-; CHECK-LABEL: st2_16b
-; CHECK st2.16b
- call void @llvm.arm64.neon.st2.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i8* %P)
- ret void
-}
-
-define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) nounwind {
-; CHECK-LABEL: st3_16b
-; CHECK st3.16b
- call void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P)
- ret void
-}
-
-define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P) nounwind {
-; CHECK-LABEL: st4_16b
-; CHECK st4.16b
- call void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v16i8.p0i8(<16 x i8>, <16 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*) nounwind readonly
-
-define void @st2_4h(<4 x i16> %A, <4 x i16> %B, i16* %P) nounwind {
-; CHECK-LABEL: st2_4h
-; CHECK st2.4h
- call void @llvm.arm64.neon.st2.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, i16* %P)
- ret void
-}
-
-define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P) nounwind {
-; CHECK-LABEL: st3_4h
-; CHECK st3.4h
- call void @llvm.arm64.neon.st3.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P)
- ret void
-}
-
-define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P) nounwind {
-; CHECK-LABEL: st4_4h
-; CHECK st4.4h
- call void @llvm.arm64.neon.st4.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v4i16.p0i16(<4 x i16>, <4 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i16*) nounwind readonly
-
-define void @st2_8h(<8 x i16> %A, <8 x i16> %B, i16* %P) nounwind {
-; CHECK-LABEL: st2_8h
-; CHECK st2.8h
- call void @llvm.arm64.neon.st2.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i16* %P)
- ret void
-}
-
-define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P) nounwind {
-; CHECK-LABEL: st3_8h
-; CHECK st3.8h
- call void @llvm.arm64.neon.st3.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P)
- ret void
-}
-
-define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P) nounwind {
-; CHECK-LABEL: st4_8h
-; CHECK st4.8h
- call void @llvm.arm64.neon.st4.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v8i16.p0i16(<8 x i16>, <8 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i16*) nounwind readonly
-
-define void @st2_2s(<2 x i32> %A, <2 x i32> %B, i32* %P) nounwind {
-; CHECK-LABEL: st2_2s
-; CHECK st2.2s
- call void @llvm.arm64.neon.st2.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, i32* %P)
- ret void
-}
-
-define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P) nounwind {
-; CHECK-LABEL: st3_2s
-; CHECK st3.2s
- call void @llvm.arm64.neon.st3.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P)
- ret void
-}
-
-define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P) nounwind {
-; CHECK-LABEL: st4_2s
-; CHECK st4.2s
- call void @llvm.arm64.neon.st4.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v2i32.p0i32(<2 x i32>, <2 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32*) nounwind readonly
-
-define void @st2_4s(<4 x i32> %A, <4 x i32> %B, i32* %P) nounwind {
-; CHECK-LABEL: st2_4s
-; CHECK st2.4s
- call void @llvm.arm64.neon.st2.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i32* %P)
- ret void
-}
-
-define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P) nounwind {
-; CHECK-LABEL: st3_4s
-; CHECK st3.4s
- call void @llvm.arm64.neon.st3.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P)
- ret void
-}
-
-define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P) nounwind {
-; CHECK-LABEL: st4_4s
-; CHECK st4.4s
- call void @llvm.arm64.neon.st4.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
-
-define void @st2_1d(<1 x i64> %A, <1 x i64> %B, i64* %P) nounwind {
-; CHECK-LABEL: st2_1d
-; CHECK st1.2d
- call void @llvm.arm64.neon.st2.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, i64* %P)
- ret void
-}
-
-define void @st3_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P) nounwind {
-; CHECK-LABEL: st3_1d
-; CHECK st1.3d
- call void @llvm.arm64.neon.st3.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P)
- ret void
-}
-
-define void @st4_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P) nounwind {
-; CHECK-LABEL: st4_1d
-; CHECK st1.4d
- call void @llvm.arm64.neon.st4.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v1i64.p0i64(<1 x i64>, <1 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64*) nounwind readonly
-
-define void @st2_2d(<2 x i64> %A, <2 x i64> %B, i64* %P) nounwind {
-; CHECK-LABEL: st2_2d
-; CHECK st2.2d
- call void @llvm.arm64.neon.st2.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64* %P)
- ret void
-}
-
-define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P) nounwind {
-; CHECK-LABEL: st3_2d
-; CHECK st2.3d
- call void @llvm.arm64.neon.st3.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P)
- ret void
-}
-
-define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P) nounwind {
-; CHECK-LABEL: st4_2d
-; CHECK st2.4d
- call void @llvm.arm64.neon.st4.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P)
- ret void
-}
-
-declare void @llvm.arm64.neon.st2.v2i64.p0i64(<2 x i64>, <2 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st3.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st4.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64*) nounwind readonly
-
-declare void @llvm.arm64.neon.st1x2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v4i16.p0i16(<4 x i16>, <4 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v2i32.p0i32(<2 x i32>, <2 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v2f32.p0f32(<2 x float>, <2 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v1i64.p0i64(<1 x i64>, <1 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v1f64.p0f64(<1 x double>, <1 x double>, double*) nounwind readonly
-
-define void @st1_x2_v8i8(<8 x i8> %A, <8 x i8> %B, i8* %addr) {
-; CHECK-LABEL: st1_x2_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, i8* %addr)
- ret void
-}
-
-define void @st1_x2_v4i16(<4 x i16> %A, <4 x i16> %B, i16* %addr) {
-; CHECK-LABEL: st1_x2_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, i16* %addr)
- ret void
-}
-
-define void @st1_x2_v2i32(<2 x i32> %A, <2 x i32> %B, i32* %addr) {
-; CHECK-LABEL: st1_x2_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, i32* %addr)
- ret void
-}
-
-define void @st1_x2_v2f32(<2 x float> %A, <2 x float> %B, float* %addr) {
-; CHECK-LABEL: st1_x2_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v2f32.p0f32(<2 x float> %A, <2 x float> %B, float* %addr)
- ret void
-}
-
-define void @st1_x2_v1i64(<1 x i64> %A, <1 x i64> %B, i64* %addr) {
-; CHECK-LABEL: st1_x2_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, i64* %addr)
- ret void
-}
-
-define void @st1_x2_v1f64(<1 x double> %A, <1 x double> %B, double* %addr) {
-; CHECK-LABEL: st1_x2_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v1f64.p0f64(<1 x double> %A, <1 x double> %B, double* %addr)
- ret void
-}
-
-declare void @llvm.arm64.neon.st1x2.v16i8.p0i8(<16 x i8>, <16 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v8i16.p0i16(<8 x i16>, <8 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v2i64.p0i64(<2 x i64>, <2 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x2.v2f64.p0f64(<2 x double>, <2 x double>, double*) nounwind readonly
-
-define void @st1_x2_v16i8(<16 x i8> %A, <16 x i8> %B, i8* %addr) {
-; CHECK-LABEL: st1_x2_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i8* %addr)
- ret void
-}
-
-define void @st1_x2_v8i16(<8 x i16> %A, <8 x i16> %B, i16* %addr) {
-; CHECK-LABEL: st1_x2_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i16* %addr)
- ret void
-}
-
-define void @st1_x2_v4i32(<4 x i32> %A, <4 x i32> %B, i32* %addr) {
-; CHECK-LABEL: st1_x2_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i32* %addr)
- ret void
-}
-
-define void @st1_x2_v4f32(<4 x float> %A, <4 x float> %B, float* %addr) {
-; CHECK-LABEL: st1_x2_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v4f32.p0f32(<4 x float> %A, <4 x float> %B, float* %addr)
- ret void
-}
-
-define void @st1_x2_v2i64(<2 x i64> %A, <2 x i64> %B, i64* %addr) {
-; CHECK-LABEL: st1_x2_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64* %addr)
- ret void
-}
-
-define void @st1_x2_v2f64(<2 x double> %A, <2 x double> %B, double* %addr) {
-; CHECK-LABEL: st1_x2_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x2.v2f64.p0f64(<2 x double> %A, <2 x double> %B, double* %addr)
- ret void
-}
-
-declare void @llvm.arm64.neon.st1x3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, double*) nounwind readonly
-
-define void @st1_x3_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %addr) {
-; CHECK-LABEL: st1_x3_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %addr)
- ret void
-}
-
-define void @st1_x3_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %addr) {
-; CHECK-LABEL: st1_x3_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %addr)
- ret void
-}
-
-define void @st1_x3_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %addr) {
-; CHECK-LABEL: st1_x3_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %addr)
- ret void
-}
-
-define void @st1_x3_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, float* %addr) {
-; CHECK-LABEL: st1_x3_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v2f32.p0f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, float* %addr)
- ret void
-}
-
-define void @st1_x3_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %addr) {
-; CHECK-LABEL: st1_x3_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %addr)
- ret void
-}
-
-define void @st1_x3_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, double* %addr) {
-; CHECK-LABEL: st1_x3_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, double* %addr)
- ret void
-}
-
-declare void @llvm.arm64.neon.st1x3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x3.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, double*) nounwind readonly
-
-define void @st1_x3_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %addr) {
-; CHECK-LABEL: st1_x3_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %addr)
- ret void
-}
-
-define void @st1_x3_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %addr) {
-; CHECK-LABEL: st1_x3_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %addr)
- ret void
-}
-
-define void @st1_x3_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %addr) {
-; CHECK-LABEL: st1_x3_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %addr)
- ret void
-}
-
-define void @st1_x3_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, float* %addr) {
-; CHECK-LABEL: st1_x3_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v4f32.p0f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, float* %addr)
- ret void
-}
-
-define void @st1_x3_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %addr) {
-; CHECK-LABEL: st1_x3_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %addr)
- ret void
-}
-
-define void @st1_x3_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, double* %addr) {
-; CHECK-LABEL: st1_x3_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x3.v2f64.p0f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, double* %addr)
- ret void
-}
-
-
-declare void @llvm.arm64.neon.st1x4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v2f32.p0f32(<2 x float>, <2 x float>, <2 x float>, <2 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1 x double>, <1 x double>, double*) nounwind readonly
-
-define void @st1_x4_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %addr) {
-; CHECK-LABEL: st1_x4_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %addr)
- ret void
-}
-
-define void @st1_x4_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %addr) {
-; CHECK-LABEL: st1_x4_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %addr)
- ret void
-}
-
-define void @st1_x4_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %addr) {
-; CHECK-LABEL: st1_x4_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %addr)
- ret void
-}
-
-define void @st1_x4_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, float* %addr) {
-; CHECK-LABEL: st1_x4_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v2f32.p0f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, float* %addr)
- ret void
-}
-
-define void @st1_x4_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %addr) {
-; CHECK-LABEL: st1_x4_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %addr)
- ret void
-}
-
-define void @st1_x4_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, double* %addr) {
-; CHECK-LABEL: st1_x4_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v1f64.p0f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, double* %addr)
- ret void
-}
-
-declare void @llvm.arm64.neon.st1x4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i16*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, i64*) nounwind readonly
-declare void @llvm.arm64.neon.st1x4.v2f64.p0f64(<2 x double>, <2 x double>, <2 x double>, <2 x double>, double*) nounwind readonly
-
-define void @st1_x4_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %addr) {
-; CHECK-LABEL: st1_x4_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %addr)
- ret void
-}
-
-define void @st1_x4_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %addr) {
-; CHECK-LABEL: st1_x4_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %addr)
- ret void
-}
-
-define void @st1_x4_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %addr) {
-; CHECK-LABEL: st1_x4_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %addr)
- ret void
-}
-
-define void @st1_x4_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, float* %addr) {
-; CHECK-LABEL: st1_x4_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v4f32.p0f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, float* %addr)
- ret void
-}
-
-define void @st1_x4_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %addr) {
-; CHECK-LABEL: st1_x4_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %addr)
- ret void
-}
-
-define void @st1_x4_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, double* %addr) {
-; CHECK-LABEL: st1_x4_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
- call void @llvm.arm64.neon.st1x4.v2f64.p0f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, double* %addr)
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/stack-no-frame.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stack-no-frame.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stack-no-frame.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stack-no-frame.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s
-
- at global = global [20 x i64] zeroinitializer, align 8
-
-; The following function has enough locals to need some restoring, but not a
-; frame record. In an intermediate frame refactoring, prologue and epilogue were
-; inconsistent about how much to move SP.
-define void @test_stack_no_frame() {
-; CHECK: test_stack_no_frame
-; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
- %local = alloca [20 x i64]
- %val = load volatile [20 x i64]* @global, align 8
- store volatile [20 x i64] %val, [20 x i64]* %local, align 8
-
- %val2 = load volatile [20 x i64]* %local, align 8
- store volatile [20 x i64] %val2, [20 x i64]* @global, align 8
-
-; CHECK: add sp, sp, #[[STACKSIZE]]
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/stackmap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stackmap.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stackmap.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stackmap.ll (removed)
@@ -1,288 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-;
-; Note: Print verbose stackmaps using -debug-only=stackmaps.
-
-; We are not getting the correct stack alignment when cross compiling for arm64.
-; So specify a datalayout here.
-target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
-
-; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
-; CHECK-NEXT: __LLVM_StackMaps:
-; Header
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .short 0
-; Num Functions
-; CHECK-NEXT: .long 11
-; Num LargeConstants
-; CHECK-NEXT: .long 2
-; Num Callsites
-; CHECK-NEXT: .long 11
-
-; Functions and stack size
-; CHECK-NEXT: .quad _constantargs
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _osrinline
-; CHECK-NEXT: .quad 32
-; CHECK-NEXT: .quad _osrcold
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _propertyRead
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _propertyWrite
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _jsVoidCall
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _jsIntCall
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _spilledValue
-; CHECK-NEXT: .quad 160
-; CHECK-NEXT: .quad _spilledStackMapValue
-; CHECK-NEXT: .quad 128
-; CHECK-NEXT: .quad _liveConstant
-; CHECK-NEXT: .quad 16
-; CHECK-NEXT: .quad _clobberLR
-; CHECK-NEXT: .quad 112
-
-; Num LargeConstants
-; CHECK-NEXT: .quad 4294967295
-; CHECK-NEXT: .quad 4294967296
-
-; Constant arguments
-;
-; CHECK-NEXT: .quad 1
-; CHECK-NEXT: .long L{{.*}}-_constantargs
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 4
-; SmallConstant
-; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 65535
-; SmallConstant
-; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 65536
-; SmallConstant
-; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 0
-; LargeConstant at index 0
-; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 1
-
-define void @constantargs() {
-entry:
- %0 = inttoptr i64 244837814094590 to i8*
- tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296)
- ret void
-}
-
-; Inline OSR Exit
-;
-; CHECK-LABEL: .long L{{.*}}-_osrinline
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 2
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-define void @osrinline(i64 %a, i64 %b) {
-entry:
- ; Runtime void->void call.
- call void inttoptr (i64 244837814094590 to void ()*)()
- ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars.
- call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b)
- ret void
-}
-
-; Cold OSR Exit
-;
-; 2 live variables in register.
-;
-; CHECK-LABEL: .long L{{.*}}-_osrcold
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 2
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-define void @osrcold(i64 %a, i64 %b) {
-entry:
- %test = icmp slt i64 %a, %b
- br i1 %test, label %ret, label %cold
-cold:
- ; OSR patchpoint with 12-byte nop-slide and 2 live vars.
- %thunk = inttoptr i64 244837814094590 to i8*
- call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b)
- unreachable
-ret:
- ret void
-}
-
-; Property Read
-; CHECK-LABEL: .long L{{.*}}-_propertyRead
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 0
-;
-; FIXME: There are currently no stackmap entries. After moving to
-; AnyRegCC, we will have entries for the object and return value.
-define i64 @propertyRead(i64* %obj) {
-entry:
- %resolveRead = inttoptr i64 244837814094590 to i8*
- %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj)
- %add = add i64 %result, 3
- ret i64 %add
-}
-
-; Property Write
-; CHECK-LABEL: .long L{{.*}}-_propertyWrite
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 2
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
-entry:
- %resolveWrite = inttoptr i64 244837814094590 to i8*
- call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a)
- ret void
-}
-
-; Void JS Call
-;
-; 2 live variables in registers.
-;
-; CHECK-LABEL: .long L{{.*}}-_jsVoidCall
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 2
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
-entry:
- %resolveCall = inttoptr i64 244837814094590 to i8*
- call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
- ret void
-}
-
-; i64 JS Call
-;
-; 2 live variables in registers.
-;
-; CHECK-LABEL: .long L{{.*}}-_jsIntCall
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 2
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short {{[0-9]+}}
-; CHECK-NEXT: .long 0
-define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
-entry:
- %resolveCall = inttoptr i64 244837814094590 to i8*
- %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2)
- %add = add i64 %result, 3
- ret i64 %add
-}
-
-; Spilled stack map values.
-;
-; Verify 28 stack map entries.
-;
-; CHECK-LABEL: .long L{{.*}}-_spilledValue
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 28
-;
-; Check that at least one is a spilled entry from RBP.
-; Location: Indirect FP + ...
-; CHECK: .byte 3
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 29
-define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
-entry:
- call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
- ret void
-}
-
-; Spilled stack map values.
-;
-; Verify 23 stack map entries.
-;
-; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .short 30
-;
-; Check that at least one is a spilled entry from RBP.
-; Location: Indirect FP + ...
-; CHECK: .byte 3
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 29
-define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
-entry:
- call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
- ret void
-}
-
-
-; Map a constant value.
-;
-; CHECK-LABEL: .long L{{.*}}-_liveConstant
-; CHECK-NEXT: .short 0
-; 1 location
-; CHECK-NEXT: .short 1
-; Loc 0: SmallConstant
-; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
-; CHECK-NEXT: .long 33
-
-define void @liveConstant() {
- tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33)
- ret void
-}
-
-; Map a value when LR is the only free register.
-;
-; CHECK-LABEL: .long L{{.*}}-_clobberLR
-; CHECK-NEXT: .short 0
-; 1 location
-; CHECK-NEXT: .short 1
-; Loc 0: Indirect FP (r29) - offset
-; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .short 29
-; CHECK-NEXT: .long -{{[0-9]+}}
-define void @clobberLR(i32 %a) {
- tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind
- tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a)
- ret void
-}
-
-declare void @llvm.experimental.stackmap(i64, i32, ...)
-declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
-declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
Removed: llvm/trunk/test/CodeGen/ARM64/stackpointer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stackpointer.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stackpointer.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stackpointer.ll (removed)
@@ -1,24 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s
-
-define i64 @get_stack() nounwind {
-entry:
-; CHECK-LABEL: get_stack:
-; CHECK: mov x0, sp
- %sp = call i64 @llvm.read_register.i64(metadata !0)
- ret i64 %sp
-}
-
-define void @set_stack(i64 %val) nounwind {
-entry:
-; CHECK-LABEL: set_stack:
-; CHECK: mov sp, x0
- call void @llvm.write_register.i64(metadata !0, i64 %val)
- ret void
-}
-
-declare i64 @llvm.read_register.i64(metadata) nounwind
-declare void @llvm.write_register.i64(metadata, i64) nounwind
-
-; register unsigned long current_stack_pointer asm("sp");
-; CHECK-NOT: .asciz "sp"
-!0 = metadata !{metadata !"sp\00"}
Removed: llvm/trunk/test/CodeGen/ARM64/stacksave.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stacksave.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stacksave.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stacksave.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc < %s -verify-coalescing
-; <rdar://problem/11522048>
-target triple = "arm64-apple-macosx10.8.0"
-
-; Verify that we can handle spilling the stack pointer without attempting
-; spilling it directly.
-; CHECK: f
-; CHECK: mov [[X0:x[0-9]+]], sp
-; CHECK: str [[X0]]
-; CHECK: inlineasm
-define void @f() nounwind ssp {
-entry:
- %savedstack = call i8* @llvm.stacksave() nounwind
- call void asm sideeffect "; inlineasm", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind
- call void @llvm.stackrestore(i8* %savedstack) nounwind
- ret void
-}
-
-declare i8* @llvm.stacksave() nounwind
-declare void @llvm.stackrestore(i8*) nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/stp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stp.ll (removed)
@@ -1,101 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-stp-suppress=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
-; RUN: llc < %s -march=arm64 -arm64-unscaled-mem-op=true\
-; RUN: -verify-machineinstrs -mcpu=cyclone | FileCheck -check-prefix=STUR_CHK %s
-
-; CHECK: stp_int
-; CHECK: stp w0, w1, [x2]
-define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
- store i32 %a, i32* %p, align 4
- %add.ptr = getelementptr inbounds i32* %p, i64 1
- store i32 %b, i32* %add.ptr, align 4
- ret void
-}
-
-; CHECK: stp_long
-; CHECK: stp x0, x1, [x2]
-define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
- store i64 %a, i64* %p, align 8
- %add.ptr = getelementptr inbounds i64* %p, i64 1
- store i64 %b, i64* %add.ptr, align 8
- ret void
-}
-
-; CHECK: stp_float
-; CHECK: stp s0, s1, [x0]
-define void @stp_float(float %a, float %b, float* nocapture %p) nounwind {
- store float %a, float* %p, align 4
- %add.ptr = getelementptr inbounds float* %p, i64 1
- store float %b, float* %add.ptr, align 4
- ret void
-}
-
-; CHECK: stp_double
-; CHECK: stp d0, d1, [x0]
-define void @stp_double(double %a, double %b, double* nocapture %p) nounwind {
- store double %a, double* %p, align 8
- %add.ptr = getelementptr inbounds double* %p, i64 1
- store double %b, double* %add.ptr, align 8
- ret void
-}
-
-; Test the load/store optimizer---combine ldurs into a ldp, if appropriate
-define void @stur_int(i32 %a, i32 %b, i32* nocapture %p) nounwind {
-; STUR_CHK: stur_int
-; STUR_CHK: stp w{{[0-9]+}}, {{w[0-9]+}}, [x{{[0-9]+}}, #-8]
-; STUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i32* %p, i32 -1
- store i32 %a, i32* %p1, align 2
- %p2 = getelementptr inbounds i32* %p, i32 -2
- store i32 %b, i32* %p2, align 2
- ret void
-}
-
-define void @stur_long(i64 %a, i64 %b, i64* nocapture %p) nounwind {
-; STUR_CHK: stur_long
-; STUR_CHK: stp x{{[0-9]+}}, {{x[0-9]+}}, [x{{[0-9]+}}, #-16]
-; STUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds i64* %p, i32 -1
- store i64 %a, i64* %p1, align 2
- %p2 = getelementptr inbounds i64* %p, i32 -2
- store i64 %b, i64* %p2, align 2
- ret void
-}
-
-define void @stur_float(float %a, float %b, float* nocapture %p) nounwind {
-; STUR_CHK: stur_float
-; STUR_CHK: stp s{{[0-9]+}}, {{s[0-9]+}}, [x{{[0-9]+}}, #-8]
-; STUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds float* %p, i32 -1
- store float %a, float* %p1, align 2
- %p2 = getelementptr inbounds float* %p, i32 -2
- store float %b, float* %p2, align 2
- ret void
-}
-
-define void @stur_double(double %a, double %b, double* nocapture %p) nounwind {
-; STUR_CHK: stur_double
-; STUR_CHK: stp d{{[0-9]+}}, {{d[0-9]+}}, [x{{[0-9]+}}, #-16]
-; STUR_CHK-NEXT: ret
- %p1 = getelementptr inbounds double* %p, i32 -1
- store double %a, double* %p1, align 2
- %p2 = getelementptr inbounds double* %p, i32 -2
- store double %b, double* %p2, align 2
- ret void
-}
-
-define void @splat_v4i32(i32 %v, i32 *%p) {
-entry:
-
-; CHECK-LABEL: splat_v4i32
-; CHECK-DAG: stp w0, w0, [x1]
-; CHECK-DAG: stp w0, w0, [x1, #8]
-; CHECK: ret
-
- %p17 = insertelement <4 x i32> undef, i32 %v, i32 0
- %p18 = insertelement <4 x i32> %p17, i32 %v, i32 1
- %p19 = insertelement <4 x i32> %p18, i32 %v, i32 2
- %p20 = insertelement <4 x i32> %p19, i32 %v, i32 3
- %p21 = bitcast i32* %p to <4 x i32>*
- store <4 x i32> %p20, <4 x i32>* %p21, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/strict-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/strict-align.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/strict-align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/strict-align.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-apple-darwin -arm64-no-strict-align | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-apple-darwin -arm64-strict-align | FileCheck %s --check-prefix=CHECK-STRICT
-
-define i32 @f0(i32* nocapture %p) nounwind {
-; CHECK-STRICT: ldrh [[HIGH:w[0-9]+]], [x0, #2]
-; CHECK-STRICT: ldrh [[LOW:w[0-9]+]], [x0]
-; CHECK-STRICT: bfi [[LOW]], [[HIGH]], #16, #16
-; CHECK-STRICT: ret
-
-; CHECK: ldr w0, [x0]
-; CHECK: ret
- %tmp = load i32* %p, align 2
- ret i32 %tmp
-}
-
-define i64 @f1(i64* nocapture %p) nounwind {
-; CHECK-STRICT: ldp w[[LOW:[0-9]+]], w[[HIGH:[0-9]+]], [x0]
-; CHECK-STRICT: bfi x[[LOW]], x[[HIGH]], #32, #32
-; CHECK-STRICT: ret
-
-; CHECK: ldr x0, [x0]
-; CHECK: ret
- %tmp = load i64* %p, align 4
- ret i64 %tmp
-}
Removed: llvm/trunk/test/CodeGen/ARM64/stur.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/stur.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/stur.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/stur.ll (removed)
@@ -1,98 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -mcpu=cyclone | FileCheck %s
-%struct.X = type <{ i32, i64, i64 }>
-
-define void @foo1(i32* %p, i64 %val) nounwind {
-; CHECK-LABEL: foo1:
-; CHECK: stur w1, [x0, #-4]
-; CHECK-NEXT: ret
- %tmp1 = trunc i64 %val to i32
- %ptr = getelementptr inbounds i32* %p, i64 -1
- store i32 %tmp1, i32* %ptr, align 4
- ret void
-}
-define void @foo2(i16* %p, i64 %val) nounwind {
-; CHECK-LABEL: foo2:
-; CHECK: sturh w1, [x0, #-2]
-; CHECK-NEXT: ret
- %tmp1 = trunc i64 %val to i16
- %ptr = getelementptr inbounds i16* %p, i64 -1
- store i16 %tmp1, i16* %ptr, align 2
- ret void
-}
-define void @foo3(i8* %p, i64 %val) nounwind {
-; CHECK-LABEL: foo3:
-; CHECK: sturb w1, [x0, #-1]
-; CHECK-NEXT: ret
- %tmp1 = trunc i64 %val to i8
- %ptr = getelementptr inbounds i8* %p, i64 -1
- store i8 %tmp1, i8* %ptr, align 1
- ret void
-}
-define void @foo4(i16* %p, i32 %val) nounwind {
-; CHECK-LABEL: foo4:
-; CHECK: sturh w1, [x0, #-2]
-; CHECK-NEXT: ret
- %tmp1 = trunc i32 %val to i16
- %ptr = getelementptr inbounds i16* %p, i32 -1
- store i16 %tmp1, i16* %ptr, align 2
- ret void
-}
-define void @foo5(i8* %p, i32 %val) nounwind {
-; CHECK-LABEL: foo5:
-; CHECK: sturb w1, [x0, #-1]
-; CHECK-NEXT: ret
- %tmp1 = trunc i32 %val to i8
- %ptr = getelementptr inbounds i8* %p, i32 -1
- store i8 %tmp1, i8* %ptr, align 1
- ret void
-}
-
-define void @foo(%struct.X* nocapture %p) nounwind optsize ssp {
-; CHECK-LABEL: foo:
-; CHECK-NOT: str
-; CHECK: stur xzr, [x0, #12]
-; CHECK-NEXT: stur xzr, [x0, #4]
-; CHECK-NEXT: ret
- %B = getelementptr inbounds %struct.X* %p, i64 0, i32 1
- %val = bitcast i64* %B to i8*
- call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i32 1, i1 false)
- ret void
-}
-
-declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
-
-; Unaligned 16b stores are split into 8b stores for performance.
-; radar://15424193
-
-; CHECK-LABEL: unaligned:
-; CHECK-NOT: str q0
-; CHECK: str d[[REG:[0-9]+]], [x0]
-; CHECK: ext.16b v[[REG2:[0-9]+]], v[[REG]], v[[REG]], #8
-; CHECK: str d[[REG2]], [x0, #8]
-define void @unaligned(<4 x i32>* %p, <4 x i32> %v) nounwind {
- store <4 x i32> %v, <4 x i32>* %p, align 4
- ret void
-}
-
-; CHECK-LABEL: aligned:
-; CHECK: str q0
-define void @aligned(<4 x i32>* %p, <4 x i32> %v) nounwind {
- store <4 x i32> %v, <4 x i32>* %p
- ret void
-}
-
-; Don't split one and two byte aligned stores.
-; radar://16349308
-
-; CHECK-LABEL: twobytealign:
-; CHECK: str q0
-define void @twobytealign(<4 x i32>* %p, <4 x i32> %v) nounwind {
- store <4 x i32> %v, <4 x i32>* %p, align 2
- ret void
-}
-; CHECK-LABEL: onebytealign:
-; CHECK: str q0
-define void @onebytealign(<4 x i32>* %p, <4 x i32> %v) nounwind {
- store <4 x i32> %v, <4 x i32>* %p, align 1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/subsections.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/subsections.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/subsections.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/subsections.ll (removed)
@@ -1,5 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK-MACHO
-; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK-ELF
-
-; CHECK-MACHO: .subsections_via_symbols
-; CHECK-ELF-NOT: .subsections_via_symbols
\ No newline at end of file
Removed: llvm/trunk/test/CodeGen/ARM64/subvector-extend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/subvector-extend.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/subvector-extend.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/subvector-extend.ll (removed)
@@ -1,141 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
-
-; Test efficient codegen of vector extends up from legal type to 128 bit
-; and 256 bit vector types.
-
-;-----
-; Vectors of i16.
-;-----
-define <8 x i16> @func1(<8 x i8> %v0) nounwind {
-; CHECK-LABEL: func1:
-; CHECK-NEXT: ushll.8h v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <8 x i8> %v0 to <8 x i16>
- ret <8 x i16> %r
-}
-
-define <8 x i16> @func2(<8 x i8> %v0) nounwind {
-; CHECK-LABEL: func2:
-; CHECK-NEXT: sshll.8h v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <8 x i8> %v0 to <8 x i16>
- ret <8 x i16> %r
-}
-
-define <16 x i16> @func3(<16 x i8> %v0) nounwind {
-; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll2.8h v1, v0, #0
-; CHECK-NEXT: ushll.8h v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <16 x i8> %v0 to <16 x i16>
- ret <16 x i16> %r
-}
-
-define <16 x i16> @func4(<16 x i8> %v0) nounwind {
-; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll2.8h v1, v0, #0
-; CHECK-NEXT: sshll.8h v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <16 x i8> %v0 to <16 x i16>
- ret <16 x i16> %r
-}
-
-;-----
-; Vectors of i32.
-;-----
-
-define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
-; CHECK-LABEL: afunc1:
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <4 x i16> %v0 to <4 x i32>
- ret <4 x i32> %r
-}
-
-define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
-; CHECK-LABEL: afunc2:
-; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <4 x i16> %v0 to <4 x i32>
- ret <4 x i32> %r
-}
-
-define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
-; CHECK-LABEL: afunc3:
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <8 x i16> %v0 to <8 x i32>
- ret <8 x i32> %r
-}
-
-define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
-; CHECK-LABEL: afunc4:
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <8 x i16> %v0 to <8 x i32>
- ret <8 x i32> %r
-}
-
-define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
-; CHECK-LABEL: bfunc1:
-; CHECK-NEXT: ushll.8h v0, v0, #0
-; CHECK-NEXT: ushll2.4s v1, v0, #0
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <8 x i8> %v0 to <8 x i32>
- ret <8 x i32> %r
-}
-
-define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
-; CHECK-LABEL: bfunc2:
-; CHECK-NEXT: sshll.8h v0, v0, #0
-; CHECK-NEXT: sshll2.4s v1, v0, #0
-; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <8 x i8> %v0 to <8 x i32>
- ret <8 x i32> %r
-}
-
-;-----
-; Vectors of i64.
-;-----
-
-define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
-; CHECK-LABEL: zfunc1:
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <4 x i32> %v0 to <4 x i64>
- ret <4 x i64> %r
-}
-
-define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
-; CHECK-LABEL: zfunc2:
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <4 x i32> %v0 to <4 x i64>
- ret <4 x i64> %r
-}
-
-define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
-; CHECK-LABEL: func3:
-; CHECK-NEXT: ushll.4s v0, v0, #0
-; CHECK-NEXT: ushll2.2d v1, v0, #0
-; CHECK-NEXT: ushll.2d v0, v0, #0
-; CHECK-NEXT: ret
- %r = zext <4 x i16> %v0 to <4 x i64>
- ret <4 x i64> %r
-}
-
-define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
-; CHECK-LABEL: func4:
-; CHECK-NEXT: sshll.4s v0, v0, #0
-; CHECK-NEXT: sshll2.2d v1, v0, #0
-; CHECK-NEXT: sshll.2d v0, v0, #0
-; CHECK-NEXT: ret
- %r = sext <4 x i16> %v0 to <4 x i64>
- ret <4 x i64> %r
-}
Removed: llvm/trunk/test/CodeGen/ARM64/swizzle-tbl-i16-layout.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/swizzle-tbl-i16-layout.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/swizzle-tbl-i16-layout.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/swizzle-tbl-i16-layout.ll (removed)
@@ -1,36 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-; rdar://13214163 - Make sure we generate a correct lookup table for the TBL
-; instruction when the element size of the vector is not 8 bits. We were
-; getting both the endianness wrong and the element indexing wrong.
-define <8 x i16> @foo(<8 x i16> %a) nounwind readnone {
-; CHECK: .section __TEXT,__literal16,16byte_literals
-; CHECK: .align 4
-; CHECK:lCPI0_0:
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 1 ; 0x1
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 1 ; 0x1
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 1 ; 0x1
-; CHECK: .byte 0 ; 0x0
-; CHECK: .byte 1 ; 0x1
-; CHECK: .byte 8 ; 0x8
-; CHECK: .byte 9 ; 0x9
-; CHECK: .byte 8 ; 0x8
-; CHECK: .byte 9 ; 0x9
-; CHECK: .byte 8 ; 0x8
-; CHECK: .byte 9 ; 0x9
-; CHECK: .byte 8 ; 0x8
-; CHECK: .byte 9 ; 0x9
-; CHECK: .section __TEXT,__text,regular,pure_instructions
-; CHECK: .globl _foo
-; CHECK: .align 2
-; CHECK:_foo: ; @foo
-; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0 at PAGE
-; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0 at PAGEOFF]
-; CHECK: tbl.16b v0, { v0 }, v[[REG]]
-; CHECK: ret
-
- %val = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 4, i32 4, i32 4, i32 4>
- ret <8 x i16> %val
-}
Removed: llvm/trunk/test/CodeGen/ARM64/tbl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/tbl.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/tbl.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/tbl.ll (removed)
@@ -1,132 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @tbl1_8b(<16 x i8> %A, <8 x i8> %B) nounwind {
-; CHECK: tbl1_8b
-; CHECK: tbl.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbl1.v8i8(<16 x i8> %A, <8 x i8> %B)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbl1_16b(<16 x i8> %A, <16 x i8> %B) nounwind {
-; CHECK: tbl1_16b
-; CHECK: tbl.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbl1.v16i8(<16 x i8> %A, <16 x i8> %B)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbl2_8b(<16 x i8> %A, <16 x i8> %B, <8 x i8> %C) {
-; CHECK: tbl2_8b
-; CHECK: tbl.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbl2.v8i8(<16 x i8> %A, <16 x i8> %B, <8 x i8> %C)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbl2_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
-; CHECK: tbl2_16b
-; CHECK: tbl.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbl2.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbl3_8b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <8 x i8> %D) {
-; CHECK: tbl3_8b
-; CHECK: tbl.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbl3.v8i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <8 x i8> %D)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbl3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) {
-; CHECK: tbl3_16b
-; CHECK: tbl.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbl3.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbl4_8b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <8 x i8> %E) {
-; CHECK: tbl4_8b
-; CHECK: tbl.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbl4.v8i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <8 x i8> %E)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbl4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) {
-; CHECK: tbl4_16b
-; CHECK: tbl.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbl4.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E)
- ret <16 x i8> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.tbl1.v8i8(<16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbl2.v8i8(<16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbl2.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbl3.v8i8(<16 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbl3.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbl4.v8i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbl4.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-
-define <8 x i8> @tbx1_8b(<8 x i8> %A, <16 x i8> %B, <8 x i8> %C) nounwind {
-; CHECK: tbx1_8b
-; CHECK: tbx.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbx1.v8i8(<8 x i8> %A, <16 x i8> %B, <8 x i8> %C)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbx1_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) nounwind {
-; CHECK: tbx1_16b
-; CHECK: tbx.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbx1.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbx2_8b(<8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <8 x i8> %D) {
-; CHECK: tbx2_8b
-; CHECK: tbx.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbx2.v8i8(<8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <8 x i8> %D)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbx2_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) {
-; CHECK: tbx2_16b
-; CHECK: tbx.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbx2.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbx3_8b(<8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <8 x i8> %E) {
-; CHECK: tbx3_8b
-; CHECK: tbx.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbx3.v8i8(< 8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <8 x i8> %E)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbx3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) {
-; CHECK: tbx3_16b
-; CHECK: tbx.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbx3.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E)
- ret <16 x i8> %tmp3
-}
-
-define <8 x i8> @tbx4_8b(<8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, <8 x i8> %F) {
-; CHECK: tbx4_8b
-; CHECK: tbx.8b
- %tmp3 = call <8 x i8> @llvm.arm64.neon.tbx4.v8i8(<8 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, <8 x i8> %F)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @tbx4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, <16 x i8> %F) {
-; CHECK: tbx4_16b
-; CHECK: tbx.16b
- %tmp3 = call <16 x i8> @llvm.arm64.neon.tbx4.v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, <16 x i8> %F)
- ret <16 x i8> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.tbx1.v8i8(<8 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbx1.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbx2.v8i8(<8 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbx2.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbx3.v8i8(<8 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbx3.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.tbx4.v8i8(<8 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.tbx4.v16i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
-
Removed: llvm/trunk/test/CodeGen/ARM64/this-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/this-return.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/this-return.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/this-return.ll (removed)
@@ -1,83 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-
-%struct.A = type { i8 }
-%struct.B = type { i32 }
-%struct.C = type { %struct.B }
-%struct.D = type { %struct.B }
-%struct.E = type { %struct.B, %struct.B }
-
-declare %struct.A* @A_ctor_base(%struct.A* returned)
-declare %struct.B* @B_ctor_base(%struct.B* returned, i32)
-declare %struct.B* @B_ctor_complete(%struct.B* returned, i32)
-
-declare %struct.A* @A_ctor_base_nothisret(%struct.A*)
-declare %struct.B* @B_ctor_base_nothisret(%struct.B*, i32)
-declare %struct.B* @B_ctor_complete_nothisret(%struct.B*, i32)
-
-define %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x) {
-entry:
-; CHECK-LABEL: C_ctor_base:
-; CHECK-NOT: mov {{x[0-9]+}}, x0
-; CHECK: bl {{_?A_ctor_base}}
-; CHECK-NOT: mov x0, {{x[0-9]+}}
-; CHECK: b {{_?B_ctor_base}}
- %0 = bitcast %struct.C* %this to %struct.A*
- %call = tail call %struct.A* @A_ctor_base(%struct.A* %0)
- %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
- %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x)
- ret %struct.C* %this
-}
-
-define %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) {
-entry:
-; CHECK-LABEL: C_ctor_base_nothisret:
-; CHECK: mov [[SAVETHIS:x[0-9]+]], x0
-; CHECK: bl {{_?A_ctor_base_nothisret}}
-; CHECK: mov x0, [[SAVETHIS]]
-; CHECK-NOT: b {{_?B_ctor_base_nothisret}}
- %0 = bitcast %struct.C* %this to %struct.A*
- %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0)
- %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0
- %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x)
- ret %struct.C* %this
-}
-
-define %struct.C* @C_ctor_complete(%struct.C* %this, i32 %x) {
-entry:
-; CHECK-LABEL: C_ctor_complete:
-; CHECK: b {{_?C_ctor_base}}
- %call = tail call %struct.C* @C_ctor_base(%struct.C* %this, i32 %x)
- ret %struct.C* %this
-}
-
-define %struct.C* @C_ctor_complete_nothisret(%struct.C* %this, i32 %x) {
-entry:
-; CHECK-LABEL: C_ctor_complete_nothisret:
-; CHECK-NOT: b {{_?C_ctor_base_nothisret}}
- %call = tail call %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x)
- ret %struct.C* %this
-}
-
-define %struct.D* @D_ctor_base(%struct.D* %this, i32 %x) {
-entry:
-; CHECK-LABEL: D_ctor_base:
-; CHECK-NOT: mov {{x[0-9]+}}, x0
-; CHECK: bl {{_?B_ctor_complete}}
-; CHECK-NOT: mov x0, {{x[0-9]+}}
-; CHECK: b {{_?B_ctor_complete}}
- %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0
- %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
- %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
- ret %struct.D* %this
-}
-
-define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) {
-entry:
-; CHECK-LABEL: E_ctor_base:
-; CHECK-NOT: b {{_?B_ctor_complete}}
- %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0
- %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
- %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1
- %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x)
- ret %struct.E* %this
-}
Removed: llvm/trunk/test/CodeGen/ARM64/tls-darwin.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/tls-darwin.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/tls-darwin.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/tls-darwin.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s
-
- at var = thread_local global i8 0
-
-; N.b. x0 must be the result of the first load (i.e. the address of the
-; descriptor) when tlv_get_addr is called. Likewise the result is returned in
-; x0.
-define i8 @get_var() {
-; CHECK-LABEL: get_var:
-; CHECK: adrp x[[TLVPDESC_SLOT_HI:[0-9]+]], _var at TLVPPAGE
-; CHECK: ldr x0, [x[[TLVPDESC_SLOT_HI]], _var at TLVPPAGEOFF]
-; CHECK: ldr [[TLV_GET_ADDR:x[0-9]+]], [x0]
-; CHECK: blr [[TLV_GET_ADDR]]
-; CHECK: ldrb w0, [x0]
-
- %val = load i8* @var, align 1
- ret i8 %val
-}
Removed: llvm/trunk/test/CodeGen/ARM64/tls-dynamic-together.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/tls-dynamic-together.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/tls-dynamic-together.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/tls-dynamic-together.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc -O0 -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s
-
-; If the .tlsdesccall and blr parts are emitted completely separately (even with
-; glue) then LLVM will separate them quite happily (with a spill at O0, hence
-; the option). This is definitely wrong, so we make sure they are emitted
-; together.
-
- at general_dynamic_var = external thread_local global i32
-
-define i32 @test_generaldynamic() {
-; CHECK-LABEL: test_generaldynamic:
-
- %val = load i32* @general_dynamic_var
- ret i32 %val
-
-; CHECK: .tlsdesccall general_dynamic_var
-; CHECK-NEXT: blr {{x[0-9]+}}
-}
Removed: llvm/trunk/test/CodeGen/ARM64/tls-dynamics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/tls-dynamics.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/tls-dynamics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/tls-dynamics.ll (removed)
@@ -1,135 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
-
- at general_dynamic_var = external thread_local global i32
-
-define i32 @test_generaldynamic() {
-; CHECK-LABEL: test_generaldynamic:
-
- %val = load i32* @general_dynamic_var
- ret i32 %val
-
- ; FIXME: the adrp instructions are redundant (if harmless).
-; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var
-; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
-; CHECK: .tlsdesccall general_dynamic_var
-; CHECK-NEXT: blr [[CALLEE]]
-
-; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
-; CHECK: ldr w0, [x[[TP]], x0]
-
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
-
-}
-
-define i32* @test_generaldynamic_addr() {
-; CHECK-LABEL: test_generaldynamic_addr:
-
- ret i32* @general_dynamic_var
-
- ; FIXME: the adrp instructions are redundant (if harmless).
-; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var
-; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var]
-; CHECK: .tlsdesccall general_dynamic_var
-; CHECK-NEXT: blr [[CALLEE]]
-
-; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
-; CHECK: add x0, [[TP]], x0
-
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
-}
-
- at local_dynamic_var = external thread_local(localdynamic) global i32
-
-define i32 @test_localdynamic() {
-; CHECK-LABEL: test_localdynamic:
-
- %val = load i32* @local_dynamic_var
- ret i32 %val
-
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
-; CHECK-NEXT: blr [[CALLEE]]
-
-; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
-; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var
-
-; CHECK: add x[[TPREL:[0-9]+]], x0, [[DTP_OFFSET]]
-
-; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0
-
-; CHECK: ldr w0, [x[[TPIDR]], x[[TPREL]]]
-
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
-
-}
-
-define i32* @test_localdynamic_addr() {
-; CHECK-LABEL: test_localdynamic_addr:
-
- ret i32* @local_dynamic_var
-
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
-; CHECK-NEXT: blr [[CALLEE]]
-
-; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
-; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var
-
-; CHECK: add [[TPREL:x[0-9]+]], x0, [[DTP_OFFSET]]
-
-; CHECK: mrs [[TPIDR:x[0-9]+]], TPIDR_EL0
-
-; CHECK: add x0, [[TPIDR]], [[TPREL]]
-
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
-
-}
-
-; The entire point of the local-dynamic access model is to have a single call to
-; the expensive resolver. Make sure we achieve that goal.
-
- at local_dynamic_var2 = external thread_local(localdynamic) global i32
-
-define i32 @test_localdynamic_deduplicate() {
-; CHECK-LABEL: test_localdynamic_deduplicate:
-
- %val = load i32* @local_dynamic_var
- %val2 = load i32* @local_dynamic_var2
-
- %sum = add i32 %val, %val2
- ret i32 %sum
-
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_
-; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_
-; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_]
-; CHECK: .tlsdesccall _TLS_MODULE_BASE_
-; CHECK-NEXT: blr [[CALLEE]]
-
-; CHECK-NOT: _TLS_MODULE_BASE_
-
-; CHECK: ret
-}
Removed: llvm/trunk/test/CodeGen/ARM64/tls-execs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/tls-execs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/tls-execs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/tls-execs.ll (removed)
@@ -1,63 +0,0 @@
-; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
-; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
-
- at initial_exec_var = external thread_local(initialexec) global i32
-
-define i32 @test_initial_exec() {
-; CHECK-LABEL: test_initial_exec:
- %val = load i32* @initial_exec_var
-
-; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
-; CHECK: ldr x[[TP_OFFSET:[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var]
-; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
-; CHECK: ldr w0, [x[[TP]], x[[TP_OFFSET]]]
-
-; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
-
- ret i32 %val
-}
-
-define i32* @test_initial_exec_addr() {
-; CHECK-LABEL: test_initial_exec_addr:
- ret i32* @initial_exec_var
-
-; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
-; CHECK: ldr [[TP_OFFSET:x[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var]
-; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
-; CHECK: add x0, [[TP]], [[TP_OFFSET]]
-
-; CHECK-RELOC: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
-
-}
-
- at local_exec_var = thread_local(localexec) global i32 0
-
-define i32 @test_local_exec() {
-; CHECK-LABEL: test_local_exec:
- %val = load i32* @local_exec_var
-
-; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var // encoding: [0bAAA{{[01]+}},A,0b101AAAAA,0x92]
-; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var
-; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0
-; CHECK: ldr w0, [x[[TP]], [[TP_OFFSET]]]
-
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
-
- ret i32 %val
-}
-
-define i32* @test_local_exec_addr() {
-; CHECK-LABEL: test_local_exec_addr:
- ret i32* @local_exec_var
-
-; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
-; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var
-; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0
-; CHECK: add x0, [[TP]], [[TP_OFFSET]]
-
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1
-; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
-}
Removed: llvm/trunk/test/CodeGen/ARM64/trap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/trap.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/trap.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/trap.ll (removed)
@@ -1,8 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-define void @foo() nounwind {
-; CHECK: foo
-; CHECK: brk #0x1
- tail call void @llvm.trap()
- ret void
-}
-declare void @llvm.trap() nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/trn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/trn.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/trn.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/trn.ll (removed)
@@ -1,134 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vtrni8:
-;CHECK: trn1.8b
-;CHECK: trn2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vtrni16:
-;CHECK: trn1.4h
-;CHECK: trn2.4h
-;CHECK-NEXT: add.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
- %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-; 2xi32 TRN is redundant with ZIP
-define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vtrni32:
-;CHECK: zip1.2s
-;CHECK: zip2.2s
-;CHECK-NEXT: add.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
- %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vtrnf:
-;CHECK: zip1.2s
-;CHECK: zip2.2s
-;CHECK-NEXT: fadd.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
- %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
- %tmp5 = fadd <2 x float> %tmp3, %tmp4
- ret <2 x float> %tmp5
-}
-
-define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vtrnQi8:
-;CHECK: trn1.16b
-;CHECK: trn2.16b
-;CHECK-NEXT: add.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
- %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vtrnQi16:
-;CHECK: trn1.8h
-;CHECK: trn2.8h
-;CHECK-NEXT: add.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
- %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vtrnQi32:
-;CHECK: trn1.4s
-;CHECK: trn2.4s
-;CHECK-NEXT: add.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
- %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vtrnQf:
-;CHECK: trn1.4s
-;CHECK: trn2.4s
-;CHECK-NEXT: fadd.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
- %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
- %tmp5 = fadd <4 x float> %tmp3, %tmp4
- ret <4 x float> %tmp5
-}
-
-; Undef shuffle indices should not prevent matching to VTRN:
-
-define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vtrni8_undef:
-;CHECK: trn1.8b
-;CHECK: trn2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vtrnQi16_undef:
-;CHECK: trn1.8h
-;CHECK: trn2.8h
-;CHECK-NEXT: add.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
- %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
Removed: llvm/trunk/test/CodeGen/ARM64/trunc-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/trunc-store.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/trunc-store.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/trunc-store.ll (removed)
@@ -1,75 +0,0 @@
-; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
-
-define void @bar(<8 x i16> %arg, <8 x i8>* %p) nounwind {
-; CHECK-LABEL: bar:
-; CHECK: xtn.8b v[[REG:[0-9]+]], v0
-; CHECK-NEXT: str d[[REG]], [x0]
-; CHECK-NEXT: ret
- %tmp = trunc <8 x i16> %arg to <8 x i8>
- store <8 x i8> %tmp, <8 x i8>* %p, align 8
- ret void
-}
-
- at zptr8 = common global i8* null, align 8
- at zptr16 = common global i16* null, align 8
- at zptr32 = common global i32* null, align 8
-
-define void @fct32(i32 %arg, i64 %var) {
-; CHECK: fct32
-; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr32 at GOTPAGE
-; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr32 at GOTPAGEOFF]
-; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
-; w0 is %arg
-; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
-; w1 is %var truncated
-; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2]
-; CHECK-NEXT: ret
-bb:
- %.pre37 = load i32** @zptr32, align 8
- %dec = add nsw i32 %arg, -1
- %idxprom8 = sext i32 %dec to i64
- %arrayidx9 = getelementptr inbounds i32* %.pre37, i64 %idxprom8
- %tmp = trunc i64 %var to i32
- store i32 %tmp, i32* %arrayidx9, align 4
- ret void
-}
-
-define void @fct16(i32 %arg, i64 %var) {
-; CHECK: fct16
-; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr16 at GOTPAGE
-; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr16 at GOTPAGEOFF]
-; CHECK: ldr [[GLOBALADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
-; w0 is %arg
-; CHECK-NEXT: sub w[[OFFSETREGNUM:[0-9]+]], w0, #1
-; w1 is %var truncated
-; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1]
-; CHECK-NEXT: ret
-bb:
- %.pre37 = load i16** @zptr16, align 8
- %dec = add nsw i32 %arg, -1
- %idxprom8 = sext i32 %dec to i64
- %arrayidx9 = getelementptr inbounds i16* %.pre37, i64 %idxprom8
- %tmp = trunc i64 %var to i16
- store i16 %tmp, i16* %arrayidx9, align 4
- ret void
-}
-
-define void @fct8(i32 %arg, i64 %var) {
-; CHECK: fct8
-; CHECK: adrp [[GLOBALPAGE:x[0-9]+]], _zptr8 at GOTPAGE
-; CHECK: ldr [[GLOBALOFF:x[0-9]+]], {{\[}}[[GLOBALPAGE]], _zptr8 at GOTPAGEOFF]
-; CHECK: ldr [[BASEADDR:x[0-9]+]], {{\[}}[[GLOBALOFF]]]
-; w0 is %arg
-; CHECK-NEXT: add [[ADDR:x[0-9]+]], [[BASEADDR]], w0, sxtw
-; w1 is %var truncated
-; CHECK-NEXT: sturb w1, {{\[}}[[ADDR]], #-1]
-; CHECK-NEXT: ret
-bb:
- %.pre37 = load i8** @zptr8, align 8
- %dec = add nsw i32 %arg, -1
- %idxprom8 = sext i32 %dec to i64
- %arrayidx9 = getelementptr inbounds i8* %.pre37, i64 %idxprom8
- %tmp = trunc i64 %var to i8
- store i8 %tmp, i8* %arrayidx9, align 4
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/umaxv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/umaxv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/umaxv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/umaxv.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
-; CHECK-LABEL: vmax_u8x8:
-; CHECK: umaxv.8b b[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind
- %tmp = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @bar(...)
-
-define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp {
-; CHECK-LABEL: vmax_u4x16:
-; CHECK: umaxv.4h h[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind
- %tmp = trunc i32 %vmaxv.i to i16
- %tobool = icmp eq i16 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp {
-; CHECK-LABEL: vmax_u8x16:
-; CHECK: umaxv.8h h[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind
- %tmp = trunc i32 %vmaxv.i to i16
- %tobool = icmp eq i16 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp {
-; CHECK-LABEL: vmax_u16x8:
-; CHECK: umaxv.16b b[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vmaxv.i = tail call i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind
- %tmp = trunc i32 %vmaxv.i to i8
- %tobool = icmp eq i8 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @llvm.arm64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone
-declare i32 @llvm.arm64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone
-declare i32 @llvm.arm64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone
-declare i32 @llvm.arm64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/uminv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/uminv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/uminv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/uminv.ll (removed)
@@ -1,92 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp {
-; CHECK-LABEL: vmin_u8x8:
-; CHECK: uminv.8b b[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
- %tmp = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @bar(...)
-
-define i32 @vmin_u4x16(<4 x i16> %a) nounwind ssp {
-; CHECK-LABEL: vmin_u4x16:
-; CHECK: uminv.4h h[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
- %tmp = trunc i32 %vminv.i to i16
- %tobool = icmp eq i16 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @vmin_u8x16(<8 x i16> %a) nounwind ssp {
-; CHECK-LABEL: vmin_u8x16:
-; CHECK: uminv.8h h[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
- %tmp = trunc i32 %vminv.i to i16
- %tobool = icmp eq i16 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-define i32 @vmin_u16x8(<16 x i8> %a) nounwind ssp {
-; CHECK-LABEL: vmin_u16x8:
-; CHECK: uminv.16b b[[REG:[0-9]+]], v0
-; CHECK: fmov [[REG2:w[0-9]+]], s[[REG]]
-; CHECK-NOT: and
-; CHECK: cbz [[REG2]],
-entry:
- %vminv.i = tail call i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
- %tmp = trunc i32 %vminv.i to i8
- %tobool = icmp eq i8 %tmp, 0
- br i1 %tobool, label %return, label %if.then
-
-if.then:
- %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() nounwind
- br label %return
-
-return:
- %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]
- ret i32 %retval.0
-}
-
-declare i32 @llvm.arm64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone
-declare i32 @llvm.arm64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone
-declare i32 @llvm.arm64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone
-declare i32 @llvm.arm64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone
Removed: llvm/trunk/test/CodeGen/ARM64/umov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/umov.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/umov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/umov.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define zeroext i8 @f1(<16 x i8> %a) {
-; CHECK-LABEL: f1:
-; CHECK: mov.b w0, v0[3]
-; CHECK-NEXT: ret
- %vecext = extractelement <16 x i8> %a, i32 3
- ret i8 %vecext
-}
-
-define zeroext i16 @f2(<4 x i16> %a) {
-; CHECK-LABEL: f2:
-; CHECK: mov.h w0, v0[2]
-; CHECK-NEXT: ret
- %vecext = extractelement <4 x i16> %a, i32 2
- ret i16 %vecext
-}
-
-define i32 @f3(<2 x i32> %a) {
-; CHECK-LABEL: f3:
-; CHECK: mov.s w0, v0[1]
-; CHECK-NEXT: ret
- %vecext = extractelement <2 x i32> %a, i32 1
- ret i32 %vecext
-}
-
-define i64 @f4(<2 x i64> %a) {
-; CHECK-LABEL: f4:
-; CHECK: mov.d x0, v0[1]
-; CHECK-NEXT: ret
- %vecext = extractelement <2 x i64> %a, i32 1
- ret i64 %vecext
-}
Removed: llvm/trunk/test/CodeGen/ARM64/unaligned_ldst.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/unaligned_ldst.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/unaligned_ldst.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/unaligned_ldst.ll (removed)
@@ -1,41 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-; rdar://r11231896
-
-define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind {
-entry:
-; CHECK-LABEL: t1:
-; CHECK-NOT: orr
-; CHECK: ldr [[X0:x[0-9]+]], [x1]
-; CHECK: str [[X0]], [x0]
- %tmp1 = bitcast i8* %b to i64*
- %tmp2 = bitcast i8* %a to i64*
- %tmp3 = load i64* %tmp1, align 1
- store i64 %tmp3, i64* %tmp2, align 1
- ret void
-}
-
-define void @t2(i8* nocapture %a, i8* nocapture %b) nounwind {
-entry:
-; CHECK-LABEL: t2:
-; CHECK-NOT: orr
-; CHECK: ldr [[W0:w[0-9]+]], [x1]
-; CHECK: str [[W0]], [x0]
- %tmp1 = bitcast i8* %b to i32*
- %tmp2 = bitcast i8* %a to i32*
- %tmp3 = load i32* %tmp1, align 1
- store i32 %tmp3, i32* %tmp2, align 1
- ret void
-}
-
-define void @t3(i8* nocapture %a, i8* nocapture %b) nounwind {
-entry:
-; CHECK-LABEL: t3:
-; CHECK-NOT: orr
-; CHECK: ldrh [[W0:w[0-9]+]], [x1]
-; CHECK: strh [[W0]], [x0]
- %tmp1 = bitcast i8* %b to i16*
- %tmp2 = bitcast i8* %a to i16*
- %tmp3 = load i16* %tmp1, align 1
- store i16 %tmp3, i16* %tmp2, align 1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/ARM64/uzp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/uzp.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/uzp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/uzp.ll (removed)
@@ -1,107 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vuzpi8:
-;CHECK: uzp1.8b
-;CHECK: uzp2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vuzpi16:
-;CHECK: uzp1.4h
-;CHECK: uzp2.4h
-;CHECK-NEXT: add.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
- %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vuzpQi8:
-;CHECK: uzp1.16b
-;CHECK: uzp2.16b
-;CHECK-NEXT: add.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
- %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vuzpQi16:
-;CHECK: uzp1.8h
-;CHECK: uzp2.8h
-;CHECK-NEXT: add.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
- %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vuzpQi32:
-;CHECK: uzp1.4s
-;CHECK: uzp2.4s
-;CHECK-NEXT: add.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
- %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vuzpQf:
-;CHECK: uzp1.4s
-;CHECK: uzp2.4s
-;CHECK-NEXT: fadd.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
- %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
- %tmp5 = fadd <4 x float> %tmp3, %tmp4
- ret <4 x float> %tmp5
-}
-
-; Undef shuffle indices should not prevent matching to VUZP:
-
-define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vuzpi8_undef:
-;CHECK: uzp1.8b
-;CHECK: uzp2.8b
-;CHECK-NEXT: add.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
- %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vuzpQi16_undef:
-;CHECK: uzp1.8h
-;CHECK: uzp2.8h
-;CHECK-NEXT: add.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
- %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vaargs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vaargs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vaargs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vaargs.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc < %s -march=arm64 | FileCheck %s
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
-target triple = "arm64-apple-darwin11.0.0"
-
-define float @t1(i8* nocapture %fmt, ...) nounwind ssp {
-entry:
-; CHECK: t1
-; CHECK: fcvt
- %argp = alloca i8*, align 8
- %argp1 = bitcast i8** %argp to i8*
- call void @llvm.va_start(i8* %argp1)
- %0 = va_arg i8** %argp, i32
- %1 = va_arg i8** %argp, float
- call void @llvm.va_end(i8* %argp1)
- ret float %1
-}
-
-declare void @llvm.va_start(i8*) nounwind
-
-declare void @llvm.va_end(i8*) nounwind
Removed: llvm/trunk/test/CodeGen/ARM64/vabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vabs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vabs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vabs.ll (removed)
@@ -1,804 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
-
-
-define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sabdl8h:
-;CHECK: sabdl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sabdl4s:
-;CHECK: sabdl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sabdl2d:
-;CHECK: sabdl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sabdl2_8h:
-;CHECK: sabdl2.8h
- %load1 = load <16 x i8>* %A
- %load2 = load <16 x i8>* %B
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sabdl2_4s:
-;CHECK: sabdl2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sabdl2_2d:
-;CHECK: sabdl2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uabdl8h:
-;CHECK: uabdl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uabdl4s:
-;CHECK: uabdl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uabdl2d:
-;CHECK: uabdl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uabdl2_8h:
-;CHECK: uabdl2.8h
- %load1 = load <16 x i8>* %A
- %load2 = load <16 x i8>* %B
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = zext <8 x i8> %tmp3 to <8 x i16>
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uabdl2_4s:
-;CHECK: uabdl2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = zext <4 x i16> %tmp3 to <4 x i32>
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uabdl2_2d:
-;CHECK: uabdl2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = zext <2 x i32> %tmp3 to <2 x i64>
- ret <2 x i64> %tmp4
-}
-
-define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_2s:
-;CHECK: fabd.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: fabd_4s:
-;CHECK: fabd.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @fabd_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: fabd_2d:
-;CHECK: fabd.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.fabd.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.fabd.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.fabd.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: sabd_8b:
-;CHECK: sabd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: sabd_16b:
-;CHECK: sabd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sabd_4h:
-;CHECK: sabd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sabd_8h:
-;CHECK: sabd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sabd_2s:
-;CHECK: sabd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sabd_4s:
-;CHECK: sabd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.sabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uabd_8b:
-;CHECK: uabd.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uabd_16b:
-;CHECK: uabd.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uabd_4h:
-;CHECK: uabd.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uabd_8h:
-;CHECK: uabd.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uabd_2s:
-;CHECK: uabd.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @uabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uabd_4s:
-;CHECK: uabd.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.uabd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.uabd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-
-define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqabs_8b:
-;CHECK: sqabs.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqabs.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqabs_16b:
-;CHECK: sqabs.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqabs.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqabs_4h:
-;CHECK: sqabs.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqabs.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqabs_8h:
-;CHECK: sqabs.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqabs.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqabs_2s:
-;CHECK: sqabs.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqabs.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sqabs_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqabs_4s:
-;CHECK: sqabs.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqabs.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqabs.v8i8(<8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.sqabs.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqabs.v4i16(<4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqabs.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqabs.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone
-
-define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: sqneg_8b:
-;CHECK: sqneg.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sqneg.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: sqneg_16b:
-;CHECK: sqneg.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sqneg.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: sqneg_4h:
-;CHECK: sqneg.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sqneg.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: sqneg_8h:
-;CHECK: sqneg.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sqneg.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: sqneg_2s:
-;CHECK: sqneg.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sqneg.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @sqneg_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: sqneg_4s:
-;CHECK: sqneg.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sqneg.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.sqneg.v8i8(<8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.sqneg.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.sqneg.v4i16(<4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.sqneg.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.sqneg.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone
-
-define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: abs_8b:
-;CHECK: abs.8b
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <8 x i8> @llvm.arm64.neon.abs.v8i8(<8 x i8> %tmp1)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: abs_16b:
-;CHECK: abs.16b
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <16 x i8> @llvm.arm64.neon.abs.v16i8(<16 x i8> %tmp1)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: abs_4h:
-;CHECK: abs.4h
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.abs.v4i16(<4 x i16> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: abs_8h:
-;CHECK: abs.8h
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.abs.v8i16(<8 x i16> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: abs_2s:
-;CHECK: abs.2s
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.abs.v2i32(<2 x i32> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @abs_4s(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: abs_4s:
-;CHECK: abs.4s
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.abs.v4i32(<4 x i32> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-define <1 x i64> @abs_1d(<1 x i64> %A) nounwind {
-; CHECK-LABEL: abs_1d:
-; CHECK: abs d0, d0
- %abs = call <1 x i64> @llvm.arm64.neon.abs.v1i64(<1 x i64> %A)
- ret <1 x i64> %abs
-}
-
-define i64 @abs_1d_honestly(i64 %A) nounwind {
-; CHECK-LABEL: abs_1d_honestly:
-; CHECK: abs d0, d0
- %abs = call i64 @llvm.arm64.neon.abs.i64(i64 %A)
- ret i64 %abs
-}
-
-declare <8 x i8> @llvm.arm64.neon.abs.v8i8(<8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.abs.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.abs.v4i16(<4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.abs.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.abs.v2i32(<2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.abs.v4i32(<4 x i32>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.abs.v1i64(<1 x i64>) nounwind readnone
-declare i64 @llvm.arm64.neon.abs.i64(i64) nounwind readnone
-
-define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: sabal8h:
-;CHECK: sabal.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = load <8 x i16>* %C
- %tmp4 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sabal4s:
-;CHECK: sabal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sabal2d:
-;CHECK: sabal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: sabal2_8h:
-;CHECK: sabal2.8h
- %load1 = load <16 x i8>* %A
- %load2 = load <16 x i8>* %B
- %tmp3 = load <8 x i16>* %C
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp4 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: sabal2_4s:
-;CHECK: sabal2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: sabal2_2d:
-;CHECK: sabal2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uabal8h:
-;CHECK: uabal.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = load <8 x i16>* %C
- %tmp4 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uabal4s:
-;CHECK: uabal.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp4 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: uabal2d:
-;CHECK: uabal.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp4 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uabal2_8h:
-;CHECK: uabal2.8h
- %load1 = load <16 x i8>* %A
- %load2 = load <16 x i8>* %B
- %tmp3 = load <8 x i16>* %C
- %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %tmp4 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4.1
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uabal2_4s:
-;CHECK: uabal2.4s
- %load1 = load <8 x i16>* %A
- %load2 = load <8 x i16>* %B
- %tmp3 = load <4 x i32>* %C
- %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %tmp4 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4.1
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
-;CHECK-LABEL: uabal2_2d:
-;CHECK: uabal2.2d
- %load1 = load <4 x i32>* %A
- %load2 = load <4 x i32>* %B
- %tmp3 = load <2 x i64>* %C
- %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %tmp4 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4.1
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: saba_8b:
-;CHECK: saba.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = load <8 x i8>* %C
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK-LABEL: saba_16b:
-;CHECK: saba.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- %tmp4 = load <16 x i8>* %C
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: saba_4h:
-;CHECK: saba.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = load <4 x i16>* %C
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: saba_8h:
-;CHECK: saba.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- %tmp4 = load <8 x i16>* %C
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: saba_2s:
-;CHECK: saba.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = load <2 x i32>* %C
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: saba_4s:
-;CHECK: saba.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- %tmp4 = load <4 x i32>* %C
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: uaba_8b:
-;CHECK: uaba.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- %tmp4 = load <8 x i8>* %C
- %tmp5 = add <8 x i8> %tmp3, %tmp4
- ret <8 x i8> %tmp5
-}
-
-define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK-LABEL: uaba_16b:
-;CHECK: uaba.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- %tmp4 = load <16 x i8>* %C
- %tmp5 = add <16 x i8> %tmp3, %tmp4
- ret <16 x i8> %tmp5
-}
-
-define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: uaba_4h:
-;CHECK: uaba.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- %tmp4 = load <4 x i16>* %C
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: uaba_8h:
-;CHECK: uaba.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- %tmp4 = load <8 x i16>* %C
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: uaba_2s:
-;CHECK: uaba.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- %tmp4 = load <2 x i32>* %C
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <4 x i32> @uaba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: uaba_4s:
-;CHECK: uaba.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- %tmp4 = load <4 x i32>* %C
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-; Scalar FABD
-define float @fabds(float %a, float %b) nounwind {
-; CHECK-LABEL: fabds:
-; CHECK: fabd s0, s0, s1
- %vabd.i = tail call float @llvm.arm64.sisd.fabd.f32(float %a, float %b) nounwind
- ret float %vabd.i
-}
-
-define double @fabdd(double %a, double %b) nounwind {
-; CHECK-LABEL: fabdd:
-; CHECK: fabd d0, d0, d1
- %vabd.i = tail call double @llvm.arm64.sisd.fabd.f64(double %a, double %b) nounwind
- ret double %vabd.i
-}
-
-declare double @llvm.arm64.sisd.fabd.f64(double, double) nounwind readnone
-declare float @llvm.arm64.sisd.fabd.f32(float, float) nounwind readnone
-
-define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: uabdl_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: uabdl2.2d
- %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
- %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %res = tail call <2 x i32> @llvm.arm64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
- %res1 = zext <2 x i32> %res to <2 x i64>
- ret <2 x i64> %res1
-}
-
-define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: sabdl_from_extract_dup:
-; CHECK-NOT: ext.16b
-; CHECK: sabdl2.2d
- %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
- %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %res = tail call <2 x i32> @llvm.arm64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
- %res1 = zext <2 x i32> %res to <2 x i64>
- ret <2 x i64> %res1
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vadd.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vadd.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vadd.ll (removed)
@@ -1,941 +0,0 @@
-; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
-
-define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: addhn8b:
-;CHECK: addhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @addhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: addhn4h:
-;CHECK: addhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @addhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: addhn2s:
-;CHECK: addhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.addhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @addhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
-;CHECK-LABEL: addhn2_16b:
-;CHECK: addhn.8b
-;CHECK-NEXT: addhn2.16b
- %vaddhn2.i = tail call <8 x i8> @llvm.arm64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %vaddhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %res = shufflevector <8 x i8> %vaddhn2.i, <8 x i8> %vaddhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @addhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
-;CHECK-LABEL: addhn2_8h:
-;CHECK: addhn.4h
-;CHECK-NEXT: addhn2.8h
- %vaddhn2.i = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %vaddhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %res = shufflevector <4 x i16> %vaddhn2.i, <4 x i16> %vaddhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @addhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
-;CHECK-LABEL: addhn2_4s:
-;CHECK: addhn.2s
-;CHECK-NEXT: addhn2.4s
- %vaddhn2.i = tail call <2 x i32> @llvm.arm64.neon.addhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %vaddhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.addhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %res = shufflevector <2 x i32> %vaddhn2.i, <2 x i32> %vaddhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <2 x i32> @llvm.arm64.neon.addhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.addhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-
-
-define <8 x i8> @raddhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: raddhn8b:
-;CHECK: raddhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @raddhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: raddhn4h:
-;CHECK: raddhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @raddhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: raddhn2s:
-;CHECK: raddhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <16 x i8> @raddhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
-;CHECK-LABEL: raddhn2_16b:
-;CHECK: raddhn.8b
-;CHECK-NEXT: raddhn2.16b
- %vraddhn2.i = tail call <8 x i8> @llvm.arm64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %vraddhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
- %res = shufflevector <8 x i8> %vraddhn2.i, <8 x i8> %vraddhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @raddhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
-;CHECK-LABEL: raddhn2_8h:
-;CHECK: raddhn.4h
-;CHECK-NEXT: raddhn2.8h
- %vraddhn2.i = tail call <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %vraddhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
- %res = shufflevector <4 x i16> %vraddhn2.i, <4 x i16> %vraddhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @raddhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
-;CHECK-LABEL: raddhn2_4s:
-;CHECK: raddhn.2s
-;CHECK-NEXT: raddhn2.4s
- %vraddhn2.i = tail call <2 x i32> @llvm.arm64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %vraddhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
- %res = shufflevector <2 x i32> %vraddhn2.i, <2 x i32> %vraddhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-declare <2 x i32> @llvm.arm64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <8 x i8> @llvm.arm64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-
-define <8 x i16> @saddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: saddl8h:
-;CHECK: saddl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @saddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: saddl4s:
-;CHECK: saddl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @saddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: saddl2d:
-;CHECK: saddl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @saddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
-; CHECK-LABEL: saddl2_8h:
-; CHECK-NEXT: saddl2.8h v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <16 x i8> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
- %vmovl.i.i.i = sext <8 x i8> %tmp1 to <8 x i16>
- %tmp2 = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <8 x i8>
- %vmovl.i.i5.i = sext <8 x i8> %tmp3 to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @saddl2_4s(<8 x i16> %a, <8 x i16> %b) nounwind {
-; CHECK-LABEL: saddl2_4s:
-; CHECK-NEXT: saddl2.4s v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <8 x i16> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
- %vmovl.i.i.i = sext <4 x i16> %tmp1 to <4 x i32>
- %tmp2 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <4 x i16>
- %vmovl.i.i5.i = sext <4 x i16> %tmp3 to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: saddl2_2d:
-; CHECK-NEXT: saddl2.2d v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <4 x i32> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
- %vmovl.i.i.i = sext <2 x i32> %tmp1 to <2 x i64>
- %tmp2 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <2 x i32>
- %vmovl.i.i5.i = sext <2 x i32> %tmp3 to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <2 x i64> %add.i
-}
-
-define <8 x i16> @uaddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uaddl8h:
-;CHECK: uaddl.8h
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uaddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uaddl4s:
-;CHECK: uaddl.4s
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uaddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uaddl2d:
-;CHECK: uaddl.2d
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-
-define <8 x i16> @uaddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
-; CHECK-LABEL: uaddl2_8h:
-; CHECK-NEXT: uaddl2.8h v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <16 x i8> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
- %vmovl.i.i.i = zext <8 x i8> %tmp1 to <8 x i16>
- %tmp2 = bitcast <16 x i8> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <8 x i8>
- %vmovl.i.i5.i = zext <8 x i8> %tmp3 to <8 x i16>
- %add.i = add <8 x i16> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <8 x i16> %add.i
-}
-
-define <4 x i32> @uaddl2_4s(<8 x i16> %a, <8 x i16> %b) nounwind {
-; CHECK-LABEL: uaddl2_4s:
-; CHECK-NEXT: uaddl2.4s v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <8 x i16> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
- %vmovl.i.i.i = zext <4 x i16> %tmp1 to <4 x i32>
- %tmp2 = bitcast <8 x i16> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <4 x i16>
- %vmovl.i.i5.i = zext <4 x i16> %tmp3 to <4 x i32>
- %add.i = add <4 x i32> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <4 x i32> %add.i
-}
-
-define <2 x i64> @uaddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind {
-; CHECK-LABEL: uaddl2_2d:
-; CHECK-NEXT: uaddl2.2d v0, v0, v1
-; CHECK-NEXT: ret
- %tmp = bitcast <4 x i32> %a to <2 x i64>
- %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
- %vmovl.i.i.i = zext <2 x i32> %tmp1 to <2 x i64>
- %tmp2 = bitcast <4 x i32> %b to <2 x i64>
- %shuffle.i.i4.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
- %tmp3 = bitcast <1 x i64> %shuffle.i.i4.i to <2 x i32>
- %vmovl.i.i5.i = zext <2 x i32> %tmp3 to <2 x i64>
- %add.i = add <2 x i64> %vmovl.i.i.i, %vmovl.i.i5.i
- ret <2 x i64> %add.i
-}
-
-define <8 x i16> @uaddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: uaddw8h:
-;CHECK: uaddw.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @uaddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uaddw4s:
-;CHECK: uaddw.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uaddw2d:
-;CHECK: uaddw.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: uaddw2_8h:
-;CHECK: uaddw2.8h
- %tmp1 = load <8 x i16>* %A
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = zext <8 x i8> %high2 to <8 x i16>
-
- %res = add <8 x i16> %tmp1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uaddw2_4s:
-;CHECK: uaddw2.4s
- %tmp1 = load <4 x i32>* %A
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = zext <4 x i16> %high2 to <4 x i32>
-
- %res = add <4 x i32> %tmp1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uaddw2_2d:
-;CHECK: uaddw2.2d
- %tmp1 = load <2 x i64>* %A
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = zext <2 x i32> %high2 to <2 x i64>
-
- %res = add <2 x i64> %tmp1, %ext2
- ret <2 x i64> %res
-}
-
-define <8 x i16> @saddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: saddw8h:
-;CHECK: saddw.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
- %tmp4 = add <8 x i16> %tmp1, %tmp3
- ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @saddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: saddw4s:
-;CHECK: saddw.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
- %tmp4 = add <4 x i32> %tmp1, %tmp3
- ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: saddw2d:
-;CHECK: saddw.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
- %tmp4 = add <2 x i64> %tmp1, %tmp3
- ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: saddw2_8h:
-;CHECK: saddw2.8h
- %tmp1 = load <8 x i16>* %A
-
- %tmp2 = load <16 x i8>* %B
- %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- %ext2 = sext <8 x i8> %high2 to <8 x i16>
-
- %res = add <8 x i16> %tmp1, %ext2
- ret <8 x i16> %res
-}
-
-define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: saddw2_4s:
-;CHECK: saddw2.4s
- %tmp1 = load <4 x i32>* %A
-
- %tmp2 = load <8 x i16>* %B
- %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
- %ext2 = sext <4 x i16> %high2 to <4 x i32>
-
- %res = add <4 x i32> %tmp1, %ext2
- ret <4 x i32> %res
-}
-
-define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: saddw2_2d:
-;CHECK: saddw2.2d
- %tmp1 = load <2 x i64>* %A
-
- %tmp2 = load <4 x i32>* %B
- %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
- %ext2 = sext <2 x i32> %high2 to <2 x i64>
-
- %res = add <2 x i64> %tmp1, %ext2
- ret <2 x i64> %res
-}
-
-define <4 x i16> @saddlp4h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: saddlp4h:
-;CHECK: saddlp.4h
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @saddlp2s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: saddlp2s:
-;CHECK: saddlp.2s
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @saddlp1d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: saddlp1d:
-;CHECK: saddlp.1d
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <1 x i64> @llvm.arm64.neon.saddlp.v1i64.v2i32(<2 x i32> %tmp1)
- ret <1 x i64> %tmp3
-}
-
-define <8 x i16> @saddlp8h(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: saddlp8h:
-;CHECK: saddlp.8h
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @saddlp4s(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: saddlp4s:
-;CHECK: saddlp.4s
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @saddlp2d(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: saddlp2d:
-;CHECK: saddlp.2d
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1)
- ret <2 x i64> %tmp3
-}
-
-declare <4 x i16> @llvm.arm64.neon.saddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.saddlp.v2i32.v4i16(<4 x i16>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.saddlp.v1i64.v2i32(<2 x i32>) nounwind readnone
-
-declare <8 x i16> @llvm.arm64.neon.saddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.saddlp.v4i32.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.saddlp.v2i64.v4i32(<4 x i32>) nounwind readnone
-
-define <4 x i16> @uaddlp4h(<8 x i8>* %A) nounwind {
-;CHECK-LABEL: uaddlp4h:
-;CHECK: uaddlp.4h
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
- ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @uaddlp2s(<4 x i16>* %A) nounwind {
-;CHECK-LABEL: uaddlp2s:
-;CHECK: uaddlp.2s
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
- ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @uaddlp1d(<2 x i32>* %A) nounwind {
-;CHECK-LABEL: uaddlp1d:
-;CHECK: uaddlp.1d
- %tmp1 = load <2 x i32>* %A
- %tmp3 = call <1 x i64> @llvm.arm64.neon.uaddlp.v1i64.v2i32(<2 x i32> %tmp1)
- ret <1 x i64> %tmp3
-}
-
-define <8 x i16> @uaddlp8h(<16 x i8>* %A) nounwind {
-;CHECK-LABEL: uaddlp8h:
-;CHECK: uaddlp.8h
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
- ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @uaddlp4s(<8 x i16>* %A) nounwind {
-;CHECK-LABEL: uaddlp4s:
-;CHECK: uaddlp.4s
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @uaddlp2d(<4 x i32>* %A) nounwind {
-;CHECK-LABEL: uaddlp2d:
-;CHECK: uaddlp.2d
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1)
- ret <2 x i64> %tmp3
-}
-
-declare <4 x i16> @llvm.arm64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.uaddlp.v2i32.v4i16(<4 x i16>) nounwind readnone
-declare <1 x i64> @llvm.arm64.neon.uaddlp.v1i64.v2i32(<2 x i32>) nounwind readnone
-
-declare <8 x i16> @llvm.arm64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.uaddlp.v4i32.v8i16(<8 x i16>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.uaddlp.v2i64.v4i32(<4 x i32>) nounwind readnone
-
-define <4 x i16> @sadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: sadalp4h:
-;CHECK: sadalp.4h
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1)
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @sadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: sadalp2s:
-;CHECK: sadalp.2s
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1)
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <8 x i16> @sadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: sadalp8h:
-;CHECK: sadalp.8h
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1)
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @sadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: sadalp4s:
-;CHECK: sadalp.4s
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1)
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @sadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: sadalp2d:
-;CHECK: sadalp.2d
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1)
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <4 x i16> @uadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: uadalp4h:
-;CHECK: uadalp.4h
- %tmp1 = load <8 x i8>* %A
- %tmp3 = call <4 x i16> @llvm.arm64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1)
- %tmp4 = load <4 x i16>* %B
- %tmp5 = add <4 x i16> %tmp3, %tmp4
- ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @uadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: uadalp2s:
-;CHECK: uadalp.2s
- %tmp1 = load <4 x i16>* %A
- %tmp3 = call <2 x i32> @llvm.arm64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1)
- %tmp4 = load <2 x i32>* %B
- %tmp5 = add <2 x i32> %tmp3, %tmp4
- ret <2 x i32> %tmp5
-}
-
-define <8 x i16> @uadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: uadalp8h:
-;CHECK: uadalp.8h
- %tmp1 = load <16 x i8>* %A
- %tmp3 = call <8 x i16> @llvm.arm64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1)
- %tmp4 = load <8 x i16>* %B
- %tmp5 = add <8 x i16> %tmp3, %tmp4
- ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @uadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: uadalp4s:
-;CHECK: uadalp.4s
- %tmp1 = load <8 x i16>* %A
- %tmp3 = call <4 x i32> @llvm.arm64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1)
- %tmp4 = load <4 x i32>* %B
- %tmp5 = add <4 x i32> %tmp3, %tmp4
- ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @uadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: uadalp2d:
-;CHECK: uadalp.2d
- %tmp1 = load <4 x i32>* %A
- %tmp3 = call <2 x i64> @llvm.arm64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1)
- %tmp4 = load <2 x i64>* %B
- %tmp5 = add <2 x i64> %tmp3, %tmp4
- ret <2 x i64> %tmp5
-}
-
-define <8 x i8> @addp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: addp_8b:
-;CHECK: addp.8b
- %tmp1 = load <8 x i8>* %A
- %tmp2 = load <8 x i8>* %B
- %tmp3 = call <8 x i8> @llvm.arm64.neon.addp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
- ret <8 x i8> %tmp3
-}
-
-define <16 x i8> @addp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: addp_16b:
-;CHECK: addp.16b
- %tmp1 = load <16 x i8>* %A
- %tmp2 = load <16 x i8>* %B
- %tmp3 = call <16 x i8> @llvm.arm64.neon.addp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
- ret <16 x i8> %tmp3
-}
-
-define <4 x i16> @addp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: addp_4h:
-;CHECK: addp.4h
- %tmp1 = load <4 x i16>* %A
- %tmp2 = load <4 x i16>* %B
- %tmp3 = call <4 x i16> @llvm.arm64.neon.addp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
- ret <4 x i16> %tmp3
-}
-
-define <8 x i16> @addp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: addp_8h:
-;CHECK: addp.8h
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %tmp3 = call <8 x i16> @llvm.arm64.neon.addp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
- ret <8 x i16> %tmp3
-}
-
-define <2 x i32> @addp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: addp_2s:
-;CHECK: addp.2s
- %tmp1 = load <2 x i32>* %A
- %tmp2 = load <2 x i32>* %B
- %tmp3 = call <2 x i32> @llvm.arm64.neon.addp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
- ret <2 x i32> %tmp3
-}
-
-define <4 x i32> @addp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: addp_4s:
-;CHECK: addp.4s
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %tmp3 = call <4 x i32> @llvm.arm64.neon.addp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
- ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @addp_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: addp_2d:
-;CHECK: addp.2d
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %tmp3 = call <2 x i64> @llvm.arm64.neon.addp.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
- ret <2 x i64> %tmp3
-}
-
-declare <8 x i8> @llvm.arm64.neon.addp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
-declare <16 x i8> @llvm.arm64.neon.addp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
-declare <4 x i16> @llvm.arm64.neon.addp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
-declare <8 x i16> @llvm.arm64.neon.addp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
-declare <2 x i32> @llvm.arm64.neon.addp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.addp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i64> @llvm.arm64.neon.addp.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <2 x float> @faddp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: faddp_2s:
-;CHECK: faddp.2s
- %tmp1 = load <2 x float>* %A
- %tmp2 = load <2 x float>* %B
- %tmp3 = call <2 x float> @llvm.arm64.neon.addp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
- ret <2 x float> %tmp3
-}
-
-define <4 x float> @faddp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: faddp_4s:
-;CHECK: faddp.4s
- %tmp1 = load <4 x float>* %A
- %tmp2 = load <4 x float>* %B
- %tmp3 = call <4 x float> @llvm.arm64.neon.addp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
- ret <4 x float> %tmp3
-}
-
-define <2 x double> @faddp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
-;CHECK-LABEL: faddp_2d:
-;CHECK: faddp.2d
- %tmp1 = load <2 x double>* %A
- %tmp2 = load <2 x double>* %B
- %tmp3 = call <2 x double> @llvm.arm64.neon.addp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
- ret <2 x double> %tmp3
-}
-
-declare <2 x float> @llvm.arm64.neon.addp.v2f32(<2 x float>, <2 x float>) nounwind readnone
-declare <4 x float> @llvm.arm64.neon.addp.v4f32(<4 x float>, <4 x float>) nounwind readnone
-declare <2 x double> @llvm.arm64.neon.addp.v2f64(<2 x double>, <2 x double>) nounwind readnone
-
-define <2 x i64> @uaddl2_duprhs(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: uaddl2_duprhs
-; CHECK-NOT: ext.16b
-; CHECK: uaddl2.2d
- %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
- %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>
- %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>
-
- %res = add <2 x i64> %lhs.ext, %rhs.ext
- ret <2 x i64> %res
-}
-
-define <2 x i64> @saddl2_duplhs(i32 %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: saddl2_duplhs
-; CHECK-NOT: ext.16b
-; CHECK: saddl2.2d
- %lhsvec.tmp = insertelement <2 x i32> undef, i32 %lhs, i32 0
- %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 1
-
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>
- %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>
-
- %res = add <2 x i64> %lhs.ext, %rhs.ext
- ret <2 x i64> %res
-}
-
-define <2 x i64> @usubl2_duprhs(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: usubl2_duprhs
-; CHECK-NOT: ext.16b
-; CHECK: usubl2.2d
- %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
- %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
- %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>
- %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>
-
- %res = sub <2 x i64> %lhs.ext, %rhs.ext
- ret <2 x i64> %res
-}
-
-define <2 x i64> @ssubl2_duplhs(i32 %lhs, <4 x i32> %rhs) {
-; CHECK-LABEL: ssubl2_duplhs
-; CHECK-NOT: ext.16b
-; CHECK: ssubl2.2d
- %lhsvec.tmp = insertelement <2 x i32> undef, i32 %lhs, i32 0
- %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 1
-
- %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
- %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>
- %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>
-
- %res = sub <2 x i64> %lhs.ext, %rhs.ext
- ret <2 x i64> %res
-}
-
-define <8 x i8> @addhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: addhn8b_natural:
-;CHECK: addhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %sum = add <8 x i16> %tmp1, %tmp2
- %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
- ret <8 x i8> %narrowed
-}
-
-define <4 x i16> @addhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: addhn4h_natural:
-;CHECK: addhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %sum = add <4 x i32> %tmp1, %tmp2
- %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
- %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
- ret <4 x i16> %narrowed
-}
-
-define <2 x i32> @addhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: addhn2s_natural:
-;CHECK: addhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %sum = add <2 x i64> %tmp1, %tmp2
- %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>
- %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
- ret <2 x i32> %narrowed
-}
-
-define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: addhn2_16b_natural:
-;CHECK: addhn2.16b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %sum = add <8 x i16> %tmp1, %tmp2
- %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
- %res = shufflevector <8 x i8> %low, <8 x i8> %narrowed, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: addhn2_8h_natural:
-;CHECK: addhn2.8h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %sum = add <4 x i32> %tmp1, %tmp2
- %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
- %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
- %res = shufflevector <4 x i16> %low, <4 x i16> %narrowed, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: addhn2_4s_natural:
-;CHECK: addhn2.4s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %sum = add <2 x i64> %tmp1, %tmp2
- %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>
- %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
- %res = shufflevector <2 x i32> %low, <2 x i32> %narrowed, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
-
-define <8 x i8> @subhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: subhn8b_natural:
-;CHECK: subhn.8b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %diff = sub <8 x i16> %tmp1, %tmp2
- %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
- ret <8 x i8> %narrowed
-}
-
-define <4 x i16> @subhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: subhn4h_natural:
-;CHECK: subhn.4h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %diff = sub <4 x i32> %tmp1, %tmp2
- %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>
- %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
- ret <4 x i16> %narrowed
-}
-
-define <2 x i32> @subhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: subhn2s_natural:
-;CHECK: subhn.2s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %diff = sub <2 x i64> %tmp1, %tmp2
- %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>
- %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
- ret <2 x i32> %narrowed
-}
-
-define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: subhn2_16b_natural:
-;CHECK: subhn2.16b
- %tmp1 = load <8 x i16>* %A
- %tmp2 = load <8 x i16>* %B
- %diff = sub <8 x i16> %tmp1, %tmp2
- %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
- %narrowed = trunc <8 x i16> %high_bits to <8 x i8>
- %res = shufflevector <8 x i8> %low, <8 x i8> %narrowed, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %res
-}
-
-define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: subhn2_8h_natural:
-;CHECK: subhn2.8h
- %tmp1 = load <4 x i32>* %A
- %tmp2 = load <4 x i32>* %B
- %diff = sub <4 x i32> %tmp1, %tmp2
- %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>
- %narrowed = trunc <4 x i32> %high_bits to <4 x i16>
- %res = shufflevector <4 x i16> %low, <4 x i16> %narrowed, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %res
-}
-
-define <4 x i32> @subhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: subhn2_4s_natural:
-;CHECK: subhn2.4s
- %tmp1 = load <2 x i64>* %A
- %tmp2 = load <2 x i64>* %B
- %diff = sub <2 x i64> %tmp1, %tmp2
- %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>
- %narrowed = trunc <2 x i64> %high_bits to <2 x i32>
- %res = shufflevector <2 x i32> %low, <2 x i32> %narrowed, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %res
-}
Removed: llvm/trunk/test/CodeGen/ARM64/vaddlv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vaddlv.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vaddlv.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vaddlv.ll (removed)
@@ -1,26 +0,0 @@
-; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
-
-define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone {
-; CHECK: test_vaddlv_s32
-; CHECK: saddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
-; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddlv.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
- ret i64 %vaddlv.i
-}
-
-define i64 @test_vaddlv_u32(<2 x i32> %a1) nounwind readnone {
-; CHECK: test_vaddlv_u32
-; CHECK: uaddlp.1d v[[REGNUM:[0-9]+]], v[[INREG:[0-9]+]]
-; CHECK-NEXT: fmov x[[OUTREG:[0-9]+]], d[[REGNUM]]
-; CHECK-NEXT: ret
-entry:
- %vaddlv.i = tail call i64 @llvm.arm64.neon.uaddlv.i64.v2i32(<2 x i32> %a1) nounwind
- ret i64 %vaddlv.i
-}
-
-declare i64 @llvm.arm64.neon.uaddlv.i64.v2i32(<2 x i32>) nounwind readnone
-
-declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone
-
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