[llvm] r209577 - AArch64/ARM64: move ARM64 into AArch64's place
Tim Northover
tnorthover at apple.com
Sat May 24 05:50:31 PDT 2014
Removed: llvm/trunk/test/MC/ARM64/simd-ldst.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/simd-ldst.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/simd-ldst.s (original)
+++ llvm/trunk/test/MC/ARM64/simd-ldst.s (removed)
@@ -1,2404 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s
-
-_ld1st1_multiple:
- ld1.8b {v0}, [x1]
- ld1.8b {v0, v1}, [x1]
- ld1.8b {v0, v1, v2}, [x1]
- ld1.8b {v0, v1, v2, v3}, [x1]
-
- ld1.8b {v3}, [x1]
- ld1.8b {v3, v4}, [x2]
- ld1.8b {v4, v5, v6}, [x3]
- ld1.8b {v7, v8, v9, v10}, [x4]
-
- ld1.16b {v0}, [x1]
- ld1.16b {v0, v1}, [x1]
- ld1.16b {v0, v1, v2}, [x1]
- ld1.16b {v0, v1, v2, v3}, [x1]
-
- ld1.4h {v0}, [x1]
- ld1.4h {v0, v1}, [x1]
- ld1.4h {v0, v1, v2}, [x1]
- ld1.4h {v0, v1, v2, v3}, [x1]
-
- ld1.8h {v0}, [x1]
- ld1.8h {v0, v1}, [x1]
- ld1.8h {v0, v1, v2}, [x1]
- ld1.8h {v0, v1, v2, v3}, [x1]
-
- ld1.2s {v0}, [x1]
- ld1.2s {v0, v1}, [x1]
- ld1.2s {v0, v1, v2}, [x1]
- ld1.2s {v0, v1, v2, v3}, [x1]
-
- ld1.4s {v0}, [x1]
- ld1.4s {v0, v1}, [x1]
- ld1.4s {v0, v1, v2}, [x1]
- ld1.4s {v0, v1, v2, v3}, [x1]
-
- ld1.1d {v0}, [x1]
- ld1.1d {v0, v1}, [x1]
- ld1.1d {v0, v1, v2}, [x1]
- ld1.1d {v0, v1, v2, v3}, [x1]
-
- ld1.2d {v0}, [x1]
- ld1.2d {v0, v1}, [x1]
- ld1.2d {v0, v1, v2}, [x1]
- ld1.2d {v0, v1, v2, v3}, [x1]
-
- st1.8b {v0}, [x1]
- st1.8b {v0, v1}, [x1]
- st1.8b {v0, v1, v2}, [x1]
- st1.8b {v0, v1, v2, v3}, [x1]
-
- st1.16b {v0}, [x1]
- st1.16b {v0, v1}, [x1]
- st1.16b {v0, v1, v2}, [x1]
- st1.16b {v0, v1, v2, v3}, [x1]
-
- st1.4h {v0}, [x1]
- st1.4h {v0, v1}, [x1]
- st1.4h {v0, v1, v2}, [x1]
- st1.4h {v0, v1, v2, v3}, [x1]
-
- st1.8h {v0}, [x1]
- st1.8h {v0, v1}, [x1]
- st1.8h {v0, v1, v2}, [x1]
- st1.8h {v0, v1, v2, v3}, [x1]
-
- st1.2s {v0}, [x1]
- st1.2s {v0, v1}, [x1]
- st1.2s {v0, v1, v2}, [x1]
- st1.2s {v0, v1, v2, v3}, [x1]
-
- st1.4s {v0}, [x1]
- st1.4s {v0, v1}, [x1]
- st1.4s {v0, v1, v2}, [x1]
- st1.4s {v0, v1, v2, v3}, [x1]
-
- st1.1d {v0}, [x1]
- st1.1d {v0, v1}, [x1]
- st1.1d {v0, v1, v2}, [x1]
- st1.1d {v0, v1, v2, v3}, [x1]
-
- st1.2d {v0}, [x1]
- st1.2d {v0, v1}, [x1]
- st1.2d {v0, v1, v2}, [x1]
- st1.2d {v0, v1, v2, v3}, [x1]
-
- st1.2d {v5}, [x1]
- st1.2d {v7, v8}, [x10]
- st1.2d {v11, v12, v13}, [x1]
- st1.2d {v28, v29, v30, v31}, [x13]
-
-; CHECK: _ld1st1_multiple:
-; CHECK: ld1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x0c]
-; CHECK: ld1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x0c]
-; CHECK: ld1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x0c]
-; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x0c]
-
-; CHECK: ld1.8b { v3 }, [x1] ; encoding: [0x23,0x70,0x40,0x0c]
-; CHECK: ld1.8b { v3, v4 }, [x2] ; encoding: [0x43,0xa0,0x40,0x0c]
-; CHECK: ld1.8b { v4, v5, v6 }, [x3] ; encoding: [0x64,0x60,0x40,0x0c]
-; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
-
-; CHECK: ld1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x4c]
-; CHECK: ld1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x4c]
-; CHECK: ld1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x4c]
-; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x4c]
-
-; CHECK: ld1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x0c]
-; CHECK: ld1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x0c]
-; CHECK: ld1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x0c]
-; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x0c]
-
-; CHECK: ld1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x4c]
-; CHECK: ld1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x4c]
-; CHECK: ld1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x4c]
-; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x4c]
-
-; CHECK: ld1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x0c]
-; CHECK: ld1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x0c]
-; CHECK: ld1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x0c]
-; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x0c]
-
-; CHECK: ld1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x4c]
-; CHECK: ld1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x4c]
-; CHECK: ld1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x4c]
-; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x4c]
-
-; CHECK: ld1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x0c]
-; CHECK: ld1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x0c]
-; CHECK: ld1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x0c]
-; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x0c]
-
-; CHECK: ld1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x4c]
-; CHECK: ld1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x4c]
-; CHECK: ld1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x4c]
-; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x4c]
-
-
-; CHECK: st1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x0c]
-; CHECK: st1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x0c]
-; CHECK: st1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x0c]
-; CHECK: st1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x0c]
-
-; CHECK: st1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x4c]
-; CHECK: st1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x4c]
-; CHECK: st1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x4c]
-; CHECK: st1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x4c]
-
-; CHECK: st1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x0c]
-; CHECK: st1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x0c]
-; CHECK: st1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x0c]
-; CHECK: st1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x0c]
-
-; CHECK: st1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x4c]
-; CHECK: st1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x4c]
-; CHECK: st1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x4c]
-; CHECK: st1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x4c]
-
-; CHECK: st1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x0c]
-; CHECK: st1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x0c]
-; CHECK: st1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x0c]
-; CHECK: st1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x0c]
-
-; CHECK: st1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x4c]
-; CHECK: st1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x4c]
-; CHECK: st1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x4c]
-; CHECK: st1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x4c]
-
-; CHECK: st1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x0c]
-; CHECK: st1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x0c]
-; CHECK: st1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x0c]
-; CHECK: st1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x0c]
-
-; CHECK: st1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x4c]
-; CHECK: st1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x4c]
-; CHECK: st1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x4c]
-; CHECK: st1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x4c]
-
-; CHECK: st1.2d { v5 }, [x1] ; encoding: [0x25,0x7c,0x00,0x4c]
-; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c]
-; CHECK: st1.2d { v11, v12, v13 }, [x1] ; encoding: [0x2b,0x6c,0x00,0x4c]
-; CHECK: st1.2d { v28, v29, v30, v31 }, [x13] ; encoding: [0xbc,0x2d,0x00,0x4c]
-
-_ld2st2_multiple:
- ld2.8b {v4, v5}, [x19]
- ld2.16b {v4, v5}, [x19]
- ld2.4h {v4, v5}, [x19]
- ld2.8h {v4, v5}, [x19]
- ld2.2s {v4, v5}, [x19]
- ld2.4s {v4, v5}, [x19]
- ld2.2d {v4, v5}, [x19]
-
- st2.8b {v4, v5}, [x19]
- st2.16b {v4, v5}, [x19]
- st2.4h {v4, v5}, [x19]
- st2.8h {v4, v5}, [x19]
- st2.2s {v4, v5}, [x19]
- st2.4s {v4, v5}, [x19]
- st2.2d {v4, v5}, [x19]
-
-
-; CHECK: _ld2st2_multiple
-; CHECK: ld2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x0c]
-; CHECK: ld2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x4c]
-; CHECK: ld2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x0c]
-; CHECK: ld2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x4c]
-; CHECK: ld2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x0c]
-; CHECK: ld2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x4c]
-; CHECK: ld2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x40,0x4c]
-
-; CHECK: st2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x0c]
-; CHECK: st2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x4c]
-; CHECK: st2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x0c]
-; CHECK: st2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x4c]
-; CHECK: st2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x0c]
-; CHECK: st2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x4c]
-; CHECK: st2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x00,0x4c]
-
-
-ld3st3_multiple:
- ld3.8b {v4, v5, v6}, [x19]
- ld3.16b {v4, v5, v6}, [x19]
- ld3.4h {v4, v5, v6}, [x19]
- ld3.8h {v4, v5, v6}, [x19]
- ld3.2s {v4, v5, v6}, [x19]
- ld3.4s {v4, v5, v6}, [x19]
- ld3.2d {v4, v5, v6}, [x19]
-
- ld3.8b {v9, v10, v11}, [x9]
- ld3.16b {v14, v15, v16}, [x19]
- ld3.4h {v24, v25, v26}, [x29]
- ld3.8h {v30, v31, v0}, [x9]
- ld3.2s {v2, v3, v4}, [x19]
- ld3.4s {v4, v5, v6}, [x29]
- ld3.2d {v7, v8, v9}, [x9]
-
- st3.8b {v4, v5, v6}, [x19]
- st3.16b {v4, v5, v6}, [x19]
- st3.4h {v4, v5, v6}, [x19]
- st3.8h {v4, v5, v6}, [x19]
- st3.2s {v4, v5, v6}, [x19]
- st3.4s {v4, v5, v6}, [x19]
- st3.2d {v4, v5, v6}, [x19]
-
- st3.8b {v10, v11, v12}, [x9]
- st3.16b {v14, v15, v16}, [x19]
- st3.4h {v24, v25, v26}, [x29]
- st3.8h {v30, v31, v0}, [x9]
- st3.2s {v2, v3, v4}, [x19]
- st3.4s {v7, v8, v9}, [x29]
- st3.2d {v4, v5, v6}, [x9]
-
-; CHECK: ld3st3_multiple:
-; CHECK: ld3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x0c]
-; CHECK: ld3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x0c]
-; CHECK: ld3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x4c]
-; CHECK: ld3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x4c]
-; CHECK: ld3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x40,0x4c]
-
-; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
-; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c]
-; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c]
-; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c]
-; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
-
-; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c]
-; CHECK: st3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x4c]
-; CHECK: st3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x0c]
-; CHECK: st3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x4c]
-; CHECK: st3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x4c]
-; CHECK: st3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x00,0x4c]
-
-; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c]
-; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c]
-; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c]
-; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c]
-; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
-; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c]
-
-ld4st4_multiple:
- ld4.8b {v4, v5, v6, v7}, [x19]
- ld4.16b {v4, v5, v6, v7}, [x19]
- ld4.4h {v4, v5, v6, v7}, [x19]
- ld4.8h {v4, v5, v6, v7}, [x19]
- ld4.2s {v4, v5, v6, v7}, [x19]
- ld4.4s {v4, v5, v6, v7}, [x19]
- ld4.2d {v4, v5, v6, v7}, [x19]
-
- st4.8b {v4, v5, v6, v7}, [x19]
- st4.16b {v4, v5, v6, v7}, [x19]
- st4.4h {v4, v5, v6, v7}, [x19]
- st4.8h {v4, v5, v6, v7}, [x19]
- st4.2s {v4, v5, v6, v7}, [x19]
- st4.4s {v4, v5, v6, v7}, [x19]
- st4.2d {v4, v5, v6, v7}, [x19]
-
-; CHECK: ld4st4_multiple:
-; CHECK: ld4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x0c]
-; CHECK: ld4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x4c]
-; CHECK: ld4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x0c]
-; CHECK: ld4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x4c]
-; CHECK: ld4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x0c]
-; CHECK: ld4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x4c]
-; CHECK: ld4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x40,0x4c]
-
-; CHECK: st4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x0c]
-; CHECK: st4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x4c]
-; CHECK: st4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x0c]
-; CHECK: st4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x4c]
-; CHECK: st4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x0c]
-; CHECK: st4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x4c]
-; CHECK: st4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x00,0x4c]
-
-;-----------------------------------------------------------------------------
-; Post-increment versions.
-;-----------------------------------------------------------------------------
-
-_ld1st1_multiple_post:
- ld1.8b {v0}, [x1], x15
- ld1.8b {v0, v1}, [x1], x15
- ld1.8b {v0, v1, v2}, [x1], x15
- ld1.8b {v0, v1, v2, v3}, [x1], x15
-
- ld1.16b {v0}, [x1], x15
- ld1.16b {v0, v1}, [x1], x15
- ld1.16b {v0, v1, v2}, [x1], x15
- ld1.16b {v0, v1, v2, v3}, [x1], x15
-
- ld1.4h {v0}, [x1], x15
- ld1.4h {v0, v1}, [x1], x15
- ld1.4h {v0, v1, v2}, [x1], x15
- ld1.4h {v0, v1, v2, v3}, [x1], x15
-
- ld1.8h {v0}, [x1], x15
- ld1.8h {v0, v1}, [x1], x15
- ld1.8h {v0, v1, v2}, [x1], x15
- ld1.8h {v0, v1, v2, v3}, [x1], x15
-
- ld1.2s {v0}, [x1], x15
- ld1.2s {v0, v1}, [x1], x15
- ld1.2s {v0, v1, v2}, [x1], x15
- ld1.2s {v0, v1, v2, v3}, [x1], x15
-
- ld1.4s {v0}, [x1], x15
- ld1.4s {v0, v1}, [x1], x15
- ld1.4s {v0, v1, v2}, [x1], x15
- ld1.4s {v0, v1, v2, v3}, [x1], x15
-
- ld1.1d {v0}, [x1], x15
- ld1.1d {v0, v1}, [x1], x15
- ld1.1d {v0, v1, v2}, [x1], x15
- ld1.1d {v0, v1, v2, v3}, [x1], x15
-
- ld1.2d {v0}, [x1], x15
- ld1.2d {v0, v1}, [x1], x15
- ld1.2d {v0, v1, v2}, [x1], x15
- ld1.2d {v0, v1, v2, v3}, [x1], x15
-
- st1.8b {v0}, [x1], x15
- st1.8b {v0, v1}, [x1], x15
- st1.8b {v0, v1, v2}, [x1], x15
- st1.8b {v0, v1, v2, v3}, [x1], x15
-
- st1.16b {v0}, [x1], x15
- st1.16b {v0, v1}, [x1], x15
- st1.16b {v0, v1, v2}, [x1], x15
- st1.16b {v0, v1, v2, v3}, [x1], x15
-
- st1.4h {v0}, [x1], x15
- st1.4h {v0, v1}, [x1], x15
- st1.4h {v0, v1, v2}, [x1], x15
- st1.4h {v0, v1, v2, v3}, [x1], x15
-
- st1.8h {v0}, [x1], x15
- st1.8h {v0, v1}, [x1], x15
- st1.8h {v0, v1, v2}, [x1], x15
- st1.8h {v0, v1, v2, v3}, [x1], x15
-
- st1.2s {v0}, [x1], x15
- st1.2s {v0, v1}, [x1], x15
- st1.2s {v0, v1, v2}, [x1], x15
- st1.2s {v0, v1, v2, v3}, [x1], x15
-
- st1.4s {v0}, [x1], x15
- st1.4s {v0, v1}, [x1], x15
- st1.4s {v0, v1, v2}, [x1], x15
- st1.4s {v0, v1, v2, v3}, [x1], x15
-
- st1.1d {v0}, [x1], x15
- st1.1d {v0, v1}, [x1], x15
- st1.1d {v0, v1, v2}, [x1], x15
- st1.1d {v0, v1, v2, v3}, [x1], x15
-
- st1.2d {v0}, [x1], x15
- st1.2d {v0, v1}, [x1], x15
- st1.2d {v0, v1, v2}, [x1], x15
- st1.2d {v0, v1, v2, v3}, [x1], x15
-
- ld1.8b {v0}, [x1], #8
- ld1.8b {v0, v1}, [x1], #16
- ld1.8b {v0, v1, v2}, [x1], #24
- ld1.8b {v0, v1, v2, v3}, [x1], #32
-
- ld1.16b {v0}, [x1], #16
- ld1.16b {v0, v1}, [x1], #32
- ld1.16b {v0, v1, v2}, [x1], #48
- ld1.16b {v0, v1, v2, v3}, [x1], #64
-
- ld1.4h {v0}, [x1], #8
- ld1.4h {v0, v1}, [x1], #16
- ld1.4h {v0, v1, v2}, [x1], #24
- ld1.4h {v0, v1, v2, v3}, [x1], #32
-
- ld1.8h {v0}, [x1], #16
- ld1.8h {v0, v1}, [x1], #32
- ld1.8h {v0, v1, v2}, [x1], #48
- ld1.8h {v0, v1, v2, v3}, [x1], #64
-
- ld1.2s {v0}, [x1], #8
- ld1.2s {v0, v1}, [x1], #16
- ld1.2s {v0, v1, v2}, [x1], #24
- ld1.2s {v0, v1, v2, v3}, [x1], #32
-
- ld1.4s {v0}, [x1], #16
- ld1.4s {v0, v1}, [x1], #32
- ld1.4s {v0, v1, v2}, [x1], #48
- ld1.4s {v0, v1, v2, v3}, [x1], #64
-
- ld1.1d {v0}, [x1], #8
- ld1.1d {v0, v1}, [x1], #16
- ld1.1d {v0, v1, v2}, [x1], #24
- ld1.1d {v0, v1, v2, v3}, [x1], #32
-
- ld1.2d {v0}, [x1], #16
- ld1.2d {v0, v1}, [x1], #32
- ld1.2d {v0, v1, v2}, [x1], #48
- ld1.2d {v0, v1, v2, v3}, [x1], #64
-
- st1.8b {v0}, [x1], #8
- st1.8b {v0, v1}, [x1], #16
- st1.8b {v0, v1, v2}, [x1], #24
- st1.8b {v0, v1, v2, v3}, [x1], #32
-
- st1.16b {v0}, [x1], #16
- st1.16b {v0, v1}, [x1], #32
- st1.16b {v0, v1, v2}, [x1], #48
- st1.16b {v0, v1, v2, v3}, [x1], #64
-
- st1.4h {v0}, [x1], #8
- st1.4h {v0, v1}, [x1], #16
- st1.4h {v0, v1, v2}, [x1], #24
- st1.4h {v0, v1, v2, v3}, [x1], #32
-
- st1.8h {v0}, [x1], #16
- st1.8h {v0, v1}, [x1], #32
- st1.8h {v0, v1, v2}, [x1], #48
- st1.8h {v0, v1, v2, v3}, [x1], #64
-
- st1.2s {v0}, [x1], #8
- st1.2s {v0, v1}, [x1], #16
- st1.2s {v0, v1, v2}, [x1], #24
- st1.2s {v0, v1, v2, v3}, [x1], #32
-
- st1.4s {v0}, [x1], #16
- st1.4s {v0, v1}, [x1], #32
- st1.4s {v0, v1, v2}, [x1], #48
- st1.4s {v0, v1, v2, v3}, [x1], #64
-
- st1.1d {v0}, [x1], #8
- st1.1d {v0, v1}, [x1], #16
- st1.1d {v0, v1, v2}, [x1], #24
- st1.1d {v0, v1, v2, v3}, [x1], #32
-
- st1.2d {v0}, [x1], #16
- st1.2d {v0, v1}, [x1], #32
- st1.2d {v0, v1, v2}, [x1], #48
- st1.2d {v0, v1, v2, v3}, [x1], #64
-
-; CHECK: ld1st1_multiple_post:
-; CHECK: ld1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x0c]
-; CHECK: ld1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x0c]
-; CHECK: ld1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x0c]
-; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x0c]
-
-; CHECK: ld1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x4c]
-; CHECK: ld1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x4c]
-; CHECK: ld1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x4c]
-; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x4c]
-
-; CHECK: ld1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x0c]
-; CHECK: ld1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x0c]
-; CHECK: ld1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x0c]
-; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x0c]
-
-; CHECK: ld1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x4c]
-; CHECK: ld1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x4c]
-; CHECK: ld1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x4c]
-; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x4c]
-
-; CHECK: ld1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x0c]
-; CHECK: ld1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x0c]
-; CHECK: ld1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x0c]
-; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x0c]
-
-; CHECK: ld1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x4c]
-; CHECK: ld1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x4c]
-; CHECK: ld1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x4c]
-; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x4c]
-
-; CHECK: ld1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x0c]
-; CHECK: ld1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x0c]
-; CHECK: ld1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x0c]
-; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x0c]
-
-; CHECK: ld1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x4c]
-; CHECK: ld1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x4c]
-; CHECK: ld1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x4c]
-; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x4c]
-
-; CHECK: st1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x0c]
-; CHECK: st1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x0c]
-; CHECK: st1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x0c]
-; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x0c]
-
-; CHECK: st1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x4c]
-; CHECK: st1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x4c]
-; CHECK: st1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x4c]
-; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x4c]
-
-; CHECK: st1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x0c]
-; CHECK: st1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x0c]
-; CHECK: st1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x0c]
-; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x0c]
-
-; CHECK: st1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x4c]
-; CHECK: st1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x4c]
-; CHECK: st1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x4c]
-; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x4c]
-
-; CHECK: st1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x0c]
-; CHECK: st1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x0c]
-; CHECK: st1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x0c]
-; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x0c]
-
-; CHECK: st1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x4c]
-; CHECK: st1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x4c]
-; CHECK: st1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x4c]
-; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x4c]
-
-; CHECK: st1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x0c]
-; CHECK: st1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x0c]
-; CHECK: st1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x0c]
-; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x0c]
-
-; CHECK: st1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x4c]
-; CHECK: st1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x4c]
-; CHECK: st1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x4c]
-; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x4c]
-
-; CHECK: ld1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0xdf,0x0c]
-; CHECK: ld1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0xdf,0x0c]
-; CHECK: ld1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0xdf,0x0c]
-; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0xdf,0x0c]
-
-; CHECK: ld1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0xdf,0x4c]
-; CHECK: ld1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0xdf,0x4c]
-; CHECK: ld1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0xdf,0x4c]
-; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0xdf,0x4c]
-
-; CHECK: ld1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0xdf,0x0c]
-; CHECK: ld1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0xdf,0x0c]
-; CHECK: ld1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0xdf,0x0c]
-; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0xdf,0x0c]
-
-; CHECK: ld1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0xdf,0x4c]
-; CHECK: ld1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0xdf,0x4c]
-; CHECK: ld1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0xdf,0x4c]
-; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0xdf,0x4c]
-
-; CHECK: ld1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0xdf,0x0c]
-; CHECK: ld1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0xdf,0x0c]
-; CHECK: ld1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0xdf,0x0c]
-; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0xdf,0x0c]
-
-; CHECK: ld1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0xdf,0x4c]
-; CHECK: ld1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0xdf,0x4c]
-; CHECK: ld1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0xdf,0x4c]
-; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0xdf,0x4c]
-
-; CHECK: ld1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0xdf,0x0c]
-; CHECK: ld1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0xdf,0x0c]
-; CHECK: ld1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0xdf,0x0c]
-; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0xdf,0x0c]
-
-; CHECK: ld1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0xdf,0x4c]
-; CHECK: ld1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0xdf,0x4c]
-; CHECK: ld1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0xdf,0x4c]
-; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0xdf,0x4c]
-
-; CHECK: st1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0x9f,0x0c]
-; CHECK: st1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0x9f,0x0c]
-; CHECK: st1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0x9f,0x0c]
-; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0x9f,0x0c]
-
-; CHECK: st1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0x9f,0x4c]
-; CHECK: st1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0x9f,0x4c]
-; CHECK: st1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0x9f,0x4c]
-; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0x9f,0x4c]
-
-; CHECK: st1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0x9f,0x0c]
-; CHECK: st1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0x9f,0x0c]
-; CHECK: st1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0x9f,0x0c]
-; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0x9f,0x0c]
-
-; CHECK: st1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0x9f,0x4c]
-; CHECK: st1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0x9f,0x4c]
-; CHECK: st1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0x9f,0x4c]
-; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0x9f,0x4c]
-
-; CHECK: st1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0x9f,0x0c]
-; CHECK: st1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0x9f,0x0c]
-; CHECK: st1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0x9f,0x0c]
-; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0x9f,0x0c]
-
-; CHECK: st1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0x9f,0x4c]
-; CHECK: st1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0x9f,0x4c]
-; CHECK: st1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0x9f,0x4c]
-; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0x9f,0x4c]
-
-; CHECK: st1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0x9f,0x0c]
-; CHECK: st1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0x9f,0x0c]
-; CHECK: st1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0x9f,0x0c]
-; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0x9f,0x0c]
-
-; CHECK: st1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0x9f,0x4c]
-; CHECK: st1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0x9f,0x4c]
-; CHECK: st1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0x9f,0x4c]
-; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0x9f,0x4c]
-
-
-_ld2st2_multiple_post:
- ld2.8b {v0, v1}, [x1], x15
- ld2.16b {v0, v1}, [x1], x15
- ld2.4h {v0, v1}, [x1], x15
- ld2.8h {v0, v1}, [x1], x15
- ld2.2s {v0, v1}, [x1], x15
- ld2.4s {v0, v1}, [x1], x15
- ld2.2d {v0, v1}, [x1], x15
-
- st2.8b {v0, v1}, [x1], x15
- st2.16b {v0, v1}, [x1], x15
- st2.4h {v0, v1}, [x1], x15
- st2.8h {v0, v1}, [x1], x15
- st2.2s {v0, v1}, [x1], x15
- st2.4s {v0, v1}, [x1], x15
- st2.2d {v0, v1}, [x1], x15
-
- ld2.8b {v0, v1}, [x1], #16
- ld2.16b {v0, v1}, [x1], #32
- ld2.4h {v0, v1}, [x1], #16
- ld2.8h {v0, v1}, [x1], #32
- ld2.2s {v0, v1}, [x1], #16
- ld2.4s {v0, v1}, [x1], #32
- ld2.2d {v0, v1}, [x1], #32
-
- st2.8b {v0, v1}, [x1], #16
- st2.16b {v0, v1}, [x1], #32
- st2.4h {v0, v1}, [x1], #16
- st2.8h {v0, v1}, [x1], #32
- st2.2s {v0, v1}, [x1], #16
- st2.4s {v0, v1}, [x1], #32
- st2.2d {v0, v1}, [x1], #32
-
-
-; CHECK: ld2st2_multiple_post:
-; CHECK: ld2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x0c]
-; CHECK: ld2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x4c]
-; CHECK: ld2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x0c]
-; CHECK: ld2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x4c]
-; CHECK: ld2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x0c]
-; CHECK: ld2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x4c]
-; CHECK: ld2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0xcf,0x4c]
-
-; CHECK: st2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x0c]
-; CHECK: st2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x4c]
-; CHECK: st2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x0c]
-; CHECK: st2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x4c]
-; CHECK: st2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x0c]
-; CHECK: st2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x4c]
-; CHECK: st2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0x8f,0x4c]
-
-; CHECK: ld2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0xdf,0x0c]
-; CHECK: ld2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0xdf,0x4c]
-; CHECK: ld2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0xdf,0x0c]
-; CHECK: ld2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0xdf,0x4c]
-; CHECK: ld2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0xdf,0x0c]
-; CHECK: ld2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0xdf,0x4c]
-; CHECK: ld2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0xdf,0x4c]
-
-; CHECK: st2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0x9f,0x0c]
-; CHECK: st2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0x9f,0x4c]
-; CHECK: st2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0x9f,0x0c]
-; CHECK: st2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0x9f,0x4c]
-; CHECK: st2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0x9f,0x0c]
-; CHECK: st2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0x9f,0x4c]
-; CHECK: st2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0x9f,0x4c]
-
-
-_ld3st3_multiple_post:
- ld3.8b {v0, v1, v2}, [x1], x15
- ld3.16b {v0, v1, v2}, [x1], x15
- ld3.4h {v0, v1, v2}, [x1], x15
- ld3.8h {v0, v1, v2}, [x1], x15
- ld3.2s {v0, v1, v2}, [x1], x15
- ld3.4s {v0, v1, v2}, [x1], x15
- ld3.2d {v0, v1, v2}, [x1], x15
-
- st3.8b {v0, v1, v2}, [x1], x15
- st3.16b {v0, v1, v2}, [x1], x15
- st3.4h {v0, v1, v2}, [x1], x15
- st3.8h {v0, v1, v2}, [x1], x15
- st3.2s {v0, v1, v2}, [x1], x15
- st3.4s {v0, v1, v2}, [x1], x15
- st3.2d {v0, v1, v2}, [x1], x15
-
- ld3.8b {v0, v1, v2}, [x1], #24
- ld3.16b {v0, v1, v2}, [x1], #48
- ld3.4h {v0, v1, v2}, [x1], #24
- ld3.8h {v0, v1, v2}, [x1], #48
- ld3.2s {v0, v1, v2}, [x1], #24
- ld3.4s {v0, v1, v2}, [x1], #48
- ld3.2d {v0, v1, v2}, [x1], #48
-
- st3.8b {v0, v1, v2}, [x1], #24
- st3.16b {v0, v1, v2}, [x1], #48
- st3.4h {v0, v1, v2}, [x1], #24
- st3.8h {v0, v1, v2}, [x1], #48
- st3.2s {v0, v1, v2}, [x1], #24
- st3.4s {v0, v1, v2}, [x1], #48
- st3.2d {v0, v1, v2}, [x1], #48
-
-; CHECK: ld3st3_multiple_post:
-; CHECK: ld3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x0c]
-; CHECK: ld3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x4c]
-; CHECK: ld3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x0c]
-; CHECK: ld3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x4c]
-; CHECK: ld3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x0c]
-; CHECK: ld3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x4c]
-; CHECK: ld3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0xcf,0x4c]
-
-; CHECK: st3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x0c]
-; CHECK: st3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x4c]
-; CHECK: st3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x0c]
-; CHECK: st3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x4c]
-; CHECK: st3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x0c]
-; CHECK: st3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x4c]
-; CHECK: st3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0x8f,0x4c]
-
-; CHECK: ld3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0xdf,0x0c]
-; CHECK: ld3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0xdf,0x4c]
-; CHECK: ld3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0xdf,0x0c]
-; CHECK: ld3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0xdf,0x4c]
-; CHECK: ld3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0xdf,0x0c]
-; CHECK: ld3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0xdf,0x4c]
-; CHECK: ld3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0xdf,0x4c]
-
-; CHECK: st3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0x9f,0x0c]
-; CHECK: st3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0x9f,0x4c]
-; CHECK: st3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0x9f,0x0c]
-; CHECK: st3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0x9f,0x4c]
-; CHECK: st3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0x9f,0x0c]
-; CHECK: st3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0x9f,0x4c]
-; CHECK: st3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0x9f,0x4c]
-
-_ld4st4_multiple_post:
- ld4.8b {v0, v1, v2, v3}, [x1], x15
- ld4.16b {v0, v1, v2, v3}, [x1], x15
- ld4.4h {v0, v1, v2, v3}, [x1], x15
- ld4.8h {v0, v1, v2, v3}, [x1], x15
- ld4.2s {v0, v1, v2, v3}, [x1], x15
- ld4.4s {v0, v1, v2, v3}, [x1], x15
- ld4.2d {v0, v1, v2, v3}, [x1], x15
-
- st4.8b {v0, v1, v2, v3}, [x1], x15
- st4.16b {v0, v1, v2, v3}, [x1], x15
- st4.4h {v0, v1, v2, v3}, [x1], x15
- st4.8h {v0, v1, v2, v3}, [x1], x15
- st4.2s {v0, v1, v2, v3}, [x1], x15
- st4.4s {v0, v1, v2, v3}, [x1], x15
- st4.2d {v0, v1, v2, v3}, [x1], x15
-
- ld4.8b {v0, v1, v2, v3}, [x1], #32
- ld4.16b {v0, v1, v2, v3}, [x1], #64
- ld4.4h {v0, v1, v2, v3}, [x1], #32
- ld4.8h {v0, v1, v2, v3}, [x1], #64
- ld4.2s {v0, v1, v2, v3}, [x1], #32
- ld4.4s {v0, v1, v2, v3}, [x1], #64
- ld4.2d {v0, v1, v2, v3}, [x1], #64
-
- st4.8b {v0, v1, v2, v3}, [x1], #32
- st4.16b {v0, v1, v2, v3}, [x1], #64
- st4.4h {v0, v1, v2, v3}, [x1], #32
- st4.8h {v0, v1, v2, v3}, [x1], #64
- st4.2s {v0, v1, v2, v3}, [x1], #32
- st4.4s {v0, v1, v2, v3}, [x1], #64
- st4.2d {v0, v1, v2, v3}, [x1], #64
-
-
-; CHECK: ld4st4_multiple_post:
-; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x0c]
-; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x4c]
-; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x0c]
-; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x4c]
-; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x0c]
-; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x4c]
-; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0xcf,0x4c]
-
-; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x0c]
-; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x4c]
-; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x0c]
-; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x4c]
-; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x0c]
-; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x4c]
-; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0x8f,0x4c]
-
-; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0xdf,0x0c]
-; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0xdf,0x4c]
-; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0xdf,0x0c]
-; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0xdf,0x4c]
-; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0xdf,0x0c]
-; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0xdf,0x4c]
-; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0xdf,0x4c]
-
-; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0x9f,0x0c]
-; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0x9f,0x4c]
-; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0x9f,0x0c]
-; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0x9f,0x4c]
-; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0x9f,0x0c]
-; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0x9f,0x4c]
-; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0x9f,0x4c]
-
-ld1r:
- ld1r.8b {v4}, [x2]
- ld1r.8b {v4}, [x2], x3
- ld1r.16b {v4}, [x2]
- ld1r.16b {v4}, [x2], x3
- ld1r.4h {v4}, [x2]
- ld1r.4h {v4}, [x2], x3
- ld1r.8h {v4}, [x2]
- ld1r.8h {v4}, [x2], x3
- ld1r.2s {v4}, [x2]
- ld1r.2s {v4}, [x2], x3
- ld1r.4s {v4}, [x2]
- ld1r.4s {v4}, [x2], x3
- ld1r.1d {v4}, [x2]
- ld1r.1d {v4}, [x2], x3
- ld1r.2d {v4}, [x2]
- ld1r.2d {v4}, [x2], x3
-
- ld1r.8b {v4}, [x2], #1
- ld1r.16b {v4}, [x2], #1
- ld1r.4h {v4}, [x2], #2
- ld1r.8h {v4}, [x2], #2
- ld1r.2s {v4}, [x2], #4
- ld1r.4s {v4}, [x2], #4
- ld1r.1d {v4}, [x2], #8
- ld1r.2d {v4}, [x2], #8
-
-; CHECK: ld1r:
-; CHECK: ld1r.8b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x0d]
-; CHECK: ld1r.8b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x0d]
-; CHECK: ld1r.16b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x4d]
-; CHECK: ld1r.16b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x4d]
-; CHECK: ld1r.4h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x0d]
-; CHECK: ld1r.4h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x0d]
-; CHECK: ld1r.8h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x4d]
-; CHECK: ld1r.8h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x4d]
-; CHECK: ld1r.2s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x0d]
-; CHECK: ld1r.2s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x0d]
-; CHECK: ld1r.4s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x4d]
-; CHECK: ld1r.4s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x4d]
-; CHECK: ld1r.1d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x0d]
-; CHECK: ld1r.1d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x0d]
-; CHECK: ld1r.2d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x4d]
-; CHECK: ld1r.2d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x4d]
-
-; CHECK: ld1r.8b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x0d]
-; CHECK: ld1r.16b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x4d]
-; CHECK: ld1r.4h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x0d]
-; CHECK: ld1r.8h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x4d]
-; CHECK: ld1r.2s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x0d]
-; CHECK: ld1r.4s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x4d]
-; CHECK: ld1r.1d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x0d]
-; CHECK: ld1r.2d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x4d]
-
-ld2r:
- ld2r.8b {v4, v5}, [x2]
- ld2r.8b {v4, v5}, [x2], x3
- ld2r.16b {v4, v5}, [x2]
- ld2r.16b {v4, v5}, [x2], x3
- ld2r.4h {v4, v5}, [x2]
- ld2r.4h {v4, v5}, [x2], x3
- ld2r.8h {v4, v5}, [x2]
- ld2r.8h {v4, v5}, [x2], x3
- ld2r.2s {v4, v5}, [x2]
- ld2r.2s {v4, v5}, [x2], x3
- ld2r.4s {v4, v5}, [x2]
- ld2r.4s {v4, v5}, [x2], x3
- ld2r.1d {v4, v5}, [x2]
- ld2r.1d {v4, v5}, [x2], x3
- ld2r.2d {v4, v5}, [x2]
- ld2r.2d {v4, v5}, [x2], x3
-
- ld2r.8b {v4, v5}, [x2], #2
- ld2r.16b {v4, v5}, [x2], #2
- ld2r.4h {v4, v5}, [x2], #4
- ld2r.8h {v4, v5}, [x2], #4
- ld2r.2s {v4, v5}, [x2], #8
- ld2r.4s {v4, v5}, [x2], #8
- ld2r.1d {v4, v5}, [x2], #16
- ld2r.2d {v4, v5}, [x2], #16
-
-; CHECK: ld2r:
-; CHECK: ld2r.8b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x0d]
-; CHECK: ld2r.8b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x0d]
-; CHECK: ld2r.16b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x4d]
-; CHECK: ld2r.16b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x4d]
-; CHECK: ld2r.4h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x0d]
-; CHECK: ld2r.4h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x0d]
-; CHECK: ld2r.8h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x4d]
-; CHECK: ld2r.8h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x4d]
-; CHECK: ld2r.2s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x0d]
-; CHECK: ld2r.2s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x0d]
-; CHECK: ld2r.4s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x4d]
-; CHECK: ld2r.4s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x4d]
-; CHECK: ld2r.1d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x0d]
-; CHECK: ld2r.1d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x0d]
-; CHECK: ld2r.2d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x4d]
-; CHECK: ld2r.2d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x4d]
-
-; CHECK: ld2r.8b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x0d]
-; CHECK: ld2r.16b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x4d]
-; CHECK: ld2r.4h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x0d]
-; CHECK: ld2r.8h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x4d]
-; CHECK: ld2r.2s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x0d]
-; CHECK: ld2r.4s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x4d]
-; CHECK: ld2r.1d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x0d]
-; CHECK: ld2r.2d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x4d]
-
-ld3r:
- ld3r.8b {v4, v5, v6}, [x2]
- ld3r.8b {v4, v5, v6}, [x2], x3
- ld3r.16b {v4, v5, v6}, [x2]
- ld3r.16b {v4, v5, v6}, [x2], x3
- ld3r.4h {v4, v5, v6}, [x2]
- ld3r.4h {v4, v5, v6}, [x2], x3
- ld3r.8h {v4, v5, v6}, [x2]
- ld3r.8h {v4, v5, v6}, [x2], x3
- ld3r.2s {v4, v5, v6}, [x2]
- ld3r.2s {v4, v5, v6}, [x2], x3
- ld3r.4s {v4, v5, v6}, [x2]
- ld3r.4s {v4, v5, v6}, [x2], x3
- ld3r.1d {v4, v5, v6}, [x2]
- ld3r.1d {v4, v5, v6}, [x2], x3
- ld3r.2d {v4, v5, v6}, [x2]
- ld3r.2d {v4, v5, v6}, [x2], x3
-
- ld3r.8b {v4, v5, v6}, [x2], #3
- ld3r.16b {v4, v5, v6}, [x2], #3
- ld3r.4h {v4, v5, v6}, [x2], #6
- ld3r.8h {v4, v5, v6}, [x2], #6
- ld3r.2s {v4, v5, v6}, [x2], #12
- ld3r.4s {v4, v5, v6}, [x2], #12
- ld3r.1d {v4, v5, v6}, [x2], #24
- ld3r.2d {v4, v5, v6}, [x2], #24
-
-; CHECK: ld3r:
-; CHECK: ld3r.8b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x0d]
-; CHECK: ld3r.8b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x0d]
-; CHECK: ld3r.16b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x4d]
-; CHECK: ld3r.16b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x4d]
-; CHECK: ld3r.4h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x0d]
-; CHECK: ld3r.4h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x0d]
-; CHECK: ld3r.8h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x4d]
-; CHECK: ld3r.8h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x4d]
-; CHECK: ld3r.2s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x0d]
-; CHECK: ld3r.2s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x0d]
-; CHECK: ld3r.4s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x4d]
-; CHECK: ld3r.4s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x4d]
-; CHECK: ld3r.1d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x0d]
-; CHECK: ld3r.1d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x0d]
-; CHECK: ld3r.2d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x4d]
-; CHECK: ld3r.2d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x4d]
-
-; CHECK: ld3r.8b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x0d]
-; CHECK: ld3r.16b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x4d]
-; CHECK: ld3r.4h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x0d]
-; CHECK: ld3r.8h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x4d]
-; CHECK: ld3r.2s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x0d]
-; CHECK: ld3r.4s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x4d]
-; CHECK: ld3r.1d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x0d]
-; CHECK: ld3r.2d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x4d]
-
-ld4r:
- ld4r.8b {v4, v5, v6, v7}, [x2]
- ld4r.8b {v4, v5, v6, v7}, [x2], x3
- ld4r.16b {v4, v5, v6, v7}, [x2]
- ld4r.16b {v4, v5, v6, v7}, [x2], x3
- ld4r.4h {v4, v5, v6, v7}, [x2]
- ld4r.4h {v4, v5, v6, v7}, [x2], x3
- ld4r.8h {v4, v5, v6, v7}, [x2]
- ld4r.8h {v4, v5, v6, v7}, [x2], x3
- ld4r.2s {v4, v5, v6, v7}, [x2]
- ld4r.2s {v4, v5, v6, v7}, [x2], x3
- ld4r.4s {v4, v5, v6, v7}, [x2]
- ld4r.4s {v4, v5, v6, v7}, [x2], x3
- ld4r.1d {v4, v5, v6, v7}, [x2]
- ld4r.1d {v4, v5, v6, v7}, [x2], x3
- ld4r.2d {v4, v5, v6, v7}, [x2]
- ld4r.2d {v4, v5, v6, v7}, [x2], x3
-
- ld4r.8b {v4, v5, v6, v7}, [x2], #4
- ld4r.16b {v5, v6, v7, v8}, [x2], #4
- ld4r.4h {v6, v7, v8, v9}, [x2], #8
- ld4r.8h {v1, v2, v3, v4}, [x2], #8
- ld4r.2s {v2, v3, v4, v5}, [x2], #16
- ld4r.4s {v3, v4, v5, v6}, [x2], #16
- ld4r.1d {v0, v1, v2, v3}, [x2], #32
- ld4r.2d {v4, v5, v6, v7}, [x2], #32
-
-; CHECK: ld4r:
-; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x0d]
-; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x0d]
-; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x4d]
-; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x4d]
-; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x0d]
-; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x0d]
-; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x4d]
-; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x4d]
-; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x0d]
-; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x0d]
-; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x4d]
-; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x4d]
-; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x0d]
-; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x0d]
-; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x4d]
-; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x4d]
-
-; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], #4 ; encoding: [0x44,0xe0,0xff,0x0d]
-; CHECK: ld4r.16b { v5, v6, v7, v8 }, [x2], #4 ; encoding: [0x45,0xe0,0xff,0x4d]
-; CHECK: ld4r.4h { v6, v7, v8, v9 }, [x2], #8 ; encoding: [0x46,0xe4,0xff,0x0d]
-; CHECK: ld4r.8h { v1, v2, v3, v4 }, [x2], #8 ; encoding: [0x41,0xe4,0xff,0x4d]
-; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d]
-; CHECK: ld4r.4s { v3, v4, v5, v6 }, [x2], #16 ; encoding: [0x43,0xe8,0xff,0x4d]
-; CHECK: ld4r.1d { v0, v1, v2, v3 }, [x2], #32 ; encoding: [0x40,0xec,0xff,0x0d]
-; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], #32 ; encoding: [0x44,0xec,0xff,0x4d]
-
-
-_ld1:
- ld1.b {v4}[13], [x3]
- ld1.h {v4}[2], [x3]
- ld1.s {v4}[2], [x3]
- ld1.d {v4}[1], [x3]
- ld1.b {v4}[13], [x3], x5
- ld1.h {v4}[2], [x3], x5
- ld1.s {v4}[2], [x3], x5
- ld1.d {v4}[1], [x3], x5
- ld1.b {v4}[13], [x3], #1
- ld1.h {v4}[2], [x3], #2
- ld1.s {v4}[2], [x3], #4
- ld1.d {v4}[1], [x3], #8
-
-; CHECK: _ld1:
-; CHECK: ld1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x40,0x4d]
-; CHECK: ld1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x40,0x0d]
-; CHECK: ld1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x40,0x4d]
-; CHECK: ld1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x40,0x4d]
-; CHECK: ld1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0xc5,0x4d]
-; CHECK: ld1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0xc5,0x0d]
-; CHECK: ld1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0xc5,0x4d]
-; CHECK: ld1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0xc5,0x4d]
-; CHECK: ld1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0xdf,0x4d]
-; CHECK: ld1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0xdf,0x0d]
-; CHECK: ld1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0xdf,0x4d]
-; CHECK: ld1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0xdf,0x4d]
-
-_ld2:
- ld2.b {v4, v5}[13], [x3]
- ld2.h {v4, v5}[2], [x3]
- ld2.s {v4, v5}[2], [x3]
- ld2.d {v4, v5}[1], [x3]
- ld2.b {v4, v5}[13], [x3], x5
- ld2.h {v4, v5}[2], [x3], x5
- ld2.s {v4, v5}[2], [x3], x5
- ld2.d {v4, v5}[1], [x3], x5
- ld2.b {v4, v5}[13], [x3], #2
- ld2.h {v4, v5}[2], [x3], #4
- ld2.s {v4, v5}[2], [x3], #8
- ld2.d {v4, v5}[1], [x3], #16
-
-
-; CHECK: _ld2:
-; CHECK: ld2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x60,0x4d]
-; CHECK: ld2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x60,0x0d]
-; CHECK: ld2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x60,0x4d]
-; CHECK: ld2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x60,0x4d]
-; CHECK: ld2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xe5,0x4d]
-; CHECK: ld2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xe5,0x0d]
-; CHECK: ld2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xe5,0x4d]
-; CHECK: ld2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xe5,0x4d]
-; CHECK: ld2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xff,0x4d]
-; CHECK: ld2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xff,0x0d]
-; CHECK: ld2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xff,0x4d]
-; CHECK: ld2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xff,0x4d]
-
-
-_ld3:
- ld3.b {v4, v5, v6}[13], [x3]
- ld3.h {v4, v5, v6}[2], [x3]
- ld3.s {v4, v5, v6}[2], [x3]
- ld3.d {v4, v5, v6}[1], [x3]
- ld3.b {v4, v5, v6}[13], [x3], x5
- ld3.h {v4, v5, v6}[2], [x3], x5
- ld3.s {v4, v5, v6}[2], [x3], x5
- ld3.d {v4, v5, v6}[1], [x3], x5
- ld3.b {v4, v5, v6}[13], [x3], #3
- ld3.h {v4, v5, v6}[2], [x3], #6
- ld3.s {v4, v5, v6}[2], [x3], #12
- ld3.d {v4, v5, v6}[1], [x3], #24
-
-
-; CHECK: _ld3:
-; CHECK: ld3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x40,0x4d]
-; CHECK: ld3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x40,0x0d]
-; CHECK: ld3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x40,0x4d]
-; CHECK: ld3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x40,0x4d]
-; CHECK: ld3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0xc5,0x4d]
-; CHECK: ld3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0xc5,0x0d]
-; CHECK: ld3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xc5,0x4d]
-; CHECK: ld3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xc5,0x4d]
-; CHECK: ld3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0xdf,0x4d]
-; CHECK: ld3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0xdf,0x0d]
-; CHECK: ld3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0xdf,0x4d]
-; CHECK: ld3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0xdf,0x4d]
-
-
-_ld4:
- ld4.b {v4, v5, v6, v7}[13], [x3]
- ld4.h {v4, v5, v6, v7}[2], [x3]
- ld4.s {v4, v5, v6, v7}[2], [x3]
- ld4.d {v4, v5, v6, v7}[1], [x3]
- ld4.b {v4, v5, v6, v7}[13], [x3], x5
- ld4.h {v4, v5, v6, v7}[2], [x3], x5
- ld4.s {v4, v5, v6, v7}[2], [x3], x5
- ld4.d {v4, v5, v6, v7}[1], [x3], x5
- ld4.b {v4, v5, v6, v7}[13], [x3], #4
- ld4.h {v4, v5, v6, v7}[2], [x3], #8
- ld4.s {v4, v5, v6, v7}[2], [x3], #16
- ld4.d {v4, v5, v6, v7}[1], [x3], #32
-
-; CHECK: _ld4:
-; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x60,0x4d]
-; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x60,0x0d]
-; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x60,0x4d]
-; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x60,0x4d]
-; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xe5,0x4d]
-; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xe5,0x0d]
-; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xe5,0x4d]
-; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xe5,0x4d]
-; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xff,0x4d]
-; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xff,0x0d]
-; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xff,0x4d]
-; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xff,0x4d]
-
-_st1:
- st1.b {v4}[13], [x3]
- st1.h {v4}[2], [x3]
- st1.s {v4}[2], [x3]
- st1.d {v4}[1], [x3]
- st1.b {v4}[13], [x3], x5
- st1.h {v4}[2], [x3], x5
- st1.s {v4}[2], [x3], x5
- st1.d {v4}[1], [x3], x5
- st1.b {v4}[13], [x3], #1
- st1.h {v4}[2], [x3], #2
- st1.s {v4}[2], [x3], #4
- st1.d {v4}[1], [x3], #8
-
-; CHECK: _st1:
-; CHECK: st1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x00,0x4d]
-; CHECK: st1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x00,0x0d]
-; CHECK: st1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x00,0x4d]
-; CHECK: st1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x00,0x4d]
-; CHECK: st1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0x85,0x4d]
-; CHECK: st1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0x85,0x0d]
-; CHECK: st1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0x85,0x4d]
-; CHECK: st1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0x85,0x4d]
-; CHECK: st1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0x9f,0x4d]
-; CHECK: st1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0x9f,0x0d]
-; CHECK: st1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0x9f,0x4d]
-; CHECK: st1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0x9f,0x4d]
-
-_st2:
- st2.b {v4, v5}[13], [x3]
- st2.h {v4, v5}[2], [x3]
- st2.s {v4, v5}[2], [x3]
- st2.d {v4, v5}[1], [x3]
- st2.b {v4, v5}[13], [x3], x5
- st2.h {v4, v5}[2], [x3], x5
- st2.s {v4, v5}[2], [x3], x5
- st2.d {v4, v5}[1], [x3], x5
- st2.b {v4, v5}[13], [x3], #2
- st2.h {v4, v5}[2], [x3], #4
- st2.s {v4, v5}[2], [x3], #8
- st2.d {v4, v5}[1], [x3], #16
-
-; CHECK: _st2:
-; CHECK: st2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x20,0x4d]
-; CHECK: st2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x20,0x0d]
-; CHECK: st2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x20,0x4d]
-; CHECK: st2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x20,0x4d]
-; CHECK: st2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xa5,0x4d]
-; CHECK: st2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xa5,0x0d]
-; CHECK: st2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xa5,0x4d]
-; CHECK: st2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xa5,0x4d]
-; CHECK: st2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xbf,0x4d]
-; CHECK: st2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xbf,0x0d]
-; CHECK: st2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xbf,0x4d]
-; CHECK: st2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xbf,0x4d]
-
-
-_st3:
- st3.b {v4, v5, v6}[13], [x3]
- st3.h {v4, v5, v6}[2], [x3]
- st3.s {v4, v5, v6}[2], [x3]
- st3.d {v4, v5, v6}[1], [x3]
- st3.b {v4, v5, v6}[13], [x3], x5
- st3.h {v4, v5, v6}[2], [x3], x5
- st3.s {v4, v5, v6}[2], [x3], x5
- st3.d {v4, v5, v6}[1], [x3], x5
- st3.b {v4, v5, v6}[13], [x3], #3
- st3.h {v4, v5, v6}[2], [x3], #6
- st3.s {v4, v5, v6}[2], [x3], #12
- st3.d {v4, v5, v6}[1], [x3], #24
-
-; CHECK: _st3:
-; CHECK: st3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x00,0x4d]
-; CHECK: st3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x00,0x0d]
-; CHECK: st3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x00,0x4d]
-; CHECK: st3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x00,0x4d]
-; CHECK: st3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0x85,0x4d]
-; CHECK: st3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0x85,0x0d]
-; CHECK: st3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0x85,0x4d]
-; CHECK: st3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0x85,0x4d]
-; CHECK: st3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0x9f,0x4d]
-; CHECK: st3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0x9f,0x0d]
-; CHECK: st3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0x9f,0x4d]
-; CHECK: st3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0x9f,0x4d]
-
-_st4:
- st4.b {v4, v5, v6, v7}[13], [x3]
- st4.h {v4, v5, v6, v7}[2], [x3]
- st4.s {v4, v5, v6, v7}[2], [x3]
- st4.d {v4, v5, v6, v7}[1], [x3]
- st4.b {v4, v5, v6, v7}[13], [x3], x5
- st4.h {v4, v5, v6, v7}[2], [x3], x5
- st4.s {v4, v5, v6, v7}[2], [x3], x5
- st4.d {v4, v5, v6, v7}[1], [x3], x5
- st4.b {v4, v5, v6, v7}[13], [x3], #4
- st4.h {v4, v5, v6, v7}[2], [x3], #8
- st4.s {v4, v5, v6, v7}[2], [x3], #16
- st4.d {v4, v5, v6, v7}[1], [x3], #32
-
-; CHECK: _st4:
-; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x20,0x4d]
-; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x20,0x0d]
-; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x20,0x4d]
-; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x20,0x4d]
-; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xa5,0x4d]
-; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xa5,0x0d]
-; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xa5,0x4d]
-; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xa5,0x4d]
-; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xbf,0x4d]
-; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xbf,0x0d]
-; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xbf,0x4d]
-; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xbf,0x4d]
-
-
-;---------
-; ARM verbose syntax equivalents to the above.
-;---------
-verbose_syntax:
-
- ld1 { v1.8b }, [x1]
- ld1 { v2.8b, v3.8b }, [x1]
- ld1 { v3.8b, v4.8b, v5.8b }, [x1]
- ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1]
-
- ld1 { v1.16b }, [x1]
- ld1 { v2.16b, v3.16b }, [x1]
- ld1 { v3.16b, v4.16b, v5.16b }, [x1]
- ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1]
-
- ld1 { v1.4h }, [x1]
- ld1 { v2.4h, v3.4h }, [x1]
- ld1 { v3.4h, v4.4h, v5.4h }, [x1]
- ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1]
-
- ld1 { v1.8h }, [x1]
- ld1 { v2.8h, v3.8h }, [x1]
- ld1 { v3.8h, v4.8h, v5.8h }, [x1]
- ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1]
-
- ld1 { v1.2s }, [x1]
- ld1 { v2.2s, v3.2s }, [x1]
- ld1 { v3.2s, v4.2s, v5.2s }, [x1]
- ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1]
-
- ld1 { v1.4s }, [x1]
- ld1 { v2.4s, v3.4s }, [x1]
- ld1 { v3.4s, v4.4s, v5.4s }, [x1]
- ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1]
-
- ld1 { v1.1d }, [x1]
- ld1 { v2.1d, v3.1d }, [x1]
- ld1 { v3.1d, v4.1d, v5.1d }, [x1]
- ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1]
-
- ld1 { v1.2d }, [x1]
- ld1 { v2.2d, v3.2d }, [x1]
- ld1 { v3.2d, v4.2d, v5.2d }, [x1]
- ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1]
-
- st1 { v1.8b }, [x1]
- st1 { v2.8b, v3.8b }, [x1]
- st1 { v3.8b, v4.8b, v5.8b }, [x1]
- st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1]
-
- st1 { v1.16b }, [x1]
- st1 { v2.16b, v3.16b }, [x1]
- st1 { v3.16b, v4.16b, v5.16b }, [x1]
- st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1]
-
- st1 { v1.4h }, [x1]
- st1 { v2.4h, v3.4h }, [x1]
- st1 { v3.4h, v4.4h, v5.4h }, [x1]
- st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1]
-
- st1 { v1.8h }, [x1]
- st1 { v2.8h, v3.8h }, [x1]
- st1 { v3.8h, v4.8h, v5.8h }, [x1]
- st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1]
-
- st1 { v1.2s }, [x1]
- st1 { v2.2s, v3.2s }, [x1]
- st1 { v3.2s, v4.2s, v5.2s }, [x1]
- st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1]
-
- st1 { v1.4s }, [x1]
- st1 { v2.4s, v3.4s }, [x1]
- st1 { v3.4s, v4.4s, v5.4s }, [x1]
- st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1]
-
- st1 { v1.1d }, [x1]
- st1 { v2.1d, v3.1d }, [x1]
- st1 { v3.1d, v4.1d, v5.1d }, [x1]
- st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1]
-
- st1 { v1.2d }, [x1]
- st1 { v2.2d, v3.2d }, [x1]
- st1 { v3.2d, v4.2d, v5.2d }, [x1]
- st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1]
-
- ld2 { v3.8b, v4.8b }, [x19]
- ld2 { v3.16b, v4.16b }, [x19]
- ld2 { v3.4h, v4.4h }, [x19]
- ld2 { v3.8h, v4.8h }, [x19]
- ld2 { v3.2s, v4.2s }, [x19]
- ld2 { v3.4s, v4.4s }, [x19]
- ld2 { v3.2d, v4.2d }, [x19]
-
- st2 { v3.8b, v4.8b }, [x19]
- st2 { v3.16b, v4.16b }, [x19]
- st2 { v3.4h, v4.4h }, [x19]
- st2 { v3.8h, v4.8h }, [x19]
- st2 { v3.2s, v4.2s }, [x19]
- st2 { v3.4s, v4.4s }, [x19]
- st2 { v3.2d, v4.2d }, [x19]
-
- ld3 { v2.8b, v3.8b, v4.8b }, [x19]
- ld3 { v2.16b, v3.16b, v4.16b }, [x19]
- ld3 { v2.4h, v3.4h, v4.4h }, [x19]
- ld3 { v2.8h, v3.8h, v4.8h }, [x19]
- ld3 { v2.2s, v3.2s, v4.2s }, [x19]
- ld3 { v2.4s, v3.4s, v4.4s }, [x19]
- ld3 { v2.2d, v3.2d, v4.2d }, [x19]
-
- st3 { v2.8b, v3.8b, v4.8b }, [x19]
- st3 { v2.16b, v3.16b, v4.16b }, [x19]
- st3 { v2.4h, v3.4h, v4.4h }, [x19]
- st3 { v2.8h, v3.8h, v4.8h }, [x19]
- st3 { v2.2s, v3.2s, v4.2s }, [x19]
- st3 { v2.4s, v3.4s, v4.4s }, [x19]
- st3 { v2.2d, v3.2d, v4.2d }, [x19]
-
- ld4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
- ld4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
- ld4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
- ld4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
- ld4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
- ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
- ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
-
- st4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
- st4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
- st4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
- st4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
- st4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
- st4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
- st4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
-
- ld1 { v1.8b }, [x1], x15
- ld1 { v2.8b, v3.8b }, [x1], x15
- ld1 { v3.8b, v4.8b, v5.8b }, [x1], x15
- ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
-
- ld1 { v1.16b }, [x1], x15
- ld1 { v2.16b, v3.16b }, [x1], x15
- ld1 { v3.16b, v4.16b, v5.16b }, [x1], x15
- ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
-
- ld1 { v1.4h }, [x1], x15
- ld1 { v2.4h, v3.4h }, [x1], x15
- ld1 { v3.4h, v4.4h, v5.4h }, [x1], x15
- ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
-
- ld1 { v1.8h }, [x1], x15
- ld1 { v2.8h, v3.8h }, [x1], x15
- ld1 { v3.8h, v4.8h, v5.8h }, [x1], x15
- ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
-
- ld1 { v1.2s }, [x1], x15
- ld1 { v2.2s, v3.2s }, [x1], x15
- ld1 { v3.2s, v4.2s, v5.2s }, [x1], x15
- ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
-
- ld1 { v1.4s }, [x1], x15
- ld1 { v2.4s, v3.4s }, [x1], x15
- ld1 { v3.4s, v4.4s, v5.4s }, [x1], x15
- ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
-
- ld1 { v1.1d }, [x1], x15
- ld1 { v2.1d, v3.1d }, [x1], x15
- ld1 { v3.1d, v4.1d, v5.1d }, [x1], x15
- ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15
-
- ld1 { v1.2d }, [x1], x15
- ld1 { v2.2d, v3.2d }, [x1], x15
- ld1 { v3.2d, v4.2d, v5.2d }, [x1], x15
- ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
-
- st1 { v1.8b }, [x1], x15
- st1 { v2.8b, v3.8b }, [x1], x15
- st1 { v3.8b, v4.8b, v5.8b }, [x1], x15
- st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
-
- st1 { v1.16b }, [x1], x15
- st1 { v2.16b, v3.16b }, [x1], x15
- st1 { v3.16b, v4.16b, v5.16b }, [x1], x15
- st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
-
- st1 { v1.4h }, [x1], x15
- st1 { v2.4h, v3.4h }, [x1], x15
- st1 { v3.4h, v4.4h, v5.4h }, [x1], x15
- st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
-
- st1 { v1.8h }, [x1], x15
- st1 { v2.8h, v3.8h }, [x1], x15
- st1 { v3.8h, v4.8h, v5.8h }, [x1], x15
- st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
-
- st1 { v1.2s }, [x1], x15
- st1 { v2.2s, v3.2s }, [x1], x15
- st1 { v3.2s, v4.2s, v5.2s }, [x1], x15
- st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
-
- st1 { v1.4s }, [x1], x15
- st1 { v2.4s, v3.4s }, [x1], x15
- st1 { v3.4s, v4.4s, v5.4s }, [x1], x15
- st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
-
- st1 { v1.1d }, [x1], x15
- st1 { v2.1d, v3.1d }, [x1], x15
- st1 { v3.1d, v4.1d, v5.1d }, [x1], x15
- st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15
-
- st1 { v1.2d }, [x1], x15
- st1 { v2.2d, v3.2d }, [x1], x15
- st1 { v3.2d, v4.2d, v5.2d }, [x1], x15
- st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
-
- ld1 { v1.8b }, [x1], #8
- ld1 { v2.8b, v3.8b }, [x1], #16
- ld1 { v3.8b, v4.8b, v5.8b }, [x1], #24
- ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
-
- ld1 { v1.16b }, [x1], #16
- ld1 { v2.16b, v3.16b }, [x1], #32
- ld1 { v3.16b, v4.16b, v5.16b }, [x1], #48
- ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
-
- ld1 { v1.4h }, [x1], #8
- ld1 { v2.4h, v3.4h }, [x1], #16
- ld1 { v3.4h, v4.4h, v5.4h }, [x1], #24
- ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
-
- ld1 { v1.8h }, [x1], #16
- ld1 { v2.8h, v3.8h }, [x1], #32
- ld1 { v3.8h, v4.8h, v5.8h }, [x1], #48
- ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
-
- ld1 { v1.2s }, [x1], #8
- ld1 { v2.2s, v3.2s }, [x1], #16
- ld1 { v3.2s, v4.2s, v5.2s }, [x1], #24
- ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
-
- ld1 { v1.4s }, [x1], #16
- ld1 { v2.4s, v3.4s }, [x1], #32
- ld1 { v3.4s, v4.4s, v5.4s }, [x1], #48
- ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
-
- ld1 { v1.1d }, [x1], #8
- ld1 { v2.1d, v3.1d }, [x1], #16
- ld1 { v3.1d, v4.1d, v5.1d }, [x1], #24
- ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32
-
- ld1 { v1.2d }, [x1], #16
- ld1 { v2.2d, v3.2d }, [x1], #32
- ld1 { v3.2d, v4.2d, v5.2d }, [x1], #48
- ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
-
- st1 { v1.8b }, [x1], #8
- st1 { v2.8b, v3.8b }, [x1], #16
- st1 { v3.8b, v4.8b, v5.8b }, [x1], #24
- st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
-
- st1 { v1.16b }, [x1], #16
- st1 { v2.16b, v3.16b }, [x1], #32
- st1 { v3.16b, v4.16b, v5.16b }, [x1], #48
- st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
-
- st1 { v1.4h }, [x1], #8
- st1 { v2.4h, v3.4h }, [x1], #16
- st1 { v3.4h, v4.4h, v5.4h }, [x1], #24
- st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
-
- st1 { v1.8h }, [x1], #16
- st1 { v2.8h, v3.8h }, [x1], #32
- st1 { v3.8h, v4.8h, v5.8h }, [x1], #48
- st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
-
- st1 { v1.2s }, [x1], #8
- st1 { v2.2s, v3.2s }, [x1], #16
- st1 { v3.2s, v4.2s, v5.2s }, [x1], #24
- st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
-
- st1 { v1.4s }, [x1], #16
- st1 { v2.4s, v3.4s }, [x1], #32
- st1 { v3.4s, v4.4s, v5.4s }, [x1], #48
- st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
-
- st1 { v1.1d }, [x1], #8
- st1 { v2.1d, v3.1d }, [x1], #16
- st1 { v3.1d, v4.1d, v5.1d }, [x1], #24
- st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32
-
- st1 { v1.2d }, [x1], #16
- st1 { v2.2d, v3.2d }, [x1], #32
- st1 { v3.2d, v4.2d, v5.2d }, [x1], #48
- st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
-
- ld2 { v2.8b, v3.8b }, [x1], x15
- ld2 { v2.16b, v3.16b }, [x1], x15
- ld2 { v2.4h, v3.4h }, [x1], x15
- ld2 { v2.8h, v3.8h }, [x1], x15
- ld2 { v2.2s, v3.2s }, [x1], x15
- ld2 { v2.4s, v3.4s }, [x1], x15
- ld2 { v2.2d, v3.2d }, [x1], x15
-
- st2 { v2.8b, v3.8b }, [x1], x15
- st2 { v2.16b, v3.16b }, [x1], x15
- st2 { v2.4h, v3.4h }, [x1], x15
- st2 { v2.8h, v3.8h }, [x1], x15
- st2 { v2.2s, v3.2s }, [x1], x15
- st2 { v2.4s, v3.4s }, [x1], x15
- st2 { v2.2d, v3.2d }, [x1], x15
-
- ld2 { v2.8b, v3.8b }, [x1], #16
- ld2 { v2.16b, v3.16b }, [x1], #32
- ld2 { v2.4h, v3.4h }, [x1], #16
- ld2 { v2.8h, v3.8h }, [x1], #32
- ld2 { v2.2s, v3.2s }, [x1], #16
- ld2 { v2.4s, v3.4s }, [x1], #32
- ld2 { v2.2d, v3.2d }, [x1], #32
-
- st2 { v2.8b, v3.8b }, [x1], #16
- st2 { v2.16b, v3.16b }, [x1], #32
- st2 { v2.4h, v3.4h }, [x1], #16
- st2 { v2.8h, v3.8h }, [x1], #32
- st2 { v2.2s, v3.2s }, [x1], #16
- st2 { v2.4s, v3.4s }, [x1], #32
- st2 { v2.2d, v3.2d }, [x1], #32
-
- ld3 { v3.8b, v4.8b, v5.8b }, [x1], x15
- ld3 { v3.16b, v4.16b, v5.16b }, [x1], x15
- ld3 { v3.4h, v4.4h, v5.4h }, [x1], x15
- ld3 { v3.8h, v4.8h, v5.8h }, [x1], x15
- ld3 { v3.2s, v4.2s, v5.2s }, [x1], x15
- ld3 { v3.4s, v4.4s, v5.4s }, [x1], x15
- ld3 { v3.2d, v4.2d, v5.2d }, [x1], x15
-
- st3 { v3.8b, v4.8b, v5.8b }, [x1], x15
- st3 { v3.16b, v4.16b, v5.16b }, [x1], x15
- st3 { v3.4h, v4.4h, v5.4h }, [x1], x15
- st3 { v3.8h, v4.8h, v5.8h }, [x1], x15
- st3 { v3.2s, v4.2s, v5.2s }, [x1], x15
- st3 { v3.4s, v4.4s, v5.4s }, [x1], x15
- st3 { v3.2d, v4.2d, v5.2d }, [x1], x15
- ld3 { v3.8b, v4.8b, v5.8b }, [x1], #24
-
- ld3 { v3.16b, v4.16b, v5.16b }, [x1], #48
- ld3 { v3.4h, v4.4h, v5.4h }, [x1], #24
- ld3 { v3.8h, v4.8h, v5.8h }, [x1], #48
- ld3 { v3.2s, v4.2s, v5.2s }, [x1], #24
- ld3 { v3.4s, v4.4s, v5.4s }, [x1], #48
- ld3 { v3.2d, v4.2d, v5.2d }, [x1], #48
-
- st3 { v3.8b, v4.8b, v5.8b }, [x1], #24
- st3 { v3.16b, v4.16b, v5.16b }, [x1], #48
- st3 { v3.4h, v4.4h, v5.4h }, [x1], #24
- st3 { v3.8h, v4.8h, v5.8h }, [x1], #48
- st3 { v3.2s, v4.2s, v5.2s }, [x1], #24
- st3 { v3.4s, v4.4s, v5.4s }, [x1], #48
- st3 { v3.2d, v4.2d, v5.2d }, [x1], #48
-
- ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
- ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
- ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
- ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
- ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
- ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
- ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
-
- st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
- st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
- st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
- st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
- st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
- st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
- st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
-
- ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
- ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
- ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
- ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
- ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
- ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
- ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
-
- st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
- st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
- st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
- st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
- st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
- st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
- st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
-
-
- ld1r { v12.8b }, [x2]
- ld1r { v12.8b }, [x2], x3
- ld1r { v12.16b }, [x2]
- ld1r { v12.16b }, [x2], x3
- ld1r { v12.4h }, [x2]
- ld1r { v12.4h }, [x2], x3
- ld1r { v12.8h }, [x2]
- ld1r { v12.8h }, [x2], x3
- ld1r { v12.2s }, [x2]
- ld1r { v12.2s }, [x2], x3
- ld1r { v12.4s }, [x2]
- ld1r { v12.4s }, [x2], x3
- ld1r { v12.1d }, [x2]
- ld1r { v12.1d }, [x2], x3
- ld1r { v12.2d }, [x2]
- ld1r { v12.2d }, [x2], x3
-
- ld1r { v12.8b }, [x2], #1
- ld1r { v12.16b }, [x2], #1
- ld1r { v12.4h }, [x2], #2
- ld1r { v12.8h }, [x2], #2
- ld1r { v12.2s }, [x2], #4
- ld1r { v12.4s }, [x2], #4
- ld1r { v12.1d }, [x2], #8
- ld1r { v12.2d }, [x2], #8
- ld2r { v3.8b, v4.8b }, [x2]
- ld2r { v3.8b, v4.8b }, [x2], x3
- ld2r { v3.16b, v4.16b }, [x2]
- ld2r { v3.16b, v4.16b }, [x2], x3
- ld2r { v3.4h, v4.4h }, [x2]
- ld2r { v3.4h, v4.4h }, [x2], x3
- ld2r { v3.8h, v4.8h }, [x2]
- ld2r { v3.8h, v4.8h }, [x2], x3
- ld2r { v3.2s, v4.2s }, [x2]
- ld2r { v3.2s, v4.2s }, [x2], x3
- ld2r { v3.4s, v4.4s }, [x2]
- ld2r { v3.4s, v4.4s }, [x2], x3
- ld2r { v3.1d, v4.1d }, [x2]
- ld2r { v3.1d, v4.1d }, [x2], x3
- ld2r { v3.2d, v4.2d }, [x2]
- ld2r { v3.2d, v4.2d }, [x2], x3
-
- ld2r { v3.8b, v4.8b }, [x2], #2
- ld2r { v3.16b, v4.16b }, [x2], #2
- ld2r { v3.4h, v4.4h }, [x2], #4
- ld2r { v3.8h, v4.8h }, [x2], #4
- ld2r { v3.2s, v4.2s }, [x2], #8
- ld2r { v3.4s, v4.4s }, [x2], #8
- ld2r { v3.1d, v4.1d }, [x2], #16
- ld2r { v3.2d, v4.2d }, [x2], #16
-
- ld3r { v2.8b, v3.8b, v4.8b }, [x2]
- ld3r { v2.8b, v3.8b, v4.8b }, [x2], x3
- ld3r { v2.16b, v3.16b, v4.16b }, [x2]
- ld3r { v2.16b, v3.16b, v4.16b }, [x2], x3
- ld3r { v2.4h, v3.4h, v4.4h }, [x2]
- ld3r { v2.4h, v3.4h, v4.4h }, [x2], x3
- ld3r { v2.8h, v3.8h, v4.8h }, [x2]
- ld3r { v2.8h, v3.8h, v4.8h }, [x2], x3
- ld3r { v2.2s, v3.2s, v4.2s }, [x2]
- ld3r { v2.2s, v3.2s, v4.2s }, [x2], x3
- ld3r { v2.4s, v3.4s, v4.4s }, [x2]
- ld3r { v2.4s, v3.4s, v4.4s }, [x2], x3
- ld3r { v2.1d, v3.1d, v4.1d }, [x2]
- ld3r { v2.1d, v3.1d, v4.1d }, [x2], x3
- ld3r { v2.2d, v3.2d, v4.2d }, [x2]
- ld3r { v2.2d, v3.2d, v4.2d }, [x2], x3
-
- ld3r { v2.8b, v3.8b, v4.8b }, [x2], #3
- ld3r { v2.16b, v3.16b, v4.16b }, [x2], #3
- ld3r { v2.4h, v3.4h, v4.4h }, [x2], #6
- ld3r { v2.8h, v3.8h, v4.8h }, [x2], #6
- ld3r { v2.2s, v3.2s, v4.2s }, [x2], #12
- ld3r { v2.4s, v3.4s, v4.4s }, [x2], #12
- ld3r { v2.1d, v3.1d, v4.1d }, [x2], #24
- ld3r { v2.2d, v3.2d, v4.2d }, [x2], #24
-
- ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2]
- ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], x3
- ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2]
- ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], x3
- ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2]
- ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], x3
- ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2]
- ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], x3
- ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2]
- ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], x3
- ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2]
- ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], x3
- ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2]
- ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], x3
- ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2]
- ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], x3
-
- ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], #4
- ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], #4
- ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], #8
- ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], #8
- ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], #16
- ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], #16
- ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], #32
- ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], #32
-
- ld1 { v6.b }[13], [x3]
- ld1 { v6.h }[2], [x3]
- ld1 { v6.s }[2], [x3]
- ld1 { v6.d }[1], [x3]
- ld1 { v6.b }[13], [x3], x5
- ld1 { v6.h }[2], [x3], x5
- ld1 { v6.s }[2], [x3], x5
- ld1 { v6.d }[1], [x3], x5
- ld1 { v6.b }[13], [x3], #1
- ld1 { v6.h }[2], [x3], #2
- ld1 { v6.s }[2], [x3], #4
- ld1 { v6.d }[1], [x3], #8
-
- ld2 { v5.b, v6.b }[13], [x3]
- ld2 { v5.h, v6.h }[2], [x3]
- ld2 { v5.s, v6.s }[2], [x3]
- ld2 { v5.d, v6.d }[1], [x3]
- ld2 { v5.b, v6.b }[13], [x3], x5
- ld2 { v5.h, v6.h }[2], [x3], x5
- ld2 { v5.s, v6.s }[2], [x3], x5
- ld2 { v5.d, v6.d }[1], [x3], x5
- ld2 { v5.b, v6.b }[13], [x3], #2
- ld2 { v5.h, v6.h }[2], [x3], #4
- ld2 { v5.s, v6.s }[2], [x3], #8
- ld2 { v5.d, v6.d }[1], [x3], #16
-
- ld3 { v7.b, v8.b, v9.b }[13], [x3]
- ld3 { v7.h, v8.h, v9.h }[2], [x3]
- ld3 { v7.s, v8.s, v9.s }[2], [x3]
- ld3 { v7.d, v8.d, v9.d }[1], [x3]
- ld3 { v7.b, v8.b, v9.b }[13], [x3], x5
- ld3 { v7.h, v8.h, v9.h }[2], [x3], x5
- ld3 { v7.s, v8.s, v9.s }[2], [x3], x5
- ld3 { v7.d, v8.d, v9.d }[1], [x3], x5
- ld3 { v7.b, v8.b, v9.b }[13], [x3], #3
- ld3 { v7.h, v8.h, v9.h }[2], [x3], #6
- ld3 { v7.s, v8.s, v9.s }[2], [x3], #12
- ld3 { v7.d, v8.d, v9.d }[1], [x3], #24
-
- ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
- ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
- ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
- ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
- ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
- ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
- ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
- ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
- ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
- ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
- ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
- ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
-
- st1 { v6.b }[13], [x3]
- st1 { v6.h }[2], [x3]
- st1 { v6.s }[2], [x3]
- st1 { v6.d }[1], [x3]
- st1 { v6.b }[13], [x3], x5
- st1 { v6.h }[2], [x3], x5
- st1 { v6.s }[2], [x3], x5
- st1 { v6.d }[1], [x3], x5
- st1 { v6.b }[13], [x3], #1
- st1 { v6.h }[2], [x3], #2
- st1 { v6.s }[2], [x3], #4
- st1 { v6.d }[1], [x3], #8
-
-
- st2 { v5.b, v6.b }[13], [x3]
- st2 { v5.h, v6.h }[2], [x3]
- st2 { v5.s, v6.s }[2], [x3]
- st2 { v5.d, v6.d }[1], [x3]
- st2 { v5.b, v6.b }[13], [x3], x5
- st2 { v5.h, v6.h }[2], [x3], x5
- st2 { v5.s, v6.s }[2], [x3], x5
- st2 { v5.d, v6.d }[1], [x3], x5
- st2 { v5.b, v6.b }[13], [x3], #2
- st2 { v5.h, v6.h }[2], [x3], #4
- st2 { v5.s, v6.s }[2], [x3], #8
- st2 { v5.d, v6.d }[1], [x3], #16
-
- st3 { v7.b, v8.b, v9.b }[13], [x3]
- st3 { v7.h, v8.h, v9.h }[2], [x3]
- st3 { v7.s, v8.s, v9.s }[2], [x3]
- st3 { v7.d, v8.d, v9.d }[1], [x3]
- st3 { v7.b, v8.b, v9.b }[13], [x3], x5
- st3 { v7.h, v8.h, v9.h }[2], [x3], x5
- st3 { v7.s, v8.s, v9.s }[2], [x3], x5
- st3 { v7.d, v8.d, v9.d }[1], [x3], x5
- st3 { v7.b, v8.b, v9.b }[13], [x3], #3
- st3 { v7.h, v8.h, v9.h }[2], [x3], #6
- st3 { v7.s, v8.s, v9.s }[2], [x3], #12
- st3 { v7.d, v8.d, v9.d }[1], [x3], #24
-
- st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
- st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
- st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
- st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
- st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
- st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
- st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
- st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
- st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
- st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
- st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
- st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
-
-; CHECK: ld1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x0c]
-; CHECK: ld1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x0c]
-; CHECK: ld1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x0c]
-; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x0c]
-; CHECK: ld1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x4c]
-; CHECK: ld1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x4c]
-; CHECK: ld1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x4c]
-; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x4c]
-; CHECK: ld1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x0c]
-; CHECK: ld1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x0c]
-; CHECK: ld1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x0c]
-; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x0c]
-; CHECK: ld1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x4c]
-; CHECK: ld1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x4c]
-; CHECK: ld1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x4c]
-; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x4c]
-; CHECK: ld1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x0c]
-; CHECK: ld1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x0c]
-; CHECK: ld1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x0c]
-; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x0c]
-; CHECK: ld1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x4c]
-; CHECK: ld1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x4c]
-; CHECK: ld1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x4c]
-; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x4c]
-; CHECK: ld1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x0c]
-; CHECK: ld1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x0c]
-; CHECK: ld1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x0c]
-; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x0c]
-; CHECK: ld1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x4c]
-; CHECK: ld1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x4c]
-; CHECK: ld1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x4c]
-; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x4c]
-; CHECK: st1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x0c]
-; CHECK: st1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x0c]
-; CHECK: st1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x0c]
-; CHECK: st1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x0c]
-; CHECK: st1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x4c]
-; CHECK: st1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x4c]
-; CHECK: st1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x4c]
-; CHECK: st1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x4c]
-; CHECK: st1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x0c]
-; CHECK: st1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x0c]
-; CHECK: st1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x0c]
-; CHECK: st1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x0c]
-; CHECK: st1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x4c]
-; CHECK: st1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x4c]
-; CHECK: st1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x4c]
-; CHECK: st1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x4c]
-; CHECK: st1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x0c]
-; CHECK: st1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x0c]
-; CHECK: st1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x0c]
-; CHECK: st1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x0c]
-; CHECK: st1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x4c]
-; CHECK: st1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x4c]
-; CHECK: st1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x4c]
-; CHECK: st1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x4c]
-; CHECK: st1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x0c]
-; CHECK: st1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x0c]
-; CHECK: st1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x0c]
-; CHECK: st1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x0c]
-; CHECK: st1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x4c]
-; CHECK: st1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x4c]
-; CHECK: st1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x4c]
-; CHECK: st1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x4c]
-; CHECK: ld2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x0c]
-; CHECK: ld2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x4c]
-; CHECK: ld2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x0c]
-; CHECK: ld2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x4c]
-; CHECK: ld2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x0c]
-; CHECK: ld2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x4c]
-; CHECK: ld2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x40,0x4c]
-; CHECK: st2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x0c]
-; CHECK: st2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x4c]
-; CHECK: st2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x0c]
-; CHECK: st2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x4c]
-; CHECK: st2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x0c]
-; CHECK: st2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x4c]
-; CHECK: st2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x00,0x4c]
-; CHECK: ld3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x0c]
-; CHECK: ld3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x0c]
-; CHECK: ld3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x4c]
-; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x4c]
-; CHECK: ld3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x40,0x4c]
-; CHECK: st3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x0c]
-; CHECK: st3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x4c]
-; CHECK: st3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x0c]
-; CHECK: st3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x4c]
-; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x4c]
-; CHECK: st3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x00,0x4c]
-; CHECK: ld4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x0c]
-; CHECK: ld4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x4c]
-; CHECK: ld4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x0c]
-; CHECK: ld4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x4c]
-; CHECK: ld4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x0c]
-; CHECK: ld4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x4c]
-; CHECK: ld4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x40,0x4c]
-; CHECK: st4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x0c]
-; CHECK: st4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x4c]
-; CHECK: st4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x0c]
-; CHECK: st4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x4c]
-; CHECK: st4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x0c]
-; CHECK: st4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x4c]
-; CHECK: st4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x00,0x4c]
-; CHECK: ld1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x0c]
-; CHECK: ld1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x0c]
-; CHECK: ld1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x0c]
-; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x0c]
-; CHECK: ld1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x4c]
-; CHECK: ld1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x4c]
-; CHECK: ld1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x4c]
-; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x4c]
-; CHECK: ld1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x0c]
-; CHECK: ld1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x0c]
-; CHECK: ld1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x0c]
-; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x0c]
-; CHECK: ld1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x4c]
-; CHECK: ld1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x4c]
-; CHECK: ld1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x4c]
-; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x4c]
-; CHECK: ld1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x0c]
-; CHECK: ld1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x0c]
-; CHECK: ld1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x0c]
-; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x0c]
-; CHECK: ld1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x4c]
-; CHECK: ld1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x4c]
-; CHECK: ld1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x4c]
-; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x4c]
-; CHECK: ld1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x0c]
-; CHECK: ld1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x0c]
-; CHECK: ld1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x0c]
-; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x0c]
-; CHECK: ld1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x4c]
-; CHECK: ld1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x4c]
-; CHECK: ld1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x4c]
-; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x4c]
-; CHECK: st1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x0c]
-; CHECK: st1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x0c]
-; CHECK: st1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x0c]
-; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x0c]
-; CHECK: st1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x4c]
-; CHECK: st1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x4c]
-; CHECK: st1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x4c]
-; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x4c]
-; CHECK: st1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x0c]
-; CHECK: st1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x0c]
-; CHECK: st1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x0c]
-; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x0c]
-; CHECK: st1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x4c]
-; CHECK: st1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x4c]
-; CHECK: st1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x4c]
-; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x4c]
-; CHECK: st1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x0c]
-; CHECK: st1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x0c]
-; CHECK: st1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x0c]
-; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x0c]
-; CHECK: st1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x4c]
-; CHECK: st1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x4c]
-; CHECK: st1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x4c]
-; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x4c]
-; CHECK: st1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x0c]
-; CHECK: st1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x0c]
-; CHECK: st1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x0c]
-; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x0c]
-; CHECK: st1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x4c]
-; CHECK: st1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x4c]
-; CHECK: st1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x4c]
-; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x4c]
-; CHECK: ld1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0xdf,0x0c]
-; CHECK: ld1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0xdf,0x0c]
-; CHECK: ld1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0xdf,0x0c]
-; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0xdf,0x0c]
-; CHECK: ld1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0xdf,0x4c]
-; CHECK: ld1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0xdf,0x4c]
-; CHECK: ld1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0xdf,0x4c]
-; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0xdf,0x4c]
-; CHECK: ld1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0xdf,0x0c]
-; CHECK: ld1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0xdf,0x0c]
-; CHECK: ld1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0xdf,0x0c]
-; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0xdf,0x0c]
-; CHECK: ld1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0xdf,0x4c]
-; CHECK: ld1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0xdf,0x4c]
-; CHECK: ld1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0xdf,0x4c]
-; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0xdf,0x4c]
-; CHECK: ld1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0xdf,0x0c]
-; CHECK: ld1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0xdf,0x0c]
-; CHECK: ld1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0xdf,0x0c]
-; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0xdf,0x0c]
-; CHECK: ld1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0xdf,0x4c]
-; CHECK: ld1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0xdf,0x4c]
-; CHECK: ld1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0xdf,0x4c]
-; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0xdf,0x4c]
-; CHECK: ld1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0xdf,0x0c]
-; CHECK: ld1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0xdf,0x0c]
-; CHECK: ld1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0xdf,0x0c]
-; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0xdf,0x0c]
-; CHECK: ld1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0xdf,0x4c]
-; CHECK: ld1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0xdf,0x4c]
-; CHECK: ld1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0xdf,0x4c]
-; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0xdf,0x4c]
-; CHECK: st1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0x9f,0x0c]
-; CHECK: st1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0x9f,0x0c]
-; CHECK: st1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0x9f,0x0c]
-; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0x9f,0x0c]
-; CHECK: st1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0x9f,0x4c]
-; CHECK: st1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0x9f,0x4c]
-; CHECK: st1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0x9f,0x4c]
-; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0x9f,0x4c]
-; CHECK: st1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0x9f,0x0c]
-; CHECK: st1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0x9f,0x0c]
-; CHECK: st1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0x9f,0x0c]
-; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0x9f,0x0c]
-; CHECK: st1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0x9f,0x4c]
-; CHECK: st1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0x9f,0x4c]
-; CHECK: st1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0x9f,0x4c]
-; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0x9f,0x4c]
-; CHECK: st1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0x9f,0x0c]
-; CHECK: st1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0x9f,0x0c]
-; CHECK: st1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0x9f,0x0c]
-; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0x9f,0x0c]
-; CHECK: st1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0x9f,0x4c]
-; CHECK: st1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0x9f,0x4c]
-; CHECK: st1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0x9f,0x4c]
-; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0x9f,0x4c]
-; CHECK: st1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0x9f,0x0c]
-; CHECK: st1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0x9f,0x0c]
-; CHECK: st1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0x9f,0x0c]
-; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0x9f,0x0c]
-; CHECK: st1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0x9f,0x4c]
-; CHECK: st1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0x9f,0x4c]
-; CHECK: st1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0x9f,0x4c]
-; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0x9f,0x4c]
-; CHECK: ld2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x0c]
-; CHECK: ld2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x4c]
-; CHECK: ld2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x0c]
-; CHECK: ld2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x4c]
-; CHECK: ld2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x0c]
-; CHECK: ld2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x4c]
-; CHECK: ld2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0xcf,0x4c]
-; CHECK: st2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x0c]
-; CHECK: st2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x4c]
-; CHECK: st2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x0c]
-; CHECK: st2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x4c]
-; CHECK: st2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x0c]
-; CHECK: st2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x4c]
-; CHECK: st2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0x8f,0x4c]
-; CHECK: ld2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0xdf,0x0c]
-; CHECK: ld2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0xdf,0x4c]
-; CHECK: ld2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0xdf,0x0c]
-; CHECK: ld2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0xdf,0x4c]
-; CHECK: ld2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0xdf,0x0c]
-; CHECK: ld2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0xdf,0x4c]
-; CHECK: ld2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0xdf,0x4c]
-; CHECK: st2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0x9f,0x0c]
-; CHECK: st2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0x9f,0x4c]
-; CHECK: st2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0x9f,0x0c]
-; CHECK: st2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0x9f,0x4c]
-; CHECK: st2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0x9f,0x0c]
-; CHECK: st2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0x9f,0x4c]
-; CHECK: st2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0x9f,0x4c]
-; CHECK: ld3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x0c]
-; CHECK: ld3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x4c]
-; CHECK: ld3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x0c]
-; CHECK: ld3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x4c]
-; CHECK: ld3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x0c]
-; CHECK: ld3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x4c]
-; CHECK: ld3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0xcf,0x4c]
-; CHECK: st3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x0c]
-; CHECK: st3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x4c]
-; CHECK: st3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x0c]
-; CHECK: st3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x4c]
-; CHECK: st3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x0c]
-; CHECK: st3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x4c]
-; CHECK: st3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0x8f,0x4c]
-; CHECK: ld3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0xdf,0x0c]
-; CHECK: ld3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0xdf,0x4c]
-; CHECK: ld3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0xdf,0x0c]
-; CHECK: ld3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0xdf,0x4c]
-; CHECK: ld3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0xdf,0x0c]
-; CHECK: ld3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0xdf,0x4c]
-; CHECK: ld3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0xdf,0x4c]
-; CHECK: st3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0x9f,0x0c]
-; CHECK: st3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0x9f,0x4c]
-; CHECK: st3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0x9f,0x0c]
-; CHECK: st3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0x9f,0x4c]
-; CHECK: st3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0x9f,0x0c]
-; CHECK: st3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0x9f,0x4c]
-; CHECK: st3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0x9f,0x4c]
-; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x0c]
-; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x4c]
-; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x0c]
-; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x4c]
-; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x0c]
-; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x4c]
-; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0xcf,0x4c]
-; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x0c]
-; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x4c]
-; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x0c]
-; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x4c]
-; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x0c]
-; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x4c]
-; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0x8f,0x4c]
-; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0xdf,0x0c]
-; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0xdf,0x4c]
-; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0xdf,0x0c]
-; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0xdf,0x4c]
-; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0xdf,0x0c]
-; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0xdf,0x4c]
-; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0xdf,0x4c]
-; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0x9f,0x0c]
-; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0x9f,0x4c]
-; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0x9f,0x0c]
-; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0x9f,0x4c]
-; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0x9f,0x0c]
-; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0x9f,0x4c]
-; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0x9f,0x4c]
-; CHECK: ld1r.8b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x0d]
-; CHECK: ld1r.8b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x0d]
-; CHECK: ld1r.16b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x4d]
-; CHECK: ld1r.16b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x4d]
-; CHECK: ld1r.4h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x0d]
-; CHECK: ld1r.4h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x0d]
-; CHECK: ld1r.8h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x4d]
-; CHECK: ld1r.8h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x4d]
-; CHECK: ld1r.2s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x0d]
-; CHECK: ld1r.2s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x0d]
-; CHECK: ld1r.4s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x4d]
-; CHECK: ld1r.4s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x4d]
-; CHECK: ld1r.1d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x0d]
-; CHECK: ld1r.1d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x0d]
-; CHECK: ld1r.2d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x4d]
-; CHECK: ld1r.2d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x4d]
-; CHECK: ld1r.8b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x0d]
-; CHECK: ld1r.16b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x4d]
-; CHECK: ld1r.4h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x0d]
-; CHECK: ld1r.8h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x4d]
-; CHECK: ld1r.2s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x0d]
-; CHECK: ld1r.4s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x4d]
-; CHECK: ld1r.1d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x0d]
-; CHECK: ld1r.2d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x4d]
-; CHECK: ld2r.8b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x0d]
-; CHECK: ld2r.8b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x0d]
-; CHECK: ld2r.16b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x4d]
-; CHECK: ld2r.16b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x4d]
-; CHECK: ld2r.4h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x0d]
-; CHECK: ld2r.4h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x0d]
-; CHECK: ld2r.8h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x4d]
-; CHECK: ld2r.8h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x4d]
-; CHECK: ld2r.2s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x0d]
-; CHECK: ld2r.2s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x0d]
-; CHECK: ld2r.4s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x4d]
-; CHECK: ld2r.4s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x4d]
-; CHECK: ld2r.1d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x0d]
-; CHECK: ld2r.1d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x0d]
-; CHECK: ld2r.2d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x4d]
-; CHECK: ld2r.2d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x4d]
-; CHECK: ld2r.8b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x0d]
-; CHECK: ld2r.16b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x4d]
-; CHECK: ld2r.4h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x0d]
-; CHECK: ld2r.8h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x4d]
-; CHECK: ld2r.2s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x0d]
-; CHECK: ld2r.4s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x4d]
-; CHECK: ld2r.1d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x0d]
-; CHECK: ld2r.2d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x4d]
-; CHECK: ld3r.8b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x0d]
-; CHECK: ld3r.8b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x0d]
-; CHECK: ld3r.16b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x4d]
-; CHECK: ld3r.16b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x4d]
-; CHECK: ld3r.4h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x0d]
-; CHECK: ld3r.4h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x0d]
-; CHECK: ld3r.8h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x4d]
-; CHECK: ld3r.8h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x4d]
-; CHECK: ld3r.2s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x0d]
-; CHECK: ld3r.2s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x0d]
-; CHECK: ld3r.4s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x4d]
-; CHECK: ld3r.4s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x4d]
-; CHECK: ld3r.1d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x0d]
-; CHECK: ld3r.1d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x0d]
-; CHECK: ld3r.2d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x4d]
-; CHECK: ld3r.2d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x4d]
-; CHECK: ld3r.8b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x0d]
-; CHECK: ld3r.16b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x4d]
-; CHECK: ld3r.4h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x0d]
-; CHECK: ld3r.8h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x4d]
-; CHECK: ld3r.2s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x0d]
-; CHECK: ld3r.4s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x4d]
-; CHECK: ld3r.1d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x0d]
-; CHECK: ld3r.2d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x4d]
-; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x0d]
-; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x0d]
-; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x4d]
-; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x4d]
-; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x0d]
-; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x0d]
-; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x4d]
-; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x4d]
-; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x0d]
-; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x0d]
-; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x4d]
-; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x4d]
-; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x0d]
-; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x0d]
-; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x4d]
-; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x4d]
-; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x0d]
-; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x4d]
-; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x0d]
-; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x4d]
-; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d]
-; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x4d]
-; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x0d]
-; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x4d]
-; CHECK: ld1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x40,0x4d]
-; CHECK: ld1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x40,0x0d]
-; CHECK: ld1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x40,0x4d]
-; CHECK: ld1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x40,0x4d]
-; CHECK: ld1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0xc5,0x4d]
-; CHECK: ld1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0xc5,0x0d]
-; CHECK: ld1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0xc5,0x4d]
-; CHECK: ld1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0xc5,0x4d]
-; CHECK: ld1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0xdf,0x4d]
-; CHECK: ld1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0xdf,0x0d]
-; CHECK: ld1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0xdf,0x4d]
-; CHECK: ld1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0xdf,0x4d]
-; CHECK: ld2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x60,0x4d]
-; CHECK: ld2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x60,0x0d]
-; CHECK: ld2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x60,0x4d]
-; CHECK: ld2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x60,0x4d]
-; CHECK: ld2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xe5,0x4d]
-; CHECK: ld2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xe5,0x0d]
-; CHECK: ld2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xe5,0x4d]
-; CHECK: ld2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xe5,0x4d]
-; CHECK: ld2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xff,0x4d]
-; CHECK: ld2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xff,0x0d]
-; CHECK: ld2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xff,0x4d]
-; CHECK: ld2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xff,0x4d]
-; CHECK: ld3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x40,0x4d]
-; CHECK: ld3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x40,0x0d]
-; CHECK: ld3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x40,0x4d]
-; CHECK: ld3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x40,0x4d]
-; CHECK: ld3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0xc5,0x4d]
-; CHECK: ld3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0xc5,0x0d]
-; CHECK: ld3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xc5,0x4d]
-; CHECK: ld3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xc5,0x4d]
-; CHECK: ld3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0xdf,0x4d]
-; CHECK: ld3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0xdf,0x0d]
-; CHECK: ld3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0xdf,0x4d]
-; CHECK: ld3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0xdf,0x4d]
-; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x60,0x4d]
-; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x60,0x0d]
-; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x60,0x4d]
-; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x60,0x4d]
-; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xe5,0x4d]
-; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xe5,0x0d]
-; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xe5,0x4d]
-; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xe5,0x4d]
-; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xff,0x4d]
-; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xff,0x0d]
-; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xff,0x4d]
-; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xff,0x4d]
-; CHECK: st1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x00,0x4d]
-; CHECK: st1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x00,0x0d]
-; CHECK: st1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x00,0x4d]
-; CHECK: st1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x00,0x4d]
-; CHECK: st1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0x85,0x4d]
-; CHECK: st1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0x85,0x0d]
-; CHECK: st1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0x85,0x4d]
-; CHECK: st1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0x85,0x4d]
-; CHECK: st1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0x9f,0x4d]
-; CHECK: st1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0x9f,0x0d]
-; CHECK: st1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0x9f,0x4d]
-; CHECK: st1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0x9f,0x4d]
-; CHECK: st2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x20,0x4d]
-; CHECK: st2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x20,0x0d]
-; CHECK: st2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x20,0x4d]
-; CHECK: st2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x20,0x4d]
-; CHECK: st2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xa5,0x4d]
-; CHECK: st2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xa5,0x0d]
-; CHECK: st2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xa5,0x4d]
-; CHECK: st2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xa5,0x4d]
-; CHECK: st2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xbf,0x4d]
-; CHECK: st2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xbf,0x0d]
-; CHECK: st2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xbf,0x4d]
-; CHECK: st2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xbf,0x4d]
-; CHECK: st3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x00,0x4d]
-; CHECK: st3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x00,0x0d]
-; CHECK: st3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x00,0x4d]
-; CHECK: st3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x00,0x4d]
-; CHECK: st3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0x85,0x4d]
-; CHECK: st3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0x85,0x0d]
-; CHECK: st3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0x85,0x4d]
-; CHECK: st3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0x85,0x4d]
-; CHECK: st3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0x9f,0x4d]
-; CHECK: st3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0x9f,0x0d]
-; CHECK: st3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0x9f,0x4d]
-; CHECK: st3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0x9f,0x4d]
-; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x20,0x4d]
-; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x20,0x0d]
-; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x20,0x4d]
-; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x20,0x4d]
-; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xa5,0x4d]
-; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xa5,0x0d]
-; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xa5,0x4d]
-; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xa5,0x4d]
-; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xbf,0x4d]
-; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xbf,0x0d]
-; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xbf,0x4d]
-; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xbf,0x4d]
Removed: llvm/trunk/test/MC/ARM64/small-data-fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/small-data-fixups.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/small-data-fixups.s (original)
+++ llvm/trunk/test/MC/ARM64/small-data-fixups.s (removed)
@@ -1,24 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o - %s | macho-dump | FileCheck %s
-
-foo:
- .long 0
-bar:
- .long 1
-
-baz:
- .byte foo - bar
- .short foo - bar
-
-; CHECK: # Relocation 0
-; CHECK: (('word-0', 0x9),
-; CHECK: ('word-1', 0x1a000002)),
-; CHECK: # Relocation 1
-; CHECK: (('word-0', 0x9),
-; CHECK: ('word-1', 0xa000001)),
-; CHECK: # Relocation 2
-; CHECK: (('word-0', 0x8),
-; CHECK: ('word-1', 0x18000002)),
-; CHECK: # Relocation 3
-; CHECK: (('word-0', 0x8),
-; CHECK: ('word-1', 0x8000001)),
-
Removed: llvm/trunk/test/MC/ARM64/spsel-sysreg.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/spsel-sysreg.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/spsel-sysreg.s (original)
+++ llvm/trunk/test/MC/ARM64/spsel-sysreg.s (removed)
@@ -1,24 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s
-// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-msr SPSel, #0
-msr SPSel, x0
-msr DAIFSet, #0
-msr ESR_EL1, x0
-mrs x0, SPSel
-mrs x0, ESR_EL1
-
-// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5]
-// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5]
-// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5]
-// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5]
-// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5]
-// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5]
-
-
-msr DAIFSet, x0
-msr ESR_EL1, #0
-mrs x0, DAIFSet
-// CHECK-ERRORS: error: immediate must be an integer in range [0, 15]
-// CHECK-ERRORS: error: invalid operand for instruction
-// CHECK-ERRORS: error: expected readable system register
Removed: llvm/trunk/test/MC/ARM64/system-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/system-encoding.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/system-encoding.s (original)
+++ llvm/trunk/test/MC/ARM64/system-encoding.s (removed)
@@ -1,623 +0,0 @@
-; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
-; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
-foo:
-
-;-----------------------------------------------------------------------------
-; Simple encodings (instuctions w/ no operands)
-;-----------------------------------------------------------------------------
-
- nop
- sev
- sevl
- wfe
- wfi
- yield
-
-; CHECK: nop ; encoding: [0x1f,0x20,0x03,0xd5]
-; CHECK: sev ; encoding: [0x9f,0x20,0x03,0xd5]
-; CHECK: sevl ; encoding: [0xbf,0x20,0x03,0xd5]
-; CHECK: wfe ; encoding: [0x5f,0x20,0x03,0xd5]
-; CHECK: wfi ; encoding: [0x7f,0x20,0x03,0xd5]
-; CHECK: yield ; encoding: [0x3f,0x20,0x03,0xd5]
-
-;-----------------------------------------------------------------------------
-; Single-immediate operand instructions
-;-----------------------------------------------------------------------------
-
- clrex #10
-; CHECK: clrex #10 ; encoding: [0x5f,0x3a,0x03,0xd5]
- isb #15
- isb sy
-; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5]
-; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5]
- dmb #3
- dmb osh
-; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
-; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
- dsb #7
- dsb nsh
-; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5]
-; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5]
-
-;-----------------------------------------------------------------------------
-; Generic system instructions
-;-----------------------------------------------------------------------------
- sys #2, c0, c5, #7
-; CHECK: encoding: [0xff,0x05,0x0a,0xd5]
- sys #7, C6, c10, #7, x7
-; CHECK: encoding: [0xe7,0x6a,0x0f,0xd5]
- sysl x20, #6, c3, C15, #7
-; CHECK: encoding: [0xf4,0x3f,0x2e,0xd5]
-
-; Check for error on invalid 'C' operand value.
- sys #2, c16, c5, #7
-; CHECK-ERRORS: error: Expected cN operand where 0 <= N <= 15
-
-;-----------------------------------------------------------------------------
-; MSR/MRS instructions
-;-----------------------------------------------------------------------------
- msr ACTLR_EL1, x3
- msr ACTLR_EL2, x3
- msr ACTLR_EL3, x3
- msr AFSR0_EL1, x3
- msr AFSR0_EL2, x3
- msr AFSR0_EL3, x3
- msr AFSR1_EL1, x3
- msr AFSR1_EL2, x3
- msr AFSR1_EL3, x3
- msr AMAIR_EL1, x3
- msr AMAIR_EL2, x3
- msr AMAIR_EL3, x3
- msr CNTFRQ_EL0, x3
- msr CNTHCTL_EL2, x3
- msr CNTHP_CTL_EL2, x3
- msr CNTHP_CVAL_EL2, x3
- msr CNTHP_TVAL_EL2, x3
- msr CNTKCTL_EL1, x3
- msr CNTP_CTL_EL0, x3
- msr CNTP_CVAL_EL0, x3
- msr CNTP_TVAL_EL0, x3
- msr CNTVOFF_EL2, x3
- msr CNTV_CTL_EL0, x3
- msr CNTV_CVAL_EL0, x3
- msr CNTV_TVAL_EL0, x3
- msr CONTEXTIDR_EL1, x3
- msr CPACR_EL1, x3
- msr CPTR_EL2, x3
- msr CPTR_EL3, x3
- msr CSSELR_EL1, x3
- msr CURRENTEL, x3
- msr DACR32_EL2, x3
- msr ESR_EL1, x3
- msr ESR_EL2, x3
- msr ESR_EL3, x3
- msr FAR_EL1, x3
- msr FAR_EL2, x3
- msr FAR_EL3, x3
- msr FPEXC32_EL2, x3
- msr HACR_EL2, x3
- msr HCR_EL2, x3
- msr HPFAR_EL2, x3
- msr HSTR_EL2, x3
- msr IFSR32_EL2, x3
- msr MAIR_EL1, x3
- msr MAIR_EL2, x3
- msr MAIR_EL3, x3
- msr MDCR_EL2, x3
- msr MDCR_EL3, x3
- msr PAR_EL1, x3
- msr SCR_EL3, x3
- msr SCTLR_EL1, x3
- msr SCTLR_EL2, x3
- msr SCTLR_EL3, x3
- msr SDER32_EL3, x3
- msr TCR_EL1, x3
- msr TCR_EL2, x3
- msr TCR_EL3, x3
- msr TEECR32_EL1, x3
- msr TEEHBR32_EL1, x3
- msr TPIDRRO_EL0, x3
- msr TPIDR_EL0, x3
- msr TPIDR_EL1, x3
- msr TPIDR_EL2, x3
- msr TPIDR_EL3, x3
- msr TTBR0_EL1, x3
- msr TTBR0_EL2, x3
- msr TTBR0_EL3, x3
- msr TTBR1_EL1, x3
- msr VBAR_EL1, x3
- msr VBAR_EL2, x3
- msr VBAR_EL3, x3
- msr VMPIDR_EL2, x3
- msr VPIDR_EL2, x3
- msr VTCR_EL2, x3
- msr VTTBR_EL2, x3
- msr SPSel, x3
- msr S3_2_C11_C6_4, x1
-; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5]
-; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5]
-; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5]
-; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5]
-; CHECK: msr AFSR0_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5]
-; CHECK: msr AFSR0_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5]
-; CHECK: msr AFSR1_EL1, x3 ; encoding: [0x23,0x51,0x18,0xd5]
-; CHECK: msr AFSR1_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5]
-; CHECK: msr AFSR1_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5]
-; CHECK: msr AMAIR_EL1, x3 ; encoding: [0x03,0xa3,0x18,0xd5]
-; CHECK: msr AMAIR_EL2, x3 ; encoding: [0x03,0xa3,0x1c,0xd5]
-; CHECK: msr AMAIR_EL3, x3 ; encoding: [0x03,0xa3,0x1e,0xd5]
-; CHECK: msr CNTFRQ_EL0, x3 ; encoding: [0x03,0xe0,0x1b,0xd5]
-; CHECK: msr CNTHCTL_EL2, x3 ; encoding: [0x03,0xe1,0x1c,0xd5]
-; CHECK: msr CNTHP_CTL_EL2, x3 ; encoding: [0x23,0xe2,0x1c,0xd5]
-; CHECK: msr CNTHP_CVAL_EL2, x3 ; encoding: [0x43,0xe2,0x1c,0xd5]
-; CHECK: msr CNTHP_TVAL_EL2, x3 ; encoding: [0x03,0xe2,0x1c,0xd5]
-; CHECK: msr CNTKCTL_EL1, x3 ; encoding: [0x03,0xe1,0x18,0xd5]
-; CHECK: msr CNTP_CTL_EL0, x3 ; encoding: [0x23,0xe2,0x1b,0xd5]
-; CHECK: msr CNTP_CVAL_EL0, x3 ; encoding: [0x43,0xe2,0x1b,0xd5]
-; CHECK: msr CNTP_TVAL_EL0, x3 ; encoding: [0x03,0xe2,0x1b,0xd5]
-; CHECK: msr CNTVOFF_EL2, x3 ; encoding: [0x63,0xe0,0x1c,0xd5]
-; CHECK: msr CNTV_CTL_EL0, x3 ; encoding: [0x23,0xe3,0x1b,0xd5]
-; CHECK: msr CNTV_CVAL_EL0, x3 ; encoding: [0x43,0xe3,0x1b,0xd5]
-; CHECK: msr CNTV_TVAL_EL0, x3 ; encoding: [0x03,0xe3,0x1b,0xd5]
-; CHECK: msr CONTEXTIDR_EL1, x3 ; encoding: [0x23,0xd0,0x18,0xd5]
-; CHECK: msr CPACR_EL1, x3 ; encoding: [0x43,0x10,0x18,0xd5]
-; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5]
-; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5]
-; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CURRENTEL, x3 ; encoding: [0x43,0x42,0x18,0xd5]
-; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5]
-; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5]
-; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5]
-; CHECK: msr ESR_EL3, x3 ; encoding: [0x03,0x52,0x1e,0xd5]
-; CHECK: msr FAR_EL1, x3 ; encoding: [0x03,0x60,0x18,0xd5]
-; CHECK: msr FAR_EL2, x3 ; encoding: [0x03,0x60,0x1c,0xd5]
-; CHECK: msr FAR_EL3, x3 ; encoding: [0x03,0x60,0x1e,0xd5]
-; CHECK: msr FPEXC32_EL2, x3 ; encoding: [0x03,0x53,0x1c,0xd5]
-; CHECK: msr HACR_EL2, x3 ; encoding: [0xe3,0x11,0x1c,0xd5]
-; CHECK: msr HCR_EL2, x3 ; encoding: [0x03,0x11,0x1c,0xd5]
-; CHECK: msr HPFAR_EL2, x3 ; encoding: [0x83,0x60,0x1c,0xd5]
-; CHECK: msr HSTR_EL2, x3 ; encoding: [0x63,0x11,0x1c,0xd5]
-; CHECK: msr IFSR32_EL2, x3 ; encoding: [0x23,0x50,0x1c,0xd5]
-; CHECK: msr MAIR_EL1, x3 ; encoding: [0x03,0xa2,0x18,0xd5]
-; CHECK: msr MAIR_EL2, x3 ; encoding: [0x03,0xa2,0x1c,0xd5]
-; CHECK: msr MAIR_EL3, x3 ; encoding: [0x03,0xa2,0x1e,0xd5]
-; CHECK: msr MDCR_EL2, x3 ; encoding: [0x23,0x11,0x1c,0xd5]
-; CHECK: msr MDCR_EL3, x3 ; encoding: [0x23,0x13,0x1e,0xd5]
-; CHECK: msr PAR_EL1, x3 ; encoding: [0x03,0x74,0x18,0xd5]
-; CHECK: msr SCR_EL3, x3 ; encoding: [0x03,0x11,0x1e,0xd5]
-; CHECK: msr SCTLR_EL1, x3 ; encoding: [0x03,0x10,0x18,0xd5]
-; CHECK: msr SCTLR_EL2, x3 ; encoding: [0x03,0x10,0x1c,0xd5]
-; CHECK: msr SCTLR_EL3, x3 ; encoding: [0x03,0x10,0x1e,0xd5]
-; CHECK: msr SDER32_EL3, x3 ; encoding: [0x23,0x11,0x1e,0xd5]
-; CHECK: msr TCR_EL1, x3 ; encoding: [0x43,0x20,0x18,0xd5]
-; CHECK: msr TCR_EL2, x3 ; encoding: [0x43,0x20,0x1c,0xd5]
-; CHECK: msr TCR_EL3, x3 ; encoding: [0x43,0x20,0x1e,0xd5]
-; CHECK: msr TEECR32_EL1, x3 ; encoding: [0x03,0x00,0x12,0xd5]
-; CHECK: msr TEEHBR32_EL1, x3 ; encoding: [0x03,0x10,0x12,0xd5]
-; CHECK: msr TPIDRRO_EL0, x3 ; encoding: [0x63,0xd0,0x1b,0xd5]
-; CHECK: msr TPIDR_EL0, x3 ; encoding: [0x43,0xd0,0x1b,0xd5]
-; CHECK: msr TPIDR_EL1, x3 ; encoding: [0x83,0xd0,0x18,0xd5]
-; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5]
-; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5]
-; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5]
-; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5]
-; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5]
-; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5]
-; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5]
-; CHECK: msr VBAR_EL2, x3 ; encoding: [0x03,0xc0,0x1c,0xd5]
-; CHECK: msr VBAR_EL3, x3 ; encoding: [0x03,0xc0,0x1e,0xd5]
-; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5]
-; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5]
-; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5]
-; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5]
-; CHECK: msr SPSEL, x3 ; encoding: [0x03,0x42,0x18,0xd5]
-; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5]
-
- mrs x3, ACTLR_EL1
- mrs x3, ACTLR_EL2
- mrs x3, ACTLR_EL3
- mrs x3, AFSR0_EL1
- mrs x3, AFSR0_EL2
- mrs x3, AFSR0_EL3
- mrs x3, AIDR_EL1
- mrs x3, AFSR1_EL1
- mrs x3, AFSR1_EL2
- mrs x3, AFSR1_EL3
- mrs x3, AMAIR_EL1
- mrs x3, AMAIR_EL2
- mrs x3, AMAIR_EL3
- mrs x3, CCSIDR_EL1
- mrs x3, CLIDR_EL1
- mrs x3, CNTFRQ_EL0
- mrs x3, CNTHCTL_EL2
- mrs x3, CNTHP_CTL_EL2
- mrs x3, CNTHP_CVAL_EL2
- mrs x3, CNTHP_TVAL_EL2
- mrs x3, CNTKCTL_EL1
- mrs x3, CNTPCT_EL0
- mrs x3, CNTP_CTL_EL0
- mrs x3, CNTP_CVAL_EL0
- mrs x3, CNTP_TVAL_EL0
- mrs x3, CNTVCT_EL0
- mrs x3, CNTVOFF_EL2
- mrs x3, CNTV_CTL_EL0
- mrs x3, CNTV_CVAL_EL0
- mrs x3, CNTV_TVAL_EL0
- mrs x3, CONTEXTIDR_EL1
- mrs x3, CPACR_EL1
- mrs x3, CPTR_EL2
- mrs x3, CPTR_EL3
- mrs x3, CSSELR_EL1
- mrs x3, CTR_EL0
- mrs x3, CURRENTEL
- mrs x3, DACR32_EL2
- mrs x3, DCZID_EL0
- mrs x3, REVIDR_EL1
- mrs x3, ESR_EL1
- mrs x3, ESR_EL2
- mrs x3, ESR_EL3
- mrs x3, FAR_EL1
- mrs x3, FAR_EL2
- mrs x3, FAR_EL3
- mrs x3, FPEXC32_EL2
- mrs x3, HACR_EL2
- mrs x3, HCR_EL2
- mrs x3, HPFAR_EL2
- mrs x3, HSTR_EL2
- mrs x3, ID_AA64DFR0_EL1
- mrs x3, ID_AA64DFR1_EL1
- mrs x3, ID_AA64ISAR0_EL1
- mrs x3, ID_AA64ISAR1_EL1
- mrs x3, ID_AA64MMFR0_EL1
- mrs x3, ID_AA64MMFR1_EL1
- mrs x3, ID_AA64PFR0_EL1
- mrs x3, ID_AA64PFR1_EL1
- mrs x3, IFSR32_EL2
- mrs x3, ISR_EL1
- mrs x3, MAIR_EL1
- mrs x3, MAIR_EL2
- mrs x3, MAIR_EL3
- mrs x3, MDCR_EL2
- mrs x3, MDCR_EL3
- mrs x3, MIDR_EL1
- mrs x3, MPIDR_EL1
- mrs x3, MVFR0_EL1
- mrs x3, MVFR1_EL1
- mrs x3, PAR_EL1
- mrs x3, RVBAR_EL1
- mrs x3, RVBAR_EL2
- mrs x3, RVBAR_EL3
- mrs x3, SCR_EL3
- mrs x3, SCTLR_EL1
- mrs x3, SCTLR_EL2
- mrs x3, SCTLR_EL3
- mrs x3, SDER32_EL3
- mrs x3, TCR_EL1
- mrs x3, TCR_EL2
- mrs x3, TCR_EL3
- mrs x3, TEECR32_EL1
- mrs x3, TEEHBR32_EL1
- mrs x3, TPIDRRO_EL0
- mrs x3, TPIDR_EL0
- mrs x3, TPIDR_EL1
- mrs x3, TPIDR_EL2
- mrs x3, TPIDR_EL3
- mrs x3, TTBR0_EL1
- mrs x3, TTBR0_EL2
- mrs x3, TTBR0_EL3
- mrs x3, TTBR1_EL1
- mrs x3, VBAR_EL1
- mrs x3, VBAR_EL2
- mrs x3, VBAR_EL3
- mrs x3, VMPIDR_EL2
- mrs x3, VPIDR_EL2
- mrs x3, VTCR_EL2
- mrs x3, VTTBR_EL2
-
- mrs x3, MDCCSR_EL0
- mrs x3, MDCCINT_EL1
- mrs x3, DBGDTR_EL0
- mrs x3, DBGDTRRX_EL0
- mrs x3, DBGVCR32_EL2
- mrs x3, OSDTRRX_EL1
- mrs x3, MDSCR_EL1
- mrs x3, OSDTRTX_EL1
- mrs x3, OSECCR_EL1
- mrs x3, DBGBVR0_EL1
- mrs x3, DBGBVR1_EL1
- mrs x3, DBGBVR2_EL1
- mrs x3, DBGBVR3_EL1
- mrs x3, DBGBVR4_EL1
- mrs x3, DBGBVR5_EL1
- mrs x3, DBGBVR6_EL1
- mrs x3, DBGBVR7_EL1
- mrs x3, DBGBVR8_EL1
- mrs x3, DBGBVR9_EL1
- mrs x3, DBGBVR10_EL1
- mrs x3, DBGBVR11_EL1
- mrs x3, DBGBVR12_EL1
- mrs x3, DBGBVR13_EL1
- mrs x3, DBGBVR14_EL1
- mrs x3, DBGBVR15_EL1
- mrs x3, DBGBCR0_EL1
- mrs x3, DBGBCR1_EL1
- mrs x3, DBGBCR2_EL1
- mrs x3, DBGBCR3_EL1
- mrs x3, DBGBCR4_EL1
- mrs x3, DBGBCR5_EL1
- mrs x3, DBGBCR6_EL1
- mrs x3, DBGBCR7_EL1
- mrs x3, DBGBCR8_EL1
- mrs x3, DBGBCR9_EL1
- mrs x3, DBGBCR10_EL1
- mrs x3, DBGBCR11_EL1
- mrs x3, DBGBCR12_EL1
- mrs x3, DBGBCR13_EL1
- mrs x3, DBGBCR14_EL1
- mrs x3, DBGBCR15_EL1
- mrs x3, DBGWVR0_EL1
- mrs x3, DBGWVR1_EL1
- mrs x3, DBGWVR2_EL1
- mrs x3, DBGWVR3_EL1
- mrs x3, DBGWVR4_EL1
- mrs x3, DBGWVR5_EL1
- mrs x3, DBGWVR6_EL1
- mrs x3, DBGWVR7_EL1
- mrs x3, DBGWVR8_EL1
- mrs x3, DBGWVR9_EL1
- mrs x3, DBGWVR10_EL1
- mrs x3, DBGWVR11_EL1
- mrs x3, DBGWVR12_EL1
- mrs x3, DBGWVR13_EL1
- mrs x3, DBGWVR14_EL1
- mrs x3, DBGWVR15_EL1
- mrs x3, DBGWCR0_EL1
- mrs x3, DBGWCR1_EL1
- mrs x3, DBGWCR2_EL1
- mrs x3, DBGWCR3_EL1
- mrs x3, DBGWCR4_EL1
- mrs x3, DBGWCR5_EL1
- mrs x3, DBGWCR6_EL1
- mrs x3, DBGWCR7_EL1
- mrs x3, DBGWCR8_EL1
- mrs x3, DBGWCR9_EL1
- mrs x3, DBGWCR10_EL1
- mrs x3, DBGWCR11_EL1
- mrs x3, DBGWCR12_EL1
- mrs x3, DBGWCR13_EL1
- mrs x3, DBGWCR14_EL1
- mrs x3, DBGWCR15_EL1
- mrs x3, MDRAR_EL1
- mrs x3, OSLSR_EL1
- mrs x3, OSDLR_EL1
- mrs x3, DBGPRCR_EL1
- mrs x3, DBGCLAIMSET_EL1
- mrs x3, DBGCLAIMCLR_EL1
- mrs x3, DBGAUTHSTATUS_EL1
- mrs x1, S3_2_C15_C6_4
- mrs x3, s3_3_c11_c1_4
- mrs x3, S3_3_c11_c1_4
-
-; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5]
-; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5]
-; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5]
-; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5]
-; CHECK: mrs x3, AFSR0_EL2 ; encoding: [0x03,0x51,0x3c,0xd5]
-; CHECK: mrs x3, AFSR0_EL3 ; encoding: [0x03,0x51,0x3e,0xd5]
-; CHECK: mrs x3, AIDR_EL1 ; encoding: [0xe3,0x00,0x39,0xd5]
-; CHECK: mrs x3, AFSR1_EL1 ; encoding: [0x23,0x51,0x38,0xd5]
-; CHECK: mrs x3, AFSR1_EL2 ; encoding: [0x23,0x51,0x3c,0xd5]
-; CHECK: mrs x3, AFSR1_EL3 ; encoding: [0x23,0x51,0x3e,0xd5]
-; CHECK: mrs x3, AMAIR_EL1 ; encoding: [0x03,0xa3,0x38,0xd5]
-; CHECK: mrs x3, AMAIR_EL2 ; encoding: [0x03,0xa3,0x3c,0xd5]
-; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5]
-; CHECK: mrs x3, CCSIDR_EL1 ; encoding: [0x03,0x00,0x39,0xd5]
-; CHECK: mrs x3, CLIDR_EL1 ; encoding: [0x23,0x00,0x39,0xd5]
-; CHECK: mrs x3, CNTFRQ_EL0 ; encoding: [0x03,0xe0,0x3b,0xd5]
-; CHECK: mrs x3, CNTHCTL_EL2 ; encoding: [0x03,0xe1,0x3c,0xd5]
-; CHECK: mrs x3, CNTHP_CTL_EL2 ; encoding: [0x23,0xe2,0x3c,0xd5]
-; CHECK: mrs x3, CNTHP_CVAL_EL2 ; encoding: [0x43,0xe2,0x3c,0xd5]
-; CHECK: mrs x3, CNTHP_TVAL_EL2 ; encoding: [0x03,0xe2,0x3c,0xd5]
-; CHECK: mrs x3, CNTKCTL_EL1 ; encoding: [0x03,0xe1,0x38,0xd5]
-; CHECK: mrs x3, CNTPCT_EL0 ; encoding: [0x23,0xe0,0x3b,0xd5]
-; CHECK: mrs x3, CNTP_CTL_EL0 ; encoding: [0x23,0xe2,0x3b,0xd5]
-; CHECK: mrs x3, CNTP_CVAL_EL0 ; encoding: [0x43,0xe2,0x3b,0xd5]
-; CHECK: mrs x3, CNTP_TVAL_EL0 ; encoding: [0x03,0xe2,0x3b,0xd5]
-; CHECK: mrs x3, CNTVCT_EL0 ; encoding: [0x43,0xe0,0x3b,0xd5]
-; CHECK: mrs x3, CNTVOFF_EL2 ; encoding: [0x63,0xe0,0x3c,0xd5]
-; CHECK: mrs x3, CNTV_CTL_EL0 ; encoding: [0x23,0xe3,0x3b,0xd5]
-; CHECK: mrs x3, CNTV_CVAL_EL0 ; encoding: [0x43,0xe3,0x3b,0xd5]
-; CHECK: mrs x3, CNTV_TVAL_EL0 ; encoding: [0x03,0xe3,0x3b,0xd5]
-; CHECK: mrs x3, CONTEXTIDR_EL1 ; encoding: [0x23,0xd0,0x38,0xd5]
-; CHECK: mrs x3, CPACR_EL1 ; encoding: [0x43,0x10,0x38,0xd5]
-; CHECK: mrs x3, CPTR_EL2 ; encoding: [0x43,0x11,0x3c,0xd5]
-; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5]
-; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5]
-; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5]
-; CHECK: mrs x3, CURRENTEL ; encoding: [0x43,0x42,0x38,0xd5]
-; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5]
-; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5]
-; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5]
-; CHECK: mrs x3, ESR_EL1 ; encoding: [0x03,0x52,0x38,0xd5]
-; CHECK: mrs x3, ESR_EL2 ; encoding: [0x03,0x52,0x3c,0xd5]
-; CHECK: mrs x3, ESR_EL3 ; encoding: [0x03,0x52,0x3e,0xd5]
-; CHECK: mrs x3, FAR_EL1 ; encoding: [0x03,0x60,0x38,0xd5]
-; CHECK: mrs x3, FAR_EL2 ; encoding: [0x03,0x60,0x3c,0xd5]
-; CHECK: mrs x3, FAR_EL3 ; encoding: [0x03,0x60,0x3e,0xd5]
-; CHECK: mrs x3, FPEXC32_EL2 ; encoding: [0x03,0x53,0x3c,0xd5]
-; CHECK: mrs x3, HACR_EL2 ; encoding: [0xe3,0x11,0x3c,0xd5]
-; CHECK: mrs x3, HCR_EL2 ; encoding: [0x03,0x11,0x3c,0xd5]
-; CHECK: mrs x3, HPFAR_EL2 ; encoding: [0x83,0x60,0x3c,0xd5]
-; CHECK: mrs x3, HSTR_EL2 ; encoding: [0x63,0x11,0x3c,0xd5]
-; CHECK: mrs x3, ID_AA64DFR0_EL1 ; encoding: [0x03,0x05,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64DFR1_EL1 ; encoding: [0x23,0x05,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64ISAR0_EL1 ; encoding: [0x03,0x06,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64ISAR1_EL1 ; encoding: [0x23,0x06,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64MMFR0_EL1 ; encoding: [0x03,0x07,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64PFR0_EL1 ; encoding: [0x03,0x04,0x38,0xd5]
-; CHECK: mrs x3, ID_AA64PFR1_EL1 ; encoding: [0x23,0x04,0x38,0xd5]
-; CHECK: mrs x3, IFSR32_EL2 ; encoding: [0x23,0x50,0x3c,0xd5]
-; CHECK: mrs x3, ISR_EL1 ; encoding: [0x03,0xc1,0x38,0xd5]
-; CHECK: mrs x3, MAIR_EL1 ; encoding: [0x03,0xa2,0x38,0xd5]
-; CHECK: mrs x3, MAIR_EL2 ; encoding: [0x03,0xa2,0x3c,0xd5]
-; CHECK: mrs x3, MAIR_EL3 ; encoding: [0x03,0xa2,0x3e,0xd5]
-; CHECK: mrs x3, MDCR_EL2 ; encoding: [0x23,0x11,0x3c,0xd5]
-; CHECK: mrs x3, MDCR_EL3 ; encoding: [0x23,0x13,0x3e,0xd5]
-; CHECK: mrs x3, MIDR_EL1 ; encoding: [0x03,0x00,0x38,0xd5]
-; CHECK: mrs x3, MPIDR_EL1 ; encoding: [0xa3,0x00,0x38,0xd5]
-; CHECK: mrs x3, MVFR0_EL1 ; encoding: [0x03,0x03,0x38,0xd5]
-; CHECK: mrs x3, MVFR1_EL1 ; encoding: [0x23,0x03,0x38,0xd5]
-; CHECK: mrs x3, PAR_EL1 ; encoding: [0x03,0x74,0x38,0xd5]
-; CHECK: mrs x3, RVBAR_EL1 ; encoding: [0x23,0xc0,0x38,0xd5]
-; CHECK: mrs x3, RVBAR_EL2 ; encoding: [0x23,0xc0,0x3c,0xd5]
-; CHECK: mrs x3, RVBAR_EL3 ; encoding: [0x23,0xc0,0x3e,0xd5]
-; CHECK: mrs x3, SCR_EL3 ; encoding: [0x03,0x11,0x3e,0xd5]
-; CHECK: mrs x3, SCTLR_EL1 ; encoding: [0x03,0x10,0x38,0xd5]
-; CHECK: mrs x3, SCTLR_EL2 ; encoding: [0x03,0x10,0x3c,0xd5]
-; CHECK: mrs x3, SCTLR_EL3 ; encoding: [0x03,0x10,0x3e,0xd5]
-; CHECK: mrs x3, SDER32_EL3 ; encoding: [0x23,0x11,0x3e,0xd5]
-; CHECK: mrs x3, TCR_EL1 ; encoding: [0x43,0x20,0x38,0xd5]
-; CHECK: mrs x3, TCR_EL2 ; encoding: [0x43,0x20,0x3c,0xd5]
-; CHECK: mrs x3, TCR_EL3 ; encoding: [0x43,0x20,0x3e,0xd5]
-; CHECK: mrs x3, TEECR32_EL1 ; encoding: [0x03,0x00,0x32,0xd5]
-; CHECK: mrs x3, TEEHBR32_EL1 ; encoding: [0x03,0x10,0x32,0xd5]
-; CHECK: mrs x3, TPIDRRO_EL0 ; encoding: [0x63,0xd0,0x3b,0xd5]
-; CHECK: mrs x3, TPIDR_EL0 ; encoding: [0x43,0xd0,0x3b,0xd5]
-; CHECK: mrs x3, TPIDR_EL1 ; encoding: [0x83,0xd0,0x38,0xd5]
-; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5]
-; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5]
-; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5]
-; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5]
-; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5]
-; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5]
-; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5]
-; CHECK: mrs x3, VBAR_EL2 ; encoding: [0x03,0xc0,0x3c,0xd5]
-; CHECK: mrs x3, VBAR_EL3 ; encoding: [0x03,0xc0,0x3e,0xd5]
-; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5]
-; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5]
-; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5]
-; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5]
-; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5]
-; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5]
-; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5]
-; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5]
-; CHECK: mrs x3, DBGVCR32_EL2 ; encoding: [0x03,0x07,0x34,0xd5]
-; CHECK: mrs x3, OSDTRRX_EL1 ; encoding: [0x43,0x00,0x30,0xd5]
-; CHECK: mrs x3, MDSCR_EL1 ; encoding: [0x43,0x02,0x30,0xd5]
-; CHECK: mrs x3, OSDTRTX_EL1 ; encoding: [0x43,0x03,0x30,0xd5]
-; CHECK: mrs x3, OSECCR_EL1 ; encoding: [0x43,0x06,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR0_EL1 ; encoding: [0x83,0x00,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR1_EL1 ; encoding: [0x83,0x01,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR2_EL1 ; encoding: [0x83,0x02,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR3_EL1 ; encoding: [0x83,0x03,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR4_EL1 ; encoding: [0x83,0x04,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR5_EL1 ; encoding: [0x83,0x05,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR6_EL1 ; encoding: [0x83,0x06,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR7_EL1 ; encoding: [0x83,0x07,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR8_EL1 ; encoding: [0x83,0x08,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR9_EL1 ; encoding: [0x83,0x09,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR10_EL1 ; encoding: [0x83,0x0a,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR11_EL1 ; encoding: [0x83,0x0b,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR12_EL1 ; encoding: [0x83,0x0c,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR13_EL1 ; encoding: [0x83,0x0d,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR14_EL1 ; encoding: [0x83,0x0e,0x30,0xd5]
-; CHECK: mrs x3, DBGBVR15_EL1 ; encoding: [0x83,0x0f,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR0_EL1 ; encoding: [0xa3,0x00,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR1_EL1 ; encoding: [0xa3,0x01,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR2_EL1 ; encoding: [0xa3,0x02,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR3_EL1 ; encoding: [0xa3,0x03,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR4_EL1 ; encoding: [0xa3,0x04,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR5_EL1 ; encoding: [0xa3,0x05,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR6_EL1 ; encoding: [0xa3,0x06,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR7_EL1 ; encoding: [0xa3,0x07,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR8_EL1 ; encoding: [0xa3,0x08,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR9_EL1 ; encoding: [0xa3,0x09,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR10_EL1 ; encoding: [0xa3,0x0a,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR11_EL1 ; encoding: [0xa3,0x0b,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR12_EL1 ; encoding: [0xa3,0x0c,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR13_EL1 ; encoding: [0xa3,0x0d,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR14_EL1 ; encoding: [0xa3,0x0e,0x30,0xd5]
-; CHECK: mrs x3, DBGBCR15_EL1 ; encoding: [0xa3,0x0f,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR0_EL1 ; encoding: [0xc3,0x00,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR1_EL1 ; encoding: [0xc3,0x01,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR2_EL1 ; encoding: [0xc3,0x02,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR3_EL1 ; encoding: [0xc3,0x03,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR4_EL1 ; encoding: [0xc3,0x04,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR5_EL1 ; encoding: [0xc3,0x05,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR6_EL1 ; encoding: [0xc3,0x06,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR7_EL1 ; encoding: [0xc3,0x07,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR8_EL1 ; encoding: [0xc3,0x08,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR9_EL1 ; encoding: [0xc3,0x09,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR10_EL1 ; encoding: [0xc3,0x0a,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR11_EL1 ; encoding: [0xc3,0x0b,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR12_EL1 ; encoding: [0xc3,0x0c,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR13_EL1 ; encoding: [0xc3,0x0d,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR14_EL1 ; encoding: [0xc3,0x0e,0x30,0xd5]
-; CHECK: mrs x3, DBGWVR15_EL1 ; encoding: [0xc3,0x0f,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR0_EL1 ; encoding: [0xe3,0x00,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR1_EL1 ; encoding: [0xe3,0x01,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR2_EL1 ; encoding: [0xe3,0x02,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR3_EL1 ; encoding: [0xe3,0x03,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR4_EL1 ; encoding: [0xe3,0x04,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR5_EL1 ; encoding: [0xe3,0x05,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR6_EL1 ; encoding: [0xe3,0x06,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR7_EL1 ; encoding: [0xe3,0x07,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR8_EL1 ; encoding: [0xe3,0x08,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR9_EL1 ; encoding: [0xe3,0x09,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR10_EL1 ; encoding: [0xe3,0x0a,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR11_EL1 ; encoding: [0xe3,0x0b,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR12_EL1 ; encoding: [0xe3,0x0c,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR13_EL1 ; encoding: [0xe3,0x0d,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR14_EL1 ; encoding: [0xe3,0x0e,0x30,0xd5]
-; CHECK: mrs x3, DBGWCR15_EL1 ; encoding: [0xe3,0x0f,0x30,0xd5]
-; CHECK: mrs x3, MDRAR_EL1 ; encoding: [0x03,0x10,0x30,0xd5]
-; CHECK: mrs x3, OSLSR_EL1 ; encoding: [0x83,0x11,0x30,0xd5]
-; CHECK: mrs x3, OSDLR_EL1 ; encoding: [0x83,0x13,0x30,0xd5]
-; CHECK: mrs x3, DBGPRCR_EL1 ; encoding: [0x83,0x14,0x30,0xd5]
-; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5]
-; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5]
-; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5]
-; CHECK: mrs x1, S3_2_C15_C6_4 ; encoding: [0x81,0xf6,0x3a,0xd5]
-; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
-; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5]
-
- msr RMR_EL3, x0
- msr RMR_EL2, x0
- msr RMR_EL1, x0
- msr OSLAR_EL1, x3
- msr DBGDTRTX_EL0, x3
-
-; CHECK: msr RMR_EL3, x0 ; encoding: [0x40,0xc0,0x1e,0xd5]
-; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1c,0xd5]
-; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x18,0xd5]
-; CHECK: msr OSLAR_EL1, x3 ; encoding: [0x83,0x10,0x10,0xd5]
-; CHECK: msr DBGDTRTX_EL0, x3 ; encoding: [0x03,0x05,0x13,0xd5]
-
- mrs x0, ID_PFR0_EL1
- mrs x0, ID_PFR1_EL1
- mrs x0, ID_DFR0_EL1
- mrs x0, ID_AFR0_EL1
- mrs x0, ID_ISAR0_EL1
- mrs x0, ID_ISAR1_EL1
- mrs x0, ID_ISAR2_EL1
- mrs x0, ID_ISAR3_EL1
- mrs x0, ID_ISAR4_EL1
- mrs x0, ID_ISAR5_EL1
- mrs x0, AFSR1_EL1
- mrs x0, AFSR0_EL1
- mrs x0, REVIDR_EL1
-; CHECK: mrs x0, ID_PFR0_EL1 ; encoding: [0x00,0x01,0x38,0xd5]
-; CHECK: mrs x0, ID_PFR1_EL1 ; encoding: [0x20,0x01,0x38,0xd5]
-; CHECK: mrs x0, ID_DFR0_EL1 ; encoding: [0x40,0x01,0x38,0xd5]
-; CHECK: mrs x0, ID_AFR0_EL1 ; encoding: [0x60,0x01,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR0_EL1 ; encoding: [0x00,0x02,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR1_EL1 ; encoding: [0x20,0x02,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR2_EL1 ; encoding: [0x40,0x02,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR3_EL1 ; encoding: [0x60,0x02,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR4_EL1 ; encoding: [0x80,0x02,0x38,0xd5]
-; CHECK: mrs x0, ID_ISAR5_EL1 ; encoding: [0xa0,0x02,0x38,0xd5]
-; CHECK: mrs x0, AFSR1_EL1 ; encoding: [0x20,0x51,0x38,0xd5]
-; CHECK: mrs x0, AFSR0_EL1 ; encoding: [0x00,0x51,0x38,0xd5]
-; CHECK: mrs x0, REVIDR_EL1 ; encoding: [0xc0,0x00,0x38,0xd5]
Removed: llvm/trunk/test/MC/ARM64/target-specific-sysreg.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/target-specific-sysreg.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/target-specific-sysreg.s (original)
+++ llvm/trunk/test/MC/ARM64/target-specific-sysreg.s (removed)
@@ -1,10 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -mcpu=generic -show-encoding < %s 2>&1 | \
-// RUN: FileCheck %s --check-prefix=CHECK-GENERIC
-//
-// RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \
-// RUN: FileCheck %s --check-prefix=CHECK-CYCLONE
-
-msr CPM_IOACC_CTL_EL3, x0
-
-// CHECK-GENERIC: error: expected writable system register or pstate
-// CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5]
Removed: llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s (original)
+++ llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s (removed)
@@ -1,13 +0,0 @@
-; RUN: llvm-mc -triple=arm64-apple-ios7.0 %s -o - | FileCheck %s
-; RUN: llvm-mc -triple=arm64-apple-ios7.0 -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s --check-prefix=CHECK-OBJ
-
- adrp x2, _var at TLVPPAGE
- ldr x0, [x15, _var at TLVPPAGEOFF]
- add x30, x0, _var at TLVPPAGEOFF
-; CHECK: adrp x2, _var at TLVPPAG
-; CHECK: ldr x0, [x15, _var at TLVPPAGEOFF]
-; CHECK: add x30, x0, _var at TLVPPAGEOFF
-
-; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
-; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
-; CHECK-OBJ: 0 ARM64_RELOC_TLVP_LOAD_PAGE21 _var
Removed: llvm/trunk/test/MC/ARM64/tls-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/tls-relocs.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-relocs.s (original)
+++ llvm/trunk/test/MC/ARM64/tls-relocs.s (removed)
@@ -1,320 +0,0 @@
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
-// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \
-// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s
-
-
-////////////////////////////////////////////////////////////////////////////////
-// TLS initial-exec forms
-////////////////////////////////////////////////////////////////////////////////
-
- movz x15, #:gottprel_g1:var
-// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
-
-// CHECK-ELF: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM:[^ ]+]]
-
-
- movk x13, #:gottprel_g0_nc:var
-// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
-
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
-
- adrp x11, :gottprel:var
- ldr x10, [x0, #:gottprel_lo12:var]
- ldr x9, :gottprel:var
-// CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21
-// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58]
-// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_ldr_pcrel_imm19
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]]
-
-
-////////////////////////////////////////////////////////////////////////////////
-// TLS local-exec forms
-////////////////////////////////////////////////////////////////////////////////
-
- movz x3, #:tprel_g2:var
- movn x4, #:tprel_g2:var
-// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
-// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
-
-
- movz x5, #:tprel_g1:var
- movn x6, #:tprel_g1:var
- movz w7, #:tprel_g1:var
-// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
-
-
- movk x9, #:tprel_g1_nc:var
- movk w10, #:tprel_g1_nc:var
-// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
-// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
-
-
- movz x11, #:tprel_g0:var
- movn x12, #:tprel_g0:var
- movz w13, #:tprel_g0:var
-// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
-
-
- movk x15, #:tprel_g0_nc:var
- movk w16, #:tprel_g0_nc:var
-// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
-// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
-
-
- add x21, x22, #:tprel_lo12:var
-// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
-
-
- add x25, x26, #:tprel_lo12_nc:var
-// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
-
-
- ldrb w29, [x30, #:tprel_lo12:var]
- ldrsb x29, [x28, #:tprel_lo12_nc:var]
-// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
-
-
- strh w27, [x26, #:tprel_lo12:var]
- ldrsh x25, [x24, #:tprel_lo12_nc:var]
-// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
-// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
-
-
- ldr w23, [x22, #:tprel_lo12:var]
- ldrsw x21, [x20, #:tprel_lo12_nc:var]
-// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
-// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
-
- ldr x19, [x18, #:tprel_lo12:var]
- str x17, [x16, #:tprel_lo12_nc:var]
-// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
-
-
-////////////////////////////////////////////////////////////////////////////////
-// TLS local-dynamic forms
-////////////////////////////////////////////////////////////////////////////////
-
- movz x3, #:dtprel_g2:var
- movn x4, #:dtprel_g2:var
-// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
-// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
-
-
- movz x5, #:dtprel_g1:var
- movn x6, #:dtprel_g1:var
- movz w7, #:dtprel_g1:var
-// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
-
-
- movk x9, #:dtprel_g1_nc:var
- movk w10, #:dtprel_g1_nc:var
-// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
-// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
-
-
- movz x11, #:dtprel_g0:var
- movn x12, #:dtprel_g0:var
- movz w13, #:dtprel_g0:var
-// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
-
-
- movk x15, #:dtprel_g0_nc:var
- movk w16, #:dtprel_g0_nc:var
-// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
-// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
-
-
- add x21, x22, #:dtprel_lo12:var
-// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
-
-
- add x25, x26, #:dtprel_lo12_nc:var
-// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
-
-
- ldrb w29, [x30, #:dtprel_lo12:var]
- ldrsb x29, [x28, #:dtprel_lo12_nc:var]
-// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
-
-
- strh w27, [x26, #:dtprel_lo12:var]
- ldrsh x25, [x24, #:dtprel_lo12_nc:var]
-// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
-// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
-
-
- ldr w23, [x22, #:dtprel_lo12:var]
- ldrsw x21, [x20, #:dtprel_lo12_nc:var]
-// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
-// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
-
- ldr x19, [x18, #:dtprel_lo12:var]
- str x17, [x16, #:dtprel_lo12_nc:var]
-// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
-
-////////////////////////////////////////////////////////////////////////////////
-// TLS descriptor forms
-////////////////////////////////////////////////////////////////////////////////
-
- adrp x8, :tlsdesc:var
- ldr x7, [x6, #:tlsdesc_lo12:var]
- add x5, x4, #:tlsdesc_lo12:var
- .tlsdesccall var
- blr x3
-
-// CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21
-// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
-// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
-// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12
-// CHECK: .tlsdesccall var // encoding: []
-// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call
-// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]
-
-
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]]
-// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_CALL [[VARSYM]]
-
- // Make sure symbol 5 has type STT_TLS:
-
-// CHECK-ELF: Symbols [
-// CHECK-ELF: Symbol {
-// CHECK-ELF: Name: var
-// CHECK-ELF-NEXT: Value:
-// CHECK-ELF-NEXT: Size:
-// CHECK-ELF-NEXT: Binding: Global
-// CHECK-ELF-NEXT: Type: TLS
Removed: llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM64/v128_lo-diagnostics.s (removed)
@@ -1,11 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null
-// RUN: FileCheck %s < %t
-
- sqrdmulh v0.8h, v1.8h, v16.h[0]
-// CHECK: error: invalid operand for instruction
-
- sqrdmulh h0, h1, v16.h[0]
-// CHECK: error: invalid operand for instruction
-
- sqdmull2 v0.4h, v1.8h, v16.h[0]
-// CHECK: error: invalid operand for instruction
Removed: llvm/trunk/test/MC/ARM64/variable-exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/variable-exprs.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/variable-exprs.s (original)
+++ llvm/trunk/test/MC/ARM64/variable-exprs.s (removed)
@@ -1,40 +0,0 @@
-// RUN: llvm-mc -triple arm64-apple-darwin10 %s -filetype=obj -o %t.o
-
-.data
-
- .long 0
-a:
- .long 0
-b = a
-
-c: .long b
-
-d2 = d
-.globl d2
-d3 = d + 4
-.globl d3
-
-e = a + 4
-
-g:
-f = g
- .long 0
-
- .long b
- .long e
- .long a + 4
- .long d
- .long d2
- .long d3
- .long f
- .long g
-
-///
- .text
-t0:
-Lt0_a:
- .long 0
-
- .section __DWARF,__debug_frame,regular,debug
-Lt1 = Lt0_a
- .long Lt1
Removed: llvm/trunk/test/MC/ARM64/vector-lists.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/vector-lists.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/vector-lists.s (original)
+++ llvm/trunk/test/MC/ARM64/vector-lists.s (removed)
@@ -1,20 +0,0 @@
-// RUN: not llvm-mc -triple arm64 -mattr=neon -show-encoding < %s 2>%t | FileCheck %s
-// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
-
- ST4 {v0.8B-v3.8B}, [x0]
- ST4 {v0.4H-v3.4H}, [x0]
-
-// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c]
-// CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c]
-
- ST4 {v0.8B-v4.8B}, [x0]
- ST4 {v0.8B-v3.8B,v4.8B}, [x0]
- ST4 {v0.8B-v3.8H}, [x0]
- ST4 {v0.8B-v3.16B}, [x0]
- ST4 {v0.8B-},[x0]
-
-// CHECK-ERRORS: error: invalid number of vectors
-// CHECK-ERRORS: error: '}' expected
-// CHECK-ERRORS: error: mismatched register size suffix
-// CHECK-ERRORS: error: mismatched register size suffix
-// CHECK-ERRORS: error: vector register expected
Removed: llvm/trunk/test/MC/ARM64/verbose-vector-case.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/verbose-vector-case.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/verbose-vector-case.s (original)
+++ llvm/trunk/test/MC/ARM64/verbose-vector-case.s (removed)
@@ -1,19 +0,0 @@
-// RUN: llvm-mc -triple arm64 -mattr=crypto -show-encoding < %s | FileCheck %s
-
-pmull v8.8h, v8.8b, v8.8b
-pmull2 v8.8h, v8.16b, v8.16b
-pmull v8.1q, v8.1d, v8.1d
-pmull2 v8.1q, v8.2d, v8.2d
-// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
-// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e]
-// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
-// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e]
-
-pmull v8.8H, v8.8B, v8.8B
-pmull2 v8.8H, v8.16B, v8.16B
-pmull v8.1Q, v8.1D, v8.1D
-pmull2 v8.1Q, v8.2D, v8.2D
-// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e]
-// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e]
-// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e]
-// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e]
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-advsimd.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-advsimd.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-advsimd.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-arithmetic.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-arithmetic.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-arithmetic.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-bitfield.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-bitfield.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-bitfield.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-branch.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/branch.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-branch.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-branch.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/branch.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-canonical-form.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-canonical-form.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-canonical-form.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-crc32.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-crc32.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-crc32.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-crypto.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-crypto.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-crypto.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-logical.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/logical.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-logical.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-logical.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/logical.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-memory.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/memory.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-memory.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-memory.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/memory.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/Disassembler/AArch64/arm64-system.txt (from r209576, llvm/trunk/test/MC/Disassembler/ARM64/system.txt)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-system.txt?p2=llvm/trunk/test/MC/Disassembler/AArch64/arm64-system.txt&p1=llvm/trunk/test/MC/Disassembler/ARM64/system.txt&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Modified: llvm/trunk/test/MC/Disassembler/AArch64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/lit.local.cfg?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
targets = set(config.root.targets_to_build.split())
-if 'ARM64' not in targets:
+if 'AArch64' not in targets:
config.unsupported = True
Removed: llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt (removed)
@@ -1,2283 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s
-
-0x00 0xb8 0x20 0x0e
-0x00 0xb8 0x20 0x4e
-0x00 0xb8 0x60 0x0e
-0x00 0xb8 0x60 0x4e
-0x00 0xb8 0xa0 0x0e
-0x00 0xb8 0xa0 0x4e
-
-# CHECK: abs.8b v0, v0
-# CHECK: abs.16b v0, v0
-# CHECK: abs.4h v0, v0
-# CHECK: abs.8h v0, v0
-# CHECK: abs.2s v0, v0
-# CHECK: abs.4s v0, v0
-
-0x00 0x84 0x20 0x0e
-0x00 0x84 0x20 0x4e
-0x00 0x84 0x60 0x0e
-0x00 0x84 0x60 0x4e
-0x00 0x84 0xa0 0x0e
-0x00 0x84 0xa0 0x4e
-0x00 0x84 0xe0 0x4e
-
-# CHECK: add.8b v0, v0, v0
-# CHECK: add.16b v0, v0, v0
-# CHECK: add.4h v0, v0, v0
-# CHECK: add.8h v0, v0, v0
-# CHECK: add.2s v0, v0, v0
-# CHECK: add.4s v0, v0, v0
-# CHECK: add.2d v0, v0, v0
-
-0x41 0x84 0xe3 0x5e
-
-# CHECK: add d1, d2, d3
-
-0x00 0x40 0x20 0x0e
-0x00 0x40 0x20 0x4e
-0x00 0x40 0x60 0x0e
-0x00 0x40 0x60 0x4e
-0x00 0x40 0xa0 0x0e
-0x00 0x40 0xa0 0x4e
-
-# CHECK: addhn.8b v0, v0, v0
-# CHECK: addhn2.16b v0, v0, v0
-# CHECK: addhn.4h v0, v0, v0
-# CHECK: addhn2.8h v0, v0, v0
-# CHECK: addhn.2s v0, v0, v0
-# CHECK: addhn2.4s v0, v0, v0
-
-0x00 0xbc 0x20 0x0e
-0x00 0xbc 0x20 0x4e
-0x00 0xbc 0x60 0x0e
-0x00 0xbc 0x60 0x4e
-0x00 0xbc 0xa0 0x0e
-0x00 0xbc 0xa0 0x4e
-0x00 0xbc 0xe0 0x4e
-
-# CHECK: addp.8b v0, v0, v0
-# CHECK: addp.16b v0, v0, v0
-# CHECK: addp.4h v0, v0, v0
-# CHECK: addp.8h v0, v0, v0
-# CHECK: addp.2s v0, v0, v0
-# CHECK: addp.4s v0, v0, v0
-# CHECK: addp.2d v0, v0, v0
-
-0x00 0xb8 0xf1 0x5e
-
-# CHECK: addp.2d d0, v0
-
-0x00 0xb8 0x31 0x0e
-0x00 0xb8 0x31 0x4e
-0x00 0xb8 0x71 0x0e
-0x00 0xb8 0x71 0x4e
-0x00 0xb8 0xb1 0x4e
-
-# CHECK: addv.8b b0, v0
-# CHECK: addv.16b b0, v0
-# CHECK: addv.4h h0, v0
-# CHECK: addv.8h h0, v0
-# CHECK: addv.4s s0, v0
-
-
-# INS/DUP
-0x60 0x0c 0x08 0x4e
-0x60 0x0c 0x04 0x4e
-0x60 0x0c 0x04 0x0e
-0x60 0x0c 0x02 0x4e
-0x60 0x0c 0x02 0x0e
-0x60 0x0c 0x01 0x4e
-0x60 0x0c 0x01 0x0e
-
-# CHECK: dup.2d v0, x3
-# CHECK: dup.4s v0, w3
-# CHECK: dup.2s v0, w3
-# CHECK: dup.8h v0, w3
-# CHECK: dup.4h v0, w3
-# CHECK: dup.16b v0, w3
-# CHECK: dup.8b v0, w3
-
-0x60 0x04 0x18 0x4e
-0x60 0x04 0x0c 0x0e
-0x60 0x04 0x0c 0x4e
-0x60 0x04 0x06 0x0e
-0x60 0x04 0x06 0x4e
-0x60 0x04 0x03 0x0e
-0x60 0x04 0x03 0x4e
-
-# CHECK: dup.2d v0, v3[1]
-# CHECK: dup.2s v0, v3[1]
-# CHECK: dup.4s v0, v3[1]
-# CHECK: dup.4h v0, v3[1]
-# CHECK: dup.8h v0, v3[1]
-# CHECK: dup.8b v0, v3[1]
-# CHECK: dup.16b v0, v3[1]
-
-
-0x43 0x2c 0x14 0x4e
-0x43 0x2c 0x14 0x4e
-0x43 0x3c 0x14 0x0e
-0x43 0x3c 0x14 0x0e
-0x43 0x3c 0x18 0x4e
-0x43 0x3c 0x18 0x4e
-
-# CHECK: smov.s x3, v2[2]
-# CHECK: smov.s x3, v2[2]
-# CHECK: mov.s w3, v2[2]
-# CHECK: mov.s w3, v2[2]
-# CHECK: mov.d x3, v2[1]
-# CHECK: mov.d x3, v2[1]
-
-0xa2 0x1c 0x18 0x4e
-0xa2 0x1c 0x0c 0x4e
-0xa2 0x1c 0x06 0x4e
-0xa2 0x1c 0x03 0x4e
-
-0xa2 0x1c 0x18 0x4e
-0xa2 0x1c 0x0c 0x4e
-0xa2 0x1c 0x06 0x4e
-0xa2 0x1c 0x03 0x4e
-
-# CHECK: ins.d v2[1], x5
-# CHECK: ins.s v2[1], w5
-# CHECK: ins.h v2[1], w5
-# CHECK: ins.b v2[1], w5
-
-# CHECK: ins.d v2[1], x5
-# CHECK: ins.s v2[1], w5
-# CHECK: ins.h v2[1], w5
-# CHECK: ins.b v2[1], w5
-
-0xe2 0x45 0x18 0x6e
-0xe2 0x25 0x0c 0x6e
-0xe2 0x15 0x06 0x6e
-0xe2 0x0d 0x03 0x6e
-
-0xe2 0x05 0x18 0x6e
-0xe2 0x45 0x1c 0x6e
-0xe2 0x35 0x1e 0x6e
-0xe2 0x2d 0x15 0x6e
-
-# CHECK: ins.d v2[1], v15[1]
-# CHECK: ins.s v2[1], v15[1]
-# CHECK: ins.h v2[1], v15[1]
-# CHECK: ins.b v2[1], v15[1]
-
-# CHECK: ins.d v2[1], v15[0]
-# CHECK: ins.s v2[3], v15[2]
-# CHECK: ins.h v2[7], v15[3]
-# CHECK: ins.b v2[10], v15[5]
-
-0x00 0x1c 0x20 0x0e
-0x00 0x1c 0x20 0x4e
-
-# CHECK: and.8b v0, v0, v0
-# CHECK: and.16b v0, v0, v0
-
-0x00 0x1c 0x60 0x0e
-
-# CHECK: bic.8b v0, v0, v0
-
-0x00 0x8c 0x20 0x2e
-0x00 0x3c 0x20 0x0e
-0x00 0x34 0x20 0x0e
-0x00 0x34 0x20 0x2e
-0x00 0x3c 0x20 0x2e
-0x00 0x8c 0x20 0x0e
-0x00 0xd4 0xa0 0x2e
-0x00 0xec 0x20 0x2e
-0x00 0xec 0xa0 0x2e
-0x00 0xd4 0x20 0x2e
-0x00 0xd4 0x20 0x0e
-0x00 0xe4 0x20 0x0e
-0x00 0xe4 0x20 0x2e
-0x00 0xe4 0xa0 0x2e
-0x00 0xfc 0x20 0x2e
-0x00 0xc4 0x20 0x2e
-0x00 0xc4 0x20 0x0e
-0x00 0xf4 0x20 0x2e
-0x00 0xf4 0x20 0x0e
-0x00 0xc4 0xa0 0x2e
-0x00 0xc4 0xa0 0x0e
-0x00 0xf4 0xa0 0x2e
-0x00 0xf4 0xa0 0x0e
-0x00 0xcc 0x20 0x0e
-0x00 0xcc 0xa0 0x0e
-0x00 0xdc 0x20 0x0e
-0x00 0xdc 0x20 0x2e
-0x00 0xfc 0x20 0x0e
-0x00 0xfc 0xa0 0x0e
-0x00 0xd4 0xa0 0x0e
-0x00 0x94 0x20 0x0e
-0x00 0x94 0x20 0x2e
-0x00 0x9c 0x20 0x0e
-0x00 0x9c 0x20 0x2e
-0x00 0x7c 0x20 0x0e
-0x00 0x74 0x20 0x0e
-0x00 0x04 0x20 0x0e
-0x00 0x24 0x20 0x0e
-0x00 0xa4 0x20 0x0e
-0x00 0x64 0x20 0x0e
-0x00 0xac 0x20 0x0e
-0x00 0x6c 0x20 0x0e
-0x00 0x0c 0x20 0x0e
-0x00 0xb4 0x60 0x0e
-0x00 0xb4 0x60 0x2e
-0x00 0x5c 0x20 0x0e
-0x00 0x4c 0x20 0x0e
-0x00 0x2c 0x20 0x0e
-0x00 0x14 0x20 0x0e
-0x00 0x54 0x20 0x0e
-0x00 0x44 0x20 0x0e
-0x00 0x84 0x20 0x2e
-0x00 0x7c 0x20 0x2e
-0x00 0x74 0x20 0x2e
-0x00 0x04 0x20 0x2e
-0x00 0x24 0x20 0x2e
-0x00 0xa4 0x20 0x2e
-0x00 0x64 0x20 0x2e
-0x00 0xac 0x20 0x2e
-0x00 0x6c 0x20 0x2e
-0x00 0x0c 0x20 0x2e
-0x00 0x5c 0x20 0x2e
-0x00 0x4c 0x20 0x2e
-0x00 0x2c 0x20 0x2e
-0x00 0x14 0x20 0x2e
-0x00 0x54 0x20 0x2e
-0x00 0x44 0x20 0x2e
-
-# CHECK: cmeq.8b v0, v0, v0
-# CHECK: cmge.8b v0, v0, v0
-# CHECK: cmgt.8b v0, v0, v0
-# CHECK: cmhi.8b v0, v0, v0
-# CHECK: cmhs.8b v0, v0, v0
-# CHECK: cmtst.8b v0, v0, v0
-# CHECK: fabd.2s v0, v0, v0
-# CHECK: facge.2s v0, v0, v0
-# CHECK: facgt.2s v0, v0, v0
-# CHECK: faddp.2s v0, v0, v0
-# CHECK: fadd.2s v0, v0, v0
-# CHECK: fcmeq.2s v0, v0, v0
-# CHECK: fcmge.2s v0, v0, v0
-# CHECK: fcmgt.2s v0, v0, v0
-# CHECK: fdiv.2s v0, v0, v0
-# CHECK: fmaxnmp.2s v0, v0, v0
-# CHECK: fmaxnm.2s v0, v0, v0
-# CHECK: fmaxp.2s v0, v0, v0
-# CHECK: fmax.2s v0, v0, v0
-# CHECK: fminnmp.2s v0, v0, v0
-# CHECK: fminnm.2s v0, v0, v0
-# CHECK: fminp.2s v0, v0, v0
-# CHECK: fmin.2s v0, v0, v0
-# CHECK: fmla.2s v0, v0, v0
-# CHECK: fmls.2s v0, v0, v0
-# CHECK: fmulx.2s v0, v0, v0
-# CHECK: fmul.2s v0, v0, v0
-# CHECK: frecps.2s v0, v0, v0
-# CHECK: frsqrts.2s v0, v0, v0
-# CHECK: fsub.2s v0, v0, v0
-# CHECK: mla.8b v0, v0, v0
-# CHECK: mls.8b v0, v0, v0
-# CHECK: mul.8b v0, v0, v0
-# CHECK: pmul.8b v0, v0, v0
-# CHECK: saba.8b v0, v0, v0
-# CHECK: sabd.8b v0, v0, v0
-# CHECK: shadd.8b v0, v0, v0
-# CHECK: shsub.8b v0, v0, v0
-# CHECK: smaxp.8b v0, v0, v0
-# CHECK: smax.8b v0, v0, v0
-# CHECK: sminp.8b v0, v0, v0
-# CHECK: smin.8b v0, v0, v0
-# CHECK: sqadd.8b v0, v0, v0
-# CHECK: sqdmulh.4h v0, v0, v0
-# CHECK: sqrdmulh.4h v0, v0, v0
-# CHECK: sqrshl.8b v0, v0, v0
-# CHECK: sqshl.8b v0, v0, v0
-# CHECK: sqsub.8b v0, v0, v0
-# CHECK: srhadd.8b v0, v0, v0
-# CHECK: srshl.8b v0, v0, v0
-# CHECK: sshl.8b v0, v0, v0
-# CHECK: sub.8b v0, v0, v0
-# CHECK: uaba.8b v0, v0, v0
-# CHECK: uabd.8b v0, v0, v0
-# CHECK: uhadd.8b v0, v0, v0
-# CHECK: uhsub.8b v0, v0, v0
-# CHECK: umaxp.8b v0, v0, v0
-# CHECK: umax.8b v0, v0, v0
-# CHECK: uminp.8b v0, v0, v0
-# CHECK: umin.8b v0, v0, v0
-# CHECK: uqadd.8b v0, v0, v0
-# CHECK: uqrshl.8b v0, v0, v0
-# CHECK: uqshl.8b v0, v0, v0
-# CHECK: uqsub.8b v0, v0, v0
-# CHECK: urhadd.8b v0, v0, v0
-# CHECK: urshl.8b v0, v0, v0
-# CHECK: ushl.8b v0, v0, v0
-
-0x00 0x1c 0xe0 0x2e
-0x00 0x1c 0xa0 0x2e
-0x00 0x1c 0x60 0x2e
-0x00 0x1c 0x20 0x2e
-0x00 0x1c 0xe0 0x0e
-0x00 0x1c 0xa1 0x0e
-
-# CHECK: bif.8b v0, v0, v0
-# CHECK: bit.8b v0, v0, v0
-# CHECK: bsl.8b v0, v0, v0
-# CHECK: eor.8b v0, v0, v0
-# CHECK: orn.8b v0, v0, v0
-# CHECK: orr.8b v0, v0, v1
-
-0x00 0x68 0x20 0x0e
-0x00 0x68 0x20 0x4e
-0x00 0x68 0x60 0x0e
-0x00 0x68 0x60 0x4e
-0x00 0x68 0xa0 0x0e
-0x00 0x68 0xa0 0x4e
-
-# CHECK: sadalp.4h v0, v0
-# CHECK: sadalp.8h v0, v0
-# CHECK: sadalp.2s v0, v0
-# CHECK: sadalp.4s v0, v0
-# CHECK: sadalp.1d v0, v0
-# CHECK: sadalp.2d v0, v0
-
-0x00 0x48 0x20 0x0e
-0x00 0x48 0x20 0x2e
-0x00 0x58 0x20 0x0e
-0x00 0xf8 0xa0 0x0e
-0x00 0xc8 0x21 0x0e
-0x00 0xc8 0x21 0x2e
-0x00 0xb8 0x21 0x0e
-0x00 0xb8 0x21 0x2e
-0x00 0xa8 0x21 0x0e
-0x00 0xa8 0x21 0x2e
-0x00 0xa8 0xa1 0x0e
-0x00 0xa8 0xa1 0x2e
-0x00 0xb8 0xa1 0x0e
-0x00 0xb8 0xa1 0x2e
-0x00 0xf8 0xa0 0x2e
-0x00 0xd8 0xa1 0x0e
-0x00 0xd8 0xa1 0x2e
-0x00 0xf8 0xa1 0x2e
-0x00 0xb8 0x20 0x2e
-0x00 0x58 0x20 0x2e
-0x00 0x58 0x60 0x2e
-0x00 0x18 0x20 0x0e
-0x00 0x08 0x20 0x2e
-0x00 0x08 0x20 0x0e
-0x00 0x68 0x20 0x0e
-0x00 0x28 0x20 0x0e
-0x00 0xd8 0x21 0x0e
-0x00 0x38 0x21 0x2e
-0x00 0x78 0x20 0x0e
-0x00 0x78 0x20 0x2e
-0x00 0x48 0x21 0x0e
-0x00 0x28 0x21 0x2e
-0x00 0x38 0x20 0x0e
-0x00 0x68 0x20 0x2e
-0x00 0x28 0x20 0x2e
-0x00 0xd8 0x21 0x2e
-0x00 0x48 0x21 0x2e
-0x00 0xc8 0xa1 0x0e
-0x00 0xc8 0xa1 0x2e
-0x00 0x38 0x20 0x2e
-0x00 0x28 0x21 0x0e
-0x00 0x48 0x20 0x0e
-0x00 0x48 0x20 0x2e
-0x00 0x58 0x20 0x0e
-0x00 0xf8 0xa0 0x0e
-0x00 0xc8 0x21 0x0e
-0x00 0xc8 0x21 0x2e
-0x00 0xb8 0x21 0x0e
-0x00 0xb8 0x21 0x2e
-0x00 0xa8 0x21 0x0e
-0x00 0xa8 0x21 0x2e
-0x00 0xa8 0xa1 0x0e
-0x00 0xa8 0xa1 0x2e
-0x00 0xb8 0xa1 0x0e
-0x00 0xb8 0xa1 0x2e
-0x00 0xf8 0xa0 0x2e
-0x00 0xd8 0xa1 0x0e
-0x00 0xd8 0xa1 0x2e
-0x00 0xf8 0xa1 0x2e
-0x00 0xb8 0x20 0x2e
-0x00 0x58 0x20 0x2e
-0x00 0x58 0x60 0x2e
-0x00 0x18 0x20 0x0e
-0x00 0x08 0x20 0x2e
-0x00 0x08 0x20 0x0e
-0x00 0x68 0x20 0x0e
-0x00 0x28 0x20 0x0e
-0x00 0xd8 0x21 0x0e
-0x00 0x38 0x21 0x2e
-0x00 0x78 0x20 0x0e
-0x00 0x78 0x20 0x2e
-0x00 0x48 0x21 0x0e
-0x00 0x28 0x21 0x2e
-0x00 0x38 0x20 0x0e
-0x00 0x68 0x20 0x2e
-0x00 0x28 0x20 0x2e
-0x00 0xd8 0x21 0x2e
-0x00 0x48 0x21 0x2e
-0x00 0xc8 0xa1 0x0e
-0x00 0xc8 0xa1 0x2e
-0x00 0x38 0x20 0x2e
-0x00 0x28 0x21 0x0e
-
-# CHECK: cls.8b v0, v0
-# CHECK: clz.8b v0, v0
-# CHECK: cnt.8b v0, v0
-# CHECK: fabs.2s v0, v0
-# CHECK: fcvtas.2s v0, v0
-# CHECK: fcvtau.2s v0, v0
-# CHECK: fcvtms.2s v0, v0
-# CHECK: fcvtmu.2s v0, v0
-# CHECK: fcvtns.2s v0, v0
-# CHECK: fcvtnu.2s v0, v0
-# CHECK: fcvtps.2s v0, v0
-# CHECK: fcvtpu.2s v0, v0
-# CHECK: fcvtzs.2s v0, v0
-# CHECK: fcvtzu.2s v0, v0
-# CHECK: fneg.2s v0, v0
-# CHECK: frecpe.2s v0, v0
-# CHECK: frsqrte.2s v0, v0
-# CHECK: fsqrt.2s v0, v0
-# CHECK: neg.8b v0, v0
-# CHECK: mvn.8b v0, v0
-# CHECK: rbit.8b v0, v0
-# CHECK: rev16.8b v0, v0
-# CHECK: rev32.8b v0, v0
-# CHECK: rev64.8b v0, v0
-# CHECK: sadalp.4h v0, v0
-# CHECK: saddlp.4h v0, v0
-# CHECK: scvtf.2s v0, v0
-# CHECK: shll.8h v0, v0, #8
-# CHECK: sqabs.8b v0, v0
-# CHECK: sqneg.8b v0, v0
-# CHECK: sqxtn.8b v0, v0
-# CHECK: sqxtun.8b v0, v0
-# CHECK: suqadd.8b v0, v0
-# CHECK: uadalp.4h v0, v0
-# CHECK: uaddlp.4h v0, v0
-# CHECK: ucvtf.2s v0, v0
-# CHECK: uqxtn.8b v0, v0
-# CHECK: urecpe.2s v0, v0
-# CHECK: ursqrte.2s v0, v0
-# CHECK: usqadd.8b v0, v0
-# CHECK: xtn.8b v0, v0
-
-0x00 0x98 0x20 0x0e
-0x00 0x98 0x20 0x4e
-0x00 0x98 0x60 0x0e
-0x00 0x98 0x60 0x4e
-0x00 0x98 0xa0 0x0e
-0x00 0x98 0xa0 0x4e
-0x00 0x98 0xe0 0x4e
-
-# CHECK: cmeq.8b v0, v0, #0
-# CHECK: cmeq.16b v0, v0, #0
-# CHECK: cmeq.4h v0, v0, #0
-# CHECK: cmeq.8h v0, v0, #0
-# CHECK: cmeq.2s v0, v0, #0
-# CHECK: cmeq.4s v0, v0, #0
-# CHECK: cmeq.2d v0, v0, #0
-
-0x00 0x88 0x20 0x2e
-0x00 0x88 0x20 0x0e
-0x00 0x98 0x20 0x2e
-0x00 0xa8 0x20 0x0e
-0x00 0xd8 0xa0 0x0e
-0x00 0xc8 0xa0 0x2e
-0x00 0xc8 0xa0 0x0e
-0x00 0xd8 0xa0 0x2e
-0x00 0xe8 0xa0 0x0e
-
-# CHECK: cmge.8b v0, v0, #0
-# CHECK: cmgt.8b v0, v0, #0
-# CHECK: cmle.8b v0, v0, #0
-# CHECK: cmlt.8b v0, v0, #0
-# CHECK: fcmeq.2s v0, v0, #0
-# CHECK: fcmge.2s v0, v0, #0
-# CHECK: fcmgt.2s v0, v0, #0
-# CHECK: fcmle.2s v0, v0, #0
-# CHECK: fcmlt.2s v0, v0, #0
-
-0x00 0x78 0x21 0x0e
-0x00 0x78 0x21 0x4e
-0x00 0x78 0x61 0x0e
-0x00 0x78 0x61 0x4e
-0x00 0x68 0x21 0x0e
-0x00 0x68 0x21 0x4e
-0x00 0x68 0x61 0x0e
-0x00 0x68 0x61 0x4e
-0x00 0x68 0x61 0x2e
-0x00 0x68 0x61 0x6e
-
-# CHECK: fcvtl v0.4s, v0.4h
-# CHECK: fcvtl2 v0.4s, v0.8h
-# CHECK: fcvtl v0.2d, v0.2s
-# CHECK: fcvtl2 v0.2d, v0.4s
-# CHECK: fcvtn v0.4h, v0.4s
-# CHECK: fcvtn2 v0.8h, v0.4s
-# CHECK: fcvtn v0.2s, v0.2d
-# CHECK: fcvtn2 v0.4s, v0.2d
-# CHECK: fcvtxn v0.2s, v0.2d
-# CHECK: fcvtxn2 v0.4s, v0.2d
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD modified immediate instructions
-#===-------------------------------------------------------------------------===
-
-0x20 0x14 0x00 0x2f
-0x20 0x34 0x00 0x2f
-0x20 0x54 0x00 0x2f
-0x20 0x74 0x00 0x2f
-
-# CHECK: bic.2s v0, #0x1
-# CHECK: bic.2s v0, #0x1, lsl #8
-# CHECK: bic.2s v0, #0x1, lsl #16
-# CHECK: bic.2s v0, #0x1, lsl #24
-
-0x20 0x94 0x00 0x2f
-0x20 0x94 0x00 0x2f
-0x20 0xb4 0x00 0x2f
-
-# CHECK: bic.4h v0, #0x1
-# CHECK: bic.4h v0, #0x1
-# FIXME: bic.4h v0, #0x1, lsl #8
-# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
-
-0x20 0x14 0x00 0x6f
-0x20 0x34 0x00 0x6f
-0x20 0x54 0x00 0x6f
-0x20 0x74 0x00 0x6f
-
-# CHECK: bic.4s v0, #0x1
-# CHECK: bic.4s v0, #0x1, lsl #8
-# CHECK: bic.4s v0, #0x1, lsl #16
-# CHECK: bic.4s v0, #0x1, lsl #24
-
-0x20 0x94 0x00 0x6f
-0x20 0xb4 0x00 0x6f
-
-# CHECK: bic.8h v0, #0x1
-# FIXME: bic.8h v0, #0x1, lsl #8
-# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
-
-0x00 0xf4 0x02 0x6f
-
-# CHECK: fmov.2d v0, #0.12500000
-
-0x00 0xf4 0x02 0x0f
-0x00 0xf4 0x02 0x4f
-
-# CHECK: fmov.2s v0, #0.12500000
-# CHECK: fmov.4s v0, #0.12500000
-
-0x20 0x14 0x00 0x0f
-0x20 0x34 0x00 0x0f
-0x20 0x54 0x00 0x0f
-0x20 0x74 0x00 0x0f
-
-# CHECK: orr.2s v0, #0x1
-# CHECK: orr.2s v0, #0x1, lsl #8
-# CHECK: orr.2s v0, #0x1, lsl #16
-# CHECK: orr.2s v0, #0x1, lsl #24
-
-0x20 0x94 0x00 0x0f
-0x20 0xb4 0x00 0x0f
-
-# CHECK: orr.4h v0, #0x1
-# FIXME: orr.4h v0, #0x1, lsl #8
-# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
-
-0x20 0x14 0x00 0x4f
-0x20 0x34 0x00 0x4f
-0x20 0x54 0x00 0x4f
-0x20 0x74 0x00 0x4f
-
-# CHECK: orr.4s v0, #0x1
-# CHECK: orr.4s v0, #0x1, lsl #8
-# CHECK: orr.4s v0, #0x1, lsl #16
-# CHECK: orr.4s v0, #0x1, lsl #24
-
-0x20 0x94 0x00 0x4f
-0x20 0xb4 0x00 0x4f
-
-# CHECK: orr.8h v0, #0x1
-# CHECK: orr.8h v0, #0x1, lsl #8
-
-0x21 0x70 0x40 0x0c
-0x42 0xa0 0x40 0x4c
-0x64 0x64 0x40 0x0c
-0x87 0x24 0x40 0x4c
-0x0c 0xa8 0x40 0x0c
-0x0a 0x68 0x40 0x4c
-0x2d 0xac 0x40 0x0c
-0x4f 0x7c 0x40 0x4c
-0xe0 0x03 0x40 0x0d
-
-# CHECK: ld1.8b { v1 }, [x1]
-# CHECK: ld1.16b { v2, v3 }, [x2]
-# CHECK: ld1.4h { v4, v5, v6 }, [x3]
-# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4]
-# CHECK: ld1.2s { v12, v13 }, [x0]
-# CHECK: ld1.4s { v10, v11, v12 }, [x0]
-# CHECK: ld1.1d { v13, v14 }, [x1]
-# CHECK: ld1.2d { v15 }, [x2]
-# CHECK: ld1.b { v0 }[0], [sp]
-
-0x41 0x70 0xdf 0x0c
-0x41 0xa0 0xdf 0x0c
-0x41 0x60 0xdf 0x0c
-0x41 0x20 0xdf 0x0c
-0x42 0x70 0xdf 0x4c
-0x42 0xa0 0xdf 0x4c
-0x42 0x60 0xdf 0x4c
-0x42 0x20 0xdf 0x4c
-0x64 0x74 0xdf 0x0c
-0x64 0xa4 0xdf 0x0c
-0x64 0x64 0xdf 0x0c
-0x64 0x24 0xdf 0x0c
-0x87 0x74 0xdf 0x4c
-0x87 0xa4 0xdf 0x4c
-0x87 0x64 0xdf 0x4c
-0x87 0x24 0xdf 0x4c
-0x0c 0x78 0xdf 0x0c
-0x0c 0xa8 0xdf 0x0c
-0x0c 0x68 0xdf 0x0c
-0x0c 0x28 0xdf 0x0c
-0x0a 0x78 0xdf 0x4c
-0x0a 0xa8 0xdf 0x4c
-0x0a 0x68 0xdf 0x4c
-0x0a 0x28 0xdf 0x4c
-0x2d 0x7c 0xdf 0x0c
-0x2d 0xac 0xdf 0x0c
-0x2d 0x6c 0xdf 0x0c
-0x2d 0x2c 0xdf 0x0c
-0x4f 0x7c 0xdf 0x4c
-0x4f 0xac 0xdf 0x4c
-0x4f 0x6c 0xdf 0x4c
-0x4f 0x2c 0xdf 0x4c
-
-# CHECK: ld1.8b { v1 }, [x2], #8
-# CHECK: ld1.8b { v1, v2 }, [x2], #16
-# CHECK: ld1.8b { v1, v2, v3 }, [x2], #24
-# CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32
-# CHECK: ld1.16b { v2 }, [x2], #16
-# CHECK: ld1.16b { v2, v3 }, [x2], #32
-# CHECK: ld1.16b { v2, v3, v4 }, [x2], #48
-# CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64
-# CHECK: ld1.4h { v4 }, [x3], #8
-# CHECK: ld1.4h { v4, v5 }, [x3], #16
-# CHECK: ld1.4h { v4, v5, v6 }, [x3], #24
-# CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32
-# CHECK: ld1.8h { v7 }, [x4], #16
-# CHECK: ld1.8h { v7, v8 }, [x4], #32
-# CHECK: ld1.8h { v7, v8, v9 }, [x4], #48
-# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64
-# CHECK: ld1.2s { v12 }, [x0], #8
-# CHECK: ld1.2s { v12, v13 }, [x0], #16
-# CHECK: ld1.2s { v12, v13, v14 }, [x0], #24
-# CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32
-# CHECK: ld1.4s { v10 }, [x0], #16
-# CHECK: ld1.4s { v10, v11 }, [x0], #32
-# CHECK: ld1.4s { v10, v11, v12 }, [x0], #48
-# CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64
-# CHECK: ld1.1d { v13 }, [x1], #8
-# CHECK: ld1.1d { v13, v14 }, [x1], #16
-# CHECK: ld1.1d { v13, v14, v15 }, [x1], #24
-# CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32
-# CHECK: ld1.2d { v15 }, [x2], #16
-# CHECK: ld1.2d { v15, v16 }, [x2], #32
-# CHECK: ld1.2d { v15, v16, v17 }, [x2], #48
-# CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64
-
-0x21 0x70 0x00 0x0c
-0x42 0xa0 0x00 0x4c
-0x64 0x64 0x00 0x0c
-0x87 0x24 0x00 0x4c
-0x0c 0xa8 0x00 0x0c
-0x0a 0x68 0x00 0x4c
-0x2d 0xac 0x00 0x0c
-0x4f 0x7c 0x00 0x4c
-
-# CHECK: st1.8b { v1 }, [x1]
-# CHECK: st1.16b { v2, v3 }, [x2]
-# CHECK: st1.4h { v4, v5, v6 }, [x3]
-# CHECK: st1.8h { v7, v8, v9, v10 }, [x4]
-# CHECK: st1.2s { v12, v13 }, [x0]
-# CHECK: st1.4s { v10, v11, v12 }, [x0]
-# CHECK: st1.1d { v13, v14 }, [x1]
-# CHECK: st1.2d { v15 }, [x2]
-
-0x61 0x08 0x40 0x0d
-0x82 0x84 0x40 0x4d
-0xa3 0x58 0x40 0x0d
-0xc4 0x80 0x40 0x4d
-
-# CHECK: ld1.b { v1 }[2], [x3]
-# CHECK: ld1.d { v2 }[1], [x4]
-# CHECK: ld1.h { v3 }[3], [x5]
-# CHECK: ld1.s { v4 }[2], [x6]
-
-0x61 0x08 0xdf 0x0d
-0x82 0x84 0xdf 0x4d
-0xa3 0x58 0xdf 0x0d
-0xc4 0x80 0xdf 0x4d
-
-# CHECK: ld1.b { v1 }[2], [x3], #1
-# CHECK: ld1.d { v2 }[1], [x4], #8
-# CHECK: ld1.h { v3 }[3], [x5], #2
-# CHECK: ld1.s { v4 }[2], [x6], #4
-
-0x61 0x08 0x00 0x0d
-0x82 0x84 0x00 0x4d
-0xa3 0x58 0x00 0x0d
-0xc4 0x80 0x00 0x4d
-
-# CHECK: st1.b { v1 }[2], [x3]
-# CHECK: st1.d { v2 }[1], [x4]
-# CHECK: st1.h { v3 }[3], [x5]
-# CHECK: st1.s { v4 }[2], [x6]
-
-0x61 0x08 0x9f 0x0d
-0x82 0x84 0x9f 0x4d
-0xa3 0x58 0x9f 0x0d
-0xc4 0x80 0x9f 0x4d
-
-# CHECK: st1.b { v1 }[2], [x3], #1
-# CHECK: st1.d { v2 }[1], [x4], #8
-# CHECK: st1.h { v3 }[3], [x5], #2
-# CHECK: st1.s { v4 }[2], [x6], #4
-
-0x61 0x08 0xc4 0x0d
-0x82 0x84 0xc5 0x4d
-0xa3 0x58 0xc6 0x0d
-0xc4 0x80 0xc7 0x4d
-
-# CHECK: ld1.b { v1 }[2], [x3], x4
-# CHECK: ld1.d { v2 }[1], [x4], x5
-# CHECK: ld1.h { v3 }[3], [x5], x6
-# CHECK: ld1.s { v4 }[2], [x6], x7
-
-0x61 0x08 0x84 0x0d
-0x82 0x84 0x85 0x4d
-0xa3 0x58 0x86 0x0d
-0xc4 0x80 0x87 0x4d
-
-# CHECK: st1.b { v1 }[2], [x3], x4
-# CHECK: st1.d { v2 }[1], [x4], x5
-# CHECK: st1.h { v3 }[3], [x5], x6
-# CHECK: st1.s { v4 }[2], [x6], x7
-
-0x41 0x70 0xc3 0x0c
-0x42 0xa0 0xc4 0x4c
-0x64 0x64 0xc5 0x0c
-0x87 0x24 0xc6 0x4c
-0x0c 0xa8 0xc7 0x0c
-0x0a 0x68 0xc8 0x4c
-0x2d 0xac 0xc9 0x0c
-0x4f 0x7c 0xca 0x4c
-
-# CHECK: ld1.8b { v1 }, [x2], x3
-# CHECK: ld1.16b { v2, v3 }, [x2], x4
-# CHECK: ld1.4h { v4, v5, v6 }, [x3], x5
-# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6
-# CHECK: ld1.2s { v12, v13 }, [x0], x7
-# CHECK: ld1.4s { v10, v11, v12 }, [x0], x8
-# CHECK: ld1.1d { v13, v14 }, [x1], x9
-# CHECK: ld1.2d { v15 }, [x2], x10
-
-0x41 0x70 0x83 0x0c
-0x42 0xa0 0x84 0x4c
-0x64 0x64 0x85 0x0c
-0x87 0x24 0x86 0x4c
-0x0c 0xa8 0x87 0x0c
-0x0a 0x68 0x88 0x4c
-0x2d 0xac 0x89 0x0c
-0x4f 0x7c 0x8a 0x4c
-
-# CHECK: st1.8b { v1 }, [x2], x3
-# CHECK: st1.16b { v2, v3 }, [x2], x4
-# CHECK: st1.4h { v4, v5, v6 }, [x3], x5
-# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6
-# CHECK: st1.2s { v12, v13 }, [x0], x7
-# CHECK: st1.4s { v10, v11, v12 }, [x0], x8
-# CHECK: st1.1d { v13, v14 }, [x1], x9
-# CHECK: st1.2d { v15 }, [x2], x10
-
-0x41 0x70 0x9f 0x0c
-0x41 0xa0 0x9f 0x0c
-0x41 0x60 0x9f 0x0c
-0x41 0x20 0x9f 0x0c
-0x42 0x70 0x9f 0x4c
-0x42 0xa0 0x9f 0x4c
-0x42 0x60 0x9f 0x4c
-0x42 0x20 0x9f 0x4c
-0x64 0x74 0x9f 0x0c
-0x64 0xa4 0x9f 0x0c
-0x64 0x64 0x9f 0x0c
-0x64 0x24 0x9f 0x0c
-0x87 0x74 0x9f 0x4c
-0x87 0xa4 0x9f 0x4c
-0x87 0x64 0x9f 0x4c
-0x87 0x24 0x9f 0x4c
-0x0c 0x78 0x9f 0x0c
-0x0c 0xa8 0x9f 0x0c
-0x0c 0x68 0x9f 0x0c
-0x0c 0x28 0x9f 0x0c
-0x0a 0x78 0x9f 0x4c
-0x0a 0xa8 0x9f 0x4c
-0x0a 0x68 0x9f 0x4c
-0x0a 0x28 0x9f 0x4c
-0x2d 0x7c 0x9f 0x0c
-0x2d 0xac 0x9f 0x0c
-0x2d 0x6c 0x9f 0x0c
-0x2d 0x2c 0x9f 0x0c
-0x4f 0x7c 0x9f 0x4c
-0x4f 0xac 0x9f 0x4c
-0x4f 0x6c 0x9f 0x4c
-0x4f 0x2c 0x9f 0x4c
-
-# CHECK: st1.8b { v1 }, [x2], #8
-# CHECK: st1.8b { v1, v2 }, [x2], #16
-# CHECK: st1.8b { v1, v2, v3 }, [x2], #24
-# CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32
-# CHECK: st1.16b { v2 }, [x2], #16
-# CHECK: st1.16b { v2, v3 }, [x2], #32
-# CHECK: st1.16b { v2, v3, v4 }, [x2], #48
-# CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64
-# CHECK: st1.4h { v4 }, [x3], #8
-# CHECK: st1.4h { v4, v5 }, [x3], #16
-# CHECK: st1.4h { v4, v5, v6 }, [x3], #24
-# CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32
-# CHECK: st1.8h { v7 }, [x4], #16
-# CHECK: st1.8h { v7, v8 }, [x4], #32
-# CHECK: st1.8h { v7, v8, v9 }, [x4], #48
-# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64
-# CHECK: st1.2s { v12 }, [x0], #8
-# CHECK: st1.2s { v12, v13 }, [x0], #16
-# CHECK: st1.2s { v12, v13, v14 }, [x0], #24
-# CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32
-# CHECK: st1.4s { v10 }, [x0], #16
-# CHECK: st1.4s { v10, v11 }, [x0], #32
-# CHECK: st1.4s { v10, v11, v12 }, [x0], #48
-# CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64
-# CHECK: st1.1d { v13 }, [x1], #8
-# CHECK: st1.1d { v13, v14 }, [x1], #16
-# CHECK: st1.1d { v13, v14, v15 }, [x1], #24
-# CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32
-# CHECK: st1.2d { v15 }, [x2], #16
-# CHECK: st1.2d { v15, v16 }, [x2], #32
-# CHECK: st1.2d { v15, v16, v17 }, [x2], #48
-# CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64
-
-0x21 0xc0 0x40 0x0d
-0x21 0xc0 0xc2 0x0d
-0x64 0xc4 0x40 0x0d
-0x64 0xc4 0xc5 0x0d
-0xa9 0xc8 0x40 0x0d
-0xa9 0xc8 0xc6 0x0d
-0xec 0xcc 0x40 0x0d
-0xec 0xcc 0xc8 0x0d
-
-# CHECK: ld1r.8b { v1 }, [x1]
-# CHECK: ld1r.8b { v1 }, [x1], x2
-# CHECK: ld1r.4h { v4 }, [x3]
-# CHECK: ld1r.4h { v4 }, [x3], x5
-# CHECK: ld1r.2s { v9 }, [x5]
-# CHECK: ld1r.2s { v9 }, [x5], x6
-# CHECK: ld1r.1d { v12 }, [x7]
-# CHECK: ld1r.1d { v12 }, [x7], x8
-
-0x21 0xc0 0xdf 0x0d
-0x21 0xc4 0xdf 0x0d
-0x21 0xc8 0xdf 0x0d
-0x21 0xcc 0xdf 0x0d
-
-# CHECK: ld1r.8b { v1 }, [x1], #1
-# CHECK: ld1r.4h { v1 }, [x1], #2
-# CHECK: ld1r.2s { v1 }, [x1], #4
-# CHECK: ld1r.1d { v1 }, [x1], #8
-
-0x45 0x80 0x40 0x4c
-0x0a 0x88 0x40 0x0c
-
-# CHECK: ld2.16b { v5, v6 }, [x2]
-# CHECK: ld2.2s { v10, v11 }, [x0]
-
-0x45 0x80 0x00 0x4c
-0x0a 0x88 0x00 0x0c
-
-# CHECK: st2.16b { v5, v6 }, [x2]
-# CHECK: st2.2s { v10, v11 }, [x0]
-
-0x61 0x08 0x20 0x0d
-0x82 0x84 0x20 0x4d
-0xc3 0x50 0x20 0x0d
-0xe4 0x90 0x20 0x4d
-
-# CHECK: st2.b { v1, v2 }[2], [x3]
-# CHECK: st2.d { v2, v3 }[1], [x4]
-# CHECK: st2.h { v3, v4 }[2], [x6]
-# CHECK: st2.s { v4, v5 }[3], [x7]
-
-0x61 0x08 0xbf 0x0d
-0x82 0x84 0xbf 0x4d
-0xa3 0x58 0xbf 0x0d
-0xc4 0x80 0xbf 0x4d
-
-# CHECK: st2.b { v1, v2 }[2], [x3], #2
-# CHECK: st2.d { v2, v3 }[1], [x4], #16
-# CHECK: st2.h { v3, v4 }[3], [x5], #4
-# CHECK: st2.s { v4, v5 }[2], [x6], #8
-
-0x61 0x08 0x60 0x0d
-0x82 0x84 0x60 0x4d
-0xc3 0x50 0x60 0x0d
-0xe4 0x90 0x60 0x4d
-
-# CHECK: ld2.b { v1, v2 }[2], [x3]
-# CHECK: ld2.d { v2, v3 }[1], [x4]
-# CHECK: ld2.h { v3, v4 }[2], [x6]
-# CHECK: ld2.s { v4, v5 }[3], [x7]
-
-0x61 0x08 0xff 0x0d
-0x82 0x84 0xff 0x4d
-0xa3 0x58 0xff 0x0d
-0xc4 0x80 0xff 0x4d
-
-# CHECK: ld2.b { v1, v2 }[2], [x3], #2
-# CHECK: ld2.d { v2, v3 }[1], [x4], #16
-# CHECK: ld2.h { v3, v4 }[3], [x5], #4
-# CHECK: ld2.s { v4, v5 }[2], [x6], #8
-
-0x61 0x08 0xe4 0x0d
-0x82 0x84 0xe6 0x4d
-0xa3 0x58 0xe8 0x0d
-0xc4 0x80 0xea 0x4d
-
-# CHECK: ld2.b { v1, v2 }[2], [x3], x4
-# CHECK: ld2.d { v2, v3 }[1], [x4], x6
-# CHECK: ld2.h { v3, v4 }[3], [x5], x8
-# CHECK: ld2.s { v4, v5 }[2], [x6], x10
-
-0x61 0x08 0xa4 0x0d
-0x82 0x84 0xa6 0x4d
-0xa3 0x58 0xa8 0x0d
-0xc4 0x80 0xaa 0x4d
-
-# CHECK: st2.b { v1, v2 }[2], [x3], x4
-# CHECK: st2.d { v2, v3 }[1], [x4], x6
-# CHECK: st2.h { v3, v4 }[3], [x5], x8
-# CHECK: st2.s { v4, v5 }[2], [x6], x10
-
-0x64 0x84 0xc5 0x0c
-0x0c 0x88 0xc7 0x0c
-
-# CHECK: ld2.4h { v4, v5 }, [x3], x5
-# CHECK: ld2.2s { v12, v13 }, [x0], x7
-
-0x00 0x80 0xdf 0x0c
-0x00 0x80 0xdf 0x4c
-0x00 0x84 0xdf 0x0c
-0x00 0x84 0xdf 0x4c
-0x00 0x88 0xdf 0x0c
-0x00 0x88 0xdf 0x4c
-0x00 0x8c 0xdf 0x4c
-
-# CHECK: ld2.8b { v0, v1 }, [x0], #16
-# CHECK: ld2.16b { v0, v1 }, [x0], #32
-# CHECK: ld2.4h { v0, v1 }, [x0], #16
-# CHECK: ld2.8h { v0, v1 }, [x0], #32
-# CHECK: ld2.2s { v0, v1 }, [x0], #16
-# CHECK: ld2.4s { v0, v1 }, [x0], #32
-# CHECK: ld2.2d { v0, v1 }, [x0], #32
-
-0x64 0x84 0x85 0x0c
-0x0c 0x88 0x87 0x0c
-
-# CHECK: st2.4h { v4, v5 }, [x3], x5
-# CHECK: st2.2s { v12, v13 }, [x0], x7
-
-0x00 0x80 0x9f 0x0c
-0x00 0x80 0x9f 0x4c
-0x00 0x84 0x9f 0x0c
-0x00 0x84 0x9f 0x4c
-0x00 0x88 0x9f 0x0c
-0x00 0x88 0x9f 0x4c
-0x00 0x8c 0x9f 0x4c
-
-# CHECK: st2.8b { v0, v1 }, [x0], #16
-# CHECK: st2.16b { v0, v1 }, [x0], #32
-# CHECK: st2.4h { v0, v1 }, [x0], #16
-# CHECK: st2.8h { v0, v1 }, [x0], #32
-# CHECK: st2.2s { v0, v1 }, [x0], #16
-# CHECK: st2.4s { v0, v1 }, [x0], #32
-# CHECK: st2.2d { v0, v1 }, [x0], #32
-
-0x21 0xc0 0x60 0x0d
-0x21 0xc0 0xe2 0x0d
-0x21 0xc0 0x60 0x4d
-0x21 0xc0 0xe2 0x4d
-0x21 0xc4 0x60 0x0d
-0x21 0xc4 0xe2 0x0d
-0x21 0xc4 0x60 0x4d
-0x21 0xc4 0xe2 0x4d
-0x21 0xc8 0x60 0x0d
-0x21 0xc8 0xe2 0x0d
-0x21 0xcc 0x60 0x4d
-0x21 0xcc 0xe2 0x4d
-0x21 0xcc 0x60 0x0d
-0x21 0xcc 0xe2 0x0d
-
-# CHECK: ld2r.8b { v1, v2 }, [x1]
-# CHECK: ld2r.8b { v1, v2 }, [x1], x2
-# CHECK: ld2r.16b { v1, v2 }, [x1]
-# CHECK: ld2r.16b { v1, v2 }, [x1], x2
-# CHECK: ld2r.4h { v1, v2 }, [x1]
-# CHECK: ld2r.4h { v1, v2 }, [x1], x2
-# CHECK: ld2r.8h { v1, v2 }, [x1]
-# CHECK: ld2r.8h { v1, v2 }, [x1], x2
-# CHECK: ld2r.2s { v1, v2 }, [x1]
-# CHECK: ld2r.2s { v1, v2 }, [x1], x2
-# CHECK: ld2r.2d { v1, v2 }, [x1]
-# CHECK: ld2r.2d { v1, v2 }, [x1], x2
-# CHECK: ld2r.1d { v1, v2 }, [x1]
-# CHECK: ld2r.1d { v1, v2 }, [x1], x2
-
-0x21 0xc0 0xff 0x0d
-0x21 0xc0 0xff 0x4d
-0x21 0xc4 0xff 0x0d
-0x21 0xc4 0xff 0x4d
-0x21 0xc8 0xff 0x0d
-0x21 0xcc 0xff 0x4d
-0x21 0xcc 0xff 0x0d
-
-# CHECK: ld2r.8b { v1, v2 }, [x1], #2
-# CHECK: ld2r.16b { v1, v2 }, [x1], #2
-# CHECK: ld2r.4h { v1, v2 }, [x1], #4
-# CHECK: ld2r.8h { v1, v2 }, [x1], #4
-# CHECK: ld2r.2s { v1, v2 }, [x1], #8
-# CHECK: ld2r.2d { v1, v2 }, [x1], #16
-# CHECK: ld2r.1d { v1, v2 }, [x1], #16
-
-0x21 0x40 0x40 0x0c
-0x45 0x40 0x40 0x4c
-0x0a 0x48 0x40 0x0c
-
-# CHECK: ld3.8b { v1, v2, v3 }, [x1]
-# CHECK: ld3.16b { v5, v6, v7 }, [x2]
-# CHECK: ld3.2s { v10, v11, v12 }, [x0]
-
-0x21 0x40 0x00 0x0c
-0x45 0x40 0x00 0x4c
-0x0a 0x48 0x00 0x0c
-
-# CHECK: st3.8b { v1, v2, v3 }, [x1]
-# CHECK: st3.16b { v5, v6, v7 }, [x2]
-# CHECK: st3.2s { v10, v11, v12 }, [x0]
-
-0x61 0x28 0xc4 0x0d
-0x82 0xa4 0xc5 0x4d
-0xa3 0x78 0xc6 0x0d
-0xc4 0xa0 0xc7 0x4d
-
-# CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4
-# CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5
-# CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6
-# CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7
-
-0x61 0x28 0x84 0x0d
-0x82 0xa4 0x85 0x4d
-0xa3 0x78 0x86 0x0d
-0xc4 0xa0 0x87 0x4d
-
-# CHECK: st3.b { v1, v2, v3 }[2], [x3], x4
-# CHECK: st3.d { v2, v3, v4 }[1], [x4], x5
-# CHECK: st3.h { v3, v4, v5 }[3], [x5], x6
-# CHECK: st3.s { v4, v5, v6 }[2], [x6], x7
-
-0x61 0x28 0x9f 0x0d
-0x82 0xa4 0x9f 0x4d
-0xa3 0x78 0x9f 0x0d
-0xc4 0xa0 0x9f 0x4d
-
-# CHECK: st3.b { v1, v2, v3 }[2], [x3], #3
-# CHECK: st3.d { v2, v3, v4 }[1], [x4], #24
-# CHECK: st3.h { v3, v4, v5 }[3], [x5], #6
-# CHECK: st3.s { v4, v5, v6 }[2], [x6], #12
-
-0x41 0x40 0xc3 0x0c
-0x42 0x40 0xc4 0x4c
-0x64 0x44 0xc5 0x0c
-0x87 0x44 0xc6 0x4c
-0x0c 0x48 0xc7 0x0c
-0x0a 0x48 0xc8 0x4c
-0x4f 0x4c 0xca 0x4c
-
-# CHECK: ld3.8b { v1, v2, v3 }, [x2], x3
-# CHECK: ld3.16b { v2, v3, v4 }, [x2], x4
-# CHECK: ld3.4h { v4, v5, v6 }, [x3], x5
-# CHECK: ld3.8h { v7, v8, v9 }, [x4], x6
-# CHECK: ld3.2s { v12, v13, v14 }, [x0], x7
-# CHECK: ld3.4s { v10, v11, v12 }, [x0], x8
-# CHECK: ld3.2d { v15, v16, v17 }, [x2], x10
-
-0x00 0x40 0xdf 0x0c
-0x00 0x40 0xdf 0x4c
-0x00 0x44 0xdf 0x0c
-0x00 0x44 0xdf 0x4c
-0x00 0x48 0xdf 0x0c
-0x00 0x48 0xdf 0x4c
-0x00 0x4c 0xdf 0x4c
-
-# CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
-# CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
-# CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
-# CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
-# CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
-# CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
-# CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
-
-0x41 0x40 0x83 0x0c
-0x42 0x40 0x84 0x4c
-0x64 0x44 0x85 0x0c
-0x87 0x44 0x86 0x4c
-0x0c 0x48 0x87 0x0c
-0x0a 0x48 0x88 0x4c
-0x4f 0x4c 0x8a 0x4c
-
-# CHECK: st3.8b { v1, v2, v3 }, [x2], x3
-# CHECK: st3.16b { v2, v3, v4 }, [x2], x4
-# CHECK: st3.4h { v4, v5, v6 }, [x3], x5
-# CHECK: st3.8h { v7, v8, v9 }, [x4], x6
-# CHECK: st3.2s { v12, v13, v14 }, [x0], x7
-# CHECK: st3.4s { v10, v11, v12 }, [x0], x8
-# CHECK: st3.2d { v15, v16, v17 }, [x2], x10
-
-0x00 0x40 0x9f 0x0c
-0x00 0x40 0x9f 0x4c
-0x00 0x44 0x9f 0x0c
-0x00 0x44 0x9f 0x4c
-0x00 0x48 0x9f 0x0c
-0x00 0x48 0x9f 0x4c
-0x00 0x4c 0x9f 0x4c
-
-# CHECK: st3.8b { v0, v1, v2 }, [x0], #24
-# CHECK: st3.16b { v0, v1, v2 }, [x0], #48
-# CHECK: st3.4h { v0, v1, v2 }, [x0], #24
-# CHECK: st3.8h { v0, v1, v2 }, [x0], #48
-# CHECK: st3.2s { v0, v1, v2 }, [x0], #24
-# CHECK: st3.4s { v0, v1, v2 }, [x0], #48
-# CHECK: st3.2d { v0, v1, v2 }, [x0], #48
-
-0x61 0x28 0x40 0x0d
-0x82 0xa4 0x40 0x4d
-0xc3 0x70 0x40 0x0d
-0xe4 0xb0 0x40 0x4d
-
-# CHECK: ld3.b { v1, v2, v3 }[2], [x3]
-# CHECK: ld3.d { v2, v3, v4 }[1], [x4]
-# CHECK: ld3.h { v3, v4, v5 }[2], [x6]
-# CHECK: ld3.s { v4, v5, v6 }[3], [x7]
-
-0x61 0x28 0xdf 0x0d
-0x82 0xa4 0xdf 0x4d
-0xa3 0x78 0xdf 0x0d
-0xc4 0xa0 0xdf 0x4d
-
-# CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3
-# CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24
-# CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6
-# CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12
-
-0x61 0x28 0x00 0x0d
-0x82 0xa4 0x00 0x4d
-0xc3 0x70 0x00 0x0d
-0xe4 0xb0 0x00 0x4d
-
-# CHECK: st3.b { v1, v2, v3 }[2], [x3]
-# CHECK: st3.d { v2, v3, v4 }[1], [x4]
-# CHECK: st3.h { v3, v4, v5 }[2], [x6]
-# CHECK: st3.s { v4, v5, v6 }[3], [x7]
-
-0x21 0xe0 0x40 0x0d
-0x21 0xe0 0xc2 0x0d
-0x21 0xe0 0x40 0x4d
-0x21 0xe0 0xc2 0x4d
-0x21 0xe4 0x40 0x0d
-0x21 0xe4 0xc2 0x0d
-0x21 0xe4 0x40 0x4d
-0x21 0xe4 0xc2 0x4d
-0x21 0xe8 0x40 0x0d
-0x21 0xe8 0xc2 0x0d
-0x21 0xec 0x40 0x4d
-0x21 0xec 0xc2 0x4d
-0x21 0xec 0x40 0x0d
-0x21 0xec 0xc2 0x0d
-
-# CHECK: ld3r.8b { v1, v2, v3 }, [x1]
-# CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.16b { v1, v2, v3 }, [x1]
-# CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.4h { v1, v2, v3 }, [x1]
-# CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.8h { v1, v2, v3 }, [x1]
-# CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.2s { v1, v2, v3 }, [x1]
-# CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.2d { v1, v2, v3 }, [x1]
-# CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2
-# CHECK: ld3r.1d { v1, v2, v3 }, [x1]
-# CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2
-
-0x21 0xe0 0xdf 0x0d
-0x21 0xe0 0xdf 0x4d
-0x21 0xe4 0xdf 0x0d
-0x21 0xe4 0xdf 0x4d
-0x21 0xe8 0xdf 0x0d
-0x21 0xec 0xdf 0x4d
-0x21 0xec 0xdf 0x0d
-
-# CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3
-# CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3
-# CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6
-# CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6
-# CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12
-# CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24
-# CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24
-
-0x21 0x00 0x40 0x0c
-0x45 0x00 0x40 0x4c
-0x0a 0x08 0x40 0x0c
-
-# CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
-# CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
-
-0x21 0x00 0x00 0x0c
-0x45 0x00 0x00 0x4c
-0x0a 0x08 0x00 0x0c
-
-# CHECK: st4.8b { v1, v2, v3, v4 }, [x1]
-# CHECK: st4.16b { v5, v6, v7, v8 }, [x2]
-# CHECK: st4.2s { v10, v11, v12, v13 }, [x0]
-
-0x61 0x28 0xe4 0x0d
-0x82 0xa4 0xe5 0x4d
-0xa3 0x78 0xe6 0x0d
-0xc4 0xa0 0xe7 0x4d
-
-# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4
-# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5
-# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6
-# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7
-
-0x61 0x28 0xff 0x0d
-0x82 0xa4 0xff 0x4d
-0xa3 0x78 0xff 0x0d
-0xc4 0xa0 0xff 0x4d
-
-# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4
-# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32
-# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8
-# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16
-
-0x61 0x28 0xa4 0x0d
-0x82 0xa4 0xa5 0x4d
-0xa3 0x78 0xa6 0x0d
-0xc4 0xa0 0xa7 0x4d
-
-# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4
-# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5
-# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6
-# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7
-
-0x61 0x28 0xbf 0x0d
-0x82 0xa4 0xbf 0x4d
-0xa3 0x78 0xbf 0x0d
-0xc4 0xa0 0xbf 0x4d
-
-# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4
-# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32
-# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8
-# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16
-
-0x41 0x00 0xc3 0x0c
-0x42 0x00 0xc4 0x4c
-0x64 0x04 0xc5 0x0c
-0x87 0x04 0xc6 0x4c
-0x0c 0x08 0xc7 0x0c
-0x0a 0x08 0xc8 0x4c
-0x4f 0x0c 0xca 0x4c
-
-# CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3
-# CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4
-# CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5
-# CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6
-# CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7
-# CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8
-# CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10
-
-0x00 0x00 0xdf 0x0c
-0x00 0x00 0xdf 0x4c
-0x00 0x04 0xdf 0x0c
-0x00 0x04 0xdf 0x4c
-0x00 0x08 0xdf 0x0c
-0x00 0x08 0xdf 0x4c
-0x00 0x0c 0xdf 0x4c
-
-# CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
-# CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
-# CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
-# CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
-# CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
-# CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
-# CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
-
-0x00 0x00 0x9f 0x0c
-0x00 0x00 0x9f 0x4c
-0x00 0x04 0x9f 0x0c
-0x00 0x04 0x9f 0x4c
-0x00 0x08 0x9f 0x0c
-0x00 0x08 0x9f 0x4c
-0x00 0x0c 0x9f 0x4c
-
-# CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
-# CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
-# CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
-# CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
-# CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
-# CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
-# CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
-
-0x41 0x00 0x83 0x0c
-0x42 0x00 0x84 0x4c
-0x64 0x04 0x85 0x0c
-0x87 0x04 0x86 0x4c
-0x0c 0x08 0x87 0x0c
-0x0a 0x08 0x88 0x4c
-0x4f 0x0c 0x8a 0x4c
-
-# CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3
-# CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4
-# CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5
-# CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6
-# CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7
-# CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8
-# CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10
-
-0x61 0x28 0x60 0x0d
-0x82 0xa4 0x60 0x4d
-0xc3 0x70 0x60 0x0d
-0xe4 0xb0 0x60 0x4d
-
-# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3]
-# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4]
-# CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6]
-# CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7]
-
-0x61 0x28 0x20 0x0d
-0x82 0xa4 0x20 0x4d
-0xc3 0x70 0x20 0x0d
-0xe4 0xb0 0x20 0x4d
-
-# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3]
-# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4]
-# CHECK: st4.h { v3, v4, v5, v6 }[2], [x6]
-# CHECK: st4.s { v4, v5, v6, v7 }[3], [x7]
-
-0x21 0xe0 0x60 0x0d
-0x21 0xe0 0xe2 0x0d
-0x21 0xe0 0x60 0x4d
-0x21 0xe0 0xe2 0x4d
-0x21 0xe4 0x60 0x0d
-0x21 0xe4 0xe2 0x0d
-0x21 0xe4 0x60 0x4d
-0x21 0xe4 0xe2 0x4d
-0x21 0xe8 0x60 0x0d
-0x21 0xe8 0xe2 0x0d
-0x21 0xec 0x60 0x4d
-0x21 0xec 0xe2 0x4d
-0x21 0xec 0x60 0x0d
-0x21 0xec 0xe2 0x0d
-
-# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2
-# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1]
-# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2
-
-0x21 0xe0 0xff 0x0d
-0x21 0xe0 0xff 0x4d
-0x21 0xe4 0xff 0x0d
-0x21 0xe4 0xff 0x4d
-0x21 0xe8 0xff 0x0d
-0x21 0xec 0xff 0x4d
-0x21 0xec 0xff 0x0d
-
-# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4
-# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4
-# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8
-# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8
-# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16
-# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32
-# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32
-
-0x20 0xe4 0x00 0x2f
-0x20 0xe4 0x00 0x6f
-0x20 0xe4 0x00 0x0f
-0x20 0xe4 0x00 0x4f
-
-# CHECK: movi d0, #0x000000000000ff
-# CHECK: movi.2d v0, #0x000000000000ff
-# CHECK: movi.8b v0, #0x1
-# CHECK: movi.16b v0, #0x1
-
-0x20 0x04 0x00 0x0f
-0x20 0x24 0x00 0x0f
-0x20 0x44 0x00 0x0f
-0x20 0x64 0x00 0x0f
-
-# CHECK: movi.2s v0, #0x1
-# CHECK: movi.2s v0, #0x1, lsl #8
-# CHECK: movi.2s v0, #0x1, lsl #16
-# CHECK: movi.2s v0, #0x1, lsl #24
-
-0x20 0x04 0x00 0x4f
-0x20 0x24 0x00 0x4f
-0x20 0x44 0x00 0x4f
-0x20 0x64 0x00 0x4f
-
-# CHECK: movi.4s v0, #0x1
-# CHECK: movi.4s v0, #0x1, lsl #8
-# CHECK: movi.4s v0, #0x1, lsl #16
-# CHECK: movi.4s v0, #0x1, lsl #24
-
-0x20 0x84 0x00 0x0f
-0x20 0xa4 0x00 0x0f
-
-# CHECK: movi.4h v0, #0x1
-# CHECK: movi.4h v0, #0x1, lsl #8
-
-0x20 0x84 0x00 0x4f
-0x20 0xa4 0x00 0x4f
-
-# CHECK: movi.8h v0, #0x1
-# CHECK: movi.8h v0, #0x1, lsl #8
-
-0x20 0x04 0x00 0x2f
-0x20 0x24 0x00 0x2f
-0x20 0x44 0x00 0x2f
-0x20 0x64 0x00 0x2f
-
-# CHECK: mvni.2s v0, #0x1
-# CHECK: mvni.2s v0, #0x1, lsl #8
-# CHECK: mvni.2s v0, #0x1, lsl #16
-# CHECK: mvni.2s v0, #0x1, lsl #24
-
-0x20 0x04 0x00 0x6f
-0x20 0x24 0x00 0x6f
-0x20 0x44 0x00 0x6f
-0x20 0x64 0x00 0x6f
-
-# CHECK: mvni.4s v0, #0x1
-# CHECK: mvni.4s v0, #0x1, lsl #8
-# CHECK: mvni.4s v0, #0x1, lsl #16
-# CHECK: mvni.4s v0, #0x1, lsl #24
-
-0x20 0x84 0x00 0x2f
-0x20 0xa4 0x00 0x2f
-
-# CHECK: mvni.4h v0, #0x1
-# CHECK: mvni.4h v0, #0x1, lsl #8
-
-0x20 0x84 0x00 0x6f
-0x20 0xa4 0x00 0x6f
-
-# CHECK: mvni.8h v0, #0x1
-# CHECK: mvni.8h v0, #0x1, lsl #8
-
-0x20 0xc4 0x00 0x2f
-0x20 0xd4 0x00 0x2f
-0x20 0xc4 0x00 0x6f
-0x20 0xd4 0x00 0x6f
-
-# CHECK: mvni.2s v0, #0x1, msl #8
-# CHECK: mvni.2s v0, #0x1, msl #16
-# CHECK: mvni.4s v0, #0x1, msl #8
-# CHECK: mvni.4s v0, #0x1, msl #16
-
-0x00 0x88 0x21 0x2e
-0x00 0x98 0x21 0x2e
-0x00 0x98 0xa1 0x2e
-0x00 0x98 0x21 0x0e
-0x00 0x88 0x21 0x0e
-0x00 0x88 0xa1 0x0e
-0x00 0x98 0xa1 0x0e
-
-# CHECK: frinta.2s v0, v0
-# CHECK: frintx.2s v0, v0
-# CHECK: frinti.2s v0, v0
-# CHECK: frintm.2s v0, v0
-# CHECK: frintn.2s v0, v0
-# CHECK: frintp.2s v0, v0
-# CHECK: frintz.2s v0, v0
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD scalar x index instructions
-#===-------------------------------------------------------------------------===
-
-0x00 0x18 0xa0 0x5f
-0x00 0x18 0xc0 0x5f
-0x00 0x58 0xa0 0x5f
-0x00 0x58 0xc0 0x5f
-0x00 0x98 0xa0 0x7f
-0x00 0x98 0xc0 0x7f
-0x00 0x98 0xa0 0x5f
-0x00 0x98 0xc0 0x5f
-0x00 0x38 0x70 0x5f
-0x00 0x38 0xa0 0x5f
-0x00 0x78 0x70 0x5f
-0x00 0xc8 0x70 0x5f
-0x00 0xc8 0xa0 0x5f
-0x00 0xb8 0x70 0x5f
-0x00 0xb8 0xa0 0x5f
-0x00 0xd8 0x70 0x5f
-0x00 0xd8 0xa0 0x5f
-
-# CHECK: fmla.s s0, s0, v0[3]
-# CHECK: fmla.d d0, d0, v0[1]
-# CHECK: fmls.s s0, s0, v0[3]
-# CHECK: fmls.d d0, d0, v0[1]
-# CHECK: fmulx.s s0, s0, v0[3]
-# CHECK: fmulx.d d0, d0, v0[1]
-# CHECK: fmul.s s0, s0, v0[3]
-# CHECK: fmul.d d0, d0, v0[1]
-# CHECK: sqdmlal.h s0, h0, v0[7]
-# CHECK: sqdmlal.s d0, s0, v0[3]
-# CHECK: sqdmlsl.h s0, h0, v0[7]
-# CHECK: sqdmulh.h h0, h0, v0[7]
-# CHECK: sqdmulh.s s0, s0, v0[3]
-# CHECK: sqdmull.h s0, h0, v0[7]
-# CHECK: sqdmull.s d0, s0, v0[3]
-# CHECK: sqrdmulh.h h0, h0, v0[7]
-# CHECK: sqrdmulh.s s0, s0, v0[3]
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD vector x index instructions
-#===-------------------------------------------------------------------------===
-
- 0x00 0x10 0x80 0x0f
- 0x00 0x10 0xa0 0x4f
- 0x00 0x18 0xc0 0x4f
- 0x00 0x50 0x80 0x0f
- 0x00 0x50 0xa0 0x4f
- 0x00 0x58 0xc0 0x4f
- 0x00 0x90 0x80 0x2f
- 0x00 0x90 0xa0 0x6f
- 0x00 0x98 0xc0 0x6f
- 0x00 0x90 0x80 0x0f
- 0x00 0x90 0xa0 0x4f
- 0x00 0x98 0xc0 0x4f
- 0x00 0x00 0x40 0x2f
- 0x00 0x00 0x50 0x6f
- 0x00 0x08 0x80 0x2f
- 0x00 0x08 0xa0 0x6f
- 0x00 0x40 0x40 0x2f
- 0x00 0x40 0x50 0x6f
- 0x00 0x48 0x80 0x2f
- 0x00 0x48 0xa0 0x6f
- 0x00 0x80 0x40 0x0f
- 0x00 0x80 0x50 0x4f
- 0x00 0x88 0x80 0x0f
- 0x00 0x88 0xa0 0x4f
- 0x00 0x20 0x40 0x0f
- 0x00 0x20 0x50 0x4f
- 0x00 0x28 0x80 0x0f
- 0x00 0x28 0xa0 0x4f
- 0x00 0x60 0x40 0x0f
- 0x00 0x60 0x50 0x4f
- 0x00 0x68 0x80 0x0f
- 0x00 0x68 0xa0 0x4f
- 0x00 0xa0 0x40 0x0f
- 0x00 0xa0 0x50 0x4f
- 0x00 0xa8 0x80 0x0f
- 0x00 0xa8 0xa0 0x4f
- 0x00 0x30 0x40 0x0f
- 0x00 0x30 0x50 0x4f
- 0x00 0x38 0x80 0x0f
- 0x00 0x38 0xa0 0x4f
- 0x00 0x70 0x40 0x0f
- 0x00 0x70 0x50 0x4f
- 0x00 0x78 0x80 0x0f
- 0x00 0x78 0xa0 0x4f
- 0x00 0xc0 0x40 0x0f
- 0x00 0xc0 0x50 0x4f
- 0x00 0xc8 0x80 0x0f
- 0x00 0xc8 0xa0 0x4f
- 0x00 0xb0 0x40 0x0f
- 0x00 0xb0 0x50 0x4f
- 0x00 0xb8 0x80 0x0f
- 0x00 0xb8 0xa0 0x4f
- 0x00 0xd0 0x40 0x0f
- 0x00 0xd0 0x50 0x4f
- 0x00 0xd8 0x80 0x0f
- 0x00 0xd8 0xa0 0x4f
- 0x00 0x20 0x40 0x2f
- 0x00 0x20 0x50 0x6f
- 0x00 0x28 0x80 0x2f
- 0x00 0x28 0xa0 0x6f
- 0x00 0x60 0x40 0x2f
- 0x00 0x60 0x50 0x6f
- 0x00 0x68 0x80 0x2f
- 0x00 0x68 0xa0 0x6f
- 0x00 0xa0 0x40 0x2f
- 0x00 0xa0 0x50 0x6f
- 0x00 0xa8 0x80 0x2f
- 0x00 0xa8 0xa0 0x6f
-
-# CHECK: fmla.2s v0, v0, v0[0]
-# CHECK: fmla.4s v0, v0, v0[1]
-# CHECK: fmla.2d v0, v0, v0[1]
-# CHECK: fmls.2s v0, v0, v0[0]
-# CHECK: fmls.4s v0, v0, v0[1]
-# CHECK: fmls.2d v0, v0, v0[1]
-# CHECK: fmulx.2s v0, v0, v0[0]
-# CHECK: fmulx.4s v0, v0, v0[1]
-# CHECK: fmulx.2d v0, v0, v0[1]
-# CHECK: fmul.2s v0, v0, v0[0]
-# CHECK: fmul.4s v0, v0, v0[1]
-# CHECK: fmul.2d v0, v0, v0[1]
-# CHECK: mla.4h v0, v0, v0[0]
-# CHECK: mla.8h v0, v0, v0[1]
-# CHECK: mla.2s v0, v0, v0[2]
-# CHECK: mla.4s v0, v0, v0[3]
-# CHECK: mls.4h v0, v0, v0[0]
-# CHECK: mls.8h v0, v0, v0[1]
-# CHECK: mls.2s v0, v0, v0[2]
-# CHECK: mls.4s v0, v0, v0[3]
-# CHECK: mul.4h v0, v0, v0[0]
-# CHECK: mul.8h v0, v0, v0[1]
-# CHECK: mul.2s v0, v0, v0[2]
-# CHECK: mul.4s v0, v0, v0[3]
-# CHECK: smlal.4s v0, v0, v0[0]
-# CHECK: smlal2.4s v0, v0, v0[1]
-# CHECK: smlal.2d v0, v0, v0[2]
-# CHECK: smlal2.2d v0, v0, v0[3]
-# CHECK: smlsl.4s v0, v0, v0[0]
-# CHECK: smlsl2.4s v0, v0, v0[1]
-# CHECK: smlsl.2d v0, v0, v0[2]
-# CHECK: smlsl2.2d v0, v0, v0[3]
-# CHECK: smull.4s v0, v0, v0[0]
-# CHECK: smull2.4s v0, v0, v0[1]
-# CHECK: smull.2d v0, v0, v0[2]
-# CHECK: smull2.2d v0, v0, v0[3]
-# CHECK: sqdmlal.4s v0, v0, v0[0]
-# CHECK: sqdmlal2.4s v0, v0, v0[1]
-# CHECK: sqdmlal.2d v0, v0, v0[2]
-# CHECK: sqdmlal2.2d v0, v0, v0[3]
-# CHECK: sqdmlsl.4s v0, v0, v0[0]
-# CHECK: sqdmlsl2.4s v0, v0, v0[1]
-# CHECK: sqdmlsl.2d v0, v0, v0[2]
-# CHECK: sqdmlsl2.2d v0, v0, v0[3]
-# CHECK: sqdmulh.4h v0, v0, v0[0]
-# CHECK: sqdmulh.8h v0, v0, v0[1]
-# CHECK: sqdmulh.2s v0, v0, v0[2]
-# CHECK: sqdmulh.4s v0, v0, v0[3]
-# CHECK: sqdmull.4s v0, v0, v0[0]
-# CHECK: sqdmull2.4s v0, v0, v0[1]
-# CHECK: sqdmull.2d v0, v0, v0[2]
-# CHECK: sqdmull2.2d v0, v0, v0[3]
-# CHECK: sqrdmulh.4h v0, v0, v0[0]
-# CHECK: sqrdmulh.8h v0, v0, v0[1]
-# CHECK: sqrdmulh.2s v0, v0, v0[2]
-# CHECK: sqrdmulh.4s v0, v0, v0[3]
-# CHECK: umlal.4s v0, v0, v0[0]
-# CHECK: umlal2.4s v0, v0, v0[1]
-# CHECK: umlal.2d v0, v0, v0[2]
-# CHECK: umlal2.2d v0, v0, v0[3]
-# CHECK: umlsl.4s v0, v0, v0[0]
-# CHECK: umlsl2.4s v0, v0, v0[1]
-# CHECK: umlsl.2d v0, v0, v0[2]
-# CHECK: umlsl2.2d v0, v0, v0[3]
-# CHECK: umull.4s v0, v0, v0[0]
-# CHECK: umull2.4s v0, v0, v0[1]
-# CHECK: umull.2d v0, v0, v0[2]
-# CHECK: umull2.2d v0, v0, v0[3]
-
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD scalar + shift instructions
-#===-------------------------------------------------------------------------===
-
- 0x00 0x54 0x41 0x5f
- 0x00 0x54 0x41 0x7f
- 0x00 0x9c 0x09 0x5f
- 0x00 0x9c 0x12 0x5f
- 0x00 0x9c 0x23 0x5f
- 0x00 0x8c 0x09 0x7f
- 0x00 0x8c 0x12 0x7f
- 0x00 0x8c 0x23 0x7f
- 0x00 0x64 0x09 0x7f
- 0x00 0x64 0x12 0x7f
- 0x00 0x64 0x23 0x7f
- 0x00 0x64 0x44 0x7f
- 0x00 0x74 0x09 0x5f
- 0x00 0x74 0x12 0x5f
- 0x00 0x74 0x23 0x5f
- 0x00 0x74 0x44 0x5f
- 0x00 0x94 0x09 0x5f
- 0x00 0x94 0x12 0x5f
- 0x00 0x94 0x23 0x5f
- 0x00 0x84 0x09 0x7f
- 0x00 0x84 0x12 0x7f
- 0x00 0x84 0x23 0x7f
- 0x00 0x44 0x41 0x7f
- 0x00 0x24 0x41 0x5f
- 0x00 0x34 0x41 0x5f
- 0x00 0x04 0x41 0x5f
- 0x00 0xe4 0x21 0x7f
- 0x00 0xe4 0x42 0x7f
- 0x00 0x9c 0x09 0x7f
- 0x00 0x9c 0x12 0x7f
- 0x00 0x9c 0x23 0x7f
- 0x00 0x74 0x09 0x7f
- 0x00 0x74 0x12 0x7f
- 0x00 0x74 0x23 0x7f
- 0x00 0x74 0x44 0x7f
- 0x00 0x94 0x09 0x7f
- 0x00 0x94 0x12 0x7f
- 0x00 0x94 0x23 0x7f
- 0x00 0x24 0x41 0x7f
- 0x00 0x34 0x41 0x7f
- 0x00 0x04 0x41 0x7f
- 0x00 0x14 0x41 0x7f
-
-# CHECK: shl d0, d0, #1
-# CHECK: sli d0, d0, #1
-# CHECK: sqrshrn b0, h0, #7
-# CHECK: sqrshrn h0, s0, #14
-# CHECK: sqrshrn s0, d0, #29
-# CHECK: sqrshrun b0, h0, #7
-# CHECK: sqrshrun h0, s0, #14
-# CHECK: sqrshrun s0, d0, #29
-# CHECK: sqshlu b0, b0, #1
-# CHECK: sqshlu h0, h0, #2
-# CHECK: sqshlu s0, s0, #3
-# CHECK: sqshlu d0, d0, #4
-# CHECK: sqshl b0, b0, #1
-# CHECK: sqshl h0, h0, #2
-# CHECK: sqshl s0, s0, #3
-# CHECK: sqshl d0, d0, #4
-# CHECK: sqshrn b0, h0, #7
-# CHECK: sqshrn h0, s0, #14
-# CHECK: sqshrn s0, d0, #29
-# CHECK: sqshrun b0, h0, #7
-# CHECK: sqshrun h0, s0, #14
-# CHECK: sqshrun s0, d0, #29
-# CHECK: sri d0, d0, #63
-# CHECK: srshr d0, d0, #63
-# CHECK: srsra d0, d0, #63
-# CHECK: sshr d0, d0, #63
-# CHECK: ucvtf s0, s0, #31
-# CHECK: ucvtf d0, d0, #62
-# CHECK: uqrshrn b0, h0, #7
-# CHECK: uqrshrn h0, s0, #14
-# CHECK: uqrshrn s0, d0, #29
-# CHECK: uqshl b0, b0, #1
-# CHECK: uqshl h0, h0, #2
-# CHECK: uqshl s0, s0, #3
-# CHECK: uqshl d0, d0, #4
-# CHECK: uqshrn b0, h0, #7
-# CHECK: uqshrn h0, s0, #14
-# CHECK: uqshrn s0, d0, #29
-# CHECK: urshr d0, d0, #63
-# CHECK: ursra d0, d0, #63
-# CHECK: ushr d0, d0, #63
-# CHECK: usra d0, d0, #63
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD vector + shift instructions
-#===-------------------------------------------------------------------------===
-
- 0x00 0xfc 0x21 0x0f
- 0x00 0xfc 0x22 0x4f
- 0x00 0xfc 0x43 0x4f
- 0x00 0xfc 0x21 0x2f
- 0x00 0xfc 0x22 0x6f
- 0x00 0xfc 0x43 0x6f
- 0x00 0x8c 0x09 0x0f
- 0x00 0x8c 0x0a 0x4f
- 0x00 0x8c 0x13 0x0f
- 0x00 0x8c 0x14 0x4f
- 0x00 0x8c 0x25 0x0f
- 0x00 0x8c 0x26 0x4f
- 0x00 0xe4 0x21 0x0f
- 0x00 0xe4 0x22 0x4f
- 0x00 0xe4 0x43 0x4f
- 0x00 0x54 0x09 0x0f
- 0x00 0x54 0x0a 0x4f
- 0x00 0x54 0x13 0x0f
- 0x00 0x54 0x14 0x4f
- 0x00 0x54 0x25 0x0f
- 0x00 0x54 0x26 0x4f
- 0x00 0x54 0x47 0x4f
- 0x00 0x84 0x09 0x0f
- 0x00 0x84 0x0a 0x4f
- 0x00 0x84 0x13 0x0f
- 0x00 0x84 0x14 0x4f
- 0x00 0x84 0x25 0x0f
- 0x00 0x84 0x26 0x4f
- 0x00 0x54 0x09 0x2f
- 0x00 0x54 0x0a 0x6f
- 0x00 0x54 0x13 0x2f
- 0x00 0x54 0x14 0x6f
- 0x00 0x54 0x25 0x2f
- 0x00 0x54 0x26 0x6f
- 0x00 0x54 0x47 0x6f
- 0x00 0x9c 0x09 0x0f
- 0x00 0x9c 0x0a 0x4f
- 0x00 0x9c 0x13 0x0f
- 0x00 0x9c 0x14 0x4f
- 0x00 0x9c 0x25 0x0f
- 0x00 0x9c 0x26 0x4f
- 0x00 0x8c 0x09 0x2f
- 0x00 0x8c 0x0a 0x6f
- 0x00 0x8c 0x13 0x2f
- 0x00 0x8c 0x14 0x6f
- 0x00 0x8c 0x25 0x2f
- 0x00 0x8c 0x26 0x6f
- 0x00 0x64 0x09 0x2f
- 0x00 0x64 0x0a 0x6f
- 0x00 0x64 0x13 0x2f
- 0x00 0x64 0x14 0x6f
- 0x00 0x64 0x25 0x2f
- 0x00 0x64 0x26 0x6f
- 0x00 0x64 0x47 0x6f
- 0x00 0x74 0x09 0x0f
- 0x00 0x74 0x0a 0x4f
- 0x00 0x74 0x13 0x0f
- 0x00 0x74 0x14 0x4f
- 0x00 0x74 0x25 0x0f
- 0x00 0x74 0x26 0x4f
- 0x00 0x74 0x47 0x4f
- 0x00 0x94 0x09 0x0f
- 0x00 0x94 0x0a 0x4f
- 0x00 0x94 0x13 0x0f
- 0x00 0x94 0x14 0x4f
- 0x00 0x94 0x25 0x0f
- 0x00 0x94 0x26 0x4f
- 0x00 0x84 0x09 0x2f
- 0x00 0x84 0x0a 0x6f
- 0x00 0x84 0x13 0x2f
- 0x00 0x84 0x14 0x6f
- 0x00 0x84 0x25 0x2f
- 0x00 0x84 0x26 0x6f
- 0x00 0x44 0x09 0x2f
- 0x00 0x44 0x0a 0x6f
- 0x00 0x44 0x13 0x2f
- 0x00 0x44 0x14 0x6f
- 0x00 0x44 0x25 0x2f
- 0x00 0x44 0x26 0x6f
- 0x00 0x44 0x47 0x6f
- 0x00 0x24 0x09 0x0f
- 0x00 0x24 0x0a 0x4f
- 0x00 0x24 0x13 0x0f
- 0x00 0x24 0x14 0x4f
- 0x00 0x24 0x25 0x0f
- 0x00 0x24 0x26 0x4f
- 0x00 0x24 0x47 0x4f
- 0x00 0x34 0x09 0x0f
- 0x00 0x34 0x0a 0x4f
- 0x00 0x34 0x13 0x0f
- 0x00 0x34 0x14 0x4f
- 0x00 0x34 0x25 0x0f
- 0x00 0x34 0x26 0x4f
- 0x00 0x34 0x47 0x4f
- 0x00 0xa4 0x09 0x0f
- 0x00 0xa4 0x0a 0x4f
- 0x00 0xa4 0x13 0x0f
- 0x00 0xa4 0x14 0x4f
- 0x00 0xa4 0x25 0x0f
- 0x00 0xa4 0x26 0x4f
- 0x00 0x04 0x09 0x0f
- 0x00 0x04 0x0a 0x4f
- 0x00 0x04 0x13 0x0f
- 0x00 0x04 0x14 0x4f
- 0x00 0x04 0x25 0x0f
- 0x00 0x04 0x26 0x4f
- 0x00 0x04 0x47 0x4f
- 0x00 0x04 0x09 0x0f
- 0x00 0x14 0x0a 0x4f
- 0x00 0x14 0x13 0x0f
- 0x00 0x14 0x14 0x4f
- 0x00 0x14 0x25 0x0f
- 0x00 0x14 0x26 0x4f
- 0x00 0x14 0x47 0x4f
- 0x00 0x14 0x40 0x5f
- 0x00 0xe4 0x21 0x2f
- 0x00 0xe4 0x22 0x6f
- 0x00 0xe4 0x43 0x6f
- 0x00 0x9c 0x09 0x2f
- 0x00 0x9c 0x0a 0x6f
- 0x00 0x9c 0x13 0x2f
- 0x00 0x9c 0x14 0x6f
- 0x00 0x9c 0x25 0x2f
- 0x00 0x9c 0x26 0x6f
- 0x00 0x74 0x09 0x2f
- 0x00 0x74 0x0a 0x6f
- 0x00 0x74 0x13 0x2f
- 0x00 0x74 0x14 0x6f
- 0x00 0x74 0x25 0x2f
- 0x00 0x74 0x26 0x6f
- 0x00 0x74 0x47 0x6f
- 0x00 0x94 0x09 0x2f
- 0x00 0x94 0x0a 0x6f
- 0x00 0x94 0x13 0x2f
- 0x00 0x94 0x14 0x6f
- 0x00 0x94 0x25 0x2f
- 0x00 0x94 0x26 0x6f
- 0x00 0x24 0x09 0x2f
- 0x00 0x24 0x0a 0x6f
- 0x00 0x24 0x13 0x2f
- 0x00 0x24 0x14 0x6f
- 0x00 0x24 0x25 0x2f
- 0x00 0x24 0x26 0x6f
- 0x00 0x24 0x47 0x6f
- 0x00 0x34 0x09 0x2f
- 0x00 0x34 0x0a 0x6f
- 0x00 0x34 0x13 0x2f
- 0x00 0x34 0x14 0x6f
- 0x00 0x34 0x25 0x2f
- 0x00 0x34 0x26 0x6f
- 0x00 0x34 0x47 0x6f
- 0x00 0xa4 0x09 0x2f
- 0x00 0xa4 0x0a 0x6f
- 0x00 0xa4 0x13 0x2f
- 0x00 0xa4 0x14 0x6f
- 0x00 0xa4 0x25 0x2f
- 0x00 0xa4 0x26 0x6f
- 0x00 0x04 0x09 0x2f
- 0x00 0x04 0x0a 0x6f
- 0x00 0x04 0x13 0x2f
- 0x00 0x04 0x14 0x6f
- 0x00 0x04 0x25 0x2f
- 0x00 0x04 0x26 0x6f
- 0x00 0x04 0x47 0x6f
- 0x00 0x14 0x09 0x2f
- 0x00 0x14 0x0a 0x6f
- 0x00 0x14 0x13 0x2f
- 0x00 0x14 0x14 0x6f
- 0x00 0x14 0x25 0x2f
- 0x00 0x14 0x26 0x6f
- 0x00 0x14 0x47 0x6f
-
-# CHECK: fcvtzs.2s v0, v0, #31
-# CHECK: fcvtzs.4s v0, v0, #30
-# CHECK: fcvtzs.2d v0, v0, #61
-# CHECK: fcvtzu.2s v0, v0, #31
-# CHECK: fcvtzu.4s v0, v0, #30
-# CHECK: fcvtzu.2d v0, v0, #61
-# CHECK: rshrn.8b v0, v0, #7
-# CHECK: rshrn2.16b v0, v0, #6
-# CHECK: rshrn.4h v0, v0, #13
-# CHECK: rshrn2.8h v0, v0, #12
-# CHECK: rshrn.2s v0, v0, #27
-# CHECK: rshrn2.4s v0, v0, #26
-# CHECK: scvtf.2s v0, v0, #31
-# CHECK: scvtf.4s v0, v0, #30
-# CHECK: scvtf.2d v0, v0, #61
-# CHECK: shl.8b v0, v0, #1
-# CHECK: shl.16b v0, v0, #2
-# CHECK: shl.4h v0, v0, #3
-# CHECK: shl.8h v0, v0, #4
-# CHECK: shl.2s v0, v0, #5
-# CHECK: shl.4s v0, v0, #6
-# CHECK: shl.2d v0, v0, #7
-# CHECK: shrn.8b v0, v0, #7
-# CHECK: shrn2.16b v0, v0, #6
-# CHECK: shrn.4h v0, v0, #13
-# CHECK: shrn2.8h v0, v0, #12
-# CHECK: shrn.2s v0, v0, #27
-# CHECK: shrn2.4s v0, v0, #26
-# CHECK: sli.8b v0, v0, #1
-# CHECK: sli.16b v0, v0, #2
-# CHECK: sli.4h v0, v0, #3
-# CHECK: sli.8h v0, v0, #4
-# CHECK: sli.2s v0, v0, #5
-# CHECK: sli.4s v0, v0, #6
-# CHECK: sli.2d v0, v0, #7
-# CHECK: sqrshrn.8b v0, v0, #7
-# CHECK: sqrshrn2.16b v0, v0, #6
-# CHECK: sqrshrn.4h v0, v0, #13
-# CHECK: sqrshrn2.8h v0, v0, #12
-# CHECK: sqrshrn.2s v0, v0, #27
-# CHECK: sqrshrn2.4s v0, v0, #26
-# CHECK: sqrshrun.8b v0, v0, #7
-# CHECK: sqrshrun2.16b v0, v0, #6
-# CHECK: sqrshrun.4h v0, v0, #13
-# CHECK: sqrshrun2.8h v0, v0, #12
-# CHECK: sqrshrun.2s v0, v0, #27
-# CHECK: sqrshrun2.4s v0, v0, #26
-# CHECK: sqshlu.8b v0, v0, #1
-# CHECK: sqshlu.16b v0, v0, #2
-# CHECK: sqshlu.4h v0, v0, #3
-# CHECK: sqshlu.8h v0, v0, #4
-# CHECK: sqshlu.2s v0, v0, #5
-# CHECK: sqshlu.4s v0, v0, #6
-# CHECK: sqshlu.2d v0, v0, #7
-# CHECK: sqshl.8b v0, v0, #1
-# CHECK: sqshl.16b v0, v0, #2
-# CHECK: sqshl.4h v0, v0, #3
-# CHECK: sqshl.8h v0, v0, #4
-# CHECK: sqshl.2s v0, v0, #5
-# CHECK: sqshl.4s v0, v0, #6
-# CHECK: sqshl.2d v0, v0, #7
-# CHECK: sqshrn.8b v0, v0, #7
-# CHECK: sqshrn2.16b v0, v0, #6
-# CHECK: sqshrn.4h v0, v0, #13
-# CHECK: sqshrn2.8h v0, v0, #12
-# CHECK: sqshrn.2s v0, v0, #27
-# CHECK: sqshrn2.4s v0, v0, #26
-# CHECK: sqshrun.8b v0, v0, #7
-# CHECK: sqshrun2.16b v0, v0, #6
-# CHECK: sqshrun.4h v0, v0, #13
-# CHECK: sqshrun2.8h v0, v0, #12
-# CHECK: sqshrun.2s v0, v0, #27
-# CHECK: sqshrun2.4s v0, v0, #26
-# CHECK: sri.8b v0, v0, #7
-# CHECK: sri.16b v0, v0, #6
-# CHECK: sri.4h v0, v0, #13
-# CHECK: sri.8h v0, v0, #12
-# CHECK: sri.2s v0, v0, #27
-# CHECK: sri.4s v0, v0, #26
-# CHECK: sri.2d v0, v0, #57
-# CHECK: srshr.8b v0, v0, #7
-# CHECK: srshr.16b v0, v0, #6
-# CHECK: srshr.4h v0, v0, #13
-# CHECK: srshr.8h v0, v0, #12
-# CHECK: srshr.2s v0, v0, #27
-# CHECK: srshr.4s v0, v0, #26
-# CHECK: srshr.2d v0, v0, #57
-# CHECK: srsra.8b v0, v0, #7
-# CHECK: srsra.16b v0, v0, #6
-# CHECK: srsra.4h v0, v0, #13
-# CHECK: srsra.8h v0, v0, #12
-# CHECK: srsra.2s v0, v0, #27
-# CHECK: srsra.4s v0, v0, #26
-# CHECK: srsra.2d v0, v0, #57
-# CHECK: sshll.8h v0, v0, #1
-# CHECK: sshll2.8h v0, v0, #2
-# CHECK: sshll.4s v0, v0, #3
-# CHECK: sshll2.4s v0, v0, #4
-# CHECK: sshll.2d v0, v0, #5
-# CHECK: sshll2.2d v0, v0, #6
-# CHECK: sshr.8b v0, v0, #7
-# CHECK: sshr.16b v0, v0, #6
-# CHECK: sshr.4h v0, v0, #13
-# CHECK: sshr.8h v0, v0, #12
-# CHECK: sshr.2s v0, v0, #27
-# CHECK: sshr.4s v0, v0, #26
-# CHECK: sshr.2d v0, v0, #57
-# CHECK: sshr.8b v0, v0, #7
-# CHECK: ssra.16b v0, v0, #6
-# CHECK: ssra.4h v0, v0, #13
-# CHECK: ssra.8h v0, v0, #12
-# CHECK: ssra.2s v0, v0, #27
-# CHECK: ssra.4s v0, v0, #26
-# CHECK: ssra.2d v0, v0, #57
-# CHECK: ssra d0, d0, #64
-# CHECK: ucvtf.2s v0, v0, #31
-# CHECK: ucvtf.4s v0, v0, #30
-# CHECK: ucvtf.2d v0, v0, #61
-# CHECK: uqrshrn.8b v0, v0, #7
-# CHECK: uqrshrn2.16b v0, v0, #6
-# CHECK: uqrshrn.4h v0, v0, #13
-# CHECK: uqrshrn2.8h v0, v0, #12
-# CHECK: uqrshrn.2s v0, v0, #27
-# CHECK: uqrshrn2.4s v0, v0, #26
-# CHECK: uqshl.8b v0, v0, #1
-# CHECK: uqshl.16b v0, v0, #2
-# CHECK: uqshl.4h v0, v0, #3
-# CHECK: uqshl.8h v0, v0, #4
-# CHECK: uqshl.2s v0, v0, #5
-# CHECK: uqshl.4s v0, v0, #6
-# CHECK: uqshl.2d v0, v0, #7
-# CHECK: uqshrn.8b v0, v0, #7
-# CHECK: uqshrn2.16b v0, v0, #6
-# CHECK: uqshrn.4h v0, v0, #13
-# CHECK: uqshrn2.8h v0, v0, #12
-# CHECK: uqshrn.2s v0, v0, #27
-# CHECK: uqshrn2.4s v0, v0, #26
-# CHECK: urshr.8b v0, v0, #7
-# CHECK: urshr.16b v0, v0, #6
-# CHECK: urshr.4h v0, v0, #13
-# CHECK: urshr.8h v0, v0, #12
-# CHECK: urshr.2s v0, v0, #27
-# CHECK: urshr.4s v0, v0, #26
-# CHECK: urshr.2d v0, v0, #57
-# CHECK: ursra.8b v0, v0, #7
-# CHECK: ursra.16b v0, v0, #6
-# CHECK: ursra.4h v0, v0, #13
-# CHECK: ursra.8h v0, v0, #12
-# CHECK: ursra.2s v0, v0, #27
-# CHECK: ursra.4s v0, v0, #26
-# CHECK: ursra.2d v0, v0, #57
-# CHECK: ushll.8h v0, v0, #1
-# CHECK: ushll2.8h v0, v0, #2
-# CHECK: ushll.4s v0, v0, #3
-# CHECK: ushll2.4s v0, v0, #4
-# CHECK: ushll.2d v0, v0, #5
-# CHECK: ushll2.2d v0, v0, #6
-# CHECK: ushr.8b v0, v0, #7
-# CHECK: ushr.16b v0, v0, #6
-# CHECK: ushr.4h v0, v0, #13
-# CHECK: ushr.8h v0, v0, #12
-# CHECK: ushr.2s v0, v0, #27
-# CHECK: ushr.4s v0, v0, #26
-# CHECK: ushr.2d v0, v0, #57
-# CHECK: usra.8b v0, v0, #7
-# CHECK: usra.16b v0, v0, #6
-# CHECK: usra.4h v0, v0, #13
-# CHECK: usra.8h v0, v0, #12
-# CHECK: usra.2s v0, v0, #27
-# CHECK: usra.4s v0, v0, #26
-# CHECK: usra.2d v0, v0, #57
-
-
- 0x00 0xe0 0x20 0x0e
- 0x00 0xe0 0x20 0x4e
- 0x00 0xe0 0xe0 0x0e
- 0x00 0xe0 0xe0 0x4e
-
-# CHECK: pmull.8h v0, v0, v0
-# CHECK: pmull2.8h v0, v0, v0
-# CHECK: pmull.1q v0, v0, v0
-# CHECK: pmull2.1q v0, v0, v0
-
- 0x41 0xd8 0x70 0x7e
- 0x83 0xd8 0x30 0x7e
-# CHECK: faddp.2d d1, v2
-# CHECK: faddp.2s s3, v4
-
- 0x82 0x60 0x01 0x4e
- 0x80 0x60 0x01 0x0e
- 0xa2 0x00 0x01 0x4e
- 0xa0 0x00 0x01 0x0e
- 0xa2 0x40 0x01 0x4e
- 0xa0 0x40 0x01 0x0e
- 0xc2 0x20 0x01 0x4e
- 0xc0 0x20 0x01 0x0e
-
-# CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1
-# CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1
-# CHECK: tbl.16b v2, { v5 }, v1
-# CHECK: tbl.8b v0, { v5 }, v1
-# CHECK: tbl.16b v2, { v5, v6, v7 }, v1
-# CHECK: tbl.8b v0, { v5, v6, v7 }, v1
-# CHECK: tbl.16b v2, { v6, v7 }, v1
-# CHECK: tbl.8b v0, { v6, v7 }, v1
-#
- 0x82 0x70 0x01 0x4e
- 0x80 0x70 0x01 0x0e
- 0xa2 0x10 0x01 0x4e
- 0xa0 0x10 0x01 0x0e
- 0xa2 0x50 0x01 0x4e
- 0xa0 0x50 0x01 0x0e
- 0xc2 0x30 0x01 0x4e
- 0xc0 0x30 0x01 0x0e
-
-# CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1
-# CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1
-# CHECK: tbx.16b v2, { v5 }, v1
-# CHECK: tbx.8b v0, { v5 }, v1
-# CHECK: tbx.16b v2, { v5, v6, v7 }, v1
-# CHECK: tbx.8b v0, { v5, v6, v7 }, v1
-# CHECK: tbx.16b v2, { v6, v7 }, v1
-# CHECK: tbx.8b v0, { v6, v7 }, v1
-#
-
-0x00 0x80 0x20 0x0e
-0x00 0x80 0x20 0x4e
-0x00 0x80 0xa0 0x0e
-0x00 0x80 0xa0 0x4e
-
-# CHECK: smlal.8h v0, v0, v0
-# CHECK: smlal2.8h v0, v0, v0
-# CHECK: smlal.2d v0, v0, v0
-# CHECK: smlal2.2d v0, v0, v0
-
-0x00 0x80 0x20 0x2e
-0x00 0x80 0x20 0x6e
-0x00 0x80 0xa0 0x2e
-0x00 0x80 0xa0 0x6e
-
-# CHECK: umlal.8h v0, v0, v0
-# CHECK: umlal2.8h v0, v0, v0
-# CHECK: umlal.2d v0, v0, v0
-# CHECK: umlal2.2d v0, v0, v0
-
-0x00 0x90 0x60 0x5e
-0x00 0x90 0xa0 0x5e
-0x00 0xb0 0x60 0x5e
-0x00 0xb0 0xa0 0x5e
-
-# CHECK: sqdmlal s0, h0, h0
-# CHECK: sqdmlal d0, s0, s0
-# CHECK: sqdmlsl s0, h0, h0
-# CHECK: sqdmlsl d0, s0, s0
-
-0xaa 0xc5 0xc7 0x4d
-0xaa 0xc9 0xc7 0x4d
-0xaa 0xc1 0xc7 0x4d
-
-# CHECK: ld1r.8h { v10 }, [x13], x7
-# CHECK: ld1r.4s { v10 }, [x13], x7
-# CHECK: ld1r.16b { v10 }, [x13], x7
-
-0x00 0xd0 0x60 0x5e
-0x00 0xd0 0xa0 0x5e
-# CHECK: sqdmull s0, h0, h0
-# CHECK: sqdmull d0, s0, s0
-
-0x00 0xd8 0xa1 0x7e
-0x00 0xd8 0xe1 0x7e
-
-# CHECK: frsqrte s0, s0
-# CHECK: frsqrte d0, d0
-
-0xca 0xcd 0xc7 0x4d
-0xea 0xc9 0xe7 0x4d
-0xea 0xe9 0xc7 0x4d
-0xea 0xe9 0xe7 0x4d
-# CHECK: ld1r.2d { v10 }, [x14], x7
-# CHECK: ld2r.4s { v10, v11 }, [x15], x7
-# CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7
-# CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7
-
-#===-------------------------------------------------------------------------===
-# AdvSIMD scalar three same
-#===-------------------------------------------------------------------------===
-0x62 0xdc 0x21 0x5e
-# CHECK: fmulx s2, s3, s1
-0x62 0xdc 0x61 0x5e
-# CHECK: fmulx d2, d3, d1
-
-
-# rdar://12511369
-0xe8 0x6b 0xdf 0x4c
-# CHECK: ld1.4s { v8, v9, v10 }, [sp], #48
Removed: llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt (removed)
@@ -1,526 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-#==---------------------------------------------------------------------------==
-# Add/Subtract with carry/borrow
-#==---------------------------------------------------------------------------==
-
-0x41 0x00 0x03 0x1a
-0x41 0x00 0x03 0x9a
-0x85 0x00 0x03 0x3a
-0x85 0x00 0x03 0xba
-
-# CHECK: adc w1, w2, w3
-# CHECK: adc x1, x2, x3
-# CHECK: adcs w5, w4, w3
-# CHECK: adcs x5, x4, x3
-
-0x41 0x00 0x03 0x5a
-0x41 0x00 0x03 0xda
-0x41 0x00 0x03 0x7a
-0x41 0x00 0x03 0xfa
-
-# CHECK: sbc w1, w2, w3
-# CHECK: sbc x1, x2, x3
-# CHECK: sbcs w1, w2, w3
-# CHECK: sbcs x1, x2, x3
-
-#==---------------------------------------------------------------------------==
-# Add/Subtract with (optionally shifted) immediate
-#==---------------------------------------------------------------------------==
-
-0x83 0x00 0x10 0x11
-0x83 0x00 0x10 0x91
-
-# CHECK: add w3, w4, #1024
-# CHECK: add x3, x4, #1024
-
-0x83 0x00 0x50 0x11
-0x83 0x00 0x40 0x11
-0x83 0x00 0x50 0x91
-0x83 0x00 0x40 0x91
-0xff 0x83 0x00 0x91
-
-# CHECK: add w3, w4, #1024, lsl #12
-# CHECK: add x3, x4, #1024, lsl #12
-# CHECK: add x3, x4, #0, lsl #12
-# CHECK: add sp, sp, #32
-
-0x83 0x00 0x10 0x31
-0x83 0x00 0x50 0x31
-0x83 0x00 0x10 0xb1
-0x83 0x00 0x50 0xb1
-0xff 0x83 0x00 0xb1
-
-# CHECK: adds w3, w4, #1024
-# CHECK: adds w3, w4, #1024, lsl #12
-# CHECK: adds x3, x4, #1024
-# CHECK: adds x3, x4, #1024, lsl #12
-# CHECK: cmn sp, #32
-
-0x83 0x00 0x10 0x51
-0x83 0x00 0x50 0x51
-0x83 0x00 0x10 0xd1
-0x83 0x00 0x50 0xd1
-0xff 0x83 0x00 0xd1
-
-# CHECK: sub w3, w4, #1024
-# CHECK: sub w3, w4, #1024, lsl #12
-# CHECK: sub x3, x4, #1024
-# CHECK: sub x3, x4, #1024, lsl #12
-# CHECK: sub sp, sp, #32
-
-0x83 0x00 0x10 0x71
-0x83 0x00 0x50 0x71
-0x83 0x00 0x10 0xf1
-0x83 0x00 0x50 0xf1
-0xff 0x83 0x00 0xf1
-
-# CHECK: subs w3, w4, #1024
-# CHECK: subs w3, w4, #1024, lsl #12
-# CHECK: subs x3, x4, #1024
-# CHECK: subs x3, x4, #1024, lsl #12
-# CHECK: cmp sp, #32
-
-#==---------------------------------------------------------------------------==
-# Add/Subtract register with (optional) shift
-#==---------------------------------------------------------------------------==
-
-0xac 0x01 0x0e 0x0b
-0xac 0x01 0x0e 0x8b
-0xac 0x31 0x0e 0x0b
-0xac 0x31 0x0e 0x8b
-0xac 0x29 0x4e 0x0b
-0xac 0x29 0x4e 0x8b
-0xac 0x1d 0x8e 0x0b
-0xac 0x9d 0x8e 0x8b
-
-# CHECK: add w12, w13, w14
-# CHECK: add x12, x13, x14
-# CHECK: add w12, w13, w14, lsl #12
-# CHECK: add x12, x13, x14, lsl #12
-# CHECK: add w12, w13, w14, lsr #10
-# CHECK: add x12, x13, x14, lsr #10
-# CHECK: add w12, w13, w14, asr #7
-# CHECK: add x12, x13, x14, asr #39
-
-0xac 0x01 0x0e 0x4b
-0xac 0x01 0x0e 0xcb
-0xac 0x31 0x0e 0x4b
-0xac 0x31 0x0e 0xcb
-0xac 0x29 0x4e 0x4b
-0xac 0x29 0x4e 0xcb
-0xac 0x1d 0x8e 0x4b
-0xac 0x9d 0x8e 0xcb
-
-# CHECK: sub w12, w13, w14
-# CHECK: sub x12, x13, x14
-# CHECK: sub w12, w13, w14, lsl #12
-# CHECK: sub x12, x13, x14, lsl #12
-# CHECK: sub w12, w13, w14, lsr #10
-# CHECK: sub x12, x13, x14, lsr #10
-# CHECK: sub w12, w13, w14, asr #7
-# CHECK: sub x12, x13, x14, asr #39
-
-0xac 0x01 0x0e 0x2b
-0xac 0x01 0x0e 0xab
-0xac 0x31 0x0e 0x2b
-0xac 0x31 0x0e 0xab
-0xac 0x29 0x4e 0x2b
-0xac 0x29 0x4e 0xab
-0xac 0x1d 0x8e 0x2b
-0xac 0x9d 0x8e 0xab
-
-# CHECK: adds w12, w13, w14
-# CHECK: adds x12, x13, x14
-# CHECK: adds w12, w13, w14, lsl #12
-# CHECK: adds x12, x13, x14, lsl #12
-# CHECK: adds w12, w13, w14, lsr #10
-# CHECK: adds x12, x13, x14, lsr #10
-# CHECK: adds w12, w13, w14, asr #7
-# CHECK: adds x12, x13, x14, asr #39
-
-0xac 0x01 0x0e 0x6b
-0xac 0x01 0x0e 0xeb
-0xac 0x31 0x0e 0x6b
-0xac 0x31 0x0e 0xeb
-0xac 0x29 0x4e 0x6b
-0xac 0x29 0x4e 0xeb
-0xac 0x1d 0x8e 0x6b
-0xac 0x9d 0x8e 0xeb
-
-# CHECK: subs w12, w13, w14
-# CHECK: subs x12, x13, x14
-# CHECK: subs w12, w13, w14, lsl #12
-# CHECK: subs x12, x13, x14, lsl #12
-# CHECK: subs w12, w13, w14, lsr #10
-# CHECK: subs x12, x13, x14, lsr #10
-# CHECK: subs w12, w13, w14, asr #7
-# CHECK: subs x12, x13, x14, asr #39
-
-#==---------------------------------------------------------------------------==
-# Add/Subtract with (optional) extend
-#==---------------------------------------------------------------------------==
-
-0x41 0x00 0x23 0x0b
-0x41 0x20 0x23 0x0b
-0x41 0x40 0x23 0x0b
-0x41 0x60 0x23 0x0b
-0x41 0x80 0x23 0x0b
-0x41 0xa0 0x23 0x0b
-0x41 0xc0 0x23 0x0b
-0x41 0xe0 0x23 0x0b
-
-# CHECK: add w1, w2, w3, uxtb
-# CHECK: add w1, w2, w3, uxth
-# CHECK: add w1, w2, w3
-# CHECK: add w1, w2, w3, uxtx
-# CHECK: add w1, w2, w3, sxtb
-# CHECK: add w1, w2, w3, sxth
-# CHECK: add w1, w2, w3, sxtw
-# CHECK: add w1, w2, w3, sxtx
-
-0x41 0x00 0x23 0x8b
-0x41 0x20 0x23 0x8b
-0x41 0x40 0x23 0x8b
-0x41 0x80 0x23 0x8b
-0x41 0xa0 0x23 0x8b
-0x41 0xc0 0x23 0x8b
-
-# CHECK: add x1, x2, w3, uxtb
-# CHECK: add x1, x2, w3, uxth
-# CHECK: add x1, x2, w3, uxtw
-# CHECK: add x1, x2, w3, sxtb
-# CHECK: add x1, x2, w3, sxth
-# CHECK: add x1, x2, w3, sxtw
-
-0xe1 0x43 0x23 0x0b
-0xe1 0x43 0x23 0x0b
-0x5f 0x60 0x23 0x8b
-0x5f 0x60 0x23 0x8b
-
-# CHECK: add w1, wsp, w3
-# CHECK: add w1, wsp, w3
-# CHECK: add sp, x2, x3
-# CHECK: add sp, x2, x3
-
-0x41 0x00 0x23 0x4b
-0x41 0x20 0x23 0x4b
-0x41 0x40 0x23 0x4b
-0x41 0x60 0x23 0x4b
-0x41 0x80 0x23 0x4b
-0x41 0xa0 0x23 0x4b
-0x41 0xc0 0x23 0x4b
-0x41 0xe0 0x23 0x4b
-
-# CHECK: sub w1, w2, w3, uxtb
-# CHECK: sub w1, w2, w3, uxth
-# CHECK: sub w1, w2, w3
-# CHECK: sub w1, w2, w3, uxtx
-# CHECK: sub w1, w2, w3, sxtb
-# CHECK: sub w1, w2, w3, sxth
-# CHECK: sub w1, w2, w3, sxtw
-# CHECK: sub w1, w2, w3, sxtx
-
-0x41 0x00 0x23 0xcb
-0x41 0x20 0x23 0xcb
-0x41 0x40 0x23 0xcb
-0x41 0x80 0x23 0xcb
-0x41 0xa0 0x23 0xcb
-0x41 0xc0 0x23 0xcb
-
-# CHECK: sub x1, x2, w3, uxtb
-# CHECK: sub x1, x2, w3, uxth
-# CHECK: sub x1, x2, w3, uxtw
-# CHECK: sub x1, x2, w3, sxtb
-# CHECK: sub x1, x2, w3, sxth
-# CHECK: sub x1, x2, w3, sxtw
-
-0xe1 0x43 0x23 0x4b
-0xe1 0x43 0x23 0x4b
-0x5f 0x60 0x23 0xcb
-0x5f 0x60 0x23 0xcb
-
-# CHECK: sub w1, wsp, w3
-# CHECK: sub w1, wsp, w3
-# CHECK: sub sp, x2, x3
-# CHECK: sub sp, x2, x3
-
-0x41 0x00 0x23 0x2b
-0x41 0x20 0x23 0x2b
-0x41 0x40 0x23 0x2b
-0x41 0x60 0x23 0x2b
-0x41 0x80 0x23 0x2b
-0x41 0xa0 0x23 0x2b
-0x41 0xc0 0x23 0x2b
-0x41 0xe0 0x23 0x2b
-
-# CHECK: adds w1, w2, w3, uxtb
-# CHECK: adds w1, w2, w3, uxth
-# CHECK: adds w1, w2, w3
-# CHECK: adds w1, w2, w3, uxtx
-# CHECK: adds w1, w2, w3, sxtb
-# CHECK: adds w1, w2, w3, sxth
-# CHECK: adds w1, w2, w3, sxtw
-# CHECK: adds w1, w2, w3, sxtx
-
-0x41 0x00 0x23 0xab
-0x41 0x20 0x23 0xab
-0x41 0x40 0x23 0xab
-0x41 0x80 0x23 0xab
-0x41 0xa0 0x23 0xab
-0x41 0xc0 0x23 0xab
-
-# CHECK: adds x1, x2, w3, uxtb
-# CHECK: adds x1, x2, w3, uxth
-# CHECK: adds x1, x2, w3, uxtw
-# CHECK: adds x1, x2, w3, sxtb
-# CHECK: adds x1, x2, w3, sxth
-# CHECK: adds x1, x2, w3, sxtw
-
-0xe1 0x43 0x23 0x2b
-0xe1 0x43 0x23 0x2b
-
-# CHECK: adds w1, wsp, w3
-# CHECK: adds w1, wsp, w3
-
-0x41 0x00 0x23 0x6b
-0x41 0x20 0x23 0x6b
-0x41 0x40 0x23 0x6b
-0x41 0x60 0x23 0x6b
-0x41 0x80 0x23 0x6b
-0x41 0xa0 0x23 0x6b
-0x41 0xc0 0x23 0x6b
-0x41 0xe0 0x23 0x6b
-
-# CHECK: subs w1, w2, w3, uxtb
-# CHECK: subs w1, w2, w3, uxth
-# CHECK: subs w1, w2, w3
-# CHECK: subs w1, w2, w3, uxtx
-# CHECK: subs w1, w2, w3, sxtb
-# CHECK: subs w1, w2, w3, sxth
-# CHECK: subs w1, w2, w3, sxtw
-# CHECK: subs w1, w2, w3, sxtx
-
-0x41 0x00 0x23 0xeb
-0x41 0x20 0x23 0xeb
-0x41 0x40 0x23 0xeb
-0x41 0x80 0x23 0xeb
-0x41 0xa0 0x23 0xeb
-0x41 0xc0 0x23 0xeb
-
-# CHECK: subs x1, x2, w3, uxtb
-# CHECK: subs x1, x2, w3, uxth
-# CHECK: subs x1, x2, w3, uxtw
-# CHECK: subs x1, x2, w3, sxtb
-# CHECK: subs x1, x2, w3, sxth
-# CHECK: subs x1, x2, w3, sxtw
-
-0xe1 0x43 0x23 0x6b
-0xe1 0x43 0x23 0x6b
-
-# CHECK: subs w1, wsp, w3
-# CHECK: subs w1, wsp, w3
-
-0x1f 0x41 0x28 0xeb
-0x3f 0x41 0x28 0x6b
-0xff 0x43 0x28 0x6b
-0xff 0x43 0x28 0xeb
-
-# CHECK: cmp x8, w8, uxtw
-# CHECK: cmp w9, w8, uxtw
-# CHECK: cmp wsp, w8
-# CHECK: cmp sp, w8
-
-0x3f 0x41 0x28 0x4b
-0xe1 0x43 0x28 0x4b
-0xff 0x43 0x28 0x4b
-0x3f 0x41 0x28 0xcb
-0xe1 0x43 0x28 0xcb
-0xff 0x43 0x28 0xcb
-0xe1 0x43 0x28 0x6b
-0xe1 0x43 0x28 0xeb
-
-# CHECK: sub wsp, w9, w8
-# CHECK: sub w1, wsp, w8
-# CHECK: sub wsp, wsp, w8
-# CHECK: sub sp, x9, w8
-# CHECK: sub x1, sp, w8
-# CHECK: sub sp, sp, w8
-# CHECK: subs w1, wsp, w8
-# CHECK: subs x1, sp, w8
-
-#==---------------------------------------------------------------------------==
-# Signed/Unsigned divide
-#==---------------------------------------------------------------------------==
-
-0x41 0x0c 0xc3 0x1a
-0x41 0x0c 0xc3 0x9a
-0x41 0x08 0xc3 0x1a
-0x41 0x08 0xc3 0x9a
-
-# CHECK: sdiv w1, w2, w3
-# CHECK: sdiv x1, x2, x3
-# CHECK: udiv w1, w2, w3
-# CHECK: udiv x1, x2, x3
-
-#==---------------------------------------------------------------------------==
-# Variable shifts
-#==---------------------------------------------------------------------------==
-
- 0x41 0x28 0xc3 0x1a
-# CHECK: asr w1, w2, w3
- 0x41 0x28 0xc3 0x9a
-# CHECK: asr x1, x2, x3
- 0x41 0x20 0xc3 0x1a
-# CHECK: lsl w1, w2, w3
- 0x41 0x20 0xc3 0x9a
-# CHECK: lsl x1, x2, x3
- 0x41 0x24 0xc3 0x1a
-# CHECK: lsr w1, w2, w3
- 0x41 0x24 0xc3 0x9a
-# CHECK: lsr x1, x2, x3
- 0x41 0x2c 0xc3 0x1a
-# CHECK: ror w1, w2, w3
- 0x41 0x2c 0xc3 0x9a
-# CHECK: ror x1, x2, x3
-
-#==---------------------------------------------------------------------------==
-# One operand instructions
-#==---------------------------------------------------------------------------==
-
- 0x41 0x14 0xc0 0x5a
-# CHECK: cls w1, w2
- 0x41 0x14 0xc0 0xda
-# CHECK: cls x1, x2
- 0x41 0x10 0xc0 0x5a
-# CHECK: clz w1, w2
- 0x41 0x10 0xc0 0xda
-# CHECK: clz x1, x2
- 0x41 0x00 0xc0 0x5a
-# CHECK: rbit w1, w2
- 0x41 0x00 0xc0 0xda
-# CHECK: rbit x1, x2
- 0x41 0x08 0xc0 0x5a
-# CHECK: rev w1, w2
- 0x41 0x0c 0xc0 0xda
-# CHECK: rev x1, x2
- 0x41 0x04 0xc0 0x5a
-# CHECK: rev16 w1, w2
- 0x41 0x04 0xc0 0xda
-# CHECK: rev16 x1, x2
- 0x41 0x08 0xc0 0xda
-# CHECK: rev32 x1, x2
-
-#==---------------------------------------------------------------------------==
-# 6.6.1 Multiply-add instructions
-#==---------------------------------------------------------------------------==
-
-0x41 0x10 0x03 0x1b
-0x41 0x10 0x03 0x9b
-0x41 0x90 0x03 0x1b
-0x41 0x90 0x03 0x9b
-0x41 0x10 0x23 0x9b
-0x41 0x90 0x23 0x9b
-0x41 0x10 0xa3 0x9b
-0x41 0x90 0xa3 0x9b
-
-# CHECK: madd w1, w2, w3, w4
-# CHECK: madd x1, x2, x3, x4
-# CHECK: msub w1, w2, w3, w4
-# CHECK: msub x1, x2, x3, x4
-# CHECK: smaddl x1, w2, w3, x4
-# CHECK: smsubl x1, w2, w3, x4
-# CHECK: umaddl x1, w2, w3, x4
-# CHECK: umsubl x1, w2, w3, x4
-
-#==---------------------------------------------------------------------------==
-# Multiply-high instructions
-#==---------------------------------------------------------------------------==
-
-0x41 0x7c 0x43 0x9b
-0x41 0x7c 0xc3 0x9b
-
-# CHECK: smulh x1, x2, x3
-# CHECK: umulh x1, x2, x3
-
-#==---------------------------------------------------------------------------==
-# Move immediate instructions
-#==---------------------------------------------------------------------------==
-
-0x20 0x00 0x80 0x52
-0x20 0x00 0x80 0xd2
-0x20 0x00 0xa0 0x52
-0x20 0x00 0xa0 0xd2
-
-# CHECK: movz w0, #0x1
-# CHECK: movz x0, #0x1
-# CHECK: movz w0, #0x1, lsl #16
-# CHECK: movz x0, #0x1, lsl #16
-
-0x40 0x00 0x80 0x12
-0x40 0x00 0x80 0x92
-0x40 0x00 0xa0 0x12
-0x40 0x00 0xa0 0x92
-
-# CHECK: movn w0, #0x2
-# CHECK: movn x0, #0x2
-# CHECK: movn w0, #0x2, lsl #16
-# CHECK: movn x0, #0x2, lsl #16
-
-0x20 0x00 0x80 0x72
-0x20 0x00 0x80 0xf2
-0x20 0x00 0xa0 0x72
-0x20 0x00 0xa0 0xf2
-
-# CHECK: movk w0, #0x1
-# CHECK: movk x0, #0x1
-# CHECK: movk w0, #0x1, lsl #16
-# CHECK: movk x0, #0x1, lsl #16
-
-#==---------------------------------------------------------------------------==
-# Conditionally set flags instructions
-#==---------------------------------------------------------------------------==
-
- 0x1f 0x00 0x00 0x31
-# CHECK: cmn w0, #0
- 0x1f 0xfc 0x03 0xb1
-# CHECK: x0, #255
-
- 0x23 0x08 0x42 0x3a
-# CHECK: ccmn w1, #2, #3, eq
- 0x23 0x08 0x42 0xba
-# CHECK: ccmn x1, #2, #3, eq
- 0x23 0x08 0x42 0x7a
-# CHECK: ccmp w1, #2, #3, eq
- 0x23 0x08 0x42 0xfa
-# CHECK: ccmp x1, #2, #3, eq
-
- 0x23 0x00 0x42 0x3a
-# CHECK: ccmn w1, w2, #3, eq
- 0x23 0x00 0x42 0xba
-# CHECK: ccmn x1, x2, #3, eq
- 0x23 0x00 0x42 0x7a
-# CHECK: ccmp w1, w2, #3, eq
- 0x23 0x00 0x42 0xfa
-# CHECK: ccmp x1, x2, #3, eq
-
-#==---------------------------------------------------------------------------==
-# Conditional select instructions
-#==---------------------------------------------------------------------------==
-
- 0x41 0x00 0x83 0x1a
-# CHECK: csel w1, w2, w3, eq
- 0x41 0x00 0x83 0x9a
-# CHECK: csel x1, x2, x3, eq
- 0x41 0x04 0x83 0x1a
-# CHECK: csinc w1, w2, w3, eq
- 0x41 0x04 0x83 0x9a
-# CHECK: csinc x1, x2, x3, eq
- 0x41 0x00 0x83 0x5a
-# CHECK: csinv w1, w2, w3, eq
- 0x41 0x00 0x83 0xda
-# CHECK: csinv x1, x2, x3, eq
- 0x41 0x04 0x83 0x5a
-# CHECK: csneg w1, w2, w3, eq
- 0x41 0x04 0x83 0xda
-# CHECK: csneg x1, x2, x3, eq
Removed: llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/basic-a64-undefined.txt (removed)
@@ -1,31 +0,0 @@
-# These spawn another process so they're rather expensive. Not many.
-
-# LDR/STR: undefined if option field is 10x or 00x.
-# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s
-
-# Instructions notionally in the add/sub (extended register) sheet, but with
-# invalid shift amount or "opt" field.
-# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# MOVK with sf == 0 and hw<1> == 1 is unallocated.
-# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
-# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
-# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# EXT on vectors of i8 must have imm<3> = 0.
-# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# SCVTF on fixed point W-registers is undefined if scale<5> == 0.
-# Same with FCVTZS and FCVTZU.
-# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
Removed: llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt (removed)
@@ -1,29 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-#==---------------------------------------------------------------------------==
-# 5.4.4 Bitfield Operations
-#==---------------------------------------------------------------------------==
-
-0x41 0x3c 0x01 0x33
-0x41 0x3c 0x41 0xb3
-0x41 0x3c 0x01 0x13
-0x41 0x3c 0x41 0x93
-0x41 0x3c 0x01 0x53
-0x41 0x3c 0x41 0xd3
-
-# CHECK: bfxil w1, w2, #1, #15
-# CHECK: bfxil x1, x2, #1, #15
-# CHECK: sbfx w1, w2, #1, #15
-# CHECK: sbfx x1, x2, #1, #15
-# CHECK: ubfx w1, w2, #1, #15
-# CHECK: ubfx x1, x2, #1, #15
-
-#==---------------------------------------------------------------------------==
-# 5.4.5 Extract (immediate)
-#==---------------------------------------------------------------------------==
-
-0x41 0x3c 0x83 0x13
-0x62 0x04 0xc4 0x93
-
-# CHECK: extr w1, w2, w3, #15
-# CHECK: extr x2, x3, x4, #1
Removed: llvm/trunk/test/MC/Disassembler/ARM64/branch.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/branch.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/branch.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/branch.txt (removed)
@@ -1,75 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-#-----------------------------------------------------------------------------
-# Unconditional branch (register) instructions.
-#-----------------------------------------------------------------------------
-
- 0xc0 0x03 0x5f 0xd6
-# CHECK: ret
- 0x20 0x00 0x5f 0xd6
-# CHECK: ret x1
- 0xe0 0x03 0xbf 0xd6
-# CHECK: drps
- 0xe0 0x03 0x9f 0xd6
-# CHECK: eret
- 0xa0 0x00 0x1f 0xd6
-# CHECK: br x5
- 0x20 0x01 0x3f 0xd6
-# CHECK: blr x9
- 0x0B 0x00 0x18 0x37
-# CHECK: tbnz w11, #3, #0
-
-#-----------------------------------------------------------------------------
-# Exception generation instructions.
-#-----------------------------------------------------------------------------
-
- 0x20 0x00 0x20 0xd4
-# CHECK: brk #0x1
- 0x41 0x00 0xa0 0xd4
-# CHECK: dcps1 #0x2
- 0x62 0x00 0xa0 0xd4
-# CHECK: dcps2 #0x3
- 0x83 0x00 0xa0 0xd4
-# CHECK: dcps3 #0x4
- 0xa0 0x00 0x40 0xd4
-# CHECK: hlt #0x5
- 0xc2 0x00 0x00 0xd4
-# CHECK: hvc #0x6
- 0xe3 0x00 0x00 0xd4
-# CHECK: smc #0x7
- 0x01 0x01 0x00 0xd4
-# CHECK: svc #0x8
-
-#-----------------------------------------------------------------------------
-# PC-relative branches (both positive and negative displacement)
-#-----------------------------------------------------------------------------
-
- 0x07 0x00 0x00 0x14
-# CHECK: b #28
- 0x06 0x00 0x00 0x94
-# CHECK: bl #24
- 0xa1 0x00 0x00 0x54
-# CHECK: b.ne #20
- 0x80 0x00 0x08 0x36
-# CHECK: tbz w0, #1, #16
- 0xe1 0xff 0xf7 0x36
-# CHECK: tbz w1, #30, #-4
- 0x60 0x00 0x08 0x37
-# CHECK: tbnz w0, #1, #12
- 0x40 0x00 0x00 0xb4
-# CHECK: cbz x0, #8
- 0x20 0x00 0x00 0xb5
-# CHECK: cbnz x0, #4
- 0x1f 0x20 0x03 0xd5
-# CHECK: nop
- 0xff 0xff 0xff 0x17
-# CHECK: b #-4
- 0xc1 0xff 0xff 0x54
-# CHECK: b.ne #-8
- 0xa0 0xff 0x0f 0x36
-# CHECK: tbz w0, #1, #-12
- 0x80 0xff 0xff 0xb4
-# CHECK: cbz x0, #-16
- 0x1f 0x20 0x03 0xd5
-# CHECK: nop
-
Removed: llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/canonical-form.txt (removed)
@@ -1,21 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s
-
-0x00 0x08 0x00 0xc8
-
-# CHECK: stxr w0, x0, [x0]
-
-0x00 0x00 0x40 0x9b
-
-# CHECK: smulh x0, x0, x0
-
-0x08 0x20 0x21 0x1e
-
-# CHECK: fcmp s0, #0.0
-
-0x1f 0x00 0x00 0x11
-
-# CHECK: mov wsp, w0
-
-0x00 0x7c 0x00 0x13
-
-# CHECK: asr w0, w0, #0
Removed: llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt (removed)
@@ -1,18 +0,0 @@
-# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s
-
-# CHECK: crc32b w5, w7, w20
-# CHECK: crc32h w28, wzr, w30
-# CHECK: crc32w w0, w1, w2
-# CHECK: crc32x w7, w9, x20
-# CHECK: crc32cb w9, w5, w4
-# CHECK: crc32ch w13, w17, w25
-# CHECK: crc32cw wzr, w3, w5
-# CHECK: crc32cx w18, w16, xzr
-0xe5 0x40 0xd4 0x1a
-0xfc 0x47 0xde 0x1a
-0x20 0x48 0xc2 0x1a
-0x27 0x4d 0xd4 0x9a
-0xa9 0x50 0xc4 0x1a
-0x2d 0x56 0xd9 0x1a
-0x7f 0x58 0xc5 0x1a
-0x12 0x5e 0xdf 0x9a
Removed: llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt (removed)
@@ -1,47 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE
-
- 0x20 0x48 0x28 0x4e
- 0x20 0x58 0x28 0x4e
- 0x20 0x68 0x28 0x4e
- 0x20 0x78 0x28 0x4e
- 0x20 0x00 0x02 0x5e
- 0x20 0x10 0x02 0x5e
- 0x20 0x20 0x02 0x5e
- 0x20 0x30 0x02 0x5e
- 0x20 0x40 0x02 0x5e
- 0x20 0x50 0x02 0x5e
- 0x20 0x60 0x02 0x5e
- 0x20 0x08 0x28 0x5e
- 0x20 0x18 0x28 0x5e
- 0x20 0x28 0x28 0x5e
-
-# CHECK: aese v0.16b, v1.16b
-# CHECK: aesd v0.16b, v1.16b
-# CHECK: aesmc v0.16b, v1.16b
-# CHECK: aesimc v0.16b, v1.16b
-# CHECK: sha1c q0, s1, v2.4s
-# CHECK: sha1p q0, s1, v2.4s
-# CHECK: sha1m q0, s1, v2.4s
-# CHECK: sha1su0 v0.4s, v1.4s, v2
-# CHECK: sha256h q0, q1, v2.4s
-# CHECK: sha256h2 q0, q1, v2.4s
-# CHECK: sha256su1 v0.4s, v1.4s, v2.4s
-# CHECK: sha1h s0, s1
-# CHECK: sha1su1 v0.4s, v1.4s
-# CHECK: sha256su0 v0.4s, v1.4s
-
-# CHECK-APPLE: aese.16b v0, v1
-# CHECK-APPLE: aesd.16b v0, v1
-# CHECK-APPLE: aesmc.16b v0, v1
-# CHECK-APPLE: aesimc.16b v0, v1
-# CHECK-APPLE: sha1c.4s q0, s1, v2
-# CHECK-APPLE: sha1p.4s q0, s1, v2
-# CHECK-APPLE: sha1m.4s q0, s1, v2
-# CHECK-APPLE: sha1su0.4s v0, v1, v2
-# CHECK-APPLE: sha256h.4s q0, q1, v2
-# CHECK-APPLE: sha256h2.4s q0, q1, v2
-# CHECK-APPLE: sha256su1.4s v0, v1, v2
-# CHECK-APPLE: sha1h s0, s1
-# CHECK-APPLE: sha1su1.4s v0, v1
-# CHECK-APPLE: sha256su0.4s v0, v1
Removed: llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt (removed)
@@ -1,6 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin -disassemble < %s 2>&1 | FileCheck %s
-
-# rdar://15226511
-0x7b 0xbf 0x25 0x72
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: 0x7b 0xbf 0x25 0x72
Removed: llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg (removed)
@@ -1,5 +0,0 @@
-config.suffixes = ['.txt']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
Removed: llvm/trunk/test/MC/Disassembler/ARM64/logical.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/logical.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/logical.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/logical.txt (removed)
@@ -1,223 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-#==---------------------------------------------------------------------------==
-# 5.4.2 Logical (immediate)
-#==---------------------------------------------------------------------------==
-
-0x00 0x00 0x00 0x12
-0x00 0x00 0x40 0x92
-0x41 0x0c 0x00 0x12
-0x41 0x0c 0x40 0x92
-0xbf 0xec 0x7c 0x92
-0x00 0x00 0x00 0x72
-0x00 0x00 0x40 0xf2
-0x41 0x0c 0x00 0x72
-0x41 0x0c 0x40 0xf2
-0x5f 0x0c 0x40 0xf2
-
-# CHECK: and w0, w0, #0x1
-# CHECK: and x0, x0, #0x1
-# CHECK: and w1, w2, #0xf
-# CHECK: and x1, x2, #0xf
-# CHECK: and sp, x5, #0xfffffffffffffff0
-# CHECK: ands w0, w0, #0x1
-# CHECK: ands x0, x0, #0x1
-# CHECK: ands w1, w2, #0xf
-# CHECK: ands x1, x2, #0xf
-# CHECK: tst x2, #0xf
-
-0x41 0x00 0x12 0x52
-0x41 0x00 0x71 0xd2
-0x5f 0x00 0x71 0xd2
-
-# CHECK: eor w1, w2, #0x4000
-# CHECK: eor x1, x2, #0x8000
-# CHECK: eor sp, x2, #0x8000
-
-0x41 0x00 0x12 0x32
-0x41 0x00 0x71 0xb2
-0x5f 0x00 0x71 0xb2
-
-# CHECK: orr w1, w2, #0x4000
-# CHECK: orr x1, x2, #0x8000
-# CHECK: orr sp, x2, #0x8000
-
-#==---------------------------------------------------------------------------==
-# 5.5.3 Logical (shifted register)
-#==---------------------------------------------------------------------------==
-
-0x41 0x00 0x03 0x0a
-0x41 0x00 0x03 0x8a
-0x41 0x08 0x03 0x0a
-0x41 0x08 0x03 0x8a
-0x41 0x08 0x43 0x0a
-0x41 0x08 0x43 0x8a
-0x41 0x08 0x83 0x0a
-0x41 0x08 0x83 0x8a
-0x41 0x08 0xc3 0x0a
-0x41 0x08 0xc3 0x8a
-
-# CHECK: and w1, w2, w3
-# CHECK: and x1, x2, x3
-# CHECK: and w1, w2, w3, lsl #2
-# CHECK: and x1, x2, x3, lsl #2
-# CHECK: and w1, w2, w3, lsr #2
-# CHECK: and x1, x2, x3, lsr #2
-# CHECK: and w1, w2, w3, asr #2
-# CHECK: and x1, x2, x3, asr #2
-# CHECK: and w1, w2, w3, ror #2
-# CHECK: and x1, x2, x3, ror #2
-
-0x41 0x00 0x03 0x6a
-0x41 0x00 0x03 0xea
-0x41 0x08 0x03 0x6a
-0x41 0x08 0x03 0xea
-0x41 0x08 0x43 0x6a
-0x41 0x08 0x43 0xea
-0x41 0x08 0x83 0x6a
-0x41 0x08 0x83 0xea
-0x41 0x08 0xc3 0x6a
-0x41 0x08 0xc3 0xea
-
-# CHECK: ands w1, w2, w3
-# CHECK: ands x1, x2, x3
-# CHECK: ands w1, w2, w3, lsl #2
-# CHECK: ands x1, x2, x3, lsl #2
-# CHECK: ands w1, w2, w3, lsr #2
-# CHECK: ands x1, x2, x3, lsr #2
-# CHECK: ands w1, w2, w3, asr #2
-# CHECK: ands x1, x2, x3, asr #2
-# CHECK: ands w1, w2, w3, ror #2
-# CHECK: ands x1, x2, x3, ror #2
-
-0x41 0x00 0x23 0x0a
-0x41 0x00 0x23 0x8a
-0x41 0x0c 0x23 0x0a
-0x41 0x0c 0x23 0x8a
-0x41 0x0c 0x63 0x0a
-0x41 0x0c 0x63 0x8a
-0x41 0x0c 0xa3 0x0a
-0x41 0x0c 0xa3 0x8a
-0x41 0x0c 0xe3 0x0a
-0x41 0x0c 0xe3 0x8a
-
-# CHECK: bic w1, w2, w3
-# CHECK: bic x1, x2, x3
-# CHECK: bic w1, w2, w3, lsl #3
-# CHECK: bic x1, x2, x3, lsl #3
-# CHECK: bic w1, w2, w3, lsr #3
-# CHECK: bic x1, x2, x3, lsr #3
-# CHECK: bic w1, w2, w3, asr #3
-# CHECK: bic x1, x2, x3, asr #3
-# CHECK: bic w1, w2, w3, ror #3
-# CHECK: bic x1, x2, x3, ror #3
-
-0x41 0x00 0x23 0x6a
-0x41 0x00 0x23 0xea
-0x41 0x0c 0x23 0x6a
-0x41 0x0c 0x23 0xea
-0x41 0x0c 0x63 0x6a
-0x41 0x0c 0x63 0xea
-0x41 0x0c 0xa3 0x6a
-0x41 0x0c 0xa3 0xea
-0x41 0x0c 0xe3 0x6a
-0x41 0x0c 0xe3 0xea
-
-# CHECK: bics w1, w2, w3
-# CHECK: bics x1, x2, x3
-# CHECK: bics w1, w2, w3, lsl #3
-# CHECK: bics x1, x2, x3, lsl #3
-# CHECK: bics w1, w2, w3, lsr #3
-# CHECK: bics x1, x2, x3, lsr #3
-# CHECK: bics w1, w2, w3, asr #3
-# CHECK: bics x1, x2, x3, asr #3
-# CHECK: bics w1, w2, w3, ror #3
-# CHECK: bics x1, x2, x3, ror #3
-
-0x41 0x00 0x23 0x4a
-0x41 0x00 0x23 0xca
-0x41 0x10 0x23 0x4a
-0x41 0x10 0x23 0xca
-0x41 0x10 0x63 0x4a
-0x41 0x10 0x63 0xca
-0x41 0x10 0xa3 0x4a
-0x41 0x10 0xa3 0xca
-0x41 0x10 0xe3 0x4a
-0x41 0x10 0xe3 0xca
-
-# CHECK: eon w1, w2, w3
-# CHECK: eon x1, x2, x3
-# CHECK: eon w1, w2, w3, lsl #4
-# CHECK: eon x1, x2, x3, lsl #4
-# CHECK: eon w1, w2, w3, lsr #4
-# CHECK: eon x1, x2, x3, lsr #4
-# CHECK: eon w1, w2, w3, asr #4
-# CHECK: eon x1, x2, x3, asr #4
-# CHECK: eon w1, w2, w3, ror #4
-# CHECK: eon x1, x2, x3, ror #4
-
-0x41 0x00 0x03 0x4a
-0x41 0x00 0x03 0xca
-0x41 0x14 0x03 0x4a
-0x41 0x14 0x03 0xca
-0x41 0x14 0x43 0x4a
-0x41 0x14 0x43 0xca
-0x41 0x14 0x83 0x4a
-0x41 0x14 0x83 0xca
-0x41 0x14 0xc3 0x4a
-0x41 0x14 0xc3 0xca
-
-# CHECK: eor w1, w2, w3
-# CHECK: eor x1, x2, x3
-# CHECK: eor w1, w2, w3, lsl #5
-# CHECK: eor x1, x2, x3, lsl #5
-# CHECK: eor w1, w2, w3, lsr #5
-# CHECK: eor x1, x2, x3, lsr #5
-# CHECK: eor w1, w2, w3, asr #5
-# CHECK: eor x1, x2, x3, asr #5
-# CHECK: eor w1, w2, w3, ror #5
-# CHECK: eor x1, x2, x3, ror #5
-
-0x41 0x00 0x03 0x2a
-0x41 0x00 0x03 0xaa
-0x41 0x18 0x03 0x2a
-0x41 0x18 0x03 0xaa
-0x41 0x18 0x43 0x2a
-0x41 0x18 0x43 0xaa
-0x41 0x18 0x83 0x2a
-0x41 0x18 0x83 0xaa
-0x41 0x18 0xc3 0x2a
-0x41 0x18 0xc3 0xaa
-
-# CHECK: orr w1, w2, w3
-# CHECK: orr x1, x2, x3
-# CHECK: orr w1, w2, w3, lsl #6
-# CHECK: orr x1, x2, x3, lsl #6
-# CHECK: orr w1, w2, w3, lsr #6
-# CHECK: orr x1, x2, x3, lsr #6
-# CHECK: orr w1, w2, w3, asr #6
-# CHECK: orr x1, x2, x3, asr #6
-# CHECK: orr w1, w2, w3, ror #6
-# CHECK: orr x1, x2, x3, ror #6
-
-0x41 0x00 0x23 0x2a
-0x41 0x00 0x23 0xaa
-0x41 0x1c 0x23 0x2a
-0x41 0x1c 0x23 0xaa
-0x41 0x1c 0x63 0x2a
-0x41 0x1c 0x63 0xaa
-0x41 0x1c 0xa3 0x2a
-0x41 0x1c 0xa3 0xaa
-0x41 0x1c 0xe3 0x2a
-0x41 0x1c 0xe3 0xaa
-
-# CHECK: orn w1, w2, w3
-# CHECK: orn x1, x2, x3
-# CHECK: orn w1, w2, w3, lsl #7
-# CHECK: orn x1, x2, x3, lsl #7
-# CHECK: orn w1, w2, w3, lsr #7
-# CHECK: orn x1, x2, x3, lsr #7
-# CHECK: orn w1, w2, w3, asr #7
-# CHECK: orn x1, x2, x3, asr #7
-# CHECK: orn w1, w2, w3, ror #7
-# CHECK: orn x1, x2, x3, ror #7
Removed: llvm/trunk/test/MC/Disassembler/ARM64/memory.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/memory.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/memory.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/memory.txt (removed)
@@ -1,564 +0,0 @@
-# RUN: llvm-mc --disassemble -triple arm64-apple-darwin < %s | FileCheck %s
-
-#-----------------------------------------------------------------------------
-# Indexed loads
-#-----------------------------------------------------------------------------
-
- 0x85 0x14 0x40 0xb9
- 0x64 0x00 0x40 0xf9
- 0xe2 0x13 0x40 0xf9
- 0xe5 0x07 0x40 0x3d
- 0xe6 0x07 0x40 0x7d
- 0xe7 0x07 0x40 0xbd
- 0xe8 0x07 0x40 0xfd
- 0xe9 0x07 0xc0 0x3d
- 0x64 0x00 0x40 0x39
- 0x20 0x78 0xa0 0xb8
- 0x85 0x50 0x40 0x39
-
-# CHECK: ldr w5, [x4, #20]
-# CHECK: ldr x4, [x3]
-# CHECK: ldr x2, [sp, #32]
-# CHECK: ldr b5, [sp, #1]
-# CHECK: ldr h6, [sp, #2]
-# CHECK: ldr s7, [sp, #4]
-# CHECK: ldr d8, [sp, #8]
-# CHECK: ldr q9, [sp, #16]
-# CHECK: ldrb w4, [x3]
-# CHECK: ldrsw x0, [x1, x0, lsl #2]
-# CHECK: ldrb w5, [x4, #20]
-# CHECK: ldrsb w9, [x3]
-# CHECK: ldrsb x2, [sp, #128]
-# CHECK: ldrh w2, [sp, #32]
-# CHECK: ldrsh w3, [sp, #32]
-# CHECK: ldrsh x5, [x9, #24]
-# CHECK: ldrsw x9, [sp, #512]
-# CHECK: prfm pldl3strm, [sp, #32]
-
- 0x69 0x00 0xc0 0x39
- 0xe2 0x03 0x82 0x39
- 0xe2 0x43 0x40 0x79
- 0xe3 0x43 0xc0 0x79
- 0x25 0x31 0x80 0x79
- 0xe9 0x03 0x82 0xb9
- 0xe5 0x13 0x80 0xf9
- 0x40 0x00 0x80 0xf9
- 0x41 0x00 0x80 0xf9
- 0x42 0x00 0x80 0xf9
- 0x43 0x00 0x80 0xf9
- 0x44 0x00 0x80 0xf9
- 0x45 0x00 0x80 0xf9
- 0x50 0x00 0x80 0xf9
- 0x51 0x00 0x80 0xf9
- 0x52 0x00 0x80 0xf9
- 0x53 0x00 0x80 0xf9
- 0x54 0x00 0x80 0xf9
- 0x55 0x00 0x80 0xf9
-
-# CHECK: prfm pldl1keep, [x2]
-# CHECK: prfm pldl1strm, [x2]
-# CHECK: prfm pldl2keep, [x2]
-# CHECK: prfm pldl2strm, [x2]
-# CHECK: prfm pldl3keep, [x2]
-# CHECK: prfm pldl3strm, [x2]
-# CHECK: prfm pstl1keep, [x2]
-# CHECK: prfm pstl1strm, [x2]
-# CHECK: prfm pstl2keep, [x2]
-# CHECK: prfm pstl2strm, [x2]
-# CHECK: prfm pstl3keep, [x2]
-# CHECK: prfm pstl3strm, [x2]
-
-#-----------------------------------------------------------------------------
-# Indexed stores
-#-----------------------------------------------------------------------------
-
- 0x64 0x00 0x00 0xf9
- 0xe2 0x13 0x00 0xf9
- 0x85 0x14 0x00 0xb9
- 0xe5 0x07 0x00 0x3d
- 0xe6 0x07 0x00 0x7d
- 0xe7 0x07 0x00 0xbd
- 0xe8 0x07 0x00 0xfd
- 0xe9 0x07 0x80 0x3d
- 0x64 0x00 0x00 0x39
- 0x85 0x50 0x00 0x39
- 0xe2 0x43 0x00 0x79
- 0x00 0xe8 0x20 0x38
- 0x00 0x48 0x20 0x38
-
-# CHECK: str x4, [x3]
-# CHECK: str x2, [sp, #32]
-# CHECK: str w5, [x4, #20]
-# CHECK: str b5, [sp, #1]
-# CHECK: str h6, [sp, #2]
-# CHECK: str s7, [sp, #4]
-# CHECK: str d8, [sp, #8]
-# CHECK: str q9, [sp, #16]
-# CHECK: strb w4, [x3]
-# CHECK: strb w5, [x4, #20]
-# CHECK: strh w2, [sp, #32]
-# CHECK: strb w0, [x0, x0, sxtx]
-# CHECK: strb w0, [x0, w0, uxtw]
-
-#-----------------------------------------------------------------------------
-# Unscaled immediate loads and stores
-#-----------------------------------------------------------------------------
-
- 0x62 0x00 0x40 0xb8
- 0xe2 0x83 0x41 0xb8
- 0x62 0x00 0x40 0xf8
- 0xe2 0x83 0x41 0xf8
- 0xe5 0x13 0x40 0x3c
- 0xe6 0x23 0x40 0x7c
- 0xe7 0x43 0x40 0xbc
- 0xe8 0x83 0x40 0xfc
- 0xe9 0x03 0xc1 0x3c
- 0x69 0x00 0xc0 0x38
- 0xe2 0x03 0x88 0x38
- 0xe3 0x03 0xc2 0x78
- 0x25 0x81 0x81 0x78
- 0xe9 0x03 0x98 0xb8
-
-# CHECK: ldur w2, [x3]
-# CHECK: ldur w2, [sp, #24]
-# CHECK: ldur x2, [x3]
-# CHECK: ldur x2, [sp, #24]
-# CHECK: ldur b5, [sp, #1]
-# CHECK: ldur h6, [sp, #2]
-# CHECK: ldur s7, [sp, #4]
-# CHECK: ldur d8, [sp, #8]
-# CHECK: ldur q9, [sp, #16]
-# CHECK: ldursb w9, [x3]
-# CHECK: ldursb x2, [sp, #128]
-# CHECK: ldursh w3, [sp, #32]
-# CHECK: ldursh x5, [x9, #24]
-# CHECK: ldursw x9, [sp, #-128]
-
- 0x64 0x00 0x00 0xb8
- 0xe2 0x03 0x02 0xb8
- 0x64 0x00 0x00 0xf8
- 0xe2 0x03 0x02 0xf8
- 0x85 0x40 0x01 0xb8
- 0xe5 0x13 0x00 0x3c
- 0xe6 0x23 0x00 0x7c
- 0xe7 0x43 0x00 0xbc
- 0xe8 0x83 0x00 0xfc
- 0xe9 0x03 0x81 0x3c
- 0x64 0x00 0x00 0x38
- 0x85 0x40 0x01 0x38
- 0xe2 0x03 0x02 0x78
- 0xe5 0x03 0x82 0xf8
-
-# CHECK: stur w4, [x3]
-# CHECK: stur w2, [sp, #32]
-# CHECK: stur x4, [x3]
-# CHECK: stur x2, [sp, #32]
-# CHECK: stur w5, [x4, #20]
-# CHECK: stur b5, [sp, #1]
-# CHECK: stur h6, [sp, #2]
-# CHECK: stur s7, [sp, #4]
-# CHECK: stur d8, [sp, #8]
-# CHECK: stur q9, [sp, #16]
-# CHECK: sturb w4, [x3]
-# CHECK: sturb w5, [x4, #20]
-# CHECK: sturh w2, [sp, #32]
-# CHECK: prfum pldl3strm, [sp, #32]
-
-#-----------------------------------------------------------------------------
-# Unprivileged loads and stores
-#-----------------------------------------------------------------------------
-
- 0x83 0x08 0x41 0xb8
- 0x83 0x08 0x41 0xf8
- 0x83 0x08 0x41 0x38
- 0x69 0x08 0xc0 0x38
- 0xe2 0x0b 0x88 0x38
- 0x83 0x08 0x41 0x78
- 0xe3 0x0b 0xc2 0x78
- 0x25 0x89 0x81 0x78
- 0xe9 0x0b 0x98 0xb8
-
-# CHECK: ldtr w3, [x4, #16]
-# CHECK: ldtr x3, [x4, #16]
-# CHECK: ldtrb w3, [x4, #16]
-# CHECK: ldtrsb w9, [x3]
-# CHECK: ldtrsb x2, [sp, #128]
-# CHECK: ldtrh w3, [x4, #16]
-# CHECK: ldtrsh w3, [sp, #32]
-# CHECK: ldtrsh x5, [x9, #24]
-# CHECK: ldtrsw x9, [sp, #-128]
-
- 0x85 0x48 0x01 0xb8
- 0x64 0x08 0x00 0xf8
- 0xe2 0x0b 0x02 0xf8
- 0x64 0x08 0x00 0x38
- 0x85 0x48 0x01 0x38
- 0xe2 0x0b 0x02 0x78
-
-# CHECK: sttr w5, [x4, #20]
-# CHECK: sttr x4, [x3]
-# CHECK: sttr x2, [sp, #32]
-# CHECK: sttrb w4, [x3]
-# CHECK: sttrb w5, [x4, #20]
-# CHECK: sttrh w2, [sp, #32]
-
-#-----------------------------------------------------------------------------
-# Pre-indexed loads and stores
-#-----------------------------------------------------------------------------
-
- 0xfd 0x8c 0x40 0xf8
- 0xfe 0x8c 0x40 0xf8
- 0x05 0x1c 0x40 0x3c
- 0x06 0x2c 0x40 0x7c
- 0x07 0x4c 0x40 0xbc
- 0x08 0x8c 0x40 0xfc
- 0x09 0x0c 0xc1 0x3c
-
-# CHECK: ldr x29, [x7, #8]!
-# CHECK: ldr x30, [x7, #8]!
-# CHECK: ldr b5, [x0, #1]!
-# CHECK: ldr h6, [x0, #2]!
-# CHECK: ldr s7, [x0, #4]!
-# CHECK: ldr d8, [x0, #8]!
-# CHECK: ldr q9, [x0, #16]!
-
- 0xfe 0x8c 0x1f 0xf8
- 0xfd 0x8c 0x1f 0xf8
- 0x05 0xfc 0x1f 0x3c
- 0x06 0xec 0x1f 0x7c
- 0x07 0xcc 0x1f 0xbc
- 0x08 0x8c 0x1f 0xfc
- 0x09 0x0c 0x9f 0x3c
-
-# CHECK: str x30, [x7, #-8]!
-# CHECK: str x29, [x7, #-8]!
-# CHECK: str b5, [x0, #-1]!
-# CHECK: str h6, [x0, #-2]!
-# CHECK: str s7, [x0, #-4]!
-# CHECK: str d8, [x0, #-8]!
-# CHECK: str q9, [x0, #-16]!
-
-#-----------------------------------------------------------------------------
-# post-indexed loads and stores
-#-----------------------------------------------------------------------------
-
- 0xfe 0x84 0x1f 0xf8
- 0xfd 0x84 0x1f 0xf8
- 0x05 0xf4 0x1f 0x3c
- 0x06 0xe4 0x1f 0x7c
- 0x07 0xc4 0x1f 0xbc
- 0x08 0x84 0x1f 0xfc
- 0x09 0x04 0x9f 0x3c
-
-# CHECK: str x30, [x7], #-8
-# CHECK: str x29, [x7], #-8
-# CHECK: str b5, [x0], #-1
-# CHECK: str h6, [x0], #-2
-# CHECK: str s7, [x0], #-4
-# CHECK: str d8, [x0], #-8
-# CHECK: str q9, [x0], #-16
-
- 0xfd 0x84 0x40 0xf8
- 0xfe 0x84 0x40 0xf8
- 0x05 0x14 0x40 0x3c
- 0x06 0x24 0x40 0x7c
- 0x07 0x44 0x40 0xbc
- 0x08 0x84 0x40 0xfc
- 0x09 0x04 0xc1 0x3c
-
-# CHECK: ldr x29, [x7], #8
-# CHECK: ldr x30, [x7], #8
-# CHECK: ldr b5, [x0], #1
-# CHECK: ldr h6, [x0], #2
-# CHECK: ldr s7, [x0], #4
-# CHECK: ldr d8, [x0], #8
-# CHECK: ldr q9, [x0], #16
-
-#-----------------------------------------------------------------------------
-# Load/Store pair (indexed offset)
-#-----------------------------------------------------------------------------
-
- 0xe3 0x09 0x42 0x29
- 0xe4 0x27 0x7f 0xa9
- 0xc2 0x0d 0x42 0x69
- 0xe2 0x0f 0x7e 0x69
- 0x4a 0x04 0x48 0x2d
- 0x4a 0x04 0x40 0x6d
-
-# CHECK: ldp w3, w2, [x15, #16]
-# CHECK: ldp x4, x9, [sp, #-16]
-# CHECK: ldpsw x2, x3, [x14, #16]
-# CHECK: ldpsw x2, x3, [sp, #-16]
-# CHECK: ldp s10, s1, [x2, #64]
-# CHECK: ldp d10, d1, [x2]
-
- 0xe3 0x09 0x02 0x29
- 0xe4 0x27 0x3f 0xa9
- 0x4a 0x04 0x08 0x2d
- 0x4a 0x04 0x00 0x6d
-
-# CHECK: stp w3, w2, [x15, #16]
-# CHECK: stp x4, x9, [sp, #-16]
-# CHECK: stp s10, s1, [x2, #64]
-# CHECK: stp d10, d1, [x2]
-
-#-----------------------------------------------------------------------------
-# Load/Store pair (pre-indexed)
-#-----------------------------------------------------------------------------
-
- 0xe3 0x09 0xc2 0x29
- 0xe4 0x27 0xff 0xa9
- 0xc2 0x0d 0xc2 0x69
- 0xe2 0x0f 0xfe 0x69
- 0x4a 0x04 0xc8 0x2d
- 0x4a 0x04 0xc1 0x6d
-
-# CHECK: ldp w3, w2, [x15, #16]!
-# CHECK: ldp x4, x9, [sp, #-16]!
-# CHECK: ldpsw x2, x3, [x14, #16]!
-# CHECK: ldpsw x2, x3, [sp, #-16]!
-# CHECK: ldp s10, s1, [x2, #64]!
-# CHECK: ldp d10, d1, [x2, #16]!
-
- 0xe3 0x09 0x82 0x29
- 0xe4 0x27 0xbf 0xa9
- 0x4a 0x04 0x88 0x2d
- 0x4a 0x04 0x81 0x6d
-
-# CHECK: stp w3, w2, [x15, #16]!
-# CHECK: stp x4, x9, [sp, #-16]!
-# CHECK: stp s10, s1, [x2, #64]!
-# CHECK: stp d10, d1, [x2, #16]!
-
-#-----------------------------------------------------------------------------
-# Load/Store pair (post-indexed)
-#-----------------------------------------------------------------------------
-
- 0xe3 0x09 0xc2 0x28
- 0xe4 0x27 0xff 0xa8
- 0xc2 0x0d 0xc2 0x68
- 0xe2 0x0f 0xfe 0x68
- 0x4a 0x04 0xc8 0x2c
- 0x4a 0x04 0xc1 0x6c
-
-# CHECK: ldp w3, w2, [x15], #16
-# CHECK: ldp x4, x9, [sp], #-16
-# CHECK: ldpsw x2, x3, [x14], #16
-# CHECK: ldpsw x2, x3, [sp], #-16
-# CHECK: ldp s10, s1, [x2], #64
-# CHECK: ldp d10, d1, [x2], #16
-
- 0xe3 0x09 0x82 0x28
- 0xe4 0x27 0xbf 0xa8
- 0x4a 0x04 0x88 0x2c
- 0x4a 0x04 0x81 0x6c
-
-# CHECK: stp w3, w2, [x15], #16
-# CHECK: stp x4, x9, [sp], #-16
-# CHECK: stp s10, s1, [x2], #64
-# CHECK: stp d10, d1, [x2], #16
-
-#-----------------------------------------------------------------------------
-# Load/Store pair (no-allocate)
-#-----------------------------------------------------------------------------
-
- 0xe3 0x09 0x42 0x28
- 0xe4 0x27 0x7f 0xa8
- 0x4a 0x04 0x48 0x2c
- 0x4a 0x04 0x40 0x6c
-
-# CHECK: ldnp w3, w2, [x15, #16]
-# CHECK: ldnp x4, x9, [sp, #-16]
-# CHECK: ldnp s10, s1, [x2, #64]
-# CHECK: ldnp d10, d1, [x2]
-
- 0xe3 0x09 0x02 0x28
- 0xe4 0x27 0x3f 0xa8
- 0x4a 0x04 0x08 0x2c
- 0x4a 0x04 0x00 0x6c
-
-# CHECK: stnp w3, w2, [x15, #16]
-# CHECK: stnp x4, x9, [sp, #-16]
-# CHECK: stnp s10, s1, [x2, #64]
-# CHECK: stnp d10, d1, [x2]
-
-#-----------------------------------------------------------------------------
-# Load/Store register offset
-#-----------------------------------------------------------------------------
-
- 0x00 0x68 0x60 0xb8
- 0x00 0x78 0x60 0xb8
- 0x00 0x68 0x60 0xf8
- 0x00 0x78 0x60 0xf8
- 0x00 0xe8 0x60 0xf8
-
-# CHECK: ldr w0, [x0, x0]
-# CHECK: ldr w0, [x0, x0, lsl #2]
-# CHECK: ldr x0, [x0, x0]
-# CHECK: ldr x0, [x0, x0, lsl #3]
-# CHECK: ldr x0, [x0, x0, sxtx]
-
- 0x21 0x68 0x62 0x3c
- 0x21 0x78 0x62 0x3c
- 0x21 0x68 0x62 0x7c
- 0x21 0x78 0x62 0x7c
- 0x21 0x68 0x62 0xbc
- 0x21 0x78 0x62 0xbc
- 0x21 0x68 0x62 0xfc
- 0x21 0x78 0x62 0xfc
- 0x21 0x68 0xe2 0x3c
- 0x21 0x78 0xe2 0x3c
-
-# CHECK: ldr b1, [x1, x2]
-# CHECK: ldr b1, [x1, x2, lsl #0]
-# CHECK: ldr h1, [x1, x2]
-# CHECK: ldr h1, [x1, x2, lsl #1]
-# CHECK: ldr s1, [x1, x2]
-# CHECK: ldr s1, [x1, x2, lsl #2]
-# CHECK: ldr d1, [x1, x2]
-# CHECK: ldr d1, [x1, x2, lsl #3]
-# CHECK: ldr q1, [x1, x2]
-# CHECK: ldr q1, [x1, x2, lsl #4]
-
- 0x00 0x48 0x20 0x7c
- 0xe1 0x6b 0x23 0xfc
- 0xe1 0x5b 0x23 0xfc
- 0xe1 0x6b 0xa3 0x3c
- 0xe1 0x5b 0xa3 0x3c
-
-# CHECK: str h0, [x0, w0, uxtw]
-# CHECK: str d1, [sp, x3]
-# CHECK: str d1, [sp, w3, uxtw #3]
-# CHECK: str q1, [sp, x3]
-# CHECK: str q1, [sp, w3, uxtw #4]
-
-#-----------------------------------------------------------------------------
-# Load/Store exclusive
-#-----------------------------------------------------------------------------
-
- 0x26 0x7c 0x5f 0x08
- 0x26 0x7c 0x5f 0x48
- 0x27 0x0d 0x7f 0x88
- 0x27 0x0d 0x7f 0xc8
-
-# CHECK: ldxrb w6, [x1]
-# CHECK: ldxrh w6, [x1]
-# CHECK: ldxp w7, w3, [x9]
-# CHECK: ldxp x7, x3, [x9]
-
- 0x64 0x7c 0x01 0xc8
- 0x64 0x7c 0x01 0x88
- 0x64 0x7c 0x01 0x08
- 0x64 0x7c 0x01 0x48
- 0x22 0x18 0x21 0xc8
- 0x22 0x18 0x21 0x88
-
-# CHECK: stxr w1, x4, [x3]
-# CHECK: stxr w1, w4, [x3]
-# CHECK: stxrb w1, w4, [x3]
-# CHECK: stxrh w1, w4, [x3]
-# CHECK: stxp w1, x2, x6, [x1]
-# CHECK: stxp w1, w2, w6, [x1]
-
-#-----------------------------------------------------------------------------
-# Load-acquire/Store-release non-exclusive
-#-----------------------------------------------------------------------------
-
- 0xe4 0xff 0xdf 0x88
- 0xe4 0xff 0xdf 0xc8
- 0xe4 0xff 0xdf 0x08
- 0xe4 0xff 0xdf 0x48
-
-# CHECK: ldar w4, [sp]
-# CHECK: ldar x4, [sp]
-# CHECK: ldarb w4, [sp]
-# CHECK: ldarh w4, [sp]
-
- 0xc3 0xfc 0x9f 0x88
- 0xc3 0xfc 0x9f 0xc8
- 0xc3 0xfc 0x9f 0x08
- 0xc3 0xfc 0x9f 0x48
-
-# CHECK: stlr w3, [x6]
-# CHECK: stlr x3, [x6]
-# CHECK: stlrb w3, [x6]
-# CHECK: stlrh w3, [x6]
-
-#-----------------------------------------------------------------------------
-# Load-acquire/Store-release exclusive
-#-----------------------------------------------------------------------------
-
- 0x82 0xfc 0x5f 0x88
- 0x82 0xfc 0x5f 0xc8
- 0x82 0xfc 0x5f 0x08
- 0x82 0xfc 0x5f 0x48
- 0x22 0x98 0x7f 0x88
- 0x22 0x98 0x7f 0xc8
-
-# CHECK: ldaxr w2, [x4]
-# CHECK: ldaxr x2, [x4]
-# CHECK: ldaxrb w2, [x4]
-# CHECK: ldaxrh w2, [x4]
-# CHECK: ldaxp w2, w6, [x1]
-# CHECK: ldaxp x2, x6, [x1]
-
- 0x27 0xfc 0x08 0xc8
- 0x27 0xfc 0x08 0x88
- 0x27 0xfc 0x08 0x08
- 0x27 0xfc 0x08 0x48
- 0x22 0x98 0x21 0xc8
- 0x22 0x98 0x21 0x88
-
-# CHECK: stlxr w8, x7, [x1]
-# CHECK: stlxr w8, w7, [x1]
-# CHECK: stlxrb w8, w7, [x1]
-# CHECK: stlxrh w8, w7, [x1]
-# CHECK: stlxp w1, x2, x6, [x1]
-# CHECK: stlxp w1, w2, w6, [x1]
-
-#-----------------------------------------------------------------------------
-# Load/Store with explicit LSL values
-#-----------------------------------------------------------------------------
- 0x20 0x78 0xa0 0xb8
- 0x20 0x78 0x60 0xf8
- 0x20 0x78 0x20 0xf8
- 0x20 0x78 0x60 0xb8
- 0x20 0x78 0x20 0xb8
- 0x20 0x78 0xe0 0x3c
- 0x20 0x78 0xa0 0x3c
- 0x20 0x78 0x60 0xfc
- 0x20 0x78 0x20 0xfc
- 0x20 0x78 0x60 0xbc
- 0x20 0x78 0x20 0xbc
- 0x20 0x78 0x60 0x7c
- 0x20 0x78 0x60 0x3c
- 0x20 0x78 0x60 0x38
- 0x20 0x78 0x20 0x38
- 0x20 0x78 0xe0 0x38
- 0x20 0x78 0x60 0x78
- 0x20 0x78 0x20 0x78
- 0x20 0x78 0xe0 0x78
- 0x20 0x78 0xa0 0x38
- 0x20 0x78 0xa0 0x78
-
-# CHECK: ldrsw x0, [x1, x0, lsl #2]
-# CHECK: ldr x0, [x1, x0, lsl #3]
-# CHECK: str x0, [x1, x0, lsl #3]
-# CHECK: ldr w0, [x1, x0, lsl #2]
-# CHECK: str w0, [x1, x0, lsl #2]
-# CHECK: ldr q0, [x1, x0, lsl #4]
-# CHECK: str q0, [x1, x0, lsl #4]
-# CHECK: ldr d0, [x1, x0, lsl #3]
-# CHECK: str d0, [x1, x0, lsl #3]
-# CHECK: ldr s0, [x1, x0, lsl #2]
-# CHECK: str s0, [x1, x0, lsl #2]
-# CHECK: ldr h0, [x1, x0, lsl #1]
-# CHECK: ldr b0, [x1, x0, lsl #0]
-# CHECK: ldrb w0, [x1, x0, lsl #0]
-# CHECK: strb w0, [x1, x0, lsl #0]
-# CHECK: ldrsb w0, [x1, x0, lsl #0]
-# CHECK: ldrh w0, [x1, x0, lsl #1]
-# CHECK: strh w0, [x1, x0, lsl #1]
-# CHECK: ldrsh w0, [x1, x0, lsl #1]
-# CHECK: ldrsb x0, [x1, x0, lsl #0]
-# CHECK: ldrsh x0, [x1, x0, lsl #1]
Removed: llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/non-apple-fmov.txt (removed)
@@ -1,7 +0,0 @@
-# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s
-
-0x00 0x00 0xae 0x9e
-0x00 0x00 0xaf 0x9e
-
-# CHECK: fmov x0, v0.d[1]
-# CHECK: fmov v0.d[1], x0
Removed: llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt (removed)
@@ -1,255 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s
-
-#-----------------------------------------------------------------------------
-# Floating-point arithmetic
-#-----------------------------------------------------------------------------
-
-0x41 0xc0 0x20 0x1e
-0x41 0xc0 0x60 0x1e
-
-# CHECK: fabs s1, s2
-# CHECK: fabs d1, d2
-
-0x41 0x28 0x23 0x1e
-0x41 0x28 0x63 0x1e
-
-# CHECK: fadd s1, s2, s3
-# CHECK: fadd d1, d2, d3
-
-0x41 0x18 0x23 0x1e
-0x41 0x18 0x63 0x1e
-
-# CHECK: fdiv s1, s2, s3
-# CHECK: fdiv d1, d2, d3
-
-0x41 0x10 0x03 0x1f
-0x41 0x10 0x43 0x1f
-
-# CHECK: fmadd s1, s2, s3, s4
-# CHECK: fmadd d1, d2, d3, d4
-
-0x41 0x48 0x23 0x1e
-0x41 0x48 0x63 0x1e
-0x41 0x68 0x23 0x1e
-0x41 0x68 0x63 0x1e
-
-# CHECK: fmax s1, s2, s3
-# CHECK: fmax d1, d2, d3
-# CHECK: fmaxnm s1, s2, s3
-# CHECK: fmaxnm d1, d2, d3
-
-0x41 0x58 0x23 0x1e
-0x41 0x58 0x63 0x1e
-0x41 0x78 0x23 0x1e
-0x41 0x78 0x63 0x1e
-
-# CHECK: fmin s1, s2, s3
-# CHECK: fmin d1, d2, d3
-# CHECK: fminnm s1, s2, s3
-# CHECK: fminnm d1, d2, d3
-
-0x41 0x90 0x03 0x1f
-0x41 0x90 0x43 0x1f
-
-# CHECK: fmsub s1, s2, s3, s4
-# CHECK: fmsub d1, d2, d3, d4
-
-0x41 0x08 0x23 0x1e
-0x41 0x08 0x63 0x1e
-
-# CHECK: fmul s1, s2, s3
-# CHECK: fmul d1, d2, d3
-
-0x41 0x40 0x21 0x1e
-0x41 0x40 0x61 0x1e
-
-# CHECK: fneg s1, s2
-# CHECK: fneg d1, d2
-
-0x41 0x10 0x23 0x1f
-0x41 0x10 0x63 0x1f
-
-# CHECK: fnmadd s1, s2, s3, s4
-# CHECK: fnmadd d1, d2, d3, d4
-
-0x41 0x90 0x23 0x1f
-0x41 0x90 0x63 0x1f
-
-# CHECK: fnmsub s1, s2, s3, s4
-# CHECK: fnmsub d1, d2, d3, d4
-
-0x41 0x88 0x23 0x1e
-0x41 0x88 0x63 0x1e
-
-# CHECK: fnmul s1, s2, s3
-# CHECK: fnmul d1, d2, d3
-
-0x41 0xc0 0x21 0x1e
-0x41 0xc0 0x61 0x1e
-
-# CHECK: fsqrt s1, s2
-# CHECK: fsqrt d1, d2
-
-0x41 0x38 0x23 0x1e
-0x41 0x38 0x63 0x1e
-
-# CHECK: fsub s1, s2, s3
-# CHECK: fsub d1, d2, d3
-
-#-----------------------------------------------------------------------------
-# Floating-point comparison
-#-----------------------------------------------------------------------------
-
-0x20 0x04 0x22 0x1e
-0x20 0x04 0x62 0x1e
-0x30 0x04 0x22 0x1e
-0x30 0x04 0x62 0x1e
-
-# CHECK: fccmp s1, s2, #0, eq
-# CHECK: fccmp d1, d2, #0, eq
-# CHECK: fccmpe s1, s2, #0, eq
-# CHECK: fccmpe d1, d2, #0, eq
-
-0x20 0x20 0x22 0x1e
-0x20 0x20 0x62 0x1e
-0x28 0x20 0x20 0x1e
-0x28 0x20 0x60 0x1e
-0x30 0x20 0x22 0x1e
-0x30 0x20 0x62 0x1e
-0x38 0x20 0x20 0x1e
-0x38 0x20 0x60 0x1e
-
-# CHECK: fcmp s1, s2
-# CHECK: fcmp d1, d2
-# CHECK: fcmp s1, #0.0
-# CHECK: fcmp d1, #0.0
-# CHECK: fcmpe s1, s2
-# CHECK: fcmpe d1, d2
-# CHECK: fcmpe s1, #0.0
-# CHECK: fcmpe d1, #0.0
-
-#-----------------------------------------------------------------------------
-# Floating-point conditional select
-#-----------------------------------------------------------------------------
-
-0x41 0x0c 0x23 0x1e
-0x41 0x0c 0x63 0x1e
-
-# CHECK: fcsel s1, s2, s3, eq
-# CHECK: fcsel d1, d2, d3, eq
-
-#-----------------------------------------------------------------------------
-# Floating-point convert
-#-----------------------------------------------------------------------------
-
-0x41 0xc0 0x63 0x1e
-0x41 0x40 0x62 0x1e
-0x41 0xc0 0xe2 0x1e
-0x41 0x40 0xe2 0x1e
-0x41 0xc0 0x22 0x1e
-0x41 0xc0 0x23 0x1e
-
-# CHECK: fcvt h1, d2
-# CHECK: fcvt s1, d2
-# CHECK: fcvt d1, h2
-# CHECK: fcvt s1, h2
-# CHECK: fcvt d1, s2
-# CHECK: fcvt h1, s2
-
-0x41 0x00 0x44 0x1e
-0x41 0x04 0x44 0x1e
-0x41 0x00 0x44 0x9e
-0x41 0x04 0x44 0x9e
-0x41 0x00 0x04 0x1e
-0x41 0x04 0x04 0x1e
-0x41 0x00 0x04 0x9e
-0x41 0x04 0x04 0x9e
-
-#-----------------------------------------------------------------------------
-# Floating-point move
-#-----------------------------------------------------------------------------
-
-0x41 0x00 0x27 0x1e
-0x41 0x00 0x26 0x1e
-0x41 0x00 0x67 0x9e
-0x41 0x00 0x66 0x9e
-
-# CHECK: fmov s1, w2
-# CHECK: fmov w1, s2
-# CHECK: fmov d1, x2
-# CHECK: fmov x1, d2
-
-0x01 0x10 0x28 0x1e
-0x01 0x10 0x68 0x1e
-0x01 0xf0 0x7b 0x1e
-0x01 0xf0 0x6b 0x1e
-
-# CHECK: fmov s1, #0.12500000
-# CHECK: fmov d1, #0.12500000
-# CHECK: fmov d1, #-0.48437500
-# CHECK: fmov d1, #0.48437500
-
-0x41 0x40 0x20 0x1e
-0x41 0x40 0x60 0x1e
-
-# CHECK: fmov s1, s2
-# CHECK: fmov d1, d2
-
-#-----------------------------------------------------------------------------
-# Floating-point round to integral
-#-----------------------------------------------------------------------------
-
-0x41 0x40 0x26 0x1e
-0x41 0x40 0x66 0x1e
-
-# CHECK: frinta s1, s2
-# CHECK: frinta d1, d2
-
-0x41 0xc0 0x27 0x1e
-0x41 0xc0 0x67 0x1e
-
-# CHECK: frinti s1, s2
-# CHECK: frinti d1, d2
-
-0x41 0x40 0x25 0x1e
-0x41 0x40 0x65 0x1e
-
-# CHECK: frintm s1, s2
-# CHECK: frintm d1, d2
-
-0x41 0x40 0x24 0x1e
-0x41 0x40 0x64 0x1e
-
-# CHECK: frintn s1, s2
-# CHECK: frintn d1, d2
-
-0x41 0xc0 0x24 0x1e
-0x41 0xc0 0x64 0x1e
-
-# CHECK: frintp s1, s2
-# CHECK: frintp d1, d2
-
-0x41 0x40 0x27 0x1e
-0x41 0x40 0x67 0x1e
-
-# CHECK: frintx s1, s2
-# CHECK: frintx d1, d2
-
-0x41 0xc0 0x25 0x1e
-0x41 0xc0 0x65 0x1e
-
-# CHECK: frintz s1, s2
-# CHECK: frintz d1, d2
-
- 0x00 0x3c 0xe0 0x7e
- 0x00 0x8c 0xe0 0x5e
-
-# CHECK: cmhs d0, d0, d0
-# CHECK: cmtst d0, d0, d0
-
-0x00 0x00 0xaf 0x9e
-0x00 0x00 0xae 0x9e
-
-# CHECK: fmov.d v0[1], x0
-# CHECK: fmov.d x0, v0[1]
-
Removed: llvm/trunk/test/MC/Disassembler/ARM64/system.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/system.txt?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/system.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM64/system.txt (removed)
@@ -1,62 +0,0 @@
-# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
-
-
-#-----------------------------------------------------------------------------
-# Hint encodings
-#-----------------------------------------------------------------------------
-
- 0x1f 0x20 0x03 0xd5
-# CHECK: nop
- 0x9f 0x20 0x03 0xd5
-# CHECK: sev
- 0xbf 0x20 0x03 0xd5
-# CHECK: sevl
- 0x5f 0x20 0x03 0xd5
-# CHECK: wfe
- 0x7f 0x20 0x03 0xd5
-# CHECK: wfi
- 0x3f 0x20 0x03 0xd5
-# CHECK: yield
-
-#-----------------------------------------------------------------------------
-# Single-immediate operand instructions
-#-----------------------------------------------------------------------------
-
- 0x5f 0x3a 0x03 0xd5
-# CHECK: clrex #10
- 0xdf 0x3f 0x03 0xd5
-# CHECK: isb{{$}}
- 0xdf 0x31 0x03 0xd5
-# CHECK: isb #1
- 0xbf 0x33 0x03 0xd5
-# CHECK: dmb osh
- 0x9f 0x37 0x03 0xd5
-# CHECK: dsb nsh
- 0x3f 0x76 0x08 0xd5
-# CHECK: dc ivac
-
-#-----------------------------------------------------------------------------
-# Generic system instructions
-#-----------------------------------------------------------------------------
- 0xff 0x05 0x0a 0xd5
- 0xe7 0x6a 0x0f 0xd5
- 0xf4 0x3f 0x2e 0xd5
- 0xbf 0x40 0x00 0xd5
- 0x00 0xb0 0x18 0xd5
- 0x00 0xb0 0x38 0xd5
-
-# CHECK: sys #2, c0, c5, #7
-# CHECK: sys #7, c6, c10, #7, x7
-# CHECK: sysl x20, #6, c3, c15, #7
-# CHECK: msr SPSEL, #0
-# CHECK: msr S3_0_C11_C0_0, x0
-# CHECK: mrs x0, S3_0_C11_C0_0
-
- 0x40 0xc0 0x1e 0xd5
- 0x40 0xc0 0x1c 0xd5
- 0x40 0xc0 0x18 0xd5
-
-# CHECK: msr RMR_EL3, x0
-# CHECK: msr RMR_EL2, x0
-# CHECK: msr RMR_EL1, x0
-
Copied: llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s (from r209576, llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s?p2=llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s&p1=llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-reloc.s (from r209576, llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-reloc.s?p2=llvm/trunk/test/MC/MachO/AArch64/darwin-ARM64-reloc.s&p1=llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/MC/MachO/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/AArch64/lit.local.cfg?p2=llvm/trunk/test/MC/MachO/AArch64/lit.local.cfg&p1=llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/MachO/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Removed: llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s (original)
+++ llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s (removed)
@@ -1,21 +0,0 @@
-; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o - < %s | macho-dump -dump-section-data | FileCheck %s
-; rdar://13028719
-
- .globl context_save0
- .align 6
-Lcontext_save0:
-context_save0:
- .fill 2, 8, 5
-Lcontext_save0_end:
-Lcontext_save0_size: .quad (Lcontext_save0_end - Lcontext_save0)
-
- .align 6
-Lcontext_save1:
- .fill 2, 8, 0
-Lcontext_save1_end:
-Lcontext_save1_size: .quad (Lcontext_save1_end - Lcontext_save1)
-
-Llockup_release:
- .quad 0
-
-; CHECK: ('_section_data', '05000000 00000000 05000000 00000000 10000000 00000000 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000')
Removed: llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s (original)
+++ llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s (removed)
@@ -1,157 +0,0 @@
-; RUN: llvm-mc -n -triple arm64-apple-darwin10 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s
-
- .text
-_fred:
- bl _func
- bl _func + 20
-
- adrp x3, _data at page
- ldr w2, [x3, _data at pageoff]
-
- add x3, x3, _data at pageoff + 4
-
- adrp x3, _data at page+1
- ldr w2, [x3, _data at pageoff + 4]
-
- adrp x3, _data_ext at gotpage
- ldr w2, [x3, _data_ext at gotpageoff]
-
- .data
-_data:
- .quad _foo
- .quad _foo + 4
- .quad _foo - _bar
- .quad _foo - _bar + 4
-
- .long _foo - _bar
-
- .quad _foo at got
- .long _foo at got - .
-
-
-; CHECK: ('cputype', 16777228)
-; CHECK: ('cpusubtype', 0)
-; CHECK: ('filetype', 1)
-; CHECK: ('num_load_commands', 3)
-; CHECK: ('load_commands_size', 336)
-; CHECK: ('flag', 0)
-; CHECK: ('reserved', 0)
-; CHECK: ('load_commands', [
-; CHECK: # Load Command 0
-; CHECK: (('command', 25)
-; CHECK: ('size', 232)
-; CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-; CHECK: ('vm_addr', 0)
-; CHECK: ('vm_size', 84)
-; CHECK: ('file_offset', 368)
-; CHECK: ('file_size', 84)
-; CHECK: ('maxprot', 7)
-; CHECK: ('initprot', 7)
-; CHECK: ('num_sections', 2)
-; CHECK: ('flags', 0)
-; CHECK: ('sections', [
-; CHECK: # Section 0
-; CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-; CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-; CHECK: ('address', 0)
-; CHECK: ('size', 36)
-; CHECK: ('offset', 368)
-; CHECK: ('alignment', 0)
-; CHECK: ('reloc_offset', 452)
-; CHECK: ('num_reloc', 13)
-; CHECK: ('flags', 0x80000400)
-; CHECK: ('reserved1', 0)
-; CHECK: ('reserved2', 0)
-; CHECK: ('reserved3', 0)
-; CHECK: ),
-; CHECK: ('_relocations', [
-; CHECK: # Relocation 0
-; CHECK: (('word-0', 0x20),
-; CHECK: ('word-1', 0x6c000005)),
-; CHECK: # Relocation 1
-; CHECK: (('word-0', 0x1c),
-; CHECK: ('word-1', 0x5d000005)),
-; CHECK: # Relocation 2
-; CHECK: (('word-0', 0x18),
-; CHECK: ('word-1', 0xa4000004)),
-; CHECK: # Relocation 3
-; CHECK: (('word-0', 0x18),
-; CHECK: ('word-1', 0x4c000002)),
-; CHECK: # Relocation 4
-; CHECK: (('word-0', 0x14),
-; CHECK: ('word-1', 0xa4000001)),
-; CHECK: # Relocation 5
-; CHECK: (('word-0', 0x14),
-; CHECK: ('word-1', 0x3d000002)),
-; CHECK: # Relocation 6
-; CHECK: (('word-0', 0x10),
-; CHECK: ('word-1', 0xa4000004)),
-; CHECK: # Relocation 7
-; CHECK: (('word-0', 0x10),
-; CHECK: ('word-1', 0x4c000002)),
-; CHECK: # Relocation 8
-; CHECK: (('word-0', 0xc),
-; CHECK: ('word-1', 0x4c000002)),
-; CHECK: # Relocation 9
-; CHECK: (('word-0', 0x8),
-; CHECK: ('word-1', 0x3d000002)),
-; CHECK: # Relocation 10
-; CHECK: (('word-0', 0x4),
-; CHECK: ('word-1', 0xa4000014)),
-; CHECK: # Relocation 11
-; CHECK: (('word-0', 0x4),
-; CHECK: ('word-1', 0x2d000007)),
-; CHECK: # Relocation 12
-; CHECK: (('word-0', 0x0),
-; CHECK: ('word-1', 0x2d000007)),
-; CHECK: ])
-; CHECK: ('_section_data', '00000094 00000094 03000090 620040b9 63000091 03000090 620040b9 03000090 620040b9')
-; CHECK: # Section 1
-; CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-; CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
-; CHECK: ('address', 36)
-; CHECK: ('size', 48)
-; CHECK: ('offset', 404)
-; CHECK: ('alignment', 0)
-; CHECK: ('reloc_offset', 556)
-; CHECK: ('num_reloc', 10)
-; CHECK: ('flags', 0x0)
-; CHECK: ('reserved1', 0)
-; CHECK: ('reserved2', 0)
-; CHECK: ('reserved3', 0)
-; CHECK: ),
-; CHECK: ('_relocations', [
-; CHECK: # Relocation 0
-; CHECK: (('word-0', 0x2c),
-; CHECK: ('word-1', 0x7d000006)),
-; CHECK: # Relocation 1
-; CHECK: (('word-0', 0x24),
-; CHECK: ('word-1', 0x7e000006)),
-; CHECK: # Relocation 2
-; CHECK: (('word-0', 0x20),
-; CHECK: ('word-1', 0x1c000004)),
-; CHECK: # Relocation 3
-; CHECK: (('word-0', 0x20),
-; CHECK: ('word-1', 0xc000006)),
-; CHECK: # Relocation 4
-; CHECK: (('word-0', 0x18),
-; CHECK: ('word-1', 0x1e000004)),
-; CHECK: # Relocation 5
-; CHECK: (('word-0', 0x18),
-; CHECK: ('word-1', 0xe000006)),
-; CHECK: # Relocation 6
-; CHECK: (('word-0', 0x10),
-; CHECK: ('word-1', 0x1e000004)),
-; CHECK: # Relocation 7
-; CHECK: (('word-0', 0x10),
-; CHECK: ('word-1', 0xe000006)),
-; CHECK: # Relocation 8
-; CHECK: (('word-0', 0x8),
-; CHECK: ('word-1', 0xe000006)),
-; CHECK: # Relocation 9
-; CHECK: (('word-0', 0x0),
-; CHECK: ('word-1', 0xe000006)),
-; CHECK: ])
-; CHECK: ('_section_data', '00000000 00000000 04000000 00000000 00000000 00000000 04000000 00000000 00000000 00000000 00000000 d4ffffff')
-; CHECK: ])
-; CHECK: ),
Removed: llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg (removed)
@@ -1,4 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
Copied: llvm/trunk/test/Transforms/ConstantHoisting/AArch64/const-addr.ll (from r209576, llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/AArch64/const-addr.ll?p2=llvm/trunk/test/Transforms/ConstantHoisting/AArch64/const-addr.ll&p1=llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll (from r209576, llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll?p2=llvm/trunk/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll&p1=llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg?p2=llvm/trunk/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg&p1=llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/ConstantHoisting/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,3 +1,3 @@
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Removed: llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll (original)
+++ llvm/trunk/test/Transforms/ConstantHoisting/ARM64/const-addr.ll (removed)
@@ -1,23 +0,0 @@
-; RUN: opt -mtriple=arm64-darwin-unknown -S -consthoist < %s | FileCheck %s
-
-%T = type { i32, i32, i32, i32 }
-
-define i32 @test1() nounwind {
-; CHECK-LABEL: test1
-; CHECK: %const = bitcast i64 68141056 to i64
-; CHECK: %1 = inttoptr i64 %const to %T*
-; CHECK: %o1 = getelementptr %T* %1, i32 0, i32 1
-; CHECK: %o2 = getelementptr %T* %1, i32 0, i32 2
-; CHECK: %o3 = getelementptr %T* %1, i32 0, i32 3
- %at = inttoptr i64 68141056 to %T*
- %o1 = getelementptr %T* %at, i32 0, i32 1
- %t1 = load i32* %o1
- %o2 = getelementptr %T* %at, i32 0, i32 2
- %t2 = load i32* %o2
- %a1 = add i32 %t1, %t2
- %o3 = getelementptr %T* %at, i32 0, i32 3
- %t3 = load i32* %o3
- %a2 = add i32 %a1, %t3
- ret i32 %a2
-}
-
Removed: llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll (original)
+++ llvm/trunk/test/Transforms/ConstantHoisting/ARM64/large-immediate.ll (removed)
@@ -1,27 +0,0 @@
-; RUN: opt -mtriple=arm64-darwin-unknown -S -consthoist < %s | FileCheck %s
-
-define i128 @test1(i128 %a) nounwind {
-; CHECK-LABEL: test1
-; CHECK: %const = bitcast i128 12297829382473034410122878 to i128
- %1 = add i128 %a, 12297829382473034410122878
- %2 = add i128 %1, 12297829382473034410122878
- ret i128 %2
-}
-
-; Check that we don't hoist large, but cheap constants
-define i512 @test2(i512 %a) nounwind {
-; CHECK-LABEL: test2
-; CHECK-NOT: %const = bitcast i512 7 to i512
- %1 = and i512 %a, 7
- %2 = or i512 %1, 7
- ret i512 %2
-}
-
-; Check that we don't hoist the shift value of a shift instruction.
-define i512 @test3(i512 %a) nounwind {
-; CHECK-LABEL: test3
-; CHECK-NOT: %const = bitcast i512 504 to i512
- %1 = shl i512 %a, 504
- %2 = ashr i512 %1, 504
- ret i512 %2
-}
Removed: llvm/trunk/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/ConstantHoisting/ARM64/lit.local.cfg (removed)
@@ -1,3 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
Copied: llvm/trunk/test/Transforms/GlobalMerge/AArch64/arm64.ll (from r209576, llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/AArch64/arm64.ll?p2=llvm/trunk/test/Transforms/GlobalMerge/AArch64/arm64.ll&p1=llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/GlobalMerge/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/AArch64/lit.local.cfg?p2=llvm/trunk/test/Transforms/GlobalMerge/AArch64/lit.local.cfg&p1=llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/GlobalMerge/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,4 +1,4 @@
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Removed: llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll (original)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll (removed)
@@ -1,88 +0,0 @@
-; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O0 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O0 -o - -global-merge=true | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O1 -o - | FileCheck -check-prefix=MERGE %s
-; RUN: llc %s -O1 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
-; RUN: llc %s -O1 -o - -global-merge=true | FileCheck -check-prefix=MERGE %s
-
-; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
-; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
-; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
-; MERGE: .zerofill __DATA,__bss,__MergedGlobals,60,4
-; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
-; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
-; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
-
-; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
-; NO-MERGE: .zerofill __DATA,__bss,_bar,20,2
-; NO-MERGE: .zerofill __DATA,__bss,_baz,20,2
-; NO-MERGE: .zerofill __DATA,__bss,_foo,20,2
-; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-target triple = "arm64-apple-ios7.0.0"
-
- at bar = internal global [5 x i32] zeroinitializer, align 4
- at baz = internal global [5 x i32] zeroinitializer, align 4
- at foo = internal global [5 x i32] zeroinitializer, align 4
-
-; Function Attrs: nounwind ssp
-define internal void @initialize() #0 {
- %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
- %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
- %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
- %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
- %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
- %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
- %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
- %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
- %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
- %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
- store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
- ret void
-}
-
-declare i32 @calc(...)
-
-; Function Attrs: nounwind ssp
-define internal void @calculate() #0 {
- %1 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
- %2 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
- %3 = mul nsw i32 %2, %1
- store i32 %3, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0), align 4
- %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
- %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
- %6 = mul nsw i32 %5, %4
- store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 1), align 4
- %7 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
- %8 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
- %9 = mul nsw i32 %8, %7
- store i32 %9, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 2), align 4
- %10 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
- %11 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
- %12 = mul nsw i32 %11, %10
- store i32 %12, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 3), align 4
- %13 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
- %14 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
- %15 = mul nsw i32 %14, %13
- store i32 %15, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 4), align 4
- ret void
-}
-
-; Function Attrs: nounwind readnone ssp
-define internal i32* @returnFoo() #1 {
- ret i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0)
-}
-
-attributes #0 = { nounwind ssp }
-attributes #1 = { nounwind readnone ssp }
-attributes #2 = { nounwind }
Removed: llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg (removed)
@@ -1,4 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
Modified: llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll?rev=209577&r1=209576&r2=209577&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll Sat May 24 07:50:23 2014
@@ -68,7 +68,7 @@ declare <4 x i32> @llvm.arm.neon.vmullu.
define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {
entry:
- %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
+ %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
ret <4 x i32> %a
; CHECK: entry:
; CHECK-NEXT: ret <4 x i32> zeroinitializer
@@ -76,7 +76,7 @@ entry:
define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {
entry:
- %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
ret <4 x i32> %a
; CHECK: entry:
; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
@@ -85,7 +85,7 @@ entry:
define <4 x i32> @constantMulARM64() nounwind readnone ssp {
entry:
- %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+ %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
ret <4 x i32> %a
; CHECK: entry:
; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
@@ -93,7 +93,7 @@ entry:
define <4 x i32> @constantMulSARM64() nounwind readnone ssp {
entry:
- %b = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
ret <4 x i32> %b
; CHECK: entry:
; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -101,7 +101,7 @@ entry:
define <4 x i32> @constantMulUARM64() nounwind readnone ssp {
entry:
- %b = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
ret <4 x i32> %b
; CHECK: entry:
; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
@@ -109,17 +109,17 @@ entry:
define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {
entry:
- %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
+ %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
%b = add <4 x i32> zeroinitializer, %a
ret <4 x i32> %b
; CHECK: entry:
-; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
+; CHECK-NEXT: %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
; CHECK-NEXT: ret <4 x i32> %a
}
define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {
entry:
- %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+ %a = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
%b = add <4 x i32> %x, %a
ret <4 x i32> %b
; CHECK: entry:
@@ -127,8 +127,8 @@ entry:
; CHECK-NEXT: ret <4 x i32> %b
}
-declare <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
-declare <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
; CHECK: attributes #0 = { nounwind readnone ssp }
; CHECK: attributes #1 = { nounwind readnone }
Copied: llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg?p2=llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg&p1=llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,5 +1,5 @@
config.suffixes = ['.ll']
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Copied: llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll (from r209576, llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll?p2=llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll&p1=llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll (from r209576, llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll?p2=llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll&p1=llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll (from r209576, llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll?p2=llvm/trunk/test/Transforms/LoopStrengthReduce/AArch64/req-regs.ll&p1=llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg (removed)
@@ -1,5 +0,0 @@
-config.suffixes = ['.ll']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
Removed: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll (removed)
@@ -1,33 +0,0 @@
-; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
-; rdar://10232252
-; Prevent LSR of doing poor choice that cannot be folded in addressing mode
-
-; Remove the -pre-RA-sched=list-hybrid option after fixing:
-; <rdar://problem/12702735> [ARM64][coalescer] need better register
-; coalescing for simple unit tests.
-
-; CHECK: testCase
-; CHECK: %while.body{{$}}
-; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8
-; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8
-; CHECK: %while.end
-define i32 @testCase() nounwind ssp {
-entry:
- br label %while.body
-
-while.body: ; preds = %while.body, %entry
- %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
- %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
- %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
- %incdec.ptr = getelementptr inbounds i64* %pSrc.04, i64 1
- %tmp = load volatile i64* %pSrc.04, align 8
- %incdec.ptr1 = getelementptr inbounds i64* %pDst.05, i64 1
- store volatile i64 %tmp, i64* %pDst.05, align 8
- %sub = add i64 %len.06, -8
- %cmp = icmp sgt i64 %sub, -1
- br i1 %cmp, label %while.body, label %while.end
-
-while.end: ; preds = %while.body
- tail call void inttoptr (i64 6442450944 to void ()*)() nounwind
- ret i32 0
-}
Removed: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll (removed)
@@ -1,101 +0,0 @@
-; RUN: llc < %s -O3 -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid | FileCheck %s
-; <rdar://problem/11635990> [arm64] [lsr] Inefficient EA/loop-exit calc in bzero_phys
-;
-; LSR on loop %while.cond should reassociate non-address mode
-; expressions at use %cmp16 to avoid sinking computation into %while.body18.
-;
-; Remove the -pre-RA-sched=list-hybrid option after fixing:
-; <rdar://problem/12702735> [ARM64][coalescer] need better register
-; coalescing for simple unit tests.
-
-; CHECK: @memset
-; CHECK: %while.body18{{$}}
-; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #8
-; First set the IVREG variable, then use it
-; CHECK-NEXT: sub [[IVREG:x[0-9]+]],
-; CHECK: [[IVREG]], #8
-; CHECK-NEXT: cmp [[IVREG]], #7
-; CHECK-NEXT: b.hi
-define i8* @memset(i8* %dest, i32 %val, i64 %len) nounwind ssp noimplicitfloat {
-entry:
- %cmp = icmp eq i64 %len, 0
- br i1 %cmp, label %done, label %while.cond.preheader
-
-while.cond.preheader: ; preds = %entry
- %conv = trunc i32 %val to i8
- br label %while.cond
-
-while.cond: ; preds = %while.body, %while.cond.preheader
- %ptr.0 = phi i8* [ %incdec.ptr, %while.body ], [ %dest, %while.cond.preheader ]
- %len.addr.0 = phi i64 [ %dec, %while.body ], [ %len, %while.cond.preheader ]
- %cond = icmp eq i64 %len.addr.0, 0
- br i1 %cond, label %done, label %land.rhs
-
-land.rhs: ; preds = %while.cond
- %0 = ptrtoint i8* %ptr.0 to i64
- %and = and i64 %0, 7
- %cmp5 = icmp eq i64 %and, 0
- br i1 %cmp5, label %if.end9, label %while.body
-
-while.body: ; preds = %land.rhs
- %incdec.ptr = getelementptr inbounds i8* %ptr.0, i64 1
- store i8 %conv, i8* %ptr.0, align 1, !tbaa !0
- %dec = add i64 %len.addr.0, -1
- br label %while.cond
-
-if.end9: ; preds = %land.rhs
- %conv.mask = and i32 %val, 255
- %1 = zext i32 %conv.mask to i64
- %2 = shl nuw nsw i64 %1, 8
- %ins18 = or i64 %2, %1
- %3 = shl nuw nsw i64 %1, 16
- %ins15 = or i64 %ins18, %3
- %4 = shl nuw nsw i64 %1, 24
- %5 = shl nuw nsw i64 %1, 32
- %mask8 = or i64 %ins15, %4
- %6 = shl nuw nsw i64 %1, 40
- %mask5 = or i64 %mask8, %5
- %7 = shl nuw nsw i64 %1, 48
- %8 = shl nuw i64 %1, 56
- %mask2.masked = or i64 %mask5, %6
- %mask = or i64 %mask2.masked, %7
- %ins = or i64 %mask, %8
- %9 = bitcast i8* %ptr.0 to i64*
- %cmp1636 = icmp ugt i64 %len.addr.0, 7
- br i1 %cmp1636, label %while.body18, label %while.body29.lr.ph
-
-while.body18: ; preds = %if.end9, %while.body18
- %wideptr.038 = phi i64* [ %incdec.ptr19, %while.body18 ], [ %9, %if.end9 ]
- %len.addr.137 = phi i64 [ %sub, %while.body18 ], [ %len.addr.0, %if.end9 ]
- %incdec.ptr19 = getelementptr inbounds i64* %wideptr.038, i64 1
- store i64 %ins, i64* %wideptr.038, align 8, !tbaa !2
- %sub = add i64 %len.addr.137, -8
- %cmp16 = icmp ugt i64 %sub, 7
- br i1 %cmp16, label %while.body18, label %while.end20
-
-while.end20: ; preds = %while.body18
- %cmp21 = icmp eq i64 %sub, 0
- br i1 %cmp21, label %done, label %while.body29.lr.ph
-
-while.body29.lr.ph: ; preds = %while.end20, %if.end9
- %len.addr.1.lcssa49 = phi i64 [ %sub, %while.end20 ], [ %len.addr.0, %if.end9 ]
- %wideptr.0.lcssa48 = phi i64* [ %incdec.ptr19, %while.end20 ], [ %9, %if.end9 ]
- %10 = bitcast i64* %wideptr.0.lcssa48 to i8*
- br label %while.body29
-
-while.body29: ; preds = %while.body29, %while.body29.lr.ph
- %len.addr.235 = phi i64 [ %len.addr.1.lcssa49, %while.body29.lr.ph ], [ %dec26, %while.body29 ]
- %ptr.134 = phi i8* [ %10, %while.body29.lr.ph ], [ %incdec.ptr31, %while.body29 ]
- %dec26 = add i64 %len.addr.235, -1
- %incdec.ptr31 = getelementptr inbounds i8* %ptr.134, i64 1
- store i8 %conv, i8* %ptr.134, align 1, !tbaa !0
- %cmp27 = icmp eq i64 %dec26, 0
- br i1 %cmp27, label %done, label %while.body29
-
-done: ; preds = %while.cond, %while.body29, %while.end20, %entry
- ret i8* %dest
-}
-
-!0 = metadata !{metadata !"omnipotent char", metadata !1}
-!1 = metadata !{metadata !"Simple C/C++ TBAA"}
-!2 = metadata !{metadata !"long long", metadata !0}
Removed: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll (original)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/req-regs.ll (removed)
@@ -1,70 +0,0 @@
-; RUN: llc -mcpu=cyclone -debug-only=loop-reduce < %s 2>&1 | FileCheck %s
-; REQUIRES: asserts
-
-; LSR used to fail here due to a bug in the ReqRegs test.
-; CHECK: The chosen solution requires
-; CHECK-NOT: No Satisfactory Solution
-
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios"
-
-define void @do_integer_add(i64 %iterations, i8* nocapture readonly %cookie) {
-entry:
- %N = bitcast i8* %cookie to i32*
- %0 = load i32* %N, align 4
- %add = add nsw i32 %0, 57
- %cmp56 = icmp eq i64 %iterations, 0
- br i1 %cmp56, label %while.end, label %for.cond.preheader.preheader
-
-for.cond.preheader.preheader: ; preds = %entry
- br label %for.cond.preheader
-
-while.cond.loopexit: ; preds = %for.body
- %add21.lcssa = phi i32 [ %add21, %for.body ]
- %dec58 = add i64 %dec58.in, -1
- %cmp = icmp eq i64 %dec58, 0
- br i1 %cmp, label %while.end.loopexit, label %for.cond.preheader
-
-for.cond.preheader: ; preds = %for.cond.preheader.preheader, %while.cond.loopexit
- %dec58.in = phi i64 [ %dec58, %while.cond.loopexit ], [ %iterations, %for.cond.preheader.preheader ]
- %a.057 = phi i32 [ %add21.lcssa, %while.cond.loopexit ], [ %add, %for.cond.preheader.preheader ]
- br label %for.body
-
-for.body: ; preds = %for.body, %for.cond.preheader
- %a.154 = phi i32 [ %a.057, %for.cond.preheader ], [ %add21, %for.body ]
- %i.053 = phi i32 [ 1, %for.cond.preheader ], [ %inc, %for.body ]
- %inc = add nsw i32 %i.053, 1
- %add2 = shl i32 %a.154, 1
- %add3 = add nsw i32 %add2, %i.053
- %add4 = shl i32 %add3, 1
- %add5 = add nsw i32 %add4, %i.053
- %add6 = shl i32 %add5, 1
- %add7 = add nsw i32 %add6, %i.053
- %add8 = shl i32 %add7, 1
- %add9 = add nsw i32 %add8, %i.053
- %add10 = shl i32 %add9, 1
- %add11 = add nsw i32 %add10, %i.053
- %add12 = shl i32 %add11, 1
- %add13 = add nsw i32 %add12, %i.053
- %add14 = shl i32 %add13, 1
- %add15 = add nsw i32 %add14, %i.053
- %add16 = shl i32 %add15, 1
- %add17 = add nsw i32 %add16, %i.053
- %add18 = shl i32 %add17, 1
- %add19 = add nsw i32 %add18, %i.053
- %add20 = shl i32 %add19, 1
- %add21 = add nsw i32 %add20, %i.053
- %exitcond = icmp eq i32 %inc, 1001
- br i1 %exitcond, label %while.cond.loopexit, label %for.body
-
-while.end.loopexit: ; preds = %while.cond.loopexit
- %add21.lcssa.lcssa = phi i32 [ %add21.lcssa, %while.cond.loopexit ]
- br label %while.end
-
-while.end: ; preds = %while.end.loopexit, %entry
- %a.0.lcssa = phi i32 [ %add, %entry ], [ %add21.lcssa.lcssa, %while.end.loopexit ]
- tail call void @use_int(i32 %a.0.lcssa)
- ret void
-}
-
-declare void @use_int(i32)
Copied: llvm/trunk/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll (from r209576, llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll?p2=llvm/trunk/test/Transforms/LoopVectorize/AArch64/arm64-unroll.ll&p1=llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/Transforms/LoopVectorize/AArch64/gather-cost.ll (from r209576, llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/gather-cost.ll?p2=llvm/trunk/test/Transforms/LoopVectorize/AArch64/gather-cost.ll&p1=llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/ARM64/arm64-unroll.ll (removed)
@@ -1,42 +0,0 @@
-; RUN: opt < %s -loop-vectorize -mtriple=arm64-none-linux-gnu -mattr=+neon -S | FileCheck %s
-target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
-
-; Function Attrs: nounwind
-define i32* @array_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32* %c, i32 %size) {
-;CHECK-LABEL: array_add
-;CHECK: load <4 x i32>
-;CHECK: load <4 x i32>
-;CHECK: load <4 x i32>
-;CHECK: load <4 x i32>
-;CHECK: add nsw <4 x i32>
-;CHECK: add nsw <4 x i32>
-;CHECK: store <4 x i32>
-;CHECK: store <4 x i32>
-;CHECK: ret
-entry:
- %cmp10 = icmp sgt i32 %size, 0
- br i1 %cmp10, label %for.body.preheader, label %for.end
-
-for.body.preheader: ; preds = %entry
- br label %for.body
-
-for.body: ; preds = %for.body.preheader, %for.body
- %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %for.body.preheader ]
- %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv
- %0 = load i32* %arrayidx, align 4
- %arrayidx2 = getelementptr inbounds i32* %b, i64 %indvars.iv
- %1 = load i32* %arrayidx2, align 4
- %add = add nsw i32 %1, %0
- %arrayidx4 = getelementptr inbounds i32* %c, i64 %indvars.iv
- store i32 %add, i32* %arrayidx4, align 4
- %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, %size
- br i1 %exitcond, label %for.end.loopexit, label %for.body
-
-for.end.loopexit: ; preds = %for.body
- br label %for.end
-
-for.end: ; preds = %for.end.loopexit, %entry
- ret i32* %c
-}
Removed: llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll (removed)
@@ -1,85 +0,0 @@
-; RUN: opt -loop-vectorize -mtriple=arm64-apple-ios -S -mcpu=cyclone < %s | FileCheck %s
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
-
- at kernel = global [512 x float] zeroinitializer, align 16
- at kernel2 = global [512 x float] zeroinitializer, align 16
- at kernel3 = global [512 x float] zeroinitializer, align 16
- at kernel4 = global [512 x float] zeroinitializer, align 16
- at src_data = global [1536 x float] zeroinitializer, align 16
- at r_ = global i8 0, align 1
- at g_ = global i8 0, align 1
- at b_ = global i8 0, align 1
-
-; We don't want to vectorize most loops containing gathers because they are
-; expensive.
-; Make sure we don't vectorize it.
-; CHECK-NOT: x float>
-
-define void @_Z4testmm(i64 %size, i64 %offset) {
-entry:
- %cmp53 = icmp eq i64 %size, 0
- br i1 %cmp53, label %for.end, label %for.body.lr.ph
-
-for.body.lr.ph:
- br label %for.body
-
-for.body:
- %r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ]
- %g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ]
- %v.055 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
- %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
- %add = add i64 %v.055, %offset
- %mul = mul i64 %add, 3
- %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul
- %0 = load float* %arrayidx, align 4
- %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055
- %1 = load float* %arrayidx2, align 4
- %mul3 = fmul fast float %0, %1
- %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055
- %2 = load float* %arrayidx4, align 4
- %mul5 = fmul fast float %mul3, %2
- %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055
- %3 = load float* %arrayidx6, align 4
- %mul7 = fmul fast float %mul5, %3
- %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055
- %4 = load float* %arrayidx8, align 4
- %mul9 = fmul fast float %mul7, %4
- %add10 = fadd fast float %r.057, %mul9
- %arrayidx.sum = add i64 %mul, 1
- %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
- %5 = load float* %arrayidx11, align 4
- %mul13 = fmul fast float %1, %5
- %mul15 = fmul fast float %2, %mul13
- %mul17 = fmul fast float %3, %mul15
- %mul19 = fmul fast float %4, %mul17
- %add20 = fadd fast float %g.056, %mul19
- %arrayidx.sum52 = add i64 %mul, 2
- %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
- %6 = load float* %arrayidx21, align 4
- %mul23 = fmul fast float %1, %6
- %mul25 = fmul fast float %2, %mul23
- %mul27 = fmul fast float %3, %mul25
- %mul29 = fmul fast float %4, %mul27
- %add30 = fadd fast float %b.054, %mul29
- %inc = add i64 %v.055, 1
- %exitcond = icmp ne i64 %inc, %size
- br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
-
-for.cond.for.end_crit_edge:
- %add30.lcssa = phi float [ %add30, %for.body ]
- %add20.lcssa = phi float [ %add20, %for.body ]
- %add10.lcssa = phi float [ %add10, %for.body ]
- %phitmp = fptoui float %add10.lcssa to i8
- %phitmp60 = fptoui float %add20.lcssa to i8
- %phitmp61 = fptoui float %add30.lcssa to i8
- br label %for.end
-
-for.end:
- %r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
- %g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ]
- %b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ]
- store i8 %r.0.lcssa, i8* @r_, align 1
- store i8 %g.0.lcssa, i8* @g_, align 1
- store i8 %b.0.lcssa, i8* @b_, align 1
- ret void
-}
Removed: llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg (removed)
@@ -1,6 +0,0 @@
-config.suffixes = ['.ll']
-
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
-
Copied: llvm/trunk/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg (from r209576, llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg?p2=llvm/trunk/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg&p1=llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/CostModel/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/SLPVectorizer/AArch64/lit.local.cfg Sat May 24 07:50:23 2014
@@ -1,3 +1,3 @@
targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
+if not 'AArch64' in targets:
config.unsupported = True
Copied: llvm/trunk/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll (from r209576, llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll?p2=llvm/trunk/test/Transforms/SLPVectorizer/AArch64/mismatched-intrinsics.ll&p1=llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll&r1=209576&r2=209577&rev=209577&view=diff
==============================================================================
(empty)
Removed: llvm/trunk/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg (original)
+++ llvm/trunk/test/Transforms/SLPVectorizer/ARM64/lit.local.cfg (removed)
@@ -1,3 +0,0 @@
-targets = set(config.root.targets_to_build.split())
-if not 'ARM64' in targets:
- config.unsupported = True
Removed: llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll?rev=209576&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll (original)
+++ llvm/trunk/test/Transforms/SLPVectorizer/ARM64/mismatched-intrinsics.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: opt -S -slp-vectorizer %s | FileCheck %s
-target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-target triple = "arm64-apple-ios5.0.0"
-
-define i64 @mismatched_intrinsics(<4 x i32> %in1, <2 x i32> %in2) nounwind {
-; CHECK-LABEL: @mismatched_intrinsics
-; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v4i32
-; CHECK: call i64 @llvm.arm64.neon.saddlv.i64.v2i32
-
- %vaddlvq_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1) #2
- %vaddlv_s32.i = tail call i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in2) #2
- %tst = icmp sgt i64 %vaddlvq_s32.i, %vaddlv_s32.i
- %equal = sext i1 %tst to i64
- ret i64 %equal
-}
-
-declare i64 @llvm.arm64.neon.saddlv.i64.v4i32(<4 x i32> %in1)
-declare i64 @llvm.arm64.neon.saddlv.i64.v2i32(<2 x i32> %in1)
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