[llvm] r209538 - Fix broken FileCheck prefixes

[Rafael Espíndola]

Some of these are now broken :-(

    LLVM :: CodeGen/ARM64/csel.ll
    LLVM :: CodeGen/ARM64/vmul.ll


On 23 May 2014 15:06, Nico Rieck <nico.rieck at gmail.com> wrote:
> Author: nrieck
> Date: Fri May 23 14:06:24 2014
> New Revision: 209538
>
> URL: http://llvm.org/viewvc/llvm-project?rev=209538&view=rev
> Log:
> Fix broken FileCheck prefixes
>
> Modified:
>     llvm/trunk/test/CodeGen/ARM64/cse.ll
>     llvm/trunk/test/CodeGen/ARM64/csel.ll
>     llvm/trunk/test/CodeGen/ARM64/vmul.ll
>     llvm/trunk/test/CodeGen/MSP430/fp.ll
>     llvm/trunk/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
>
> Modified: llvm/trunk/test/CodeGen/ARM64/cse.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/cse.ll?rev=209538&r1=209537&r2=209538&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM64/cse.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM64/cse.ll Fri May 23 14:06:24 2014
> @@ -13,7 +13,7 @@ entry:
>  ; CHECK: b.ge
>  ; CHECK: sub
>  ; CHECK: sub
> -; CHECK_NOT: sub
> +; CHECK-NOT: sub
>  ; CHECK: ret
>   %0 = load i32* %offset, align 4
>   %cmp = icmp slt i32 %0, %size
>
> Modified: llvm/trunk/test/CodeGen/ARM64/csel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/csel.ll?rev=209538&r1=209537&r2=209538&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM64/csel.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM64/csel.ll Fri May 23 14:06:24 2014
> @@ -79,9 +79,9 @@ define i32 @foo7(i32 %a, i32 %b) nounwin
>  entry:
>  ; CHECK-LABEL: foo7:
>  ; CHECK: sub
> -; CHECK-next: adds
> -; CHECK-next: csneg
> -; CHECK-next: b
> +; CHECK-NEXT: adds
> +; CHECK-NEXT: csneg
> +; CHECK-NEXT: b
>    %sub = sub nsw i32 %a, %b
>    %cmp = icmp sgt i32 %sub, -1
>    %sub3 = sub nsw i32 0, %sub
>
> Modified: llvm/trunk/test/CodeGen/ARM64/vmul.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmul.ll?rev=209538&r1=209537&r2=209538&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM64/vmul.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM64/vmul.ll Fri May 23 14:06:24 2014
> @@ -1201,35 +1201,35 @@ define <2 x i64> @umlsl_lane_2d(<2 x i32
>  ; Scalar FMULX
>  define float @fmulxs(float %a, float %b) nounwind {
>  ; CHECK-LABEL: fmulxs:
> -; CHECKNEXT: fmulx s0, s0, s1
> +; CHECK-NEXT: fmulx s0, s0, s1
>    %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
> -; CHECKNEXT: ret
> +; CHECK-NEXT: ret
>    ret float %fmulx.i
>  }
>
>  define double @fmulxd(double %a, double %b) nounwind {
>  ; CHECK-LABEL: fmulxd:
> -; CHECKNEXT: fmulx d0, d0, d1
> +; CHECK-NEXT: fmulx d0, d0, d1
>    %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
> -; CHECKNEXT: ret
> +; CHECK-NEXT: ret
>    ret double %fmulx.i
>  }
>
>  define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind {
>  ; CHECK-LABEL: fmulxs_lane:
> -; CHECKNEXT: fmulx.s s0, s0, v1[3]
> +; CHECK-NEXT: fmulx.s s0, s0, v1[3]
>    %b = extractelement <4 x float> %vec, i32 3
>    %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
> -; CHECKNEXT: ret
> +; CHECK-NEXT: ret
>    ret float %fmulx.i
>  }
>
>  define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind {
>  ; CHECK-LABEL: fmulxd_lane:
> -; CHECKNEXT: fmulx d0, d0, v1[1]
> +; CHECK-NEXT: fmulx d0, d0, v1[1]
>    %b = extractelement <2 x double> %vec, i32 1
>    %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
> -; CHECKNEXT: ret
> +; CHECK-NEXT: ret
>    ret double %fmulx.i
>  }
>
>
> Modified: llvm/trunk/test/CodeGen/MSP430/fp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/fp.ll?rev=209538&r1=209537&r2=209538&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MSP430/fp.ll (original)
> +++ llvm/trunk/test/CodeGen/MSP430/fp.ll Fri May 23 14:06:24 2014
> @@ -21,7 +21,7 @@ entry:
>  ; does not happen anymore. Note that the only reason an ISR is used here is that
>  ; the register allocator selects r4 first instead of fifth in a normal function.
>  define msp430_intrcc void @fpb_alloced() #0 {
> -; CHECK_LABEL: fpb_alloced:
> +; CHECK-LABEL: fpb_alloced:
>  ; CHECK-NOT: mov.b #0, r4
>  ; CHECK: nop
>    call void asm sideeffect "nop", "r"(i8 0)
>
> Modified: llvm/trunk/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll?rev=209538&r1=209537&r2=209538&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll (original)
> +++ llvm/trunk/test/Transforms/SLPVectorizer/X86/insert-element-build-vector.ll Fri May 23 14:06:24 2014
> @@ -223,7 +223,7 @@ define <4 x float> @reschedule_extract(<
>  ; instructions that are erased.
>  define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
>  ; ZEROTHRESH-LABEL: @take_credit(
> -; ZEROTHRESH-CHECK: %1 = fadd <4 x float> %a, %b
> +; ZEROTHRESH: %1 = fadd <4 x float> %a, %b
>    %a0 = extractelement <4 x float> %a, i32 0
>    %b0 = extractelement <4 x float> %b, i32 0
>    %c0 = fadd float %a0, %b0
>
>
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