R600: Add BFE DAG combines

[Matt Arsenault]

On May 13, 2014, at 4:02 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:

> On 05/13/2014 03:59 PM, Tom Stellard wrote:
>> On Tue, May 13, 2014 at 03:52:17PM -0700, Matt Arsenault wrote:
>>> On 05/13/2014 03:47 PM, Tom Stellard wrote:
>>>> On Mon, May 12, 2014 at 11:46:39AM -0700, Matt Arsenault wrote:
>>>>> On Apr 25, 2014, at 1:57 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>>>> 
>>>>>> These patches allow some simplifications of BFE nodes. I just noticed the instruction patterns aren’t actually trying to match the BFE pattern, but that can be fixed later
>>>>>> 
>>>>>> 
>>>>>> <0001-R600-Implement-computeMaskedBitsForTargetNode-for-BF.patch><0002-R600-Implement-ComputeNumSignBitsForTargetNode-for-B.patch><0003-R600-Add-dag-combine-for-BFE.patch><0004-R600-Try-to-convert-BFE-back-to-standard-bit-ops-whe.patch>
>>>>> Ping
>>>> Can you explain the purpose of patch #4?  I don't understand why we are
>>>> converting BFE back to bit ops.
>>>> 
>>>> -Tom
>>> To allow the standard DAG combines to work. The cases that convert back
>>> are already equivalent to a single standard opcode. Mostly I was seeing
>>> redundant sign extensions, and replacing an equivalent BFE with
>>> sign_extend_inreg would allow it to be removed.
>> So this only covers the case where we have used a BFE instrinsic that is
>> equivalent to sign_extend_inreg?
>> 
>> -Tom
> 
> That's the most common case. Also BFE_U32 with 0 offset becomes an and, and when the width + offset is >= 32 it's equivalent to a single shift according to the instruction description

r209459 - r209462