[llvm] r209419 - [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6

[Daniel Sanders]

Author: dsanders
Date: Thu May 22 06:42:31 2014
New Revision: 209419

URL: http://llvm.org/viewvc/llvm-project?rev=209419&view=rev
Log:
[mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6

Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

Added:
    llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1.s
    llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1.s
Modified:
    llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td?rev=209419&r1=209418&r2=209419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrInfo.td Thu May 22 06:42:31 2014
@@ -25,7 +25,6 @@ include "Mips32r6InstrFormats.td"
 // Reencoded: sdbbp
 // Reencoded: sdc2
 // Reencoded: swc2
-// Removed: addi
 // Removed: bc1any2, bc1any4
 // Removed: bc2[ft]
 // Removed: bc2f, bc2t

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=209419&r1=209418&r2=209419&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu May 22 06:42:31 2014
@@ -166,6 +166,8 @@ def HasMips32r2  :    Predicate<"Subtarg
                       AssemblerPredicate<"FeatureMips32r2">;
 def HasMips32r6  :    Predicate<"Subtarget.hasMips32r6()">,
                       AssemblerPredicate<"FeatureMips32r6">;
+def NotMips32r6  :    Predicate<"!Subtarget.hasMips32r6()">,
+                      AssemblerPredicate<"!FeatureMips32r6">;
 def IsGP64bit    :    Predicate<"Subtarget.isGP64bit()">,
                       AssemblerPredicate<"FeatureGP64Bit">;
 def IsGP32bit    :    Predicate<"!Subtarget.isGP64bit()">,
@@ -176,6 +178,8 @@ def HasMips64r2  :    Predicate<"Subtarg
                       AssemblerPredicate<"FeatureMips64r2">;
 def HasMips64r6  :    Predicate<"Subtarget.hasMips64r6()">,
                       AssemblerPredicate<"FeatureMips64r6">;
+def NotMips64r6  :    Predicate<"!Subtarget.hasMips64r6()">,
+                      AssemblerPredicate<"!FeatureMips64r6">;
 def IsN64       :     Predicate<"Subtarget.isABI_N64()">,
                       AssemblerPredicate<"FeatureN64">;
 def InMips16Mode :    Predicate<"Subtarget.inMips16Mode()">,
@@ -211,6 +215,14 @@ class GPR_64 { list<Predicate> GPRPredic
 // They are mutually exclusive.
 //===----------------------------------------------------------------------===//
 
+// FIXME: I'd prefer to use additive predicates to build the instruction sets
+//        but we are short on assembler feature bits at the moment. Using a
+//        subtractive predicate will hopefully keep us under the 32 predicate
+//        limit long enough to develop an alternative way to handle P1||P2
+//        predicates.
+class ISA_MIPS1_NOT_32R6_64R6 {
+  list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
+}
 class ISA_MIPS2    { list<Predicate> InsnPredicates = [HasMips2]; }
 class ISA_MIPS3    { list<Predicate> InsnPredicates = [HasMips3]; }
 class ISA_MIPS32   { list<Predicate> InsnPredicates = [HasMips32]; }
@@ -1000,7 +1012,8 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs G
 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
                                add>,
             ADDI_FM<0x9>, IsAsCheapAsAMove;
-def ADDi  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
+def ADDi  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
+            ISA_MIPS1_NOT_32R6_64R6;
 def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xa>;
 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,

Added: llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1.s?rev=209419&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1.s (added)
+++ llvm/trunk/test/MC/Mips/mips32r6/invalid-mips1.s Thu May 22 06:42:31 2014
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+        addi      $13,$9,26322        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

Added: llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1.s?rev=209419&view=auto
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1.s (added)
+++ llvm/trunk/test/MC/Mips/mips64r6/invalid-mips1.s Thu May 22 06:42:31 2014
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+	.set noat
+        addi      $13,$9,26322        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled