[llvm] r209126 - Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.

[Aaron Ballman]

Author: aaronballman
Date: Mon May 19 09:29:04 2014
New Revision: 209126

URL: http://llvm.org/viewvc/llvm-project?rev=209126&view=rev
Log:
Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.cpp
    llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.cpp?rev=209126&r1=209125&r2=209126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.cpp Mon May 19 09:29:04 2014
@@ -827,14 +827,11 @@ bool ARM64InstrInfo::optimizeCompareInst
 
 /// Return true if this is this instruction has a non-zero immediate
 bool ARM64InstrInfo::hasNonZeroImm(const MachineInstr *MI) const {
-  switch (MI->getOpcode()) {
-  default:
-    if (MI->getOperand(3).isImm()) {
-      unsigned val = MI->getOperand(3).getImm();
-      return (val != 0);
-    }
-    break;
+  if (MI->getOperand(3).isImm()) {
+    unsigned val = MI->getOperand(3).getImm();
+    return (val != 0);
   }
+
   return false;
 }
 

Modified: llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp?rev=209126&r1=209125&r2=209126&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/R600/AMDGPUMCInstLower.cpp Mon May 19 09:29:04 2014
@@ -37,10 +37,8 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCC
 { }
 
 enum AMDGPUMCInstLower::SISubtarget
-AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
-  switch (Gen) {
-  default: return AMDGPUMCInstLower::SI;
-  }
+AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned) const {
+  return AMDGPUMCInstLower::SI;
 }
 
 unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {