[PATCH] [ARM64] Split tbz/tbnz into W/X register variant

Tim Northover t.p.northover at gmail.com
Thu May 15 04:20:15 PDT 2014

Hi Bradley,

I've got a suggestion on this one:

Comment at: lib/Target/ARM64/ARM64InstrFormats.td:1064-1069
@@ +1063,8 @@
+multiclass TestBranch<bit op, string asm, SDNode node> {
+  def W : BaseTestBranch<GPR32, imm0_31, op, asm, node> {
+    let Inst{31} = 0;
+  }
+  // This overlaps with the W-reg case, this is intentional since
+  // both are valid.
+  def X : BaseTestBranch<GPR64, imm0_63, op, asm, node>;
This has the quirk that if someone assembles "tbz x3, #0" that's what'll be printed, doesn't it?

I think we can improve on this (both AArch64 and ARM64's solution) if we add a new RegisterOperand: "GPR32as64" or something. It'll check that the actually parsed operand is a GPR64, but add the corresponding GPR32 to the instruction in its RenderMethod.

With this, we *can* write the InstAlias, I believe (remember to set the Emit bit to 0!). It'll probably be a little bit more code, but worth it.


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