[PATCH] [ARM64] Implement NEON post-increment LD1 (lane) and post-increment LD1R

Hao Liu Hao.Liu at arm.com
Wed May 14 22:16:29 PDT 2014

Hi James,

Thanks for the code review. I've reworked on the code according to your comments.


Comment at: lib/Target/ARM64/ARM64ISelDAGToDAG.cpp:2670
@@ +2669,3 @@
+  case ARM64ISD::LD1DUPpost: {
+    if (VT == MVT::v8i8)
+      return SelectPostLoad(Node, 1, ARM64::LD1Rv8b_POST, ARM64::dsub0);
James Molloy wrote:
> Would a switch be clearer here?
Hi James,
Yes, switch is much clearer. But all the other code to select load/store is implemented like this, if we modify this, all other code needs to be modified. This will change a lot. So Tim suggested to deal with this piece of code in the future with a separate patch (see the comment in http://reviews.llvm.org/D3605).
So I just implement this piece of code like others. This will be improved in the future.

Comment at: lib/Target/ARM64/ARM64ISelLowering.cpp:7098
@@ +7097,3 @@
+  // If it is not LOAD/EXTLOAD, can not do such combine.
+  if (LD->getOpcode() != ISD::LOAD && LD->getOpcode() != ISD::EXTLOAD)
+    return SDValue();
James Molloy wrote:
> What about SEXTLOAD and ZEXTLOAD here?
Oh, I analysis this again. I find that this is always ISD::LOAD, no ISD::EXTLOAD or SEXTLOAD/ZEXTLOAD. So I remove EXTLOAD and check the type of memory operand type, which should be the same to the element type of the vector.


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