[PATCH] [X86 DAG] Lower vselects with a constant condition as blend+imm if possible

Andrea Di Biagio Andrea_DiBiagio at sn.scee.net
Wed May 14 04:39:19 PDT 2014

Hi Filipe,

I have a minor comment/suggestion (see below).

Comment at: lib/Target/X86/X86ISelLowering.cpp:7974
@@ -7963,1 +7973,3 @@
+static bool BUILD_VECTORtoBlendMask(SDValue BuildVector, unsigned &MaskValue,
+                                    SelectionDAG &DAG) {
This function could be simplified a bit if
`BuildVector` is known to always be a build_vector dag node of all ConstantSDNode (or UNDEF) elements.
I think you can easily add it as a precondition; the caller can verify if a node is a build_vector of constants (or undef values) by simply calling function
Also, given that argument 'BuildVector' can only be a build_vector dag node, you can change the signature of this function to something like:

  static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector, unsigned &MaskValue, SelectionDAG &DAG)

This is to make explicit that BuildVector can only be a `BuildVectorSDNode`.

Under the assumption that BuildVector is a build_vector of constants or UNDEFs, then
lines in the range [7992-8008] can be simplified and replaced by the folling 5 lines.

    int Lane1Cond = -1, Lane2Cond = -1;
    if (isa<ConstantSDNode>(EltCond))
      Lane1Cond = cast<ConstantSDNode>(EltCond)->isNullValue();
    if (isa<ConstantSDNode>(SndLaneEltCond))
      Lane2Cond = cast<ConstantSDNode>(SndLaneEltCond)->isNullValue();
The function will return false only if `Lane1Cond != Lane2Cond` && `Lane1Cond` and `Lane2Cond` both are >= 0.


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