[ARM64] Implement NEON post-increment LD1 (lane) and post-increment LD1R
Hao.Liu at arm.com
Wed May 14 02:07:07 PDT 2014
> -----Original Message-----
> From: Hao Liu [mailto:Hao.Liu at arm.com]
> Sent: Tuesday, May 13, 2014 6:01 PM
> To: Hao Liu; t.p.northover at gmail.com
> Cc: Amara Emerson; llvm-commits at cs.uiuc.edu
> Subject: [PATCH] [ARM64] Implement NEON post-increment LD1 (lane) and
> post-increment LD1R
> Hi t.p.northover,
> Hi Tim,
> This patch implements post-increment LD1 (lane) and post-increment LD1R.
> The implementation is like the implementation of NEON post-increment load
> with 2/3/4 vectors.
> It tries to do the following 2 combines if satisfied:
> (1) combine an ARM64ISD:DUP and a post-increment load into a post-
> increment LD1R.
> (2) combine an ISD::INSERT_VECTOR_ELT and a post-increment load into a
> post-increment LD1 (lane).
> Ask for code review.
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