R600: Add BFE DAG combines
Matthew.Arsenault at amd.com
Tue May 13 16:02:50 PDT 2014
On 05/13/2014 03:59 PM, Tom Stellard wrote:
> On Tue, May 13, 2014 at 03:52:17PM -0700, Matt Arsenault wrote:
>> On 05/13/2014 03:47 PM, Tom Stellard wrote:
>>> On Mon, May 12, 2014 at 11:46:39AM -0700, Matt Arsenault wrote:
>>>> On Apr 25, 2014, at 1:57 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>>>> These patches allow some simplifications of BFE nodes. I just noticed the instruction patterns aren’t actually trying to match the BFE pattern, but that can be fixed later
>>> Can you explain the purpose of patch #4? I don't understand why we are
>>> converting BFE back to bit ops.
>> To allow the standard DAG combines to work. The cases that convert back
>> are already equivalent to a single standard opcode. Mostly I was seeing
>> redundant sign extensions, and replacing an equivalent BFE with
>> sign_extend_inreg would allow it to be removed.
> So this only covers the case where we have used a BFE instrinsic that is
> equivalent to sign_extend_inreg?
That's the most common case. Also BFE_U32 with 0 offset becomes an and,
and when the width + offset is >= 32 it's equivalent to a single shift
according to the instruction description
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