[llvm] r208577 - [ARM64-BE] Add sphinx documentation for the ARM64 NEON implementation.

Tobias Grosser tobias at grosser.es
Mon May 12 08:36:01 PDT 2014

Thanks James, very interesting read.

> +LLVM IR has first class vector types. In LLVM IR, the zero'th element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - ``[4 x i8]`` and ``<4 x i8>`` should be represented the same in memory. Without this property there would be many special cases that the optimizer would have the cleverly handle.

have *to* cleverly


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