[llvm] r208221 - [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Daniel Sanders
daniel.sanders at imgtec.com
Wed May 7 09:25:23 PDT 2014
Author: dsanders
Date: Wed May 7 11:25:22 2014
New Revision: 208221
URL: http://llvm.org/viewvc/llvm-project?rev=208221&view=rev
Log:
[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V
Summary:
These processors will only be available for the integrated assembler at
first (CodeGen will emit a fatal error saying they are not implemented).
The intention is to work through the existing instructions and correctly
annotate the ISA they were added in so that we have a sufficiently good
base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain
instructions and I believe it is best to define ISA's using set-union's
as far as possible rather than using set-subtraction.
Reviewers: vmedic
Subscribers: emaste, llvm-commits
Differential Revision: http://reviews.llvm.org/D3569
Modified:
llvm/trunk/lib/Target/Mips/Mips.td
llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
llvm/trunk/lib/Target/Mips/MipsSubtarget.h
llvm/trunk/test/MC/Mips/mips1/valid-xfail.s
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid-xfail.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
llvm/trunk/test/MC/Mips/mips5/valid.s
Modified: llvm/trunk/lib/Target/Mips/Mips.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips.td Wed May 7 11:25:22 2014
@@ -85,20 +85,34 @@ def FeatureBitCount : SubtargetFeatur
"Enable 'count leading bits' instructions.">;
def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
"Enable 'FP indexed load/store' instructions.">;
+def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
+ "Mips I ISA Support [highly experimental]">;
+def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
+ "Mips II ISA Support [highly experimental]",
+ [FeatureMips1]>;
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
"Mips32 ISA Support",
- [FeatureCondMov, FeatureBitCount]>;
+ [FeatureMips2, FeatureCondMov,
+ FeatureBitCount]>;
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
"Mips32r2", "Mips32r2 ISA Support",
[FeatureMips32, FeatureSEInReg, FeatureSwap,
FeatureFPIdx]>;
+// FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
+// list but for now it doesn't matter since FPIdx isn't actually attached
+// to any instructions.
+def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
+ "MIPS III ISA Support [highly experimental]",
+ [FeatureMips2, FeatureGP64Bit, FeatureFP64Bit]>;
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
"Mips4", "MIPS IV ISA Support",
- [FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
- FeatureCondMov]>;
+ [FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
+def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
+ "MIPS V ISA Support [highly experimental]",
+ [FeatureMips4]>;
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
"Mips64", "Mips64 ISA Support",
- [FeatureMips4, FeatureMips32, FeatureFPIdx]>;
+ [FeatureMips5, FeatureMips32, FeatureFPIdx]>;
def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
"Mips64r2", "Mips64r2 ISA Support",
[FeatureMips64, FeatureMips32r2]>;
@@ -126,9 +140,14 @@ def FeatureCnMips : SubtargetFeature
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, MipsGenericItineraries, Features>;
+def : Proc<"mips1", [FeatureMips1, FeatureO32]>;
+def : Proc<"mips2", [FeatureMips2, FeatureO32]>;
def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
+
+def : Proc<"mips3", [FeatureMips3, FeatureN64]>;
def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
+def : Proc<"mips5", [FeatureMips5, FeatureN64]>;
def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Wed May 7 11:25:22 2014
@@ -107,6 +107,19 @@ MipsSubtarget::MipsSubtarget(const std::
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);
+ // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
+ // MIPS-V. They have not been tested and currently exist for the integrated
+ // assembler only.
+ if (MipsArchVersion == Mips1)
+ report_fatal_error("Code generation for MIPS-I is not implemented", false);
+ if (MipsArchVersion == Mips2)
+ report_fatal_error("Code generation for MIPS-II is not implemented", false);
+ if (MipsArchVersion == Mips3)
+ report_fatal_error("Code generation for MIPS-III is not implemented",
+ false);
+ if (MipsArchVersion == Mips5)
+ report_fatal_error("Code generation for MIPS-V is not implemented", false);
+
// Assert exactly one ABI was chosen.
assert(MipsABI != UnknownABI);
assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Wed May 7 11:25:22 2014
@@ -37,7 +37,8 @@ public:
};
protected:
- enum MipsArchEnum { Mips32, Mips32r2, Mips4, Mips64, Mips64r2 };
+ enum MipsArchEnum { Mips1, Mips2, Mips32, Mips32r2, Mips3, Mips4, Mips5,
+ Mips64, Mips64r2 };
// Mips architecture version
MipsArchEnum MipsArchVersion;
Modified: llvm/trunk/test/MC/Mips/mips1/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid-xfail.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid-xfail.s Wed May 7 11:25:22 2014
@@ -2,8 +2,7 @@
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
-# FIXME: Test MIPS-I instead of MIPS32
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Wed May 7 11:25:22 2014
@@ -1,7 +1,6 @@
# Instructions that are valid
#
-# FIXME: Test MIPS-I instead of MIPS32
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
.set noat
abs.d $f7,$f25 # CHECK: encoding:
Modified: llvm/trunk/test/MC/Mips/mips2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid-xfail.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid-xfail.s Wed May 7 11:25:22 2014
@@ -2,8 +2,7 @@
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
-# FIXME: Test MIPS-II instead of MIPS32
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Wed May 7 11:25:22 2014
@@ -1,7 +1,6 @@
# Instructions that are valid
#
-# FIXME: Test MIPS-II instead of MIPS32
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
.set noat
abs.d $f7,$f25 # CHECK: encoding
Modified: llvm/trunk/test/MC/Mips/mips3/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid-xfail.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid-xfail.s Wed May 7 11:25:22 2014
@@ -2,8 +2,7 @@
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
-# FIXME: Test MIPS-III instead of MIPS-IV
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Wed May 7 11:25:22 2014
@@ -1,7 +1,6 @@
# Instructions that are valid
#
-# FIXME: Test MIPS-III instead of MIPS-IV
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
.set noat
abs.d $f7,$f25 # CHECK: encoding
Modified: llvm/trunk/test/MC/Mips/mips5/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid-xfail.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid-xfail.s Wed May 7 11:25:22 2014
@@ -2,8 +2,7 @@
# they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding.
#
-# FIXME: Test MIPS-V instead of MIPS64
-# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s
+# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s
# CHECK-NOT: encoding
# XFAIL: *
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=208221&r1=208220&r2=208221&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Wed May 7 11:25:22 2014
@@ -1,7 +1,6 @@
# Instructions that are valid
#
-# FIXME: Test MIPS-V instead of MIPS64
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
.set noat
abs.d $f7,$f25 # CHECK: encoding
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