[llvm] r208198 - [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
James Molloy
james.molloy at arm.com
Wed May 7 05:33:41 PDT 2014
Author: jamesm
Date: Wed May 7 07:33:41 2014
New Revision: 208198
URL: http://llvm.org/viewvc/llvm-project?rev=208198&view=rev
Log:
[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.
The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.
Added:
llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll
llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll
Modified:
llvm/trunk/lib/Target/ARM64/ARM64CallingConvention.td
Modified: llvm/trunk/lib/Target/ARM64/ARM64CallingConvention.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64CallingConvention.td?rev=208198&r1=208197&r2=208198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64CallingConvention.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64CallingConvention.td Wed May 7 07:33:41 2014
@@ -14,6 +14,9 @@
/// CCIfAlign - Match of the original alignment of the arg
class CCIfAlign<string Align, CCAction A> :
CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
+/// CCIfBigEndian - Match only if we're in big endian mode.
+class CCIfBigEndian<CCAction A> :
+ CCIf<"State.getTarget().getDataLayout()->isBigEndian()", A>;
//===----------------------------------------------------------------------===//
// ARM AAPCS64 Calling Convention
@@ -23,6 +26,13 @@ def CC_ARM64_AAPCS : CallingConv<[
CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
+ // Big endian vectors must be passed as if they were 1-element vectors so that
+ // their lanes are in a consistent order.
+ CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
+ CCBitConvertToType<f64>>>,
+ CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
+ CCBitConvertToType<f128>>>,
+
// An SRet is passed in X8, not X0 like a normal pointer parameter.
CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
@@ -67,6 +77,13 @@ def RetCC_ARM64_AAPCS : CallingConv<[
CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
+ // Big endian vectors must be passed as if they were 1-element vectors so that
+ // their lanes are in a consistent order.
+ CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
+ CCBitConvertToType<f64>>>,
+ CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
+ CCBitConvertToType<f128>>>,
+
CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
[X0, X1, X2, X3, X4, X5, X6, X7]>>,
CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
Added: llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll?rev=208198&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/big-endian-vector-callee.ll Wed May 7 07:33:41 2014
@@ -0,0 +1,847 @@
+; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
+
+; CHECK-LABEL: test_i64_f64:
+define i64 @test_i64_f64(double %p) {
+; CHECK-NOT: rev
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_i64_v1i64:
+define i64 @test_i64_v1i64(<1 x i64> %p) {
+; CHECK-NOT: rev
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_i64_v2f32:
+define i64 @test_i64_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_i64_v2i32:
+define i64 @test_i64_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_i64_v4i16:
+define i64 @test_i64_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_i64_v8i8:
+define i64 @test_i64_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to i64
+ %3 = add i64 %2, %2
+ ret i64 %3
+}
+
+; CHECK-LABEL: test_f64_i64:
+define double @test_f64_i64(i64 %p) {
+; CHECK-NOT: rev
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_f64_v1i64:
+define double @test_f64_v1i64(<1 x i64> %p) {
+; CHECK-NOT: rev
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_f64_v2f32:
+define double @test_f64_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_f64_v2i32:
+define double @test_f64_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_f64_v4i16:
+define double @test_f64_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_f64_v8i8:
+define double @test_f64_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to double
+ %3 = fadd double %2, %2
+ ret double %3
+}
+
+; CHECK-LABEL: test_v1i64_i64:
+define <1 x i64> @test_v1i64_i64(i64 %p) {
+; CHECK-NOT: rev
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v1i64_f64:
+define <1 x i64> @test_v1i64_f64(double %p) {
+; CHECK-NOT: rev
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v1i64_v2f32:
+define <1 x i64> @test_v1i64_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v1i64_v2i32:
+define <1 x i64> @test_v1i64_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v1i64_v4i16:
+define <1 x i64> @test_v1i64_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v1i64_v8i8:
+define <1 x i64> @test_v1i64_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to <1 x i64>
+ %3 = add <1 x i64> %2, %2
+ ret <1 x i64> %3
+}
+
+; CHECK-LABEL: test_v2f32_i64:
+define <2 x float> @test_v2f32_i64(i64 %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2f32_f64:
+define <2 x float> @test_v2f32_f64(double %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2f32_v1i64:
+define <2 x float> @test_v2f32_v1i64(<1 x i64> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2f32_v2i32:
+define <2 x float> @test_v2f32_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2f32_v4i16:
+define <2 x float> @test_v2f32_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2f32_v8i8:
+define <2 x float> @test_v2f32_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to <2 x float>
+ %3 = fadd <2 x float> %2, %2
+ ret <2 x float> %3
+}
+
+; CHECK-LABEL: test_v2i32_i64:
+define <2 x i32> @test_v2i32_i64(i64 %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v2i32_f64:
+define <2 x i32> @test_v2i32_f64(double %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v2i32_v1i64:
+define <2 x i32> @test_v2i32_v1i64(<1 x i64> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v2i32_v2f32:
+define <2 x i32> @test_v2i32_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v2i32_v4i16:
+define <2 x i32> @test_v2i32_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v2i32_v8i8:
+define <2 x i32> @test_v2i32_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to <2 x i32>
+ %3 = add <2 x i32> %2, %2
+ ret <2 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i16_i64:
+define <4 x i16> @test_v4i16_i64(i64 %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v4i16_f64:
+define <4 x i16> @test_v4i16_f64(double %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v4i16_v1i64:
+define <4 x i16> @test_v4i16_v1i64(<1 x i64> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v4i16_v2f32:
+define <4 x i16> @test_v4i16_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v4i16_v2i32:
+define <4 x i16> @test_v4i16_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v4i16_v8i8:
+define <4 x i16> @test_v4i16_v8i8(<8 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = add <8 x i8> %p, %p
+ %2 = bitcast <8 x i8> %1 to <4 x i16>
+ %3 = add <4 x i16> %2, %2
+ ret <4 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i8_i64:
+define <8 x i8> @test_v8i8_i64(i64 %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add i64 %p, %p
+ %2 = bitcast i64 %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_v8i8_f64:
+define <8 x i8> @test_v8i8_f64(double %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = fadd double %p, %p
+ %2 = bitcast double %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_v8i8_v1i64:
+define <8 x i8> @test_v8i8_v1i64(<1 x i64> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <1 x i64> %p, %p
+ %2 = bitcast <1 x i64> %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_v8i8_v2f32:
+define <8 x i8> @test_v8i8_v2f32(<2 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = fadd <2 x float> %p, %p
+ %2 = bitcast <2 x float> %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_v8i8_v2i32:
+define <8 x i8> @test_v8i8_v2i32(<2 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <2 x i32> %p, %p
+ %2 = bitcast <2 x i32> %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_v8i8_v4i16:
+define <8 x i8> @test_v8i8_v4i16(<4 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = add <4 x i16> %p, %p
+ %2 = bitcast <4 x i16> %1 to <8 x i8>
+ %3 = add <8 x i8> %2, %2
+ ret <8 x i8> %3
+}
+
+; CHECK-LABEL: test_f128_v2f64:
+define fp128 @test_f128_v2f64(<2 x double> %p) {
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_f128_v2i64:
+define fp128 @test_f128_v2i64(<2 x i64> %p) {
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_f128_v4f32:
+define fp128 @test_f128_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_f128_v4i32:
+define fp128 @test_f128_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_f128_v8i16:
+define fp128 @test_f128_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_f128_v16i8:
+define fp128 @test_f128_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to fp128
+ %3 = fadd fp128 %2, %2
+ ret fp128 %3
+}
+
+; CHECK-LABEL: test_v2f64_f128:
+define <2 x double> @test_v2f64_f128(fp128 %p) {
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2f64_v2i64:
+define <2 x double> @test_v2f64_v2i64(<2 x i64> %p) {
+; CHECK: ext
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2f64_v4f32:
+define <2 x double> @test_v2f64_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2f64_v4i32:
+define <2 x double> @test_v2f64_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2f64_v8i16:
+define <2 x double> @test_v2f64_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2f64_v16i8:
+define <2 x double> @test_v2f64_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to <2 x double>
+ %3 = fadd <2 x double> %2, %2
+ ret <2 x double> %3
+}
+
+; CHECK-LABEL: test_v2i64_f128:
+define <2 x i64> @test_v2i64_f128(fp128 %p) {
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v2i64_v2f64:
+define <2 x i64> @test_v2i64_v2f64(<2 x double> %p) {
+; CHECK: ext
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v2i64_v4f32:
+define <2 x i64> @test_v2i64_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v2i64_v4i32:
+define <2 x i64> @test_v2i64_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v2i64_v8i16:
+define <2 x i64> @test_v2i64_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v2i64_v16i8:
+define <2 x i64> @test_v2i64_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to <2 x i64>
+ %3 = add <2 x i64> %2, %2
+ ret <2 x i64> %3
+}
+
+; CHECK-LABEL: test_v4f32_f128:
+define <4 x float> @test_v4f32_f128(fp128 %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4f32_v2f64:
+define <4 x float> @test_v4f32_v2f64(<2 x double> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4f32_v2i64:
+define <4 x float> @test_v4f32_v2i64(<2 x i64> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4f32_v4i32:
+define <4 x float> @test_v4f32_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4f32_v8i16:
+define <4 x float> @test_v4f32_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4f32_v16i8:
+define <4 x float> @test_v4f32_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to <4 x float>
+ %3 = fadd <4 x float> %2, %2
+ ret <4 x float> %3
+}
+
+; CHECK-LABEL: test_v4i32_f128:
+define <4 x i32> @test_v4i32_f128(fp128 %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i32_v2f64:
+define <4 x i32> @test_v4i32_v2f64(<2 x double> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i32_v2i64:
+define <4 x i32> @test_v4i32_v2i64(<2 x i64> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i32_v4f32:
+define <4 x i32> @test_v4i32_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i32_v8i16:
+define <4 x i32> @test_v4i32_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v4i32_v16i8:
+define <4 x i32> @test_v4i32_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to <4 x i32>
+ %3 = add <4 x i32> %2, %2
+ ret <4 x i32> %3
+}
+
+; CHECK-LABEL: test_v8i16_f128:
+define <8 x i16> @test_v8i16_f128(fp128 %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i16_v2f64:
+define <8 x i16> @test_v8i16_v2f64(<2 x double> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i16_v2i64:
+define <8 x i16> @test_v8i16_v2i64(<2 x i64> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i16_v4f32:
+define <8 x i16> @test_v8i16_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i16_v4i32:
+define <8 x i16> @test_v8i16_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v8i16_v16i8:
+define <8 x i16> @test_v8i16_v16i8(<16 x i8> %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = add <16 x i8> %p, %p
+ %2 = bitcast <16 x i8> %1 to <8 x i16>
+ %3 = add <8 x i16> %2, %2
+ ret <8 x i16> %3
+}
+
+; CHECK-LABEL: test_v16i8_f128:
+define <16 x i8> @test_v16i8_f128(fp128 %p) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = fadd fp128 %p, %p
+ %2 = bitcast fp128 %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
+
+; CHECK-LABEL: test_v16i8_v2f64:
+define <16 x i8> @test_v16i8_v2f64(<2 x double> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = fadd <2 x double> %p, %p
+ %2 = bitcast <2 x double> %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
+
+; CHECK-LABEL: test_v16i8_v2i64:
+define <16 x i8> @test_v16i8_v2i64(<2 x i64> %p) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = add <2 x i64> %p, %p
+ %2 = bitcast <2 x i64> %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
+
+; CHECK-LABEL: test_v16i8_v4f32:
+define <16 x i8> @test_v16i8_v4f32(<4 x float> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = fadd <4 x float> %p, %p
+ %2 = bitcast <4 x float> %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
+
+; CHECK-LABEL: test_v16i8_v4i32:
+define <16 x i8> @test_v16i8_v4i32(<4 x i32> %p) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = add <4 x i32> %p, %p
+ %2 = bitcast <4 x i32> %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
+
+; CHECK-LABEL: test_v16i8_v8i16:
+define <16 x i8> @test_v16i8_v8i16(<8 x i16> %p) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = add <8 x i16> %p, %p
+ %2 = bitcast <8 x i16> %1 to <16 x i8>
+ %3 = add <16 x i8> %2, %2
+ ret <16 x i8> %3
+}
Added: llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll?rev=208198&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/big-endian-vector-caller.ll Wed May 7 07:33:41 2014
@@ -0,0 +1,1099 @@
+; RUN: llc -mtriple arm64_be < %s -arm64-load-store-opt=false -o - | FileCheck %s
+
+; CHECK-LABEL: test_i64_f64:
+declare i64 @test_i64_f64_helper(double %p)
+define void @test_i64_f64(double* %p, i64* %q) {
+; CHECK-NOT: rev
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call i64 @test_i64_f64_helper(double %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_i64_v1i64:
+declare i64 @test_i64_v1i64_helper(<1 x i64> %p)
+define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) {
+; CHECK-NOT: rev
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_i64_v2f32:
+declare i64 @test_i64_v2f32_helper(<2 x float> %p)
+define void @test_i64_v2f32(<2 x float>* %p, i64* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_i64_v2i32:
+declare i64 @test_i64_v2i32_helper(<2 x i32> %p)
+define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_i64_v4i16:
+declare i64 @test_i64_v4i16_helper(<4 x i16> %p)
+define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_i64_v8i8:
+declare i64 @test_i64_v8i8_helper(<8 x i8> %p)
+define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2)
+ %4 = add i64 %3, %3
+ store i64 %4, i64* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_i64:
+declare double @test_f64_i64_helper(i64 %p)
+define void @test_f64_i64(i64* %p, double* %q) {
+; CHECK-NOT: rev
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call double @test_f64_i64_helper(i64 %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_v1i64:
+declare double @test_f64_v1i64_helper(<1 x i64> %p)
+define void @test_f64_v1i64(<1 x i64>* %p, double* %q) {
+; CHECK-NOT: rev
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call double @test_f64_v1i64_helper(<1 x i64> %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_v2f32:
+declare double @test_f64_v2f32_helper(<2 x float> %p)
+define void @test_f64_v2f32(<2 x float>* %p, double* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call double @test_f64_v2f32_helper(<2 x float> %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_v2i32:
+declare double @test_f64_v2i32_helper(<2 x i32> %p)
+define void @test_f64_v2i32(<2 x i32>* %p, double* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call double @test_f64_v2i32_helper(<2 x i32> %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_v4i16:
+declare double @test_f64_v4i16_helper(<4 x i16> %p)
+define void @test_f64_v4i16(<4 x i16>* %p, double* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call double @test_f64_v4i16_helper(<4 x i16> %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f64_v8i8:
+declare double @test_f64_v8i8_helper(<8 x i8> %p)
+define void @test_f64_v8i8(<8 x i8>* %p, double* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call double @test_f64_v8i8_helper(<8 x i8> %2)
+ %4 = fadd double %3, %3
+ store double %4, double* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_i64:
+declare <1 x i64> @test_v1i64_i64_helper(i64 %p)
+define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) {
+; CHECK-NOT: rev
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_f64:
+declare <1 x i64> @test_v1i64_f64_helper(double %p)
+define void @test_v1i64_f64(double* %p, <1 x i64>* %q) {
+; CHECK-NOT: rev
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call <1 x i64> @test_v1i64_f64_helper(double %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_v2f32:
+declare <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %p)
+define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_v2i32:
+declare <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %p)
+define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_v4i16:
+declare <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %p)
+define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v1i64_v8i8:
+declare <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %p)
+define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2)
+ %4 = add <1 x i64> %3, %3
+ store <1 x i64> %4, <1 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_i64:
+declare <2 x float> @test_v2f32_i64_helper(i64 %p)
+define void @test_v2f32_i64(i64* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_f64:
+declare <2 x float> @test_v2f32_f64_helper(double %p)
+define void @test_v2f32_f64(double* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call <2 x float> @test_v2f32_f64_helper(double %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_v1i64:
+declare <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %p)
+define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_v2i32:
+declare <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %p)
+define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_v4i16:
+declare <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %p)
+define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f32_v8i8:
+declare <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %p)
+define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2)
+ %4 = fadd <2 x float> %3, %3
+ store <2 x float> %4, <2 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_i64:
+declare <2 x i32> @test_v2i32_i64_helper(i64 %p)
+define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_f64:
+declare <2 x i32> @test_v2i32_f64_helper(double %p)
+define void @test_v2i32_f64(double* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call <2 x i32> @test_v2i32_f64_helper(double %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_v1i64:
+declare <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %p)
+define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_v2f32:
+declare <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %p)
+define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_v4i16:
+declare <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %p)
+define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i32_v8i8:
+declare <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %p)
+define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.2s
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2)
+ %4 = add <2 x i32> %3, %3
+ store <2 x i32> %4, <2 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_i64:
+declare <4 x i16> @test_v4i16_i64_helper(i64 %p)
+define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_f64:
+declare <4 x i16> @test_v4i16_f64_helper(double %p)
+define void @test_v4i16_f64(double* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call <4 x i16> @test_v4i16_f64_helper(double %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_v1i64:
+declare <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %p)
+define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_v2f32:
+declare <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %p)
+define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_v2i32:
+declare <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %p)
+define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i16_v8i8:
+declare <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %p)
+define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+; CHECK: rev64 v{{[0-9]+}}.4h
+ %1 = load <8 x i8>* %p
+ %2 = add <8 x i8> %1, %1
+ %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2)
+ %4 = add <4 x i16> %3, %3
+ store <4 x i16> %4, <4 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_i64:
+declare <8 x i8> @test_v8i8_i64_helper(i64 %p)
+define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load i64* %p
+ %2 = add i64 %1, %1
+ %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_f64:
+declare <8 x i8> @test_v8i8_f64_helper(double %p)
+define void @test_v8i8_f64(double* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load double* %p
+ %2 = fadd double %1, %1
+ %3 = call <8 x i8> @test_v8i8_f64_helper(double %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_v1i64:
+declare <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %p)
+define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <1 x i64>* %p
+ %2 = add <1 x i64> %1, %1
+ %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_v2f32:
+declare <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %p)
+define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <2 x float>* %p
+ %2 = fadd <2 x float> %1, %1
+ %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_v2i32:
+declare <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %p)
+define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.2s
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <2 x i32>* %p
+ %2 = add <2 x i32> %1, %1
+ %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i8_v4i16:
+declare <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %p)
+define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4h
+; CHECK: rev64 v{{[0-9]+}}.8b
+ %1 = load <4 x i16>* %p
+ %2 = add <4 x i16> %1, %1
+ %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2)
+ %4 = add <8 x i8> %3, %3
+ store <8 x i8> %4, <8 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v2f64:
+declare fp128 @test_f128_v2f64_helper(<2 x double> %p)
+define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) {
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v2i64:
+declare fp128 @test_f128_v2i64_helper(<2 x i64> %p)
+define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) {
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v4f32:
+declare fp128 @test_f128_v4f32_helper(<4 x float> %p)
+define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v4i32:
+declare fp128 @test_f128_v4i32_helper(<4 x i32> %p)
+define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v8i16:
+declare fp128 @test_f128_v8i16_helper(<8 x i16> %p)
+define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_f128_v16i8:
+declare fp128 @test_f128_v16i8_helper(<16 x i8> %p)
+define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2)
+ %4 = fadd fp128 %3, %3
+ store fp128 %4, fp128* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_f128:
+declare <2 x double> @test_v2f64_f128_helper(fp128 %p)
+define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) {
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_v2i64:
+declare <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %p)
+define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) {
+; CHECK: ext
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_v4f32:
+declare <2 x double> @test_v2f64_v4f32_helper(<4 x float> %p)
+define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_v4i32:
+declare <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %p)
+define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_v8i16:
+declare <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %p)
+define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2f64_v16i8:
+declare <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %p)
+define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2)
+ %4 = fadd <2 x double> %3, %3
+ store <2 x double> %4, <2 x double>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_f128:
+declare <2 x i64> @test_v2i64_f128_helper(fp128 %p)
+define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) {
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_v2f64:
+declare <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %p)
+define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) {
+; CHECK: ext
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_v4f32:
+declare <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %p)
+define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_v4i32:
+declare <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %p)
+define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_v8i16:
+declare <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %p)
+define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v2i64_v16i8:
+declare <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %p)
+define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2)
+ %4 = add <2 x i64> %3, %3
+ store <2 x i64> %4, <2 x i64>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_f128:
+declare <4 x float> @test_v4f32_f128_helper(fp128 %p)
+define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_v2f64:
+declare <4 x float> @test_v4f32_v2f64_helper(<2 x double> %p)
+define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_v2i64:
+declare <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %p)
+define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_v4i32:
+declare <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %p)
+define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_v8i16:
+declare <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %p)
+define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4f32_v16i8:
+declare <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %p)
+define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2)
+ %4 = fadd <4 x float> %3, %3
+ store <4 x float> %4, <4 x float>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_f128:
+declare <4 x i32> @test_v4i32_f128_helper(fp128 %p)
+define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_v2f64:
+declare <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %p)
+define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_v2i64:
+declare <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %p)
+define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_v4f32:
+declare <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %p)
+define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_v8i16:
+declare <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %p)
+define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v4i32_v16i8:
+declare <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %p)
+define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2)
+ %4 = add <4 x i32> %3, %3
+ store <4 x i32> %4, <4 x i32>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_f128:
+declare <8 x i16> @test_v8i16_f128_helper(fp128 %p)
+define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_v2f64:
+declare <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %p)
+define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_v2i64:
+declare <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %p)
+define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_v4f32:
+declare <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %p)
+define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_v4i32:
+declare <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %p)
+define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v8i16_v16i8:
+declare <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %p)
+define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+ %1 = load <16 x i8>* %p
+ %2 = add <16 x i8> %1, %1
+ %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2)
+ %4 = add <8 x i16> %3, %3
+ store <8 x i16> %4, <8 x i16>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_f128:
+declare <16 x i8> @test_v16i8_f128_helper(fp128 %p)
+define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load fp128* %p
+ %2 = fadd fp128 %1, %1
+ %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_v2f64:
+declare <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %p)
+define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <2 x double>* %p
+ %2 = fadd <2 x double> %1, %1
+ %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_v2i64:
+declare <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %p)
+define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) {
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <2 x i64>* %p
+ %2 = add <2 x i64> %1, %1
+ %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_v4f32:
+declare <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %p)
+define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <4 x float>* %p
+ %2 = fadd <4 x float> %1, %1
+ %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_v4i32:
+declare <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %p)
+define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.4s
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <4 x i32>* %p
+ %2 = add <4 x i32> %1, %1
+ %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
+
+; CHECK-LABEL: test_v16i8_v8i16:
+declare <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %p)
+define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) {
+; CHECK: rev64 v{{[0-9]+}}.8h
+; CHECK: ext
+; CHECK: rev64 v{{[0-9]+}}.16b
+; CHECK: ext
+ %1 = load <8 x i16>* %p
+ %2 = add <8 x i16> %1, %1
+ %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2)
+ %4 = add <16 x i8> %3, %3
+ store <16 x i8> %4, <16 x i8>* %q
+ ret void
+}
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