[llvm] r208179 - [mips] Move HasStdEnc to the front of the predicates lists.
Daniel Sanders
daniel.sanders at imgtec.com
Wed May 7 02:58:06 PDT 2014
Author: dsanders
Date: Wed May 7 04:58:05 2014
New Revision: 208179
URL: http://llvm.org/viewvc/llvm-project?rev=208179&view=rev
Log:
[mips] Move HasStdEnc to the front of the predicates lists.
Summary:
This will make it easier to prove that a more complicated change in the
following commit is non-functional.
No functional change.
Depends on D3506
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3549
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsCondMov.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=208179&r1=208178&r2=208179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Wed May 7 04:58:05 2014
@@ -95,7 +95,7 @@ def FNEG_MM : MMRel, ABSS_FT<"neg.d", AF
ABS_FM_MM<1, 0x2d>;
def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
- ABS_FM_MM<1, 0x1>, Requires<[NotFP64bit, HasStdEnc]>;
+ ABS_FM_MM<1, 0x1>, Requires<[HasStdEnc, NotFP64bit]>;
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>;
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=208179&r1=208178&r2=208179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed May 7 04:58:05 2014
@@ -118,7 +118,7 @@ def DSRA32 : shift_rotate_imm<"dsra32",
SRA_FM<0x3f, 0>;
// Rotate Instructions
-let Predicates = [HasMips64r2, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips64r2] in {
def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
immZExt6>, SRA_FM<0x3a, 1>;
def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=208179&r1=208178&r2=208179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Wed May 7 04:58:05 2014
@@ -132,23 +132,23 @@ def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.
let isCodeGenOnly = 1 in
def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
- CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>;
+ CMov_I_F_FM<18, 16>, Requires<[HasStdEnc, HasMips64]>;
def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
CMov_I_F_FM<19, 16>;
let isCodeGenOnly = 1 in
def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
- CMov_I_F_FM<19, 16>, Requires<[IsGP64bit, HasStdEnc]>;
+ CMov_I_F_FM<19, 16>, Requires<[HasStdEnc, IsGP64bit]>;
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM<18, 17>;
def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM<19, 17>;
}
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>;
def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
@@ -166,28 +166,28 @@ def MOVT_I : MMRel, CMov_F_I_FT<"movt",
let isCodeGenOnly = 1 in
def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
- CMov_F_I_FM<1>, Requires<[IsGP64bit, HasStdEnc]>;
+ CMov_F_I_FM<1>, Requires<[HasStdEnc, IsGP64bit]>;
def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>;
let isCodeGenOnly = 1 in
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
- CMov_F_I_FM<0>, Requires<[IsGP64bit, HasStdEnc]>;
+ CMov_F_I_FM<0>, Requires<[HasStdEnc, IsGP64bit]>;
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
CMov_F_F_FM<16, 1>;
def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
CMov_F_F_FM<16, 0>;
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
}
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>;
def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
@@ -198,7 +198,7 @@ let Predicates = [IsFP64bit, HasStdEnc],
defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
-let Predicates = [IsGP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, IsGP64bit] in {
defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
SLTiu64>;
@@ -213,7 +213,7 @@ let Predicates = [IsGP64bit, HasStdEnc]
}
defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
-let Predicates = [IsGP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, IsGP64bit] in {
defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
@@ -222,19 +222,19 @@ let Predicates = [IsGP64bit, HasStdEnc]
defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
-let Predicates = [IsGP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, IsGP64bit] in {
defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
SLTiu64>;
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
}
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
}
-let Predicates = [IsFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, IsFP64bit] in {
defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
SLTiu64>;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=208179&r1=208178&r2=208179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Wed May 7 04:58:05 2014
@@ -100,10 +100,10 @@ class ADDS_FT<string opstr, RegisterOper
multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
SDPatternOperator OpNode = null_frag> {
def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin,
IsComm, OpNode>,
- Requires<[IsFP64bit, HasStdEnc]> {
+ Requires<[HasStdEnc, IsFP64bit]> {
string DecoderNamespace = "Mips64";
}
}
@@ -117,18 +117,18 @@ class ABSS_FT<string opstr, RegisterOper
multiclass ABSS_M<string opstr, InstrItinClass Itin,
SDPatternOperator OpNode= null_frag> {
def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
- Requires<[IsFP64bit, HasStdEnc]> {
+ Requires<[HasStdEnc, IsFP64bit]> {
string DecoderNamespace = "Mips64";
}
}
multiclass ROUND_M<string opstr, InstrItinClass Itin> {
def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
def _D64 : ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>,
- Requires<[IsFP64bit, HasStdEnc]> {
+ Requires<[HasStdEnc, IsFP64bit]> {
let DecoderNamespace = "Mips64";
}
}
@@ -241,10 +241,10 @@ multiclass C_COND_M<string TypeStr, Regi
defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>;
defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
let DecoderNamespace = "Mips64" in
defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>,
- Requires<[IsFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, IsFP64bit]>;
//===----------------------------------------------------------------------===//
// Floating Point Instructions
@@ -266,7 +266,7 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CE
defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>;
defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0x8, 16>;
def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
@@ -292,7 +292,7 @@ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s",
def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x25, 17>;
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>;
def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
@@ -301,7 +301,7 @@ let Predicates = [NotFP64bit, HasStdEnc]
ABSS_FM<0x21, 16>;
}
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
ABSS_FM<0x20, 17>;
def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
@@ -357,9 +357,9 @@ def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd,
def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABSS_FM<0x6, 16>;
def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
- ABSS_FM<0x6, 17>, Requires<[NotFP64bit, HasStdEnc]>;
+ ABSS_FM<0x6, 17>, Requires<[HasStdEnc, NotFP64bit]>;
def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
- ABSS_FM<0x6, 17>, Requires<[IsFP64bit, HasStdEnc]> {
+ ABSS_FM<0x6, 17>, Requires<[HasStdEnc, IsFP64bit]> {
let DecoderNamespace = "Mips64";
}
@@ -367,12 +367,12 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opn
def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in {
def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
}
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
}
@@ -386,30 +386,30 @@ def SDC2 : SW_FT<"sdc2", COP2Opnd, NoIti
// Indexed loads and stores.
// Base register + offset register addressing mode (indicated by "x" in the
// instruction mnemonic) is disallowed under NaCl.
-let Predicates = [HasFPIdx, HasStdEnc, IsNotNaCl] in {
+let Predicates = [HasStdEnc, IsNotNaCl, HasFPIdx] in {
def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
}
-let Predicates = [HasFPIdx, NotFP64bit, HasStdEnc, NotInMicroMips,
+let Predicates = [HasStdEnc, HasFPIdx, NotFP64bit, NotInMicroMips,
IsNotNaCl] in {
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
}
-let Predicates = [HasFPIdx, IsFP64bit, HasStdEnc],
+let Predicates = [HasStdEnc, HasFPIdx, IsFP64bit],
DecoderNamespace="Mips64" in {
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
}
// Load/store doubleword indexed unaligned.
-let Predicates = [NotFP64bit, HasStdEnc, IsNotNaCl] in {
+let Predicates = [HasStdEnc, NotFP64bit, IsNotNaCl] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
}
-let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace="Mips64" in {
+let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace="Mips64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
}
@@ -428,42 +428,42 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR
ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
-let Predicates = [HasMips32r2, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips32r2] in {
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>;
}
-let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips32r2, NoNaNsFPMath] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>;
}
-let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit] in {
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
}
-let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>;
}
-let Predicates = [HasMips32r2, IsFP64bit, HasStdEnc], isCodeGenOnly=1 in {
+let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>;
}
-let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStdEnc],
+let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit, NoNaNsFPMath],
isCodeGenOnly=1 in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>;
@@ -509,10 +509,10 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
/// Floating Point Compare
def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>;
def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
let DecoderNamespace = "Mips64" in
def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
- Requires<[IsFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, IsFP64bit]>;
//===----------------------------------------------------------------------===//
// Floating Point Pseudo-Instructions
@@ -525,9 +525,9 @@ class BuildPairF64Base<RegisterOperand R
[(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>,
- Requires<[IsFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, IsFP64bit]>;
// This pseudo instr gets expanded into 2 mfc1 instrs after register
// allocation.
@@ -538,9 +538,9 @@ class ExtractElementF64Base<RegisterOper
[(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>,
- Requires<[NotFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, NotFP64bit]>;
def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
- Requires<[IsFP64bit, HasStdEnc]>;
+ Requires<[HasStdEnc, IsFP64bit]>;
//===----------------------------------------------------------------------===//
// InstAliases.
@@ -559,7 +559,7 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
(TRUNC_W_S FGR32Opnd:$src)>;
-let Predicates = [NotFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotFP64bit] in {
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
(PseudoCVT_D32_W GPR32Opnd:$src)>;
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
@@ -570,7 +570,7 @@ let Predicates = [NotFP64bit, HasStdEnc]
(CVT_D32_S FGR32Opnd:$src)>;
}
-let Predicates = [IsFP64bit, HasStdEnc] in {
+let Predicates = [HasStdEnc, IsFP64bit] in {
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
@@ -599,12 +599,12 @@ let AddedComplexity = 40 in {
def : LoadRegImmPat<LWC1, f32, load>;
def : StoreRegImmPat<SWC1, f32>;
- let Predicates = [IsFP64bit, HasStdEnc] in {
+ let Predicates = [HasStdEnc, IsFP64bit] in {
def : LoadRegImmPat<LDC164, f64, load>;
def : StoreRegImmPat<SDC164, f64>;
}
- let Predicates = [NotFP64bit, HasStdEnc] in {
+ let Predicates = [HasStdEnc, NotFP64bit] in {
def : LoadRegImmPat<LDC1, f64, load>;
def : StoreRegImmPat<SDC1, f64>;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=208179&r1=208178&r2=208179&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed May 7 04:58:05 2014
@@ -601,7 +601,7 @@ class UncondBranch<Instruction BEQInst>
let isTerminator = 1;
let isBarrier = 1;
let hasDelaySlot = 1;
- let Predicates = [RelocPIC, HasStdEnc];
+ let Predicates = [HasStdEnc, RelocPIC];
let Defs = [AT];
}
@@ -791,26 +791,26 @@ class EffectiveAddress<string opstr, Reg
class CountLeading0<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
- Requires<[HasBitCount, HasStdEnc]>;
+ Requires<[HasStdEnc, HasBitCount]>;
class CountLeading1<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
- Requires<[HasBitCount, HasStdEnc]>;
+ Requires<[HasStdEnc, HasBitCount]>;
// Sign Extend in Register.
class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
InstrItinClass itin> :
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
[(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
- let Predicates = [HasSEInReg, HasStdEnc];
+ let Predicates = [HasStdEnc, HasSEInReg];
}
// Subword Swap
class SubwordSwap<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
NoItinerary, FrmR, opstr> {
- let Predicates = [HasSwap, HasStdEnc];
+ let Predicates = [HasStdEnc, HasSwap];
let neverHasSideEffects = 1;
}
@@ -826,7 +826,7 @@ class ExtBase<string opstr, RegisterOper
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
FrmR, opstr> {
- let Predicates = [HasMips32r2, HasStdEnc];
+ let Predicates = [HasStdEnc, HasMips32r2];
}
class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
@@ -835,7 +835,7 @@ class InsBase<string opstr, RegisterOper
!strconcat(opstr, " $rt, $rs, $pos, $size"),
[(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
NoItinerary, FrmR, opstr> {
- let Predicates = [HasMips32r2, HasStdEnc];
+ let Predicates = [HasStdEnc, HasMips32r2];
let Constraints = "$src = $rt";
}
@@ -1000,7 +1000,7 @@ def SRAV : MMRel, shift_rotate_reg<"srav
SRLV_FM<7, 0>;
// Rotate Instructions
-let Predicates = [HasMips32r2, HasStdEnc] in {
+let Predicates = [HasStdEnc, HasMips32r2] in {
def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>, SRA_FM<2, 1>;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
@@ -1064,7 +1064,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<
/// Jump and Branch Instructions
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
- Requires<[RelocStatic, HasStdEnc]>, IsBranch;
+ Requires<[HasStdEnc, RelocStatic]>, IsBranch;
def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
@@ -1079,7 +1079,7 @@ def BLTZ : MMRel, CBranchZero<"bltz",
def B : UncondBranch<BEQ>;
def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
-let Predicates = [NotInMicroMips, HasStdEnc] in {
+let Predicates = [HasStdEnc, NotInMicroMips] in {
def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
}
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