[PATCH] [ARM64/AArch64] Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend

[Tim Northover]

Hi Hao,

Thanks for working on this. I've got some comments, mostly extremely minor nits (I can't see anything actually wrong with the code).

I do agree about that repeated type checking. It's rather untidy, but it's in the style of the surrounding code so we can probably deal with that separately.

Cheers.

Tim.

================
Comment at: lib/Target/ARM64/ARM64ISelDAGToDAG.cpp:1068
@@ +1067,3 @@
+  SmallVector<SDValue, 6> Ops;
+//  Ops.push_back(N->getOperand(1)); // write back register
+  Ops.push_back(RegSeq);
----------------
Commented out code.

================
Comment at: lib/Target/ARM64/ARM64ISelDAGToDAG.cpp:1219
@@ +1218,3 @@
+  EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
+  switch (NumVecs) {
+  case 4: {
----------------
Wouldn't this be neater as a for loop?

    static unsigned QSubs[] = { ARM64::qsub0, ARM64::qsub1, ARM64::qsub2, ARM64::qsub3 };
    for (int i = 0; i < NumVecs; ++i) {
      SDValue NV = CurDAG->getTargetExtractSubReg(QSubs[i], dl, WideVT, SuperReg);
      if (Narrow)
        NV = NarrowVector(NV, *CurDAG);
      ReplaceUses(SDValue(N, i), NV);
    }

(Untested).

================
Comment at: lib/Target/ARM64/ARM64ISelLowering.cpp:7017-7019
@@ +7016,5 @@
+/// to merge base address updates.
+static SDValue CombineNEONPostLoadStore(SDNode *N,
+                                          TargetLowering::DAGCombinerInfo &DCI,
+                                          SelectionDAG &DAG) {
+  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
----------------
Functions usually start with a lower-case letter, and indentation is a bit wonky here.

http://reviews.llvm.org/D3605