[llvm] r207905 - [ELFYAML] Group ELF header falgs to target specific blocks. Handle flags

[Simon Atanasyan]

Author: atanasyan
Date: Sat May  3 06:39:50 2014
New Revision: 207905

URL: http://llvm.org/viewvc/llvm-project?rev=207905&view=rev
Log:
[ELFYAML] Group ELF header falgs to target specific blocks. Handle flags
which are corresponding to the current target read from the ELF file.

This fix cannot be tested until obj2yaml does not support ELF format.

Modified:
    llvm/trunk/lib/Object/ELFYAML.cpp

Modified: llvm/trunk/lib/Object/ELFYAML.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFYAML.cpp?rev=207905&r1=207904&r2=207905&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ELFYAML.cpp (original)
+++ llvm/trunk/lib/Object/ELFYAML.cpp Sat May  3 06:39:50 2014
@@ -243,43 +243,52 @@ void ScalarEnumerationTraits<ELFYAML::EL
 
 void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
                                                  ELFYAML::ELF_EF &Value) {
+  const auto *Object = static_cast<ELFYAML::Object *>(IO.getContext());
+  assert(Object && "The IO context is not initialized");
 #define BCase(X) IO.bitSetCase(Value, #X, ELF::X);
-  BCase(EF_ARM_SOFT_FLOAT)
-  BCase(EF_ARM_VFP_FLOAT)
-  BCase(EF_ARM_EABI_UNKNOWN)
-  BCase(EF_ARM_EABI_VER1)
-  BCase(EF_ARM_EABI_VER2)
-  BCase(EF_ARM_EABI_VER3)
-  BCase(EF_ARM_EABI_VER4)
-  BCase(EF_ARM_EABI_VER5)
-  BCase(EF_ARM_EABIMASK)
-  BCase(EF_MIPS_NOREORDER)
-  BCase(EF_MIPS_PIC)
-  BCase(EF_MIPS_CPIC)
-  BCase(EF_MIPS_ABI2)
-  BCase(EF_MIPS_32BITMODE)
-  BCase(EF_MIPS_ABI_O32)
-  BCase(EF_MIPS_MICROMIPS)
-  BCase(EF_MIPS_ARCH_ASE_M16)
-  BCase(EF_MIPS_ARCH_1)
-  BCase(EF_MIPS_ARCH_2)
-  BCase(EF_MIPS_ARCH_3)
-  BCase(EF_MIPS_ARCH_4)
-  BCase(EF_MIPS_ARCH_5)
-  BCase(EF_MIPS_ARCH_32)
-  BCase(EF_MIPS_ARCH_64)
-  BCase(EF_MIPS_ARCH_32R2)
-  BCase(EF_MIPS_ARCH_64R2)
-  BCase(EF_MIPS_ARCH)
-  BCase(EF_HEXAGON_MACH_V2)
-  BCase(EF_HEXAGON_MACH_V3)
-  BCase(EF_HEXAGON_MACH_V4)
-  BCase(EF_HEXAGON_MACH_V5)
-  BCase(EF_HEXAGON_ISA_MACH)
-  BCase(EF_HEXAGON_ISA_V2)
-  BCase(EF_HEXAGON_ISA_V3)
-  BCase(EF_HEXAGON_ISA_V4)
-  BCase(EF_HEXAGON_ISA_V5)
+  switch (Object->Header.Machine) {
+  case ELF::EM_ARM:
+    BCase(EF_ARM_SOFT_FLOAT)
+    BCase(EF_ARM_VFP_FLOAT)
+    BCase(EF_ARM_EABI_UNKNOWN)
+    BCase(EF_ARM_EABI_VER1)
+    BCase(EF_ARM_EABI_VER2)
+    BCase(EF_ARM_EABI_VER3)
+    BCase(EF_ARM_EABI_VER4)
+    BCase(EF_ARM_EABI_VER5)
+    break;
+  case ELF::EM_MIPS:
+    BCase(EF_MIPS_NOREORDER)
+    BCase(EF_MIPS_PIC)
+    BCase(EF_MIPS_CPIC)
+    BCase(EF_MIPS_ABI2)
+    BCase(EF_MIPS_32BITMODE)
+    BCase(EF_MIPS_ABI_O32)
+    BCase(EF_MIPS_MICROMIPS)
+    BCase(EF_MIPS_ARCH_ASE_M16)
+    BCase(EF_MIPS_ARCH_1)
+    BCase(EF_MIPS_ARCH_2)
+    BCase(EF_MIPS_ARCH_3)
+    BCase(EF_MIPS_ARCH_4)
+    BCase(EF_MIPS_ARCH_5)
+    BCase(EF_MIPS_ARCH_32)
+    BCase(EF_MIPS_ARCH_64)
+    BCase(EF_MIPS_ARCH_32R2)
+    BCase(EF_MIPS_ARCH_64R2)
+    break;
+  case ELF::EM_HEXAGON:
+    BCase(EF_HEXAGON_MACH_V2)
+    BCase(EF_HEXAGON_MACH_V3)
+    BCase(EF_HEXAGON_MACH_V4)
+    BCase(EF_HEXAGON_MACH_V5)
+    BCase(EF_HEXAGON_ISA_V2)
+    BCase(EF_HEXAGON_ISA_V3)
+    BCase(EF_HEXAGON_ISA_V4)
+    BCase(EF_HEXAGON_ISA_V5)
+    break;
+  default:
+    llvm_unreachable("Unsupported architecture");
+  }
 #undef BCase
 }