The attached patch provides custom lowering of overflow intrinsics for the ARM architecture. This greatly improves the codeine when those intrinsics are present. For example, the following function:
define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
%sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
%1 = extractvalue { i32, i1 } %sadd, 1
%2 = zext i1 %1 to i32
ret i32 %2
}
Currently compiles to this:
_sadd_overflow: @ @sadd_overflow
@ BB#0:
cmp r1, #0
mov r3, #0
mov r2, #0
mov r12, #0
movge r3, #1
cmp r0, #0
add r0, r0, r1
movge r2, #1
cmp r2, r3
mov r3, #0
moveq r3, #1
cmp r0, #0
mov r0, #0
movge r0, #1
cmp r2, r0
movne r12, #1
and r0, r3, r12
mov pc, lr
with the patch it compiles to this:
_sadd_overflow: @ @sadd_overflow
@ BB#0:
add r2, r0, r1
mov r1, #1
cmp r2, r0
movvc r1, #0
mov r0, r1
mov pc, lr
Louis
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