[llvm] r207616 - Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.
David Blaikie
dblaikie at gmail.com
Wed Apr 30 10:31:44 PDT 2014
On Wed, Apr 30, 2014 at 12:17 AM, Craig Topper <craig.topper at gmail.com> wrote:
> Author: ctopper
> Date: Wed Apr 30 02:17:30 2014
> New Revision: 207616
>
> URL: http://llvm.org/viewvc/llvm-project?rev=207616&view=rev
> Log:
> Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introduced most of these recently.
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Apr 30 02:17:30 2014
> @@ -1563,7 +1563,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS
>
> if (N->getOpcode() == ISD::ADD) {
> Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
> - Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
> + Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
> SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
> ISD::SETULT);
> SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
> @@ -1576,7 +1576,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS
> Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
> } else {
> Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
> - Hi = DAG.getNode(ISD::SUB, dl, NVT, ArrayRef<SDValue>(HiOps, 2));
> + Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
> SDValue Cmp =
> DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
> LoOps[0], LoOps[1], ISD::SETULT);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Wed Apr 30 02:17:30 2014
> @@ -355,7 +355,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BITCA
> IntegerToVector(N->getOperand(0), NumElts, Ops, NVT.getVectorElementType());
>
> SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT,
> - ArrayRef<SDValue>(&Ops[0], NumElts));
> + makeArrayRef(Ops.data(), NumElts));
> return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), Vec);
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Apr 30 02:17:30 2014
> @@ -1745,7 +1745,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Bi
> ConcatOps[j] = UndefVal;
> }
> return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
> - ArrayRef<SDValue>(&ConcatOps[0], NumOps));
> + makeArrayRef(ConcatOps.data(), NumOps));
> }
>
> SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
> @@ -2724,8 +2724,7 @@ SDValue DAGTypeLegalizer::GenWidenVector
> if (NewLdTy != LdTy) {
> // Create a larger vector
> ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
> - ArrayRef<SDValue>(&ConcatOps[Idx],
> - End - Idx));
> + makeArrayRef(&ConcatOps[Idx], End - Idx));
> Idx = End - 1;
> LdTy = NewLdTy;
> }
> @@ -2734,7 +2733,7 @@ SDValue DAGTypeLegalizer::GenWidenVector
>
> if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
> return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
> - ArrayRef<SDValue>(&ConcatOps[Idx], End - Idx));
> + makeArrayRef(&ConcatOps[Idx], End - Idx));
>
> // We need to fill the rest with undefs to build the vector
> unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Apr 30 02:17:30 2014
> @@ -527,7 +527,7 @@ static void AddNodeIDNode(FoldingSetNode
> // Add the return value info.
> AddNodeIDValueTypes(ID, N->getVTList());
> // Add the operand info.
> - AddNodeIDOperands(ID, ArrayRef<SDUse>(N->op_begin(), N->op_end()));
> + AddNodeIDOperands(ID, makeArrayRef(N->op_begin(), N->op_end()));
We should probably have an "ops" that returns ArrayRef (ArrayRef being
the iterator_range for contiguous in-memory sequences - and handy for
other things).
> // Handle SDNode leafs with special info.
> AddNodeIDCustom(ID, N);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Apr 30 02:17:30 2014
> @@ -3480,7 +3480,7 @@ void SelectionDAGBuilder::visitLoad(cons
> if (ChainI == MaxParallelChains) {
> assert(PendingLoads.empty() && "PendingLoads must be serialized first");
> SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
> - ArrayRef<SDValue>(Chains.data(), ChainI));
> + makeArrayRef(Chains.data(), ChainI));
> Root = Chain;
> ChainI = 0;
> }
> @@ -3498,7 +3498,7 @@ void SelectionDAGBuilder::visitLoad(cons
>
> if (!ConstantMemory) {
> SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
> - ArrayRef<SDValue>(Chains.data(), ChainI));
> + makeArrayRef(Chains.data(), ChainI));
> if (isVolatile)
> DAG.setRoot(Chain);
> else
> @@ -3543,7 +3543,7 @@ void SelectionDAGBuilder::visitStore(con
> // See visitLoad comments.
> if (ChainI == MaxParallelChains) {
> SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
> - ArrayRef<SDValue>(Chains.data(), ChainI));
> + makeArrayRef(Chains.data(), ChainI));
> Root = Chain;
> ChainI = 0;
> }
> @@ -3557,7 +3557,7 @@ void SelectionDAGBuilder::visitStore(con
> }
>
> SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
> - ArrayRef<SDValue>(Chains.data(), ChainI));
> + makeArrayRef(Chains.data(), ChainI));
> DAG.setRoot(StoreNode);
> }
>
> @@ -7496,8 +7496,7 @@ void SelectionDAGISel::LowerArguments(co
> dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
> FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
>
> - SDValue Res = DAG.getMergeValues(ArrayRef<SDValue>(ArgValues.data(),
> - NumValues),
> + SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
> SDB->getCurSDLoc());
>
> SDB->setValue(I, Res);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp Wed Apr 30 02:17:30 2014
> @@ -73,7 +73,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMe
> SrcOff += VTSize;
> }
> Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
> - ArrayRef<SDValue>(TFOps, i));
> + makeArrayRef(TFOps, i));
>
> for (i = 0;
> i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
> @@ -85,7 +85,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMe
> DstOff += VTSize;
> }
> Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
> - ArrayRef<SDValue>(TFOps, i));
> + makeArrayRef(TFOps, i));
>
> EmittedNumMemOps += i;
> }
> @@ -116,7 +116,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMe
> BytesLeft -= VTSize;
> }
> Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
> - ArrayRef<SDValue>(TFOps, i));
> + makeArrayRef(TFOps, i));
>
> i = 0;
> BytesLeft = BytesLeftSave;
> @@ -138,7 +138,7 @@ ARMSelectionDAGInfo::EmitTargetCodeForMe
> BytesLeft -= VTSize;
> }
> return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
> - ArrayRef<SDValue>(TFOps, i));
> + makeArrayRef(TFOps, i));
> }
>
> // Adjust parameters for memset, EABI uses format (ptr, size, value),
>
> Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -4358,7 +4358,7 @@ static SDValue GenerateTBL(SDValue Op, A
> ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
> DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
> DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
> - ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
> + makeArrayRef(TBLMask.data(), IndexLen)));
> } else {
> if (IndexLen == 8) {
> V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
> @@ -4366,7 +4366,7 @@ static SDValue GenerateTBL(SDValue Op, A
> ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
> DAG.getConstant(Intrinsic::arm64_neon_tbl1, MVT::i32), V1Cst,
> DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
> - ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
> + makeArrayRef(TBLMask.data(), IndexLen)));
> } else {
> // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
> // cannot currently represent the register constraints on the input
> @@ -4378,7 +4378,7 @@ static SDValue GenerateTBL(SDValue Op, A
> ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
> DAG.getConstant(Intrinsic::arm64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
> DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
> - ArrayRef<SDValue>(TBLMask.data(), IndexLen)));
> + makeArrayRef(TBLMask.data(), IndexLen)));
> }
> }
> return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -489,7 +489,7 @@ static SDValue performANDCombine(SDNode
> SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
> DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT,
> Op0->getVTList(),
> - ArrayRef<SDValue>(Ops, Op0->getNumOperands()));
> + makeArrayRef(Ops, Op0->getNumOperands()));
Any idea what getNumOperands returns? Can it really return various
values <= 3? (can't be more than 3, since Ops only has 3 things). If
it's always 3, then you can just drop the makeArrayRef call entirely
and rely on the implicit conversion from array to ArrayRef.
(similar comment for the next 3 changes \/)
> return Op0;
> }
> }
> @@ -834,7 +834,7 @@ static SDValue performSRACombine(SDNode
> Op0Op0->getOperand(2) };
> DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT,
> Op0Op0->getVTList(),
> - ArrayRef<SDValue>(Ops, Op0Op0->getNumOperands()));
> + makeArrayRef(Ops, Op0Op0->getNumOperands()));
> return Op0Op0;
> }
> }
> @@ -1284,7 +1284,7 @@ static SDValue lowerMSASplatZExt(SDValue
> LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
>
> SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
> - ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
> + makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
>
> if (ViaVecTy != ResVecTy)
> Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
> @@ -1324,7 +1324,7 @@ static SDValue getBuildVectorSplat(EVT V
> SplatValueA, SplatValueB, SplatValueA, SplatValueB };
>
> SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy,
> - ArrayRef<SDValue>(Ops, ViaVecTy.getVectorNumElements()));
> + makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
>
> if (VecTy != ViaVecTy)
> Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp Wed Apr 30 02:17:30 2014
> @@ -1084,8 +1084,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUV
> }
>
> SDValue Ops[] = { Addr, Chain };
> - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
> - ArrayRef<SDValue>(Ops, 2));
> + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
> } else if (Subtarget.is64Bit()
> ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset)
> : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) {
> @@ -1271,8 +1270,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUV
>
> SDValue Ops[] = { Base, Offset, Chain };
>
> - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
> - ArrayRef<SDValue>(Ops, 3));
> + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
> } else {
> if (Subtarget.is64Bit()) {
> switch (N->getOpcode()) {
> @@ -1455,8 +1453,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDUV
> }
>
> SDValue Ops[] = { Op1, Chain };
> - LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(),
> - ArrayRef<SDValue>(Ops, 2));
> + LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops);
> }
>
> MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -3474,7 +3474,7 @@ unsigned PrepareCall(SelectionDAG &DAG,
> // descriptor.
> SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
> SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
> - ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
> + makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
> Chain = LoadFuncPtr.getValue(1);
> InFlag = LoadFuncPtr.getValue(2);
>
> @@ -3511,7 +3511,7 @@ unsigned PrepareCall(SelectionDAG &DAG,
> }
>
> Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
> - ArrayRef<SDValue>(MTCTROps, InFlag.getNode() ? 3 : 2));
> + makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
> InFlag = Chain.getValue(1);
>
> NodeTys.clear();
> @@ -3940,8 +3940,7 @@ PPCTargetLowering::LowerCall_32SVR4(SDVa
> SDValue Ops[] = { Chain, InFlag };
>
> Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
> - dl, VTs,
> - ArrayRef<SDValue>(Ops, InFlag.getNode() ? 2 : 1));
> + dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
>
> InFlag = Chain.getValue(1);
> }
> @@ -5282,7 +5281,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUN
> MVT::f64, // return register
> MVT::Glue // unused in this context
> };
> - SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, ArrayRef<SDValue>());
> + SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
>
> // Save FP register to stack slot
> int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
>
> Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -1280,7 +1280,7 @@ SDValue R600TargetLowering::LowerLOAD(SD
> NumElements = VT.getVectorNumElements();
> }
> Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT,
> - ArrayRef<SDValue>(Slots, NumElements));
> + makeArrayRef(Slots, NumElements));
> } else {
> // non-constant ptr can't be folded, keeps it as a v4f32 load
> Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
>
> Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -772,8 +772,8 @@ LowerFormalArguments(SDValue Chain, Call
> }
> // Join the stores, which are independent of one another.
> Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
> - ArrayRef<SDValue>(&MemOps[NumFixedFPRs],
> - SystemZ::NumArgFPRs-NumFixedFPRs));
> + makeArrayRef(&MemOps[NumFixedFPRs],
> + SystemZ::NumArgFPRs-NumFixedFPRs));
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=207616&r1=207615&r2=207616&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Apr 30 02:17:30 2014
> @@ -85,8 +85,8 @@ static SDValue ExtractSubVector(SDValue
> // If the input is a buildvector just emit a smaller one.
> if (Vec.getOpcode() == ISD::BUILD_VECTOR)
> return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
> - ArrayRef<SDUse>(Vec->op_begin()+NormalizedIdxVal,
> - ElemsPerChunk));
> + makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
> + ElemsPerChunk));
>
> SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
> SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
> @@ -6140,10 +6140,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV
>
> // Build both the lower and upper subvector.
> SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
> - ArrayRef<SDValue>(&V[0], NumElems/2));
> + makeArrayRef(&V[0], NumElems/2));
> SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
> - ArrayRef<SDValue>(&V[NumElems / 2],
> - NumElems/2));
> + makeArrayRef(&V[NumElems / 2], NumElems/2));
>
> // Recreate the wider vector with the lower and upper part.
> if (VT.is256BitVector())
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list