[llvm] r207628 - [ARM64] Simplify if condition.

[James Molloy]

Author: jamesm
Date: Wed Apr 30 05:15:50 2014
New Revision: 207628

URL: http://llvm.org/viewvc/llvm-project?rev=207628&view=rev
Log:
[ARM64] Simplify if condition.

v2f32 and v4f32 were missed out of these conditions, so this is also
a bugfix.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=207628&r1=207627&r2=207628&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Wed Apr 30 05:15:50 2014
@@ -1678,13 +1678,9 @@ SDValue ARM64TargetLowering::LowerFormal
         RC = &ARM64::GPR64RegClass;
       else if (RegVT == MVT::f32)
         RC = &ARM64::FPR32RegClass;
-      else if (RegVT == MVT::f64 || RegVT == MVT::v1i64 ||
-               RegVT == MVT::v1f64 || RegVT == MVT::v2i32 ||
-               RegVT == MVT::v4i16 || RegVT == MVT::v8i8)
+      else if (RegVT == MVT::f64 || RegVT.is64BitVector())
         RC = &ARM64::FPR64RegClass;
-      else if (RegVT == MVT::f128 ||RegVT == MVT::v2i64 ||
-               RegVT == MVT::v4i32||RegVT == MVT::v8i16 ||
-               RegVT == MVT::v16i8)
+      else if (RegVT == MVT::f128 || RegVT.is128BitVector())
         RC = &ARM64::FPR128RegClass;
       else
         llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");