[llvm] r207591 - R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
Tom Stellard
thomas.stellard at amd.com
Tue Apr 29 16:12:53 PDT 2014
Author: tstellar
Date: Tue Apr 29 18:12:53 2014
New Revision: 207591
URL: http://llvm.org/viewvc/llvm-project?rev=207591&view=rev
Log:
R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errors
SI_IF and SI_ELSE are terminators which also produce a value. For
these instructions ISel always inserts a COPY to move their value
to another basic block. This COPY ends up between SI_(IF|ELSE)
and the S_BRANCH* instruction at the end of the block.
This breaks MachineBasicBlock::getFirstTerminator() and also the
machine verifier which assumes that terminators are grouped together at
the end of blocks.
To solve this we coalesce the copy away right after ISel to make sure
there are no instructions in between terminators at the end of blocks.
Modified:
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/lib/Target/R600/SIInstructions.td
llvm/trunk/test/CodeGen/R600/add_i64.ll
llvm/trunk/test/CodeGen/R600/address-space.ll
llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll
llvm/trunk/test/CodeGen/R600/call.ll
llvm/trunk/test/CodeGen/R600/extload.ll
llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll
llvm/trunk/test/CodeGen/R600/gep-address-space.ll
llvm/trunk/test/CodeGen/R600/insert_vector_elt_f64.ll
llvm/trunk/test/CodeGen/R600/llvm.sqrt.ll
llvm/trunk/test/CodeGen/R600/load-i1.ll
llvm/trunk/test/CodeGen/R600/local-64.ll
llvm/trunk/test/CodeGen/R600/loop-idiom.ll
llvm/trunk/test/CodeGen/R600/register-count-comments.ll
llvm/trunk/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
llvm/trunk/test/CodeGen/R600/setcc.ll
llvm/trunk/test/CodeGen/R600/setcc64.ll
llvm/trunk/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
llvm/trunk/test/CodeGen/R600/sgpr-copy.ll
llvm/trunk/test/CodeGen/R600/si-annotate-cf-assertion.ll
llvm/trunk/test/CodeGen/R600/store-v3i64.ll
llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll
llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll
llvm/trunk/test/CodeGen/R600/uaddo.ll
llvm/trunk/test/CodeGen/R600/udivrem64.ll
llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Tue Apr 29 18:12:53 2014
@@ -444,19 +444,48 @@ SDValue SITargetLowering::LowerFormalArg
return Chain;
}
+/// Usually ISel will insert a copy between terminator insturction that output
+/// a value and the S_BRANCH* at the end of the block. This causes
+/// MachineBasicBlock::getFirstTerminator() to return the incorrect value,
+/// so we want to make sure there are no copies between terminators at the
+/// end of blocks.
+static void LowerTerminatorWithOutput(unsigned Opcode, MachineBasicBlock *BB,
+ MachineInstr *MI,
+ const TargetInstrInfo *TII,
+ MachineRegisterInfo &MRI) {
+ unsigned DstReg = MI->getOperand(0).getReg();
+ // Usually ISel will insert a copy between the SI_IF_NON_TERM instruction
+ // and the S_BRANCH* terminator. We want to replace SI_IF_NO_TERM with
+ // SI_IF and we can't have any instructions between S_BRANCH* and SI_IF,
+ // since they are both terminators
+ assert(MRI.hasOneUse(DstReg));
+ MachineOperand &Use = *MRI.use_begin(DstReg);
+ MachineInstr *UseMI = Use.getParent();
+ assert(UseMI->getOpcode() == AMDGPU::COPY);
+
+ MRI.replaceRegWith(UseMI->getOperand(0).getReg(), DstReg);
+ UseMI->eraseFromParent();
+ BuildMI(*BB, BB->getFirstTerminator(), MI->getDebugLoc(),
+ TII->get(Opcode))
+ .addOperand(MI->getOperand(0))
+ .addOperand(MI->getOperand(1))
+ .addOperand(MI->getOperand(2));
+ MI->eraseFromParent();
+}
+
MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineInstr * MI, MachineBasicBlock * BB) const {
MachineBasicBlock::iterator I = *MI;
+ const SIInstrInfo *TII =
+ static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
switch (MI->getOpcode()) {
default:
return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
case AMDGPU::BRANCH: return BB;
case AMDGPU::SI_ADDR64_RSRC: {
- const SIInstrInfo *TII =
- static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
- MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned SuperReg = MI->getOperand(0).getReg();
unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
@@ -481,9 +510,13 @@ MachineBasicBlock * SITargetLowering::Em
MI->eraseFromParent();
break;
}
- case AMDGPU::V_SUB_F64: {
- const SIInstrInfo *TII =
- static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
+ case AMDGPU::SI_IF_NON_TERM:
+ LowerTerminatorWithOutput(AMDGPU::SI_IF, BB, MI, TII, MRI);
+ break;
+ case AMDGPU::SI_ELSE_NON_TERM:
+ LowerTerminatorWithOutput(AMDGPU::SI_ELSE, BB, MI, TII, MRI);
+ break;
+ case AMDGPU::V_SUB_F64:
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
@@ -495,11 +528,9 @@ MachineBasicBlock * SITargetLowering::Em
.addImm(2); /* NEG */
MI->eraseFromParent();
break;
- }
+
case AMDGPU::SI_RegisterStorePseudo: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
- const SIInstrInfo *TII =
- static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
MachineInstrBuilder MIB =
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Tue Apr 29 18:12:53 2014
@@ -1411,21 +1411,38 @@ def LOAD_CONST : AMDGPUShaderInst <
let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
Uses = [EXEC], Defs = [EXEC] in {
+let usesCustomInserter = 1 in {
+
+def SI_IF_NON_TERM : InstSI <
+ (outs SReg_64:$dst),
+ (ins SReg_64:$vcc, brtarget:$target), "",
+ [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
+>;
+
+def SI_ELSE_NON_TERM : InstSI <
+ (outs SReg_64:$dst),
+ (ins SReg_64:$src, brtarget:$target),
+ "",
+ [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
+> {
+ let Constraints = "$src = $dst";
+}
+
+} // usesCustomInserter = 1
+
let isBranch = 1, isTerminator = 1 in {
-def SI_IF : InstSI <
+def SI_IF: InstSI <
(outs SReg_64:$dst),
(ins SReg_64:$vcc, brtarget:$target),
- "SI_IF $dst, $vcc, $target",
- [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
+ "", []
>;
def SI_ELSE : InstSI <
(outs SReg_64:$dst),
(ins SReg_64:$src, brtarget:$target),
- "SI_ELSE $dst, $src, $target",
- [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> {
-
+ "", []
+> {
let Constraints = "$src = $dst";
}
Modified: llvm/trunk/test/CodeGen/R600/add_i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/add_i64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/add_i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/add_i64.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.r600.read.tidig.x() readnone
Modified: llvm/trunk/test/CodeGen/R600/address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/address-space.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/address-space.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
; Test that codegenprepare understands address space sizes
Modified: llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/array-ptr-calc-i64.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
; XFAIL: *
-; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI %s
declare i32 @llvm.SI.tid() readnone
Modified: llvm/trunk/test/CodeGen/R600/call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/call.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/call.ll (original)
+++ llvm/trunk/test/CodeGen/R600/call.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: not llc -march=r600 -mcpu=SI < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=r600 -mcpu=SI -verify-machineinstrs< %s 2>&1 | FileCheck %s
; RUN: not llc -march=r600 -mcpu=cypress < %s 2>&1 | FileCheck %s
; CHECK: error: unsupported call to function defined_function in test_call
Modified: llvm/trunk/test/CodeGen/R600/extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extload.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extload.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extload.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: @anyext_load_i8:
; EG: AND_INT
Modified: llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extract_vector_elt_i16.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: @extract_vector_elt_v2i16
; SI: BUFFER_LOAD_USHORT
Modified: llvm/trunk/test/CodeGen/R600/gep-address-space.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/gep-address-space.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/gep-address-space.ll (original)
+++ llvm/trunk/test/CodeGen/R600/gep-address-space.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s
define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
; CHECK-LABEL: @use_gep_address_space:
Modified: llvm/trunk/test/CodeGen/R600/insert_vector_elt_f64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/insert_vector_elt_f64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/insert_vector_elt_f64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/insert_vector_elt_f64.ll Tue Apr 29 18:12:53 2014
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @dynamic_insertelement_v2f64:
Modified: llvm/trunk/test/CodeGen/R600/llvm.sqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.sqrt.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/llvm.sqrt.ll (original)
+++ llvm/trunk/test/CodeGen/R600/llvm.sqrt.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
-; RUN: llc < %s -march=r600 --mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+; RUN: llc < %s -march=r600 --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK-LABEL: @sqrt_f32
; R600-CHECK: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z
Modified: llvm/trunk/test/CodeGen/R600/load-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/load-i1.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/load-i1.ll (original)
+++ llvm/trunk/test/CodeGen/R600/load-i1.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @global_copy_i1_to_i1
Modified: llvm/trunk/test/CodeGen/R600/local-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/local-64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/local-64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/local-64.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @local_i32_load
; SI: DS_READ_B32 [[REG:v[0-9]+]], v{{[0-9]+}}, 0x1c, [M0]
Modified: llvm/trunk/test/CodeGen/R600/loop-idiom.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/loop-idiom.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/loop-idiom.ll (original)
+++ llvm/trunk/test/CodeGen/R600/loop-idiom.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
-; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+; RUN: opt -basicaa -loop-idiom -S < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "r600--"
Modified: llvm/trunk/test/CodeGen/R600/register-count-comments.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/register-count-comments.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/register-count-comments.ll (original)
+++ llvm/trunk/test/CodeGen/R600/register-count-comments.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.SI.tid() nounwind readnone
Modified: llvm/trunk/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll (original)
+++ llvm/trunk/test/CodeGen/R600/schedule-vs-if-nested-loop-failure.ll Tue Apr 29 18:12:53 2014
@@ -1,6 +1,6 @@
; XFAIL: *
; REQUIRES: asserts
-; RUN: llc -O0 -march=r600 -mcpu=SI < %s | FileCheck %s -check-prefix=SI
+; RUN: llc -O0 -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI
declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
Modified: llvm/trunk/test/CodeGen/R600/setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/setcc.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/setcc.ll (original)
+++ llvm/trunk/test/CodeGen/R600/setcc.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
; FUNC-LABEL: @setcc_v2i32
; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
Modified: llvm/trunk/test/CodeGen/R600/setcc64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/setcc64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/setcc64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/setcc64.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
; XXX: Merge this into setcc, once R600 supports 64-bit operations
Modified: llvm/trunk/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll (original)
+++ llvm/trunk/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; Copy VGPR -> SGPR used twice as an instruction operand, which is then
; used in an REG_SEQUENCE that also needs to be handled.
Modified: llvm/trunk/test/CodeGen/R600/sgpr-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/sgpr-copy.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/sgpr-copy.ll (original)
+++ llvm/trunk/test/CodeGen/R600/sgpr-copy.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
; This test checks that no VGPR to SGPR copies are created by the register
; allocator.
Modified: llvm/trunk/test/CodeGen/R600/si-annotate-cf-assertion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/si-annotate-cf-assertion.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/si-annotate-cf-assertion.ll (original)
+++ llvm/trunk/test/CodeGen/R600/si-annotate-cf-assertion.ll Tue Apr 29 18:12:53 2014
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s
define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind {
Modified: llvm/trunk/test/CodeGen/R600/store-v3i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store-v3i64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store-v3i64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store-v3i64.ll Tue Apr 29 18:12:53 2014
@@ -1,5 +1,5 @@
; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI
; SI-LABEL: @global_store_v3i64:
; SI: BUFFER_STORE_DWORDX4
Modified: llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll (original)
+++ llvm/trunk/test/CodeGen/R600/store-vector-ptrs.ll Tue Apr 29 18:12:53 2014
@@ -1,6 +1,6 @@
; REQUIRES: asserts
; XFAIL: *
-; RUN: llc -march=r600 -mcpu=SI < %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s
define void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind {
%p = getelementptr <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
Modified: llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll (original)
+++ llvm/trunk/test/CodeGen/R600/trunc-store-i1.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @global_truncstore_i32_to_i1
Modified: llvm/trunk/test/CodeGen/R600/uaddo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/uaddo.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/uaddo.ll (original)
+++ llvm/trunk/test/CodeGen/R600/uaddo.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
Modified: llvm/trunk/test/CodeGen/R600/udivrem64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/udivrem64.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/udivrem64.ll (original)
+++ llvm/trunk/test/CodeGen/R600/udivrem64.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-;XUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s
+;XUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs| FileCheck --check-prefix=SI --check-prefix=FUNC %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s
;FUNC-LABEL: @test_udiv
Modified: llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll?rev=207591&r1=207590&r2=207591&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll Tue Apr 29 18:12:53 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @unaligned_load_store_i32:
; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]]
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