[llvm] r206957 - [X86] Silvermont new scheduler model

[Hal Finkel]

----- Original Message -----
> From: "Alexey Volkov" <avolkov.intel at gmail.com>
> To: llvm-commits at cs.uiuc.edu
> Sent: Wednesday, April 23, 2014 3:57:10 AM
> Subject: [llvm] r206957 - [X86] Silvermont new scheduler model
> 
> Author: volkalex
> Date: Wed Apr 23 03:57:09 2014
> New Revision: 206957
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=206957&view=rev
> Log:
> [X86] Silvermont new scheduler model
> This model is not final and work is still in progress.
> However there are substantial improvements on integer tests mainly
> because of better RAL with new scheduler.
> 
> Differential Revision: http://reviews.llvm.org/D3451
> 
> Modified:
>     llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
> 
> Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=206957&r1=206956&r2=206957&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
> +++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Wed Apr 23 03:57:09
> 2014
> @@ -1,4 +1,4 @@

[snip]

> +// Scalar and vector floating point.
> +defm : SMWriteResPair<WriteFAdd,   FPC_RSV1, 3>;

[snip]

> -
> -  // SSE binary operations
> -  // arithmetic fp scalar
> -  InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<3, [FPC_RSV0,
> FPC_RSV1]>] >,

[snip]

Is this an intentional model change? It looks like previously floating-point addition could happen in both FPC_RSV0 or FPC_RSV1, but now it happens only in FPC_RSV1?

 -Hal

> 
> 
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-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory