[llvm] r207221 - ARM64: fix assertion in ISelDAGToDAG

[Tim Northover]

Author: tnorthover
Date: Fri Apr 25 05:48:47 2014
New Revision: 207221

URL: http://llvm.org/viewvc/llvm-project?rev=207221&view=rev
Log:
ARM64: fix assertion in ISelDAGToDAG

Also an unused variable, so double bonus!

This should deal with PR19548.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll

Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp?rev=207221&r1=207220&r2=207221&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp Fri Apr 25 05:48:47 2014
@@ -1403,8 +1403,6 @@ static bool isBitfieldDstMask(uint64_t D
   assert((VT == MVT::i32 || VT == MVT::i64) &&
          "i32 or i64 mask type expected!");
   unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
-  APInt SignificantBits =
-      ~APInt::getHighBitsSet(BitWidth, NumberOfIgnoredHighBits);
 
   APInt SignificantDstMask = APInt(BitWidth, DstMask);
   APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);

Modified: llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll?rev=207221&r1=207220&r2=207221&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/bitfield-extract.ll Fri Apr 25 05:48:47 2014
@@ -500,3 +500,20 @@ end:
   %conv3 = phi i80 [%conv, %entry], [%conv2, %then] 
   ret i80 %conv3
 }
+
+define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
+; CHECK-LABEL: test_ignored_rightbits:
+
+  %positioned_field = shl i32 %in, 3
+  %positioned_masked_field = and i32 %positioned_field, 120
+  %masked_dst = and i32 %dst, 7
+  %insertion = or i32 %masked_dst, %positioned_masked_field
+; CHECK: {{bfm|bfi}}
+
+  %shl16 = shl i32 %insertion, 8
+  %or18 = or i32 %shl16, %insertion
+  %conv19 = trunc i32 %or18 to i16
+; CHECK: {{bfm w[0-9]+, w[0-9]+, #24, #6|bfi w[0-9]+, w[0-9]+, #8, #7}}
+
+  ret i16 %conv19
+}