[llvm] r207101 - AArch64/ARM64: port more tests

[Tim Northover]

Author: tnorthover
Date: Thu Apr 24 07:11:46 2014
New Revision: 207101

URL: http://llvm.org/viewvc/llvm-project?rev=207101&view=rev
Log:
AArch64/ARM64: port more tests

Added:
    llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll
      - copied, changed from r207088, llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll
Modified:
    llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll
    llvm/trunk/test/CodeGen/AArch64/regress-wzr-allocatable.ll
    llvm/trunk/test/CodeGen/AArch64/sext_inreg.ll

Modified: llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll?rev=207101&r1=207100&r2=207101&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll Thu Apr 24 07:11:46 2014
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
 
 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
 ; is illegal in AArch64 backend, the legalizer tries to scalarize this node.

Modified: llvm/trunk/test/CodeGen/AArch64/regress-wzr-allocatable.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-wzr-allocatable.ll?rev=207101&r1=207100&r2=207101&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/regress-wzr-allocatable.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/regress-wzr-allocatable.ll Thu Apr 24 07:11:46 2014
@@ -1,5 +1,8 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0
 
+; Skipping for arm64, there's no evidence it would ever have hit the same
+; problem.
+
 ; When WZR wasn't marked as reserved, this function tried to allocate
 ; it at O0 and then generated an internal fault (mostly incidentally)
 ; when it discovered that it was already in use for a multiplication.

Modified: llvm/trunk/test/CodeGen/AArch64/sext_inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/sext_inreg.ll?rev=207101&r1=207100&r2=207101&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/sext_inreg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/sext_inreg.ll Thu Apr 24 07:11:46 2014
@@ -1,5 +1,9 @@
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
 
+; arm64: This test contains much that is unique and valuable. Unfortunately the
+; bits that are unique aren't valuable and the bits that are valuable aren't
+; unique. (weird ABI types vs bog-standard shifting & extensions).
+
 ; For formal arguments, we have the following vector type promotion,
 ; v2i8 is promoted to v2i32(f64)
 ; v2i16 is promoted to v2i32(f64)

Copied: llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll (from r207088, llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll?p2=llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll&p1=llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll&r1=207088&r2=207101&rev=207101&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-v1i1-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/aarch64-neon-v1i1-setcc.ll Thu Apr 24 07:11:46 2014
@@ -1,4 +1,5 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
 
 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
 ; is illegal in AArch64 backend, the legalizer tries to scalarize this node.
@@ -10,7 +11,7 @@
 
 define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
 ; CHECK-LABEL: test_sext_extr_cmp_0:
-; CHECK: cmge d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
   %1 = icmp sge <1 x i64> %v1, %v2
   %2 = extractelement <1 x i1> %1, i32 0
   %vget_lane = sext i1 %2 to i64
@@ -19,7 +20,7 @@ define i64 @test_sext_extr_cmp_0(<1 x i6
 
 define i64 @test_sext_extr_cmp_1(<1 x double> %v1, <1 x double> %v2) {
 ; CHECK-LABEL: test_sext_extr_cmp_1:
-; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
   %1 = fcmp oeq <1 x double> %v1, %v2
   %2 = extractelement <1 x i1> %1, i32 0
   %vget_lane = sext i1 %2 to i64
@@ -29,7 +30,7 @@ define i64 @test_sext_extr_cmp_1(<1 x do
 define <1 x i64> @test_select_v1i1_0(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
 ; CHECK-LABEL: test_select_v1i1_0:
 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
+; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
   %1 = icmp eq <1 x i64> %v1, %v2
   %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
   ret <1 x i64> %res
@@ -38,7 +39,7 @@ define <1 x i64> @test_select_v1i1_0(<1
 define <1 x i64> @test_select_v1i1_1(<1 x double> %v1, <1 x double> %v2, <1 x i64> %v3) {
 ; CHECK-LABEL: test_select_v1i1_1:
 ; CHECK: fcmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
+; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
   %1 = fcmp oeq <1 x double> %v1, %v2
   %res = select <1 x i1> %1, <1 x i64> zeroinitializer, <1 x i64> %v3
   ret <1 x i64> %res
@@ -47,7 +48,7 @@ define <1 x i64> @test_select_v1i1_1(<1
 define <1 x double> @test_select_v1i1_2(<1 x i64> %v1, <1 x i64> %v2, <1 x double> %v3) {
 ; CHECK-LABEL: test_select_v1i1_2:
 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
-; CHECK: bsl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
+; CHECK: bic v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
   %1 = icmp eq <1 x i64> %v1, %v2
   %res = select <1 x i1> %1, <1 x double> zeroinitializer, <1 x double> %v3
   ret <1 x double> %res