[llvm] r206094 - X86: Remove TargetMachine CPU auto-detection.
NAKAMURA Takumi
geek4civic at gmail.com
Mon Apr 14 21:24:42 PDT 2014
Jim, since then, JIT has been using "generic" by default. Did you intend so?
Could we resurrect host feature detection in Support?
2014-04-12 10:34 GMT+09:00 Jim Grosbach <grosbach at apple.com>:
> Author: grosbach
> Date: Fri Apr 11 20:34:29 2014
> New Revision: 206094
>
> URL: http://llvm.org/viewvc/llvm-project?rev=206094&view=rev
> Log:
> X86: Remove TargetMachine CPU auto-detection.
>
> This logic is properly in the realm of whatever is creating the
> TargetMachine. This makes plain 'llc foo.ll' consistent across
> heterogenous machines.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> llvm/trunk/lib/Target/X86/X86Subtarget.h
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=206094&r1=206093&r2=206094&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Apr 11 20:34:29 2014
> @@ -173,241 +173,6 @@ bool X86Subtarget::IsLegalToCallImmediat
> return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
> }
>
> -static bool OSHasAVXSupport() {
> -#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
> - || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
> -#if defined(__GNUC__)
> - // Check xgetbv; this uses a .byte sequence instead of the instruction
> - // directly because older assemblers do not include support for xgetbv and
> - // there is no easy way to conditionally compile based on the assembler used.
> - int rEAX, rEDX;
> - __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
> -#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
> - unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
> -#else
> - int rEAX = 0; // Ensures we return false
> -#endif
> - return (rEAX & 6) == 6;
> -#else
> - return false;
> -#endif
> -}
> -
> -void X86Subtarget::AutoDetectSubtargetFeatures() {
> - unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
> - unsigned MaxLevel;
> - union {
> - unsigned u[3];
> - char c[12];
> - } text;
> -
> - if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
> - MaxLevel < 1)
> - return;
> -
> - X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
> -
> - if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
> - if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
> - if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
> - if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
> - if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
> - if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
> - if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
> - if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
> - if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
> - X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
> - }
> -
> - bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
> - bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
> -
> - if ((ECX >> 1) & 0x1) {
> - HasPCLMUL = true;
> - ToggleFeature(X86::FeaturePCLMUL);
> - }
> - if ((ECX >> 12) & 0x1) {
> - HasFMA = true;
> - ToggleFeature(X86::FeatureFMA);
> - }
> - if (IsIntel && ((ECX >> 22) & 0x1)) {
> - HasMOVBE = true;
> - ToggleFeature(X86::FeatureMOVBE);
> - }
> - if ((ECX >> 23) & 0x1) {
> - HasPOPCNT = true;
> - ToggleFeature(X86::FeaturePOPCNT);
> - }
> - if ((ECX >> 25) & 0x1) {
> - HasAES = true;
> - ToggleFeature(X86::FeatureAES);
> - }
> - if ((ECX >> 29) & 0x1) {
> - HasF16C = true;
> - ToggleFeature(X86::FeatureF16C);
> - }
> - if (IsIntel && ((ECX >> 30) & 0x1)) {
> - HasRDRAND = true;
> - ToggleFeature(X86::FeatureRDRAND);
> - }
> -
> - if ((ECX >> 13) & 0x1) {
> - HasCmpxchg16b = true;
> - ToggleFeature(X86::FeatureCMPXCHG16B);
> - }
> -
> - if (IsIntel || IsAMD) {
> - // Determine if bit test memory instructions are slow.
> - unsigned Family = 0;
> - unsigned Model = 0;
> - X86_MC::DetectFamilyModel(EAX, Family, Model);
> - if (IsAMD || (Family == 6 && Model >= 13)) {
> - IsBTMemSlow = true;
> - ToggleFeature(X86::FeatureSlowBTMem);
> - }
> -
> - // Determine if SHLD/SHRD instructions have higher latency then the
> - // equivalent series of shifts/or instructions.
> - // FIXME: Add Intel's processors that have SHLD instructions with very
> - // poor latency.
> - if (IsAMD) {
> - IsSHLDSlow = true;
> - ToggleFeature(X86::FeatureSlowSHLD);
> - }
> -
> - // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
> - // memory access is fast. We hard code model numbers here because they
> - // aren't strictly increasing for Intel chips it seems.
> - if (IsIntel &&
> - ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
> - // Jasper Froest
> - (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
> - (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
> - (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
> - (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
> - (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
> - (Family == 6 && Model == 0x2A) || // SandyBridge
> - (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
> - (Family == 6 && Model == 0x3A) || // IvyBridge
> - (Family == 6 && Model == 0x3E) || // IvyBridge EP
> - (Family == 6 && Model == 0x3C) || // Haswell
> - (Family == 6 && Model == 0x3F) || // ...
> - (Family == 6 && Model == 0x45) || // ...
> - (Family == 6 && Model == 0x46))) { // ...
> - IsUAMemFast = true;
> - ToggleFeature(X86::FeatureFastUAMem);
> - }
> -
> - // Set processor type. Currently only Atom or Silvermont (SLM) is detected.
> - if (Family == 6 &&
> - (Model == 28 || Model == 38 || Model == 39 ||
> - Model == 53 || Model == 54)) {
> - X86ProcFamily = IntelAtom;
> -
> - UseLeaForSP = true;
> - ToggleFeature(X86::FeatureLeaForSP);
> - }
> - else if (Family == 6 &&
> - (Model == 55 || Model == 74 || Model == 77)) {
> - X86ProcFamily = IntelSLM;
> - }
> -
> - unsigned MaxExtLevel;
> - X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
> -
> - if (MaxExtLevel >= 0x80000001) {
> - X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
> - if ((EDX >> 29) & 0x1) {
> - HasX86_64 = true;
> - ToggleFeature(X86::Feature64Bit);
> - }
> - if ((ECX >> 5) & 0x1) {
> - HasLZCNT = true;
> - ToggleFeature(X86::FeatureLZCNT);
> - }
> - if (IsIntel && ((ECX >> 8) & 0x1)) {
> - HasPRFCHW = true;
> - ToggleFeature(X86::FeaturePRFCHW);
> - }
> - if (IsAMD) {
> - if ((ECX >> 6) & 0x1) {
> - HasSSE4A = true;
> - ToggleFeature(X86::FeatureSSE4A);
> - }
> - if ((ECX >> 11) & 0x1) {
> - HasXOP = true;
> - ToggleFeature(X86::FeatureXOP);
> - }
> - if ((ECX >> 16) & 0x1) {
> - HasFMA4 = true;
> - ToggleFeature(X86::FeatureFMA4);
> - }
> - }
> - }
> - }
> -
> - if (MaxLevel >= 7) {
> - if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
> - if (IsIntel && (EBX & 0x1)) {
> - HasFSGSBase = true;
> - ToggleFeature(X86::FeatureFSGSBase);
> - }
> - if ((EBX >> 3) & 0x1) {
> - HasBMI = true;
> - ToggleFeature(X86::FeatureBMI);
> - }
> - if ((EBX >> 4) & 0x1) {
> - HasHLE = true;
> - ToggleFeature(X86::FeatureHLE);
> - }
> - if (IsIntel && ((EBX >> 5) & 0x1)) {
> - X86SSELevel = AVX2;
> - ToggleFeature(X86::FeatureAVX2);
> - }
> - if (IsIntel && ((EBX >> 8) & 0x1)) {
> - HasBMI2 = true;
> - ToggleFeature(X86::FeatureBMI2);
> - }
> - if (IsIntel && ((EBX >> 11) & 0x1)) {
> - HasRTM = true;
> - ToggleFeature(X86::FeatureRTM);
> - }
> - if (IsIntel && ((EBX >> 16) & 0x1)) {
> - X86SSELevel = AVX512F;
> - ToggleFeature(X86::FeatureAVX512);
> - }
> - if (IsIntel && ((EBX >> 18) & 0x1)) {
> - HasRDSEED = true;
> - ToggleFeature(X86::FeatureRDSEED);
> - }
> - if (IsIntel && ((EBX >> 19) & 0x1)) {
> - HasADX = true;
> - ToggleFeature(X86::FeatureADX);
> - }
> - if (IsIntel && ((EBX >> 26) & 0x1)) {
> - HasPFI = true;
> - ToggleFeature(X86::FeaturePFI);
> - }
> - if (IsIntel && ((EBX >> 27) & 0x1)) {
> - HasERI = true;
> - ToggleFeature(X86::FeatureERI);
> - }
> - if (IsIntel && ((EBX >> 28) & 0x1)) {
> - HasCDI = true;
> - ToggleFeature(X86::FeatureCDI);
> - }
> - if (IsIntel && ((EBX >> 29) & 0x1)) {
> - HasSHA = true;
> - ToggleFeature(X86::FeatureSHA);
> - }
> - }
> - if (IsAMD && ((ECX >> 21) & 0x1)) {
> - HasTBM = true;
> - ToggleFeature(X86::FeatureTBM);
> - }
> - }
> -}
> -
> void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
> AttributeSet FnAttrs = MF->getFunction()->getAttributes();
> Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
> @@ -426,54 +191,23 @@ void X86Subtarget::resetSubtargetFeature
>
> void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
> std::string CPUName = CPU;
> - if (!FS.empty() || !CPU.empty()) {
> - if (CPUName.empty()) {
> -#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
> - || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
> - CPUName = sys::getHostCPUName();
> -#else
> - CPUName = "generic";
> -#endif
> - }
> + if (CPUName.empty())
> + CPUName = "generic";
>
> - // Make sure 64-bit features are available in 64-bit mode. (But make sure
> - // SSE2 can be turned off explicitly.)
> - std::string FullFS = FS;
> - if (In64BitMode) {
> - if (!FullFS.empty())
> - FullFS = "+64bit,+sse2," + FullFS;
> - else
> - FullFS = "+64bit,+sse2";
> - }
> -
> - // If feature string is not empty, parse features string.
> - ParseSubtargetFeatures(CPUName, FullFS);
> - } else {
> - if (CPUName.empty()) {
> -#if defined (__x86_64__) || defined(__i386__)
> - CPUName = sys::getHostCPUName();
> -#else
> - CPUName = "generic";
> -#endif
> - }
> - // Otherwise, use CPUID to auto-detect feature set.
> - AutoDetectSubtargetFeatures();
> -
> - // Make sure 64-bit features are available in 64-bit mode.
> - if (In64BitMode) {
> - if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
> - if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
> -
> - if (X86SSELevel < SSE2) {
> - X86SSELevel = SSE2;
> - ToggleFeature(X86::FeatureSSE1);
> - ToggleFeature(X86::FeatureSSE2);
> - }
> - }
> + // Make sure 64-bit features are available in 64-bit mode. (But make sure
> + // SSE2 can be turned off explicitly.)
> + std::string FullFS = FS;
> + if (In64BitMode) {
> + if (!FullFS.empty())
> + FullFS = "+64bit,+sse2," + FullFS;
> + else
> + FullFS = "+64bit,+sse2";
> }
>
> - // CPUName may have been set by the CPU detection code. Make sure the
> - // new MCSchedModel is used.
> + // If feature string is not empty, parse features string.
> + ParseSubtargetFeatures(CPUName, FullFS);
> +
> + // Make sure the right MCSchedModel is used.
> InitCPUSchedModel(CPUName);
>
> if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)
>
> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=206094&r1=206093&r2=206094&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Apr 11 20:34:29 2014
> @@ -235,10 +235,6 @@ public:
> /// subtarget options. Definition of function is auto generated by tblgen.
> void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
>
> - /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
> - /// instruction.
> - void AutoDetectSubtargetFeatures();
> -
> /// \brief Reset the features for the X86 target.
> void resetSubtargetFeatures(const MachineFunction *MF) override;
> private:
>
>
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