[llvm] r205867 - [ARM64] Move ARM64BaseInfo.{cpp, h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent.
James Molloy
james at jamesmolloy.co.uk
Wed Apr 9 11:49:41 PDT 2014
Hi Bob,
Thanks! I'd just started trying to fix it 15 mins ago. The "hack" line is a
pasto from lib/ARM64/MCTargetDesc/Makefile from which I copied
lib/ARM64/Utils/Makefile. I'm not sure how the "hack" got commented out :/
Thankyou for spending the time to investigate this instead of reverting the
patch chain, and please accept my apologies for breaking the autotools
build.
Cheers,
James
On 9 April 2014 19:42, Bob Wilson <bob.wilson at apple.com> wrote:
> You convinced me to try a simple fix. I think r205918 should do it.
>
> On Apr 9, 2014, at 10:39 AM, James Molloy <James.Molloy at arm.com> wrote:
>
> Hi Bob,
>
> That is regrettable, but I do understand. It should be an absolutely
> trivial fix though :(
>
> James
>
> Sent from my Windows Phone
> ------------------------------
> From: Bob Wilson <bob.wilson at apple.com>
> Sent: 09/04/2014 18:38
> To: James Molloy <James.Molloy at arm.com>
> Cc: Alexander Potapenko <glider at google.com>; Bradley Smith<Bradley.Smith at arm.com>;
> Commit Messages and Patches for LLVM <llvm-commits at cs.uiuc.edu>
> Subject: Re: [llvm] r205867 - [ARM64] Move ARM64BaseInfo.{cpp, h} into a
> Utils/ subdirectory, a la AArch64. These files are required in the decoder,
> disassembler and parser, and a layering violation was imminent.
>
> We’re seeing this with configure+make builds. I haven’t tried cmake.
>
> I don’t think we can leave the build broken like this until you get
> home. I’m sorry but I’m going to revert the entire sequence of patches that
> you committed this morning, at least back to the point where this failure
> was introduced.
>
> On Apr 9, 2014, at 10:35 AM, James Molloy <James.Molloy at arm.com> wrote:
>
> Hi Bob,
>
> My plane is just taxiing, and I can take a look at this as soon as I get
> home in an hour or so.
>
> If someone (like Tim?) gets to look at it in the meantime, please can they
> tell me?
>
> Bob, out of interest is this a cmake build or an autotools build or both
> that is breaking? I use cmake normally and it is possible I missed
> something for autotools...
>
> Many apologies for the breakage, will be fixed soon.
>
> James
>
> Sent from my Windows Phone
> ------------------------------
> From: Bob Wilson <bob.wilson at apple.com>
> Sent: 09/04/2014 17:33
> To: Alexander Potapenko <glider at google.com>; James Molloy<James.Molloy at arm.com>
> Cc: Bradley Smith <Bradley.Smith at arm.com>; Commit Messages and Patches
> for LLVM <llvm-commits at cs.uiuc.edu>
> Subject: Re: [llvm] r205867 - [ARM64] Move ARM64BaseInfo.{cpp, h} into a
> Utils/ subdirectory, a la AArch64. These files are required in the decoder,
> disassembler and parser, and a layering violation was imminent.
>
> + James
>
> This is breaking all our builds.
>
> On Apr 9, 2014, at 9:16 AM, Alexander Potapenko <glider at google.com> wrote:
>
> > Hi Bradley,
> >
> > after a bunch of your commits in range 205855-205900 my OSX buildbot
> > reports the following error. Could you please take a look?
> >
> > In file included from
> >
> /Users/buildbot/src/llvm-buildbot/slave/mac10.9/build/llvm/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp:13:
> >
> /Users/buildbot/src/llvm-buildbot/slave/mac10.9/build/llvm/lib/Target/ARM64/Utils/ARM64BaseInfo.h:22:10:
> > fatal error: 'MCTargetDesc/ARM64MCTargetDesc.h' file not found
> > #include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and friends.
> > ^
> > 1 error generated.
> >
> > On Wed, Apr 9, 2014 at 6:42 PM, Bradley Smith <bradley.smith at arm.com>
> wrote:
> >> Author: brasmi01
> >> Date: Wed Apr 9 09:42:27 2014
> >> New Revision: 205867
> >>
> >> URL: http://llvm.org/viewvc/llvm-project?rev=205867&view=rev
> >> Log:
> >> [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la
> AArch64. These files are required in the decoder, disassembler and parser,
> and a layering violation was imminent.
> >>
> >> Added:
> >> llvm/trunk/lib/Target/ARM64/Utils/
> >> llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp (contents,
> props changed)
> >> - copied, changed from r205866,
> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp
> >> llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h (contents, props
> changed)
> >> - copied, changed from r205866,
> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
> >> llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt (with props)
> >> llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt
> >> - copied, changed from r205866,
> llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
> >> llvm/trunk/lib/Target/ARM64/Utils/Makefile
> >> Removed:
> >> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp
> >> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
> >> Modified:
> >> llvm/trunk/lib/Target/ARM64/ARM64.h
> >> llvm/trunk/lib/Target/ARM64/ARM64MCInstLower.cpp
> >> llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
> >> llvm/trunk/lib/Target/ARM64/CMakeLists.txt
> >> llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
> >> llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt
> >> llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
> >> llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
> >> llvm/trunk/lib/Target/ARM64/LLVMBuild.txt
> >> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
> >> llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt
> >> llvm/trunk/lib/Target/ARM64/Makefile
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/ARM64.h
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64.h?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/ARM64.h (original)
> >> +++ llvm/trunk/lib/Target/ARM64/ARM64.h Wed Apr 9 09:42:27 2014
> >> @@ -15,7 +15,7 @@
> >> #ifndef TARGET_ARM64_H
> >> #define TARGET_ARM64_H
> >>
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "MCTargetDesc/ARM64MCTargetDesc.h"
> >> #include "llvm/Target/TargetMachine.h"
> >> #include "llvm/Support/DataTypes.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/ARM64MCInstLower.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64MCInstLower.cpp?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/ARM64MCInstLower.cpp (original)
> >> +++ llvm/trunk/lib/Target/ARM64/ARM64MCInstLower.cpp Wed Apr 9
> 09:42:27 2014
> >> @@ -13,8 +13,8 @@
> >>
> //===----------------------------------------------------------------------===//
> >>
> >> #include "ARM64MCInstLower.h"
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> #include "MCTargetDesc/ARM64MCExpr.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "llvm/CodeGen/AsmPrinter.h"
> >> #include "llvm/CodeGen/MachineBasicBlock.h"
> >> #include "llvm/CodeGen/MachineInstr.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
> >> +++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Wed Apr 9
> 09:42:27 2014
> >> @@ -8,8 +8,8 @@
> >>
> //===----------------------------------------------------------------------===//
> >>
> >> #include "MCTargetDesc/ARM64AddressingModes.h"
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> #include "MCTargetDesc/ARM64MCExpr.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "llvm/MC/MCParser/MCAsmLexer.h"
> >> #include "llvm/MC/MCParser/MCAsmParser.h"
> >> #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/CMakeLists.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/CMakeLists.txt?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/CMakeLists.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/CMakeLists.txt Wed Apr 9 09:42:27 2014
> >> @@ -48,3 +48,4 @@ add_subdirectory(AsmParser)
> >> add_subdirectory(Disassembler)
> >> add_subdirectory(InstPrinter)
> >> add_subdirectory(MCTargetDesc)
> >> +add_subdirectory(Utils)
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
> (original)
> >> +++ llvm/trunk/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp Wed
> Apr 9 09:42:27 2014
> >> @@ -14,8 +14,8 @@
> >>
> >> #include "ARM64Disassembler.h"
> >> #include "ARM64Subtarget.h"
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> #include "MCTargetDesc/ARM64AddressingModes.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "llvm/MC/MCInst.h"
> >> #include "llvm/MC/MCExpr.h"
> >> #include "llvm/MC/MCContext.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/Disassembler/LLVMBuild.txt Wed Apr 9
> 09:42:27 2014
> >> @@ -19,6 +19,6 @@
> >> type = Library
> >> name = ARM64Disassembler
> >> parent = ARM64
> >> -required_libraries = ARM64Desc ARM64Info MC Support
> >> +required_libraries = ARM64Desc ARM64Info ARM64Utils MC Support
> >> add_to_library_groups = ARM64
> >>
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
> (original)
> >> +++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp Wed
> Apr 9 09:42:27 2014
> >> @@ -14,7 +14,7 @@
> >> #define DEBUG_TYPE "asm-printer"
> >> #include "ARM64InstPrinter.h"
> >> #include "MCTargetDesc/ARM64AddressingModes.h"
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "llvm/ADT/STLExtras.h"
> >> #include "llvm/ADT/StringExtras.h"
> >> #include "llvm/MC/MCInst.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt Wed Apr 9
> 09:42:27 2014
> >> @@ -19,6 +19,6 @@
> >> type = Library
> >> name = ARM64AsmPrinter
> >> parent = ARM64
> >> -required_libraries = MC Support
> >> +required_libraries = ARM64Utils MC Support
> >> add_to_library_groups = ARM64
> >>
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/LLVMBuild.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/LLVMBuild.txt?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/LLVMBuild.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/LLVMBuild.txt Wed Apr 9 09:42:27 2014
> >> @@ -16,7 +16,7 @@
> >>
> ;===------------------------------------------------------------------------===;
> >>
> >> [common]
> >> -subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc
> TargetInfo
> >> +subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc
> TargetInfo Utils
> >>
> >> [component_0]
> >> type = TargetGroup
> >> @@ -31,6 +31,6 @@ has_jit = 1
> >> type = Library
> >> name = ARM64CodeGen
> >> parent = ARM64
> >> -required_libraries = ARM64AsmPrinter ARM64Desc ARM64Info Analysis
> AsmPrinter CodeGen Core MC SelectionDAG Support Target
> >> +required_libraries = ARM64AsmPrinter ARM64Desc ARM64Info ARM64Utils
> Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target
> >> add_to_library_groups = ARM64
> >>
> >>
> >> Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp?rev=205866&view=auto
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp
> (original)
> >> +++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp (removed)
> >> @@ -1,870 +0,0 @@
> >> -//===-- ARM64BaseInfo.cpp - ARM64 Base encoding
> information------------===//
> >> -//
> >> -// The LLVM Compiler Infrastructure
> >> -//
> >> -// This file is distributed under the University of Illinois Open
> Source
> >> -// License. See LICENSE.TXT for details.
> >> -//
> >>
> -//===----------------------------------------------------------------------===//
> >> -//
> >> -// This file provides basic encoding and assembly information for
> ARM64.
> >> -//
> >>
> -//===----------------------------------------------------------------------===//
> >> -#include "ARM64BaseInfo.h"
> >> -#include "llvm/ADT/APFloat.h"
> >> -#include "llvm/ADT/SmallVector.h"
> >> -#include "llvm/ADT/StringExtras.h"
> >> -#include "llvm/Support/Regex.h"
> >> -
> >> -using namespace llvm;
> >> -
> >> -StringRef ARM64NamedImmMapper::toString(uint32_t Value, bool &Valid)
> const {
> >> - for (unsigned i = 0; i < NumPairs; ++i) {
> >> - if (Pairs[i].Value == Value) {
> >> - Valid = true;
> >> - return Pairs[i].Name;
> >> - }
> >> - }
> >> -
> >> - Valid = false;
> >> - return StringRef();
> >> -}
> >> -
> >> -uint32_t ARM64NamedImmMapper::fromString(StringRef Name, bool &Valid)
> const {
> >> - std::string LowerCaseName = Name.lower();
> >> - for (unsigned i = 0; i < NumPairs; ++i) {
> >> - if (Pairs[i].Name == LowerCaseName) {
> >> - Valid = true;
> >> - return Pairs[i].Value;
> >> - }
> >> - }
> >> -
> >> - Valid = false;
> >> - return -1;
> >> -}
> >> -
> >> -bool ARM64NamedImmMapper::validImm(uint32_t Value) const {
> >> - return Value < TooBigImm;
> >> -}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64AT::ATMapper::ATPairs[] = {
> >> - {"s1e1r", S1E1R},
> >> - {"s1e2r", S1E2R},
> >> - {"s1e3r", S1E3R},
> >> - {"s1e1w", S1E1W},
> >> - {"s1e2w", S1E2W},
> >> - {"s1e3w", S1E3W},
> >> - {"s1e0r", S1E0R},
> >> - {"s1e0w", S1E0W},
> >> - {"s12e1r", S12E1R},
> >> - {"s12e1w", S12E1W},
> >> - {"s12e0r", S12E0R},
> >> - {"s12e0w", S12E0W},
> >> -};
> >> -
> >> -ARM64AT::ATMapper::ATMapper()
> >> - : ARM64NamedImmMapper(ATPairs, 0) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping
> ARM64DB::DBarrierMapper::DBarrierPairs[] = {
> >> - {"oshld", OSHLD},
> >> - {"oshst", OSHST},
> >> - {"osh", OSH},
> >> - {"nshld", NSHLD},
> >> - {"nshst", NSHST},
> >> - {"nsh", NSH},
> >> - {"ishld", ISHLD},
> >> - {"ishst", ISHST},
> >> - {"ish", ISH},
> >> - {"ld", LD},
> >> - {"st", ST},
> >> - {"sy", SY}
> >> -};
> >> -
> >> -ARM64DB::DBarrierMapper::DBarrierMapper()
> >> - : ARM64NamedImmMapper(DBarrierPairs, 16u) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64DC::DCMapper::DCPairs[] = {
> >> - {"zva", ZVA},
> >> - {"ivac", IVAC},
> >> - {"isw", ISW},
> >> - {"cvac", CVAC},
> >> - {"csw", CSW},
> >> - {"cvau", CVAU},
> >> - {"civac", CIVAC},
> >> - {"cisw", CISW}
> >> -};
> >> -
> >> -ARM64DC::DCMapper::DCMapper()
> >> - : ARM64NamedImmMapper(DCPairs, 0) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64IC::ICMapper::ICPairs[] = {
> >> - {"ialluis", IALLUIS},
> >> - {"iallu", IALLU},
> >> - {"ivau", IVAU}
> >> -};
> >> -
> >> -ARM64IC::ICMapper::ICMapper()
> >> - : ARM64NamedImmMapper(ICPairs, 0) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64ISB::ISBMapper::ISBPairs[] = {
> >> - {"sy", SY},
> >> -};
> >> -
> >> -ARM64ISB::ISBMapper::ISBMapper()
> >> - : ARM64NamedImmMapper(ISBPairs, 16) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64PRFM::PRFMMapper::PRFMPairs[]
> = {
> >> - {"pldl1keep", PLDL1KEEP},
> >> - {"pldl1strm", PLDL1STRM},
> >> - {"pldl2keep", PLDL2KEEP},
> >> - {"pldl2strm", PLDL2STRM},
> >> - {"pldl3keep", PLDL3KEEP},
> >> - {"pldl3strm", PLDL3STRM},
> >> - {"plil1keep", PLIL1KEEP},
> >> - {"plil1strm", PLIL1STRM},
> >> - {"plil2keep", PLIL2KEEP},
> >> - {"plil2strm", PLIL2STRM},
> >> - {"plil3keep", PLIL3KEEP},
> >> - {"plil3strm", PLIL3STRM},
> >> - {"pstl1keep", PSTL1KEEP},
> >> - {"pstl1strm", PSTL1STRM},
> >> - {"pstl2keep", PSTL2KEEP},
> >> - {"pstl2strm", PSTL2STRM},
> >> - {"pstl3keep", PSTL3KEEP},
> >> - {"pstl3strm", PSTL3STRM}
> >> -};
> >> -
> >> -ARM64PRFM::PRFMMapper::PRFMMapper()
> >> - : ARM64NamedImmMapper(PRFMPairs, 32) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping
> ARM64PState::PStateMapper::PStatePairs[] = {
> >> - {"spsel", SPSel},
> >> - {"daifset", DAIFSet},
> >> - {"daifclr", DAIFClr}
> >> -};
> >> -
> >> -ARM64PState::PStateMapper::PStateMapper()
> >> - : ARM64NamedImmMapper(PStatePairs, 0) {}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64SysReg::MRSMapper::MRSPairs[]
> = {
> >> - {"mdccsr_el0", MDCCSR_EL0},
> >> - {"dbgdtrrx_el0", DBGDTRRX_EL0},
> >> - {"mdrar_el1", MDRAR_EL1},
> >> - {"oslsr_el1", OSLSR_EL1},
> >> - {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
> >> - {"pmceid0_el0", PMCEID0_EL0},
> >> - {"pmceid1_el0", PMCEID1_EL0},
> >> - {"midr_el1", MIDR_EL1},
> >> - {"ccsidr_el1", CCSIDR_EL1},
> >> - {"clidr_el1", CLIDR_EL1},
> >> - {"ctr_el0", CTR_EL0},
> >> - {"mpidr_el1", MPIDR_EL1},
> >> - {"revidr_el1", REVIDR_EL1},
> >> - {"aidr_el1", AIDR_EL1},
> >> - {"dczid_el0", DCZID_EL0},
> >> - {"id_pfr0_el1", ID_PFR0_EL1},
> >> - {"id_pfr1_el1", ID_PFR1_EL1},
> >> - {"id_dfr0_el1", ID_DFR0_EL1},
> >> - {"id_afr0_el1", ID_AFR0_EL1},
> >> - {"id_mmfr0_el1", ID_MMFR0_EL1},
> >> - {"id_mmfr1_el1", ID_MMFR1_EL1},
> >> - {"id_mmfr2_el1", ID_MMFR2_EL1},
> >> - {"id_mmfr3_el1", ID_MMFR3_EL1},
> >> - {"id_isar0_el1", ID_ISAR0_EL1},
> >> - {"id_isar1_el1", ID_ISAR1_EL1},
> >> - {"id_isar2_el1", ID_ISAR2_EL1},
> >> - {"id_isar3_el1", ID_ISAR3_EL1},
> >> - {"id_isar4_el1", ID_ISAR4_EL1},
> >> - {"id_isar5_el1", ID_ISAR5_EL1},
> >> - {"id_aa64pfr0_el1", ID_AARM64PFR0_EL1},
> >> - {"id_aa64pfr1_el1", ID_AARM64PFR1_EL1},
> >> - {"id_aa64dfr0_el1", ID_AARM64DFR0_EL1},
> >> - {"id_aa64dfr1_el1", ID_AARM64DFR1_EL1},
> >> - {"id_aa64afr0_el1", ID_AARM64AFR0_EL1},
> >> - {"id_aa64afr1_el1", ID_AARM64AFR1_EL1},
> >> - {"id_aa64isar0_el1", ID_AARM64ISAR0_EL1},
> >> - {"id_aa64isar1_el1", ID_AARM64ISAR1_EL1},
> >> - {"id_aa64mmfr0_el1", ID_AARM64MMFR0_EL1},
> >> - {"id_aa64mmfr1_el1", ID_AARM64MMFR1_EL1},
> >> - {"mvfr0_el1", MVFR0_EL1},
> >> - {"mvfr1_el1", MVFR1_EL1},
> >> - {"mvfr2_el1", MVFR2_EL1},
> >> - {"rvbar_el1", RVBAR_EL1},
> >> - {"rvbar_el2", RVBAR_EL2},
> >> - {"rvbar_el3", RVBAR_EL3},
> >> - {"isr_el1", ISR_EL1},
> >> - {"cntpct_el0", CNTPCT_EL0},
> >> - {"cntvct_el0", CNTVCT_EL0},
> >> -
> >> - // Trace registers
> >> - {"trcstatr", TRCSTATR},
> >> - {"trcidr8", TRCIDR8},
> >> - {"trcidr9", TRCIDR9},
> >> - {"trcidr10", TRCIDR10},
> >> - {"trcidr11", TRCIDR11},
> >> - {"trcidr12", TRCIDR12},
> >> - {"trcidr13", TRCIDR13},
> >> - {"trcidr0", TRCIDR0},
> >> - {"trcidr1", TRCIDR1},
> >> - {"trcidr2", TRCIDR2},
> >> - {"trcidr3", TRCIDR3},
> >> - {"trcidr4", TRCIDR4},
> >> - {"trcidr5", TRCIDR5},
> >> - {"trcidr6", TRCIDR6},
> >> - {"trcidr7", TRCIDR7},
> >> - {"trcoslsr", TRCOSLSR},
> >> - {"trcpdsr", TRCPDSR},
> >> - {"trcdevaff0", TRCDEVAFF0},
> >> - {"trcdevaff1", TRCDEVAFF1},
> >> - {"trclsr", TRCLSR},
> >> - {"trcauthstatus", TRCAUTHSTATUS},
> >> - {"trcdevarch", TRCDEVARCH},
> >> - {"trcdevid", TRCDEVID},
> >> - {"trcdevtype", TRCDEVTYPE},
> >> - {"trcpidr4", TRCPIDR4},
> >> - {"trcpidr5", TRCPIDR5},
> >> - {"trcpidr6", TRCPIDR6},
> >> - {"trcpidr7", TRCPIDR7},
> >> - {"trcpidr0", TRCPIDR0},
> >> - {"trcpidr1", TRCPIDR1},
> >> - {"trcpidr2", TRCPIDR2},
> >> - {"trcpidr3", TRCPIDR3},
> >> - {"trccidr0", TRCCIDR0},
> >> - {"trccidr1", TRCCIDR1},
> >> - {"trccidr2", TRCCIDR2},
> >> - {"trccidr3", TRCCIDR3},
> >> -
> >> - // GICv3 registers
> >> - {"icc_iar1_el1", ICC_IAR1_EL1},
> >> - {"icc_iar0_el1", ICC_IAR0_EL1},
> >> - {"icc_hppir1_el1", ICC_HPPIR1_EL1},
> >> - {"icc_hppir0_el1", ICC_HPPIR0_EL1},
> >> - {"icc_rpr_el1", ICC_RPR_EL1},
> >> - {"ich_vtr_el2", ICH_VTR_EL2},
> >> - {"ich_eisr_el2", ICH_EISR_EL2},
> >> - {"ich_elsr_el2", ICH_ELSR_EL2}
> >> -};
> >> -
> >> -ARM64SysReg::MRSMapper::MRSMapper() {
> >> - InstPairs = &MRSPairs[0];
> >> - NumInstPairs = llvm::array_lengthof(MRSPairs);
> >> -}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64SysReg::MSRMapper::MSRPairs[]
> = {
> >> - {"dbgdtrtx_el0", DBGDTRTX_EL0},
> >> - {"oslar_el1", OSLAR_EL1},
> >> - {"pmswinc_el0", PMSWINC_EL0},
> >> -
> >> - // Trace registers
> >> - {"trcoslar", TRCOSLAR},
> >> - {"trclar", TRCLAR},
> >> -
> >> - // GICv3 registers
> >> - {"icc_eoir1_el1", ICC_EOIR1_EL1},
> >> - {"icc_eoir0_el1", ICC_EOIR0_EL1},
> >> - {"icc_dir_el1", ICC_DIR_EL1},
> >> - {"icc_sgi1r_el1", ICC_SGI1R_EL1},
> >> - {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
> >> - {"icc_sgi0r_el1", ICC_SGI0R_EL1}
> >> -};
> >> -
> >> -ARM64SysReg::MSRMapper::MSRMapper() {
> >> - InstPairs = &MSRPairs[0];
> >> - NumInstPairs = llvm::array_lengthof(MSRPairs);
> >> -}
> >> -
> >> -
> >> -const ARM64NamedImmMapper::Mapping
> ARM64SysReg::SysRegMapper::SysRegPairs[] = {
> >> - {"osdtrrx_el1", OSDTRRX_EL1},
> >> - {"osdtrtx_el1", OSDTRTX_EL1},
> >> - {"teecr32_el1", TEECR32_EL1},
> >> - {"mdccint_el1", MDCCINT_EL1},
> >> - {"mdscr_el1", MDSCR_EL1},
> >> - {"dbgdtr_el0", DBGDTR_EL0},
> >> - {"oseccr_el1", OSECCR_EL1},
> >> - {"dbgvcr32_el2", DBGVCR32_EL2},
> >> - {"dbgbvr0_el1", DBGBVR0_EL1},
> >> - {"dbgbvr1_el1", DBGBVR1_EL1},
> >> - {"dbgbvr2_el1", DBGBVR2_EL1},
> >> - {"dbgbvr3_el1", DBGBVR3_EL1},
> >> - {"dbgbvr4_el1", DBGBVR4_EL1},
> >> - {"dbgbvr5_el1", DBGBVR5_EL1},
> >> - {"dbgbvr6_el1", DBGBVR6_EL1},
> >> - {"dbgbvr7_el1", DBGBVR7_EL1},
> >> - {"dbgbvr8_el1", DBGBVR8_EL1},
> >> - {"dbgbvr9_el1", DBGBVR9_EL1},
> >> - {"dbgbvr10_el1", DBGBVR10_EL1},
> >> - {"dbgbvr11_el1", DBGBVR11_EL1},
> >> - {"dbgbvr12_el1", DBGBVR12_EL1},
> >> - {"dbgbvr13_el1", DBGBVR13_EL1},
> >> - {"dbgbvr14_el1", DBGBVR14_EL1},
> >> - {"dbgbvr15_el1", DBGBVR15_EL1},
> >> - {"dbgbcr0_el1", DBGBCR0_EL1},
> >> - {"dbgbcr1_el1", DBGBCR1_EL1},
> >> - {"dbgbcr2_el1", DBGBCR2_EL1},
> >> - {"dbgbcr3_el1", DBGBCR3_EL1},
> >> - {"dbgbcr4_el1", DBGBCR4_EL1},
> >> - {"dbgbcr5_el1", DBGBCR5_EL1},
> >> - {"dbgbcr6_el1", DBGBCR6_EL1},
> >> - {"dbgbcr7_el1", DBGBCR7_EL1},
> >> - {"dbgbcr8_el1", DBGBCR8_EL1},
> >> - {"dbgbcr9_el1", DBGBCR9_EL1},
> >> - {"dbgbcr10_el1", DBGBCR10_EL1},
> >> - {"dbgbcr11_el1", DBGBCR11_EL1},
> >> - {"dbgbcr12_el1", DBGBCR12_EL1},
> >> - {"dbgbcr13_el1", DBGBCR13_EL1},
> >> - {"dbgbcr14_el1", DBGBCR14_EL1},
> >> - {"dbgbcr15_el1", DBGBCR15_EL1},
> >> - {"dbgwvr0_el1", DBGWVR0_EL1},
> >> - {"dbgwvr1_el1", DBGWVR1_EL1},
> >> - {"dbgwvr2_el1", DBGWVR2_EL1},
> >> - {"dbgwvr3_el1", DBGWVR3_EL1},
> >> - {"dbgwvr4_el1", DBGWVR4_EL1},
> >> - {"dbgwvr5_el1", DBGWVR5_EL1},
> >> - {"dbgwvr6_el1", DBGWVR6_EL1},
> >> - {"dbgwvr7_el1", DBGWVR7_EL1},
> >> - {"dbgwvr8_el1", DBGWVR8_EL1},
> >> - {"dbgwvr9_el1", DBGWVR9_EL1},
> >> - {"dbgwvr10_el1", DBGWVR10_EL1},
> >> - {"dbgwvr11_el1", DBGWVR11_EL1},
> >> - {"dbgwvr12_el1", DBGWVR12_EL1},
> >> - {"dbgwvr13_el1", DBGWVR13_EL1},
> >> - {"dbgwvr14_el1", DBGWVR14_EL1},
> >> - {"dbgwvr15_el1", DBGWVR15_EL1},
> >> - {"dbgwcr0_el1", DBGWCR0_EL1},
> >> - {"dbgwcr1_el1", DBGWCR1_EL1},
> >> - {"dbgwcr2_el1", DBGWCR2_EL1},
> >> - {"dbgwcr3_el1", DBGWCR3_EL1},
> >> - {"dbgwcr4_el1", DBGWCR4_EL1},
> >> - {"dbgwcr5_el1", DBGWCR5_EL1},
> >> - {"dbgwcr6_el1", DBGWCR6_EL1},
> >> - {"dbgwcr7_el1", DBGWCR7_EL1},
> >> - {"dbgwcr8_el1", DBGWCR8_EL1},
> >> - {"dbgwcr9_el1", DBGWCR9_EL1},
> >> - {"dbgwcr10_el1", DBGWCR10_EL1},
> >> - {"dbgwcr11_el1", DBGWCR11_EL1},
> >> - {"dbgwcr12_el1", DBGWCR12_EL1},
> >> - {"dbgwcr13_el1", DBGWCR13_EL1},
> >> - {"dbgwcr14_el1", DBGWCR14_EL1},
> >> - {"dbgwcr15_el1", DBGWCR15_EL1},
> >> - {"teehbr32_el1", TEEHBR32_EL1},
> >> - {"osdlr_el1", OSDLR_EL1},
> >> - {"dbgprcr_el1", DBGPRCR_EL1},
> >> - {"dbgclaimset_el1", DBGCLAIMSET_EL1},
> >> - {"dbgclaimclr_el1", DBGCLAIMCLR_EL1},
> >> - {"csselr_el1", CSSELR_EL1},
> >> - {"vpidr_el2", VPIDR_EL2},
> >> - {"vmpidr_el2", VMPIDR_EL2},
> >> - {"sctlr_el1", SCTLR_EL1},
> >> - {"sctlr_el2", SCTLR_EL2},
> >> - {"sctlr_el3", SCTLR_EL3},
> >> - {"actlr_el1", ACTLR_EL1},
> >> - {"actlr_el2", ACTLR_EL2},
> >> - {"actlr_el3", ACTLR_EL3},
> >> - {"cpacr_el1", CPACR_EL1},
> >> - {"hcr_el2", HCR_EL2},
> >> - {"scr_el3", SCR_EL3},
> >> - {"mdcr_el2", MDCR_EL2},
> >> - {"sder32_el3", SDER32_EL3},
> >> - {"cptr_el2", CPTR_EL2},
> >> - {"cptr_el3", CPTR_EL3},
> >> - {"hstr_el2", HSTR_EL2},
> >> - {"hacr_el2", HACR_EL2},
> >> - {"mdcr_el3", MDCR_EL3},
> >> - {"ttbr0_el1", TTBR0_EL1},
> >> - {"ttbr0_el2", TTBR0_EL2},
> >> - {"ttbr0_el3", TTBR0_EL3},
> >> - {"ttbr1_el1", TTBR1_EL1},
> >> - {"tcr_el1", TCR_EL1},
> >> - {"tcr_el2", TCR_EL2},
> >> - {"tcr_el3", TCR_EL3},
> >> - {"vttbr_el2", VTTBR_EL2},
> >> - {"vtcr_el2", VTCR_EL2},
> >> - {"dacr32_el2", DACR32_EL2},
> >> - {"spsr_el1", SPSR_EL1},
> >> - {"spsr_el2", SPSR_EL2},
> >> - {"spsr_el3", SPSR_EL3},
> >> - {"elr_el1", ELR_EL1},
> >> - {"elr_el2", ELR_EL2},
> >> - {"elr_el3", ELR_EL3},
> >> - {"sp_el0", SP_EL0},
> >> - {"sp_el1", SP_EL1},
> >> - {"sp_el2", SP_EL2},
> >> - {"spsel", SPSel},
> >> - {"nzcv", NZCV},
> >> - {"daif", DAIF},
> >> - {"currentel", CurrentEL},
> >> - {"spsr_irq", SPSR_irq},
> >> - {"spsr_abt", SPSR_abt},
> >> - {"spsr_und", SPSR_und},
> >> - {"spsr_fiq", SPSR_fiq},
> >> - {"fpcr", FPCR},
> >> - {"fpsr", FPSR},
> >> - {"dspsr_el0", DSPSR_EL0},
> >> - {"dlr_el0", DLR_EL0},
> >> - {"ifsr32_el2", IFSR32_EL2},
> >> - {"afsr0_el1", AFSR0_EL1},
> >> - {"afsr0_el2", AFSR0_EL2},
> >> - {"afsr0_el3", AFSR0_EL3},
> >> - {"afsr1_el1", AFSR1_EL1},
> >> - {"afsr1_el2", AFSR1_EL2},
> >> - {"afsr1_el3", AFSR1_EL3},
> >> - {"esr_el1", ESR_EL1},
> >> - {"esr_el2", ESR_EL2},
> >> - {"esr_el3", ESR_EL3},
> >> - {"fpexc32_el2", FPEXC32_EL2},
> >> - {"far_el1", FAR_EL1},
> >> - {"far_el2", FAR_EL2},
> >> - {"far_el3", FAR_EL3},
> >> - {"hpfar_el2", HPFAR_EL2},
> >> - {"par_el1", PAR_EL1},
> >> - {"pmcr_el0", PMCR_EL0},
> >> - {"pmcntenset_el0", PMCNTENSET_EL0},
> >> - {"pmcntenclr_el0", PMCNTENCLR_EL0},
> >> - {"pmovsclr_el0", PMOVSCLR_EL0},
> >> - {"pmselr_el0", PMSELR_EL0},
> >> - {"pmccntr_el0", PMCCNTR_EL0},
> >> - {"pmxevtyper_el0", PMXEVTYPER_EL0},
> >> - {"pmxevcntr_el0", PMXEVCNTR_EL0},
> >> - {"pmuserenr_el0", PMUSERENR_EL0},
> >> - {"pmintenset_el1", PMINTENSET_EL1},
> >> - {"pmintenclr_el1", PMINTENCLR_EL1},
> >> - {"pmovsset_el0", PMOVSSET_EL0},
> >> - {"mair_el1", MAIR_EL1},
> >> - {"mair_el2", MAIR_EL2},
> >> - {"mair_el3", MAIR_EL3},
> >> - {"amair_el1", AMAIR_EL1},
> >> - {"amair_el2", AMAIR_EL2},
> >> - {"amair_el3", AMAIR_EL3},
> >> - {"vbar_el1", VBAR_EL1},
> >> - {"vbar_el2", VBAR_EL2},
> >> - {"vbar_el3", VBAR_EL3},
> >> - {"rmr_el1", RMR_EL1},
> >> - {"rmr_el2", RMR_EL2},
> >> - {"rmr_el3", RMR_EL3},
> >> - {"contextidr_el1", CONTEXTIDR_EL1},
> >> - {"tpidr_el0", TPIDR_EL0},
> >> - {"tpidr_el2", TPIDR_EL2},
> >> - {"tpidr_el3", TPIDR_EL3},
> >> - {"tpidrro_el0", TPIDRRO_EL0},
> >> - {"tpidr_el1", TPIDR_EL1},
> >> - {"cntfrq_el0", CNTFRQ_EL0},
> >> - {"cntvoff_el2", CNTVOFF_EL2},
> >> - {"cntkctl_el1", CNTKCTL_EL1},
> >> - {"cnthctl_el2", CNTHCTL_EL2},
> >> - {"cntp_tval_el0", CNTP_TVAL_EL0},
> >> - {"cnthp_tval_el2", CNTHP_TVAL_EL2},
> >> - {"cntps_tval_el1", CNTPS_TVAL_EL1},
> >> - {"cntp_ctl_el0", CNTP_CTL_EL0},
> >> - {"cnthp_ctl_el2", CNTHP_CTL_EL2},
> >> - {"cntps_ctl_el1", CNTPS_CTL_EL1},
> >> - {"cntp_cval_el0", CNTP_CVAL_EL0},
> >> - {"cnthp_cval_el2", CNTHP_CVAL_EL2},
> >> - {"cntps_cval_el1", CNTPS_CVAL_EL1},
> >> - {"cntv_tval_el0", CNTV_TVAL_EL0},
> >> - {"cntv_ctl_el0", CNTV_CTL_EL0},
> >> - {"cntv_cval_el0", CNTV_CVAL_EL0},
> >> - {"pmevcntr0_el0", PMEVCNTR0_EL0},
> >> - {"pmevcntr1_el0", PMEVCNTR1_EL0},
> >> - {"pmevcntr2_el0", PMEVCNTR2_EL0},
> >> - {"pmevcntr3_el0", PMEVCNTR3_EL0},
> >> - {"pmevcntr4_el0", PMEVCNTR4_EL0},
> >> - {"pmevcntr5_el0", PMEVCNTR5_EL0},
> >> - {"pmevcntr6_el0", PMEVCNTR6_EL0},
> >> - {"pmevcntr7_el0", PMEVCNTR7_EL0},
> >> - {"pmevcntr8_el0", PMEVCNTR8_EL0},
> >> - {"pmevcntr9_el0", PMEVCNTR9_EL0},
> >> - {"pmevcntr10_el0", PMEVCNTR10_EL0},
> >> - {"pmevcntr11_el0", PMEVCNTR11_EL0},
> >> - {"pmevcntr12_el0", PMEVCNTR12_EL0},
> >> - {"pmevcntr13_el0", PMEVCNTR13_EL0},
> >> - {"pmevcntr14_el0", PMEVCNTR14_EL0},
> >> - {"pmevcntr15_el0", PMEVCNTR15_EL0},
> >> - {"pmevcntr16_el0", PMEVCNTR16_EL0},
> >> - {"pmevcntr17_el0", PMEVCNTR17_EL0},
> >> - {"pmevcntr18_el0", PMEVCNTR18_EL0},
> >> - {"pmevcntr19_el0", PMEVCNTR19_EL0},
> >> - {"pmevcntr20_el0", PMEVCNTR20_EL0},
> >> - {"pmevcntr21_el0", PMEVCNTR21_EL0},
> >> - {"pmevcntr22_el0", PMEVCNTR22_EL0},
> >> - {"pmevcntr23_el0", PMEVCNTR23_EL0},
> >> - {"pmevcntr24_el0", PMEVCNTR24_EL0},
> >> - {"pmevcntr25_el0", PMEVCNTR25_EL0},
> >> - {"pmevcntr26_el0", PMEVCNTR26_EL0},
> >> - {"pmevcntr27_el0", PMEVCNTR27_EL0},
> >> - {"pmevcntr28_el0", PMEVCNTR28_EL0},
> >> - {"pmevcntr29_el0", PMEVCNTR29_EL0},
> >> - {"pmevcntr30_el0", PMEVCNTR30_EL0},
> >> - {"pmccfiltr_el0", PMCCFILTR_EL0},
> >> - {"pmevtyper0_el0", PMEVTYPER0_EL0},
> >> - {"pmevtyper1_el0", PMEVTYPER1_EL0},
> >> - {"pmevtyper2_el0", PMEVTYPER2_EL0},
> >> - {"pmevtyper3_el0", PMEVTYPER3_EL0},
> >> - {"pmevtyper4_el0", PMEVTYPER4_EL0},
> >> - {"pmevtyper5_el0", PMEVTYPER5_EL0},
> >> - {"pmevtyper6_el0", PMEVTYPER6_EL0},
> >> - {"pmevtyper7_el0", PMEVTYPER7_EL0},
> >> - {"pmevtyper8_el0", PMEVTYPER8_EL0},
> >> - {"pmevtyper9_el0", PMEVTYPER9_EL0},
> >> - {"pmevtyper10_el0", PMEVTYPER10_EL0},
> >> - {"pmevtyper11_el0", PMEVTYPER11_EL0},
> >> - {"pmevtyper12_el0", PMEVTYPER12_EL0},
> >> - {"pmevtyper13_el0", PMEVTYPER13_EL0},
> >> - {"pmevtyper14_el0", PMEVTYPER14_EL0},
> >> - {"pmevtyper15_el0", PMEVTYPER15_EL0},
> >> - {"pmevtyper16_el0", PMEVTYPER16_EL0},
> >> - {"pmevtyper17_el0", PMEVTYPER17_EL0},
> >> - {"pmevtyper18_el0", PMEVTYPER18_EL0},
> >> - {"pmevtyper19_el0", PMEVTYPER19_EL0},
> >> - {"pmevtyper20_el0", PMEVTYPER20_EL0},
> >> - {"pmevtyper21_el0", PMEVTYPER21_EL0},
> >> - {"pmevtyper22_el0", PMEVTYPER22_EL0},
> >> - {"pmevtyper23_el0", PMEVTYPER23_EL0},
> >> - {"pmevtyper24_el0", PMEVTYPER24_EL0},
> >> - {"pmevtyper25_el0", PMEVTYPER25_EL0},
> >> - {"pmevtyper26_el0", PMEVTYPER26_EL0},
> >> - {"pmevtyper27_el0", PMEVTYPER27_EL0},
> >> - {"pmevtyper28_el0", PMEVTYPER28_EL0},
> >> - {"pmevtyper29_el0", PMEVTYPER29_EL0},
> >> - {"pmevtyper30_el0", PMEVTYPER30_EL0},
> >> -
> >> - // Trace registers
> >> - {"trcprgctlr", TRCPRGCTLR},
> >> - {"trcprocselr", TRCPROCSELR},
> >> - {"trcconfigr", TRCCONFIGR},
> >> - {"trcauxctlr", TRCAUXCTLR},
> >> - {"trceventctl0r", TRCEVENTCTL0R},
> >> - {"trceventctl1r", TRCEVENTCTL1R},
> >> - {"trcstallctlr", TRCSTALLCTLR},
> >> - {"trctsctlr", TRCTSCTLR},
> >> - {"trcsyncpr", TRCSYNCPR},
> >> - {"trcccctlr", TRCCCCTLR},
> >> - {"trcbbctlr", TRCBBCTLR},
> >> - {"trctraceidr", TRCTRACEIDR},
> >> - {"trcqctlr", TRCQCTLR},
> >> - {"trcvictlr", TRCVICTLR},
> >> - {"trcviiectlr", TRCVIIECTLR},
> >> - {"trcvissctlr", TRCVISSCTLR},
> >> - {"trcvipcssctlr", TRCVIPCSSCTLR},
> >> - {"trcvdctlr", TRCVDCTLR},
> >> - {"trcvdsacctlr", TRCVDSACCTLR},
> >> - {"trcvdarcctlr", TRCVDARCCTLR},
> >> - {"trcseqevr0", TRCSEQEVR0},
> >> - {"trcseqevr1", TRCSEQEVR1},
> >> - {"trcseqevr2", TRCSEQEVR2},
> >> - {"trcseqrstevr", TRCSEQRSTEVR},
> >> - {"trcseqstr", TRCSEQSTR},
> >> - {"trcextinselr", TRCEXTINSELR},
> >> - {"trccntrldvr0", TRCCNTRLDVR0},
> >> - {"trccntrldvr1", TRCCNTRLDVR1},
> >> - {"trccntrldvr2", TRCCNTRLDVR2},
> >> - {"trccntrldvr3", TRCCNTRLDVR3},
> >> - {"trccntctlr0", TRCCNTCTLR0},
> >> - {"trccntctlr1", TRCCNTCTLR1},
> >> - {"trccntctlr2", TRCCNTCTLR2},
> >> - {"trccntctlr3", TRCCNTCTLR3},
> >> - {"trccntvr0", TRCCNTVR0},
> >> - {"trccntvr1", TRCCNTVR1},
> >> - {"trccntvr2", TRCCNTVR2},
> >> - {"trccntvr3", TRCCNTVR3},
> >> - {"trcimspec0", TRCIMSPEC0},
> >> - {"trcimspec1", TRCIMSPEC1},
> >> - {"trcimspec2", TRCIMSPEC2},
> >> - {"trcimspec3", TRCIMSPEC3},
> >> - {"trcimspec4", TRCIMSPEC4},
> >> - {"trcimspec5", TRCIMSPEC5},
> >> - {"trcimspec6", TRCIMSPEC6},
> >> - {"trcimspec7", TRCIMSPEC7},
> >> - {"trcrsctlr2", TRCRSCTLR2},
> >> - {"trcrsctlr3", TRCRSCTLR3},
> >> - {"trcrsctlr4", TRCRSCTLR4},
> >> - {"trcrsctlr5", TRCRSCTLR5},
> >> - {"trcrsctlr6", TRCRSCTLR6},
> >> - {"trcrsctlr7", TRCRSCTLR7},
> >> - {"trcrsctlr8", TRCRSCTLR8},
> >> - {"trcrsctlr9", TRCRSCTLR9},
> >> - {"trcrsctlr10", TRCRSCTLR10},
> >> - {"trcrsctlr11", TRCRSCTLR11},
> >> - {"trcrsctlr12", TRCRSCTLR12},
> >> - {"trcrsctlr13", TRCRSCTLR13},
> >> - {"trcrsctlr14", TRCRSCTLR14},
> >> - {"trcrsctlr15", TRCRSCTLR15},
> >> - {"trcrsctlr16", TRCRSCTLR16},
> >> - {"trcrsctlr17", TRCRSCTLR17},
> >> - {"trcrsctlr18", TRCRSCTLR18},
> >> - {"trcrsctlr19", TRCRSCTLR19},
> >> - {"trcrsctlr20", TRCRSCTLR20},
> >> - {"trcrsctlr21", TRCRSCTLR21},
> >> - {"trcrsctlr22", TRCRSCTLR22},
> >> - {"trcrsctlr23", TRCRSCTLR23},
> >> - {"trcrsctlr24", TRCRSCTLR24},
> >> - {"trcrsctlr25", TRCRSCTLR25},
> >> - {"trcrsctlr26", TRCRSCTLR26},
> >> - {"trcrsctlr27", TRCRSCTLR27},
> >> - {"trcrsctlr28", TRCRSCTLR28},
> >> - {"trcrsctlr29", TRCRSCTLR29},
> >> - {"trcrsctlr30", TRCRSCTLR30},
> >> - {"trcrsctlr31", TRCRSCTLR31},
> >> - {"trcssccr0", TRCSSCCR0},
> >> - {"trcssccr1", TRCSSCCR1},
> >> - {"trcssccr2", TRCSSCCR2},
> >> - {"trcssccr3", TRCSSCCR3},
> >> - {"trcssccr4", TRCSSCCR4},
> >> - {"trcssccr5", TRCSSCCR5},
> >> - {"trcssccr6", TRCSSCCR6},
> >> - {"trcssccr7", TRCSSCCR7},
> >> - {"trcsscsr0", TRCSSCSR0},
> >> - {"trcsscsr1", TRCSSCSR1},
> >> - {"trcsscsr2", TRCSSCSR2},
> >> - {"trcsscsr3", TRCSSCSR3},
> >> - {"trcsscsr4", TRCSSCSR4},
> >> - {"trcsscsr5", TRCSSCSR5},
> >> - {"trcsscsr6", TRCSSCSR6},
> >> - {"trcsscsr7", TRCSSCSR7},
> >> - {"trcsspcicr0", TRCSSPCICR0},
> >> - {"trcsspcicr1", TRCSSPCICR1},
> >> - {"trcsspcicr2", TRCSSPCICR2},
> >> - {"trcsspcicr3", TRCSSPCICR3},
> >> - {"trcsspcicr4", TRCSSPCICR4},
> >> - {"trcsspcicr5", TRCSSPCICR5},
> >> - {"trcsspcicr6", TRCSSPCICR6},
> >> - {"trcsspcicr7", TRCSSPCICR7},
> >> - {"trcpdcr", TRCPDCR},
> >> - {"trcacvr0", TRCACVR0},
> >> - {"trcacvr1", TRCACVR1},
> >> - {"trcacvr2", TRCACVR2},
> >> - {"trcacvr3", TRCACVR3},
> >> - {"trcacvr4", TRCACVR4},
> >> - {"trcacvr5", TRCACVR5},
> >> - {"trcacvr6", TRCACVR6},
> >> - {"trcacvr7", TRCACVR7},
> >> - {"trcacvr8", TRCACVR8},
> >> - {"trcacvr9", TRCACVR9},
> >> - {"trcacvr10", TRCACVR10},
> >> - {"trcacvr11", TRCACVR11},
> >> - {"trcacvr12", TRCACVR12},
> >> - {"trcacvr13", TRCACVR13},
> >> - {"trcacvr14", TRCACVR14},
> >> - {"trcacvr15", TRCACVR15},
> >> - {"trcacatr0", TRCACATR0},
> >> - {"trcacatr1", TRCACATR1},
> >> - {"trcacatr2", TRCACATR2},
> >> - {"trcacatr3", TRCACATR3},
> >> - {"trcacatr4", TRCACATR4},
> >> - {"trcacatr5", TRCACATR5},
> >> - {"trcacatr6", TRCACATR6},
> >> - {"trcacatr7", TRCACATR7},
> >> - {"trcacatr8", TRCACATR8},
> >> - {"trcacatr9", TRCACATR9},
> >> - {"trcacatr10", TRCACATR10},
> >> - {"trcacatr11", TRCACATR11},
> >> - {"trcacatr12", TRCACATR12},
> >> - {"trcacatr13", TRCACATR13},
> >> - {"trcacatr14", TRCACATR14},
> >> - {"trcacatr15", TRCACATR15},
> >> - {"trcdvcvr0", TRCDVCVR0},
> >> - {"trcdvcvr1", TRCDVCVR1},
> >> - {"trcdvcvr2", TRCDVCVR2},
> >> - {"trcdvcvr3", TRCDVCVR3},
> >> - {"trcdvcvr4", TRCDVCVR4},
> >> - {"trcdvcvr5", TRCDVCVR5},
> >> - {"trcdvcvr6", TRCDVCVR6},
> >> - {"trcdvcvr7", TRCDVCVR7},
> >> - {"trcdvcmr0", TRCDVCMR0},
> >> - {"trcdvcmr1", TRCDVCMR1},
> >> - {"trcdvcmr2", TRCDVCMR2},
> >> - {"trcdvcmr3", TRCDVCMR3},
> >> - {"trcdvcmr4", TRCDVCMR4},
> >> - {"trcdvcmr5", TRCDVCMR5},
> >> - {"trcdvcmr6", TRCDVCMR6},
> >> - {"trcdvcmr7", TRCDVCMR7},
> >> - {"trccidcvr0", TRCCIDCVR0},
> >> - {"trccidcvr1", TRCCIDCVR1},
> >> - {"trccidcvr2", TRCCIDCVR2},
> >> - {"trccidcvr3", TRCCIDCVR3},
> >> - {"trccidcvr4", TRCCIDCVR4},
> >> - {"trccidcvr5", TRCCIDCVR5},
> >> - {"trccidcvr6", TRCCIDCVR6},
> >> - {"trccidcvr7", TRCCIDCVR7},
> >> - {"trcvmidcvr0", TRCVMIDCVR0},
> >> - {"trcvmidcvr1", TRCVMIDCVR1},
> >> - {"trcvmidcvr2", TRCVMIDCVR2},
> >> - {"trcvmidcvr3", TRCVMIDCVR3},
> >> - {"trcvmidcvr4", TRCVMIDCVR4},
> >> - {"trcvmidcvr5", TRCVMIDCVR5},
> >> - {"trcvmidcvr6", TRCVMIDCVR6},
> >> - {"trcvmidcvr7", TRCVMIDCVR7},
> >> - {"trccidcctlr0", TRCCIDCCTLR0},
> >> - {"trccidcctlr1", TRCCIDCCTLR1},
> >> - {"trcvmidcctlr0", TRCVMIDCCTLR0},
> >> - {"trcvmidcctlr1", TRCVMIDCCTLR1},
> >> - {"trcitctrl", TRCITCTRL},
> >> - {"trcclaimset", TRCCLAIMSET},
> >> - {"trcclaimclr", TRCCLAIMCLR},
> >> -
> >> - // GICv3 registers
> >> - {"icc_bpr1_el1", ICC_BPR1_EL1},
> >> - {"icc_bpr0_el1", ICC_BPR0_EL1},
> >> - {"icc_pmr_el1", ICC_PMR_EL1},
> >> - {"icc_ctlr_el1", ICC_CTLR_EL1},
> >> - {"icc_ctlr_el3", ICC_CTLR_EL3},
> >> - {"icc_sre_el1", ICC_SRE_EL1},
> >> - {"icc_sre_el2", ICC_SRE_EL2},
> >> - {"icc_sre_el3", ICC_SRE_EL3},
> >> - {"icc_igrpen0_el1", ICC_IGRPEN0_EL1},
> >> - {"icc_igrpen1_el1", ICC_IGRPEN1_EL1},
> >> - {"icc_igrpen1_el3", ICC_IGRPEN1_EL3},
> >> - {"icc_seien_el1", ICC_SEIEN_EL1},
> >> - {"icc_ap0r0_el1", ICC_AP0R0_EL1},
> >> - {"icc_ap0r1_el1", ICC_AP0R1_EL1},
> >> - {"icc_ap0r2_el1", ICC_AP0R2_EL1},
> >> - {"icc_ap0r3_el1", ICC_AP0R3_EL1},
> >> - {"icc_ap1r0_el1", ICC_AP1R0_EL1},
> >> - {"icc_ap1r1_el1", ICC_AP1R1_EL1},
> >> - {"icc_ap1r2_el1", ICC_AP1R2_EL1},
> >> - {"icc_ap1r3_el1", ICC_AP1R3_EL1},
> >> - {"ich_ap0r0_el2", ICH_AP0R0_EL2},
> >> - {"ich_ap0r1_el2", ICH_AP0R1_EL2},
> >> - {"ich_ap0r2_el2", ICH_AP0R2_EL2},
> >> - {"ich_ap0r3_el2", ICH_AP0R3_EL2},
> >> - {"ich_ap1r0_el2", ICH_AP1R0_EL2},
> >> - {"ich_ap1r1_el2", ICH_AP1R1_EL2},
> >> - {"ich_ap1r2_el2", ICH_AP1R2_EL2},
> >> - {"ich_ap1r3_el2", ICH_AP1R3_EL2},
> >> - {"ich_hcr_el2", ICH_HCR_EL2},
> >> - {"ich_misr_el2", ICH_MISR_EL2},
> >> - {"ich_vmcr_el2", ICH_VMCR_EL2},
> >> - {"ich_vseir_el2", ICH_VSEIR_EL2},
> >> - {"ich_lr0_el2", ICH_LR0_EL2},
> >> - {"ich_lr1_el2", ICH_LR1_EL2},
> >> - {"ich_lr2_el2", ICH_LR2_EL2},
> >> - {"ich_lr3_el2", ICH_LR3_EL2},
> >> - {"ich_lr4_el2", ICH_LR4_EL2},
> >> - {"ich_lr5_el2", ICH_LR5_EL2},
> >> - {"ich_lr6_el2", ICH_LR6_EL2},
> >> - {"ich_lr7_el2", ICH_LR7_EL2},
> >> - {"ich_lr8_el2", ICH_LR8_EL2},
> >> - {"ich_lr9_el2", ICH_LR9_EL2},
> >> - {"ich_lr10_el2", ICH_LR10_EL2},
> >> - {"ich_lr11_el2", ICH_LR11_EL2},
> >> - {"ich_lr12_el2", ICH_LR12_EL2},
> >> - {"ich_lr13_el2", ICH_LR13_EL2},
> >> - {"ich_lr14_el2", ICH_LR14_EL2},
> >> - {"ich_lr15_el2", ICH_LR15_EL2}
> >> -};
> >> -
> >> -uint32_t
> >> -ARM64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid)
> const {
> >> - // First search the registers shared by all
> >> - std::string NameLower = Name.lower();
> >> - for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
> >> - if (SysRegPairs[i].Name == NameLower) {
> >> - Valid = true;
> >> - return SysRegPairs[i].Value;
> >> - }
> >> - }
> >> -
> >> - // Now try the instruction-specific registers (either read-only or
> >> - // write-only).
> >> - for (unsigned i = 0; i < NumInstPairs; ++i) {
> >> - if (InstPairs[i].Name == NameLower) {
> >> - Valid = true;
> >> - return InstPairs[i].Value;
> >> - }
> >> - }
> >> -
> >> - // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where
> the bits
> >> - // are: 11 xxx 1x11 xxxx xxx
> >> - Regex
> GenericRegPattern("^s3_([0-7])_c(1[15])_c([0-9]|1[0-5])_([0-7])$");
> >> -
> >> - SmallVector<StringRef, 4> Ops;
> >> - if (!GenericRegPattern.match(NameLower, &Ops)) {
> >> - Valid = false;
> >> - return -1;
> >> - }
> >> -
> >> - uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
> >> - uint32_t Bits;
> >> - Ops[1].getAsInteger(10, Op1);
> >> - Ops[2].getAsInteger(10, CRn);
> >> - Ops[3].getAsInteger(10, CRm);
> >> - Ops[4].getAsInteger(10, Op2);
> >> - Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
> >> -
> >> - Valid = true;
> >> - return Bits;
> >> -}
> >> -
> >> -std::string
> >> -ARM64SysReg::SysRegMapper::toString(uint32_t Bits, bool &Valid) const {
> >> - for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
> >> - if (SysRegPairs[i].Value == Bits) {
> >> - Valid = true;
> >> - return SysRegPairs[i].Name;
> >> - }
> >> - }
> >> -
> >> - for (unsigned i = 0; i < NumInstPairs; ++i) {
> >> - if (InstPairs[i].Value == Bits) {
> >> - Valid = true;
> >> - return InstPairs[i].Name;
> >> - }
> >> - }
> >> -
> >> - uint32_t Op0 = (Bits >> 14) & 0x3;
> >> - uint32_t Op1 = (Bits >> 11) & 0x7;
> >> - uint32_t CRn = (Bits >> 7) & 0xf;
> >> - uint32_t CRm = (Bits >> 3) & 0xf;
> >> - uint32_t Op2 = Bits & 0x7;
> >> -
> >> - // Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a
> generic
> >> - // name.
> >> - if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
> >> - Valid = false;
> >> - return "";
> >> - }
> >> -
> >> - assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic
> sysreg");
> >> -
> >> - Valid = true;
> >> - return "s3_" + utostr(Op1) + "_c" + utostr(CRn)
> >> - + "_c" + utostr(CRm) + "_" + utostr(Op2);
> >> -}
> >> -
> >> -const ARM64NamedImmMapper::Mapping ARM64TLBI::TLBIMapper::TLBIPairs[]
> = {
> >> - {"ipas2e1is", IPAS2E1IS},
> >> - {"ipas2le1is", IPAS2LE1IS},
> >> - {"vmalle1is", VMALLE1IS},
> >> - {"alle2is", ALLE2IS},
> >> - {"alle3is", ALLE3IS},
> >> - {"vae1is", VAE1IS},
> >> - {"vae2is", VAE2IS},
> >> - {"vae3is", VAE3IS},
> >> - {"aside1is", ASIDE1IS},
> >> - {"vaae1is", VAAE1IS},
> >> - {"alle1is", ALLE1IS},
> >> - {"vale1is", VALE1IS},
> >> - {"vale2is", VALE2IS},
> >> - {"vale3is", VALE3IS},
> >> - {"vmalls12e1is", VMALLS12E1IS},
> >> - {"vaale1is", VAALE1IS},
> >> - {"ipas2e1", IPAS2E1},
> >> - {"ipas2le1", IPAS2LE1},
> >> - {"vmalle1", VMALLE1},
> >> - {"alle2", ALLE2},
> >> - {"alle3", ALLE3},
> >> - {"vae1", VAE1},
> >> - {"vae2", VAE2},
> >> - {"vae3", VAE3},
> >> - {"aside1", ASIDE1},
> >> - {"vaae1", VAAE1},
> >> - {"alle1", ALLE1},
> >> - {"vale1", VALE1},
> >> - {"vale2", VALE2},
> >> - {"vale3", VALE3},
> >> - {"vmalls12e1", VMALLS12E1},
> >> - {"vaale1", VAALE1}
> >> -};
> >> -
> >> -ARM64TLBI::TLBIMapper::TLBIMapper()
> >> - : ARM64NamedImmMapper(TLBIPairs, 0) {}
> >>
> >> Removed: llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h?rev=205866&view=auto
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h (original)
> >> +++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h (removed)
> >> @@ -1,1950 +0,0 @@
> >> -//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*-
> C++ -*-===//
> >> -//
> >> -// The LLVM Compiler Infrastructure
> >> -//
> >> -// This file is distributed under the University of Illinois Open
> Source
> >> -// License. See LICENSE.TXT for details.
> >> -//
> >>
> -//===----------------------------------------------------------------------===//
> >> -//
> >> -// This file contains small standalone helper functions and enum
> definitions for
> >> -// the ARM64 target useful for the compiler back-end and the MC
> libraries.
> >> -// As such, it deliberately does not include references to LLVM core
> >> -// code gen types, passes, etc..
> >> -//
> >>
> -//===----------------------------------------------------------------------===//
> >> -
> >> -#ifndef ARM64BASEINFO_H
> >> -#define ARM64BASEINFO_H
> >> -
> >> -#include "ARM64MCTargetDesc.h"
> >> -#include "llvm/ADT/STLExtras.h"
> >> -#include "llvm/ADT/StringSwitch.h"
> >> -#include "llvm/Support/ErrorHandling.h"
> >> -
> >> -namespace llvm {
> >> -
> >> -inline static unsigned getWRegFromXReg(unsigned Reg) {
> >> - switch (Reg) {
> >> - case ARM64::X0: return ARM64::W0;
> >> - case ARM64::X1: return ARM64::W1;
> >> - case ARM64::X2: return ARM64::W2;
> >> - case ARM64::X3: return ARM64::W3;
> >> - case ARM64::X4: return ARM64::W4;
> >> - case ARM64::X5: return ARM64::W5;
> >> - case ARM64::X6: return ARM64::W6;
> >> - case ARM64::X7: return ARM64::W7;
> >> - case ARM64::X8: return ARM64::W8;
> >> - case ARM64::X9: return ARM64::W9;
> >> - case ARM64::X10: return ARM64::W10;
> >> - case ARM64::X11: return ARM64::W11;
> >> - case ARM64::X12: return ARM64::W12;
> >> - case ARM64::X13: return ARM64::W13;
> >> - case ARM64::X14: return ARM64::W14;
> >> - case ARM64::X15: return ARM64::W15;
> >> - case ARM64::X16: return ARM64::W16;
> >> - case ARM64::X17: return ARM64::W17;
> >> - case ARM64::X18: return ARM64::W18;
> >> - case ARM64::X19: return ARM64::W19;
> >> - case ARM64::X20: return ARM64::W20;
> >> - case ARM64::X21: return ARM64::W21;
> >> - case ARM64::X22: return ARM64::W22;
> >> - case ARM64::X23: return ARM64::W23;
> >> - case ARM64::X24: return ARM64::W24;
> >> - case ARM64::X25: return ARM64::W25;
> >> - case ARM64::X26: return ARM64::W26;
> >> - case ARM64::X27: return ARM64::W27;
> >> - case ARM64::X28: return ARM64::W28;
> >> - case ARM64::FP: return ARM64::W29;
> >> - case ARM64::LR: return ARM64::W30;
> >> - case ARM64::SP: return ARM64::WSP;
> >> - case ARM64::XZR: return ARM64::WZR;
> >> - }
> >> - // For anything else, return it unchanged.
> >> - return Reg;
> >> -}
> >> -
> >> -inline static unsigned getXRegFromWReg(unsigned Reg) {
> >> - switch (Reg) {
> >> - case ARM64::W0: return ARM64::X0;
> >> - case ARM64::W1: return ARM64::X1;
> >> - case ARM64::W2: return ARM64::X2;
> >> - case ARM64::W3: return ARM64::X3;
> >> - case ARM64::W4: return ARM64::X4;
> >> - case ARM64::W5: return ARM64::X5;
> >> - case ARM64::W6: return ARM64::X6;
> >> - case ARM64::W7: return ARM64::X7;
> >> - case ARM64::W8: return ARM64::X8;
> >> - case ARM64::W9: return ARM64::X9;
> >> - case ARM64::W10: return ARM64::X10;
> >> - case ARM64::W11: return ARM64::X11;
> >> - case ARM64::W12: return ARM64::X12;
> >> - case ARM64::W13: return ARM64::X13;
> >> - case ARM64::W14: return ARM64::X14;
> >> - case ARM64::W15: return ARM64::X15;
> >> - case ARM64::W16: return ARM64::X16;
> >> - case ARM64::W17: return ARM64::X17;
> >> - case ARM64::W18: return ARM64::X18;
> >> - case ARM64::W19: return ARM64::X19;
> >> - case ARM64::W20: return ARM64::X20;
> >> - case ARM64::W21: return ARM64::X21;
> >> - case ARM64::W22: return ARM64::X22;
> >> - case ARM64::W23: return ARM64::X23;
> >> - case ARM64::W24: return ARM64::X24;
> >> - case ARM64::W25: return ARM64::X25;
> >> - case ARM64::W26: return ARM64::X26;
> >> - case ARM64::W27: return ARM64::X27;
> >> - case ARM64::W28: return ARM64::X28;
> >> - case ARM64::W29: return ARM64::FP;
> >> - case ARM64::W30: return ARM64::LR;
> >> - case ARM64::WSP: return ARM64::SP;
> >> - case ARM64::WZR: return ARM64::XZR;
> >> - }
> >> - // For anything else, return it unchanged.
> >> - return Reg;
> >> -}
> >> -
> >> -static inline unsigned getBRegFromDReg(unsigned Reg) {
> >> - switch (Reg) {
> >> - case ARM64::D0: return ARM64::B0;
> >> - case ARM64::D1: return ARM64::B1;
> >> - case ARM64::D2: return ARM64::B2;
> >> - case ARM64::D3: return ARM64::B3;
> >> - case ARM64::D4: return ARM64::B4;
> >> - case ARM64::D5: return ARM64::B5;
> >> - case ARM64::D6: return ARM64::B6;
> >> - case ARM64::D7: return ARM64::B7;
> >> - case ARM64::D8: return ARM64::B8;
> >> - case ARM64::D9: return ARM64::B9;
> >> - case ARM64::D10: return ARM64::B10;
> >> - case ARM64::D11: return ARM64::B11;
> >> - case ARM64::D12: return ARM64::B12;
> >> - case ARM64::D13: return ARM64::B13;
> >> - case ARM64::D14: return ARM64::B14;
> >> - case ARM64::D15: return ARM64::B15;
> >> - case ARM64::D16: return ARM64::B16;
> >> - case ARM64::D17: return ARM64::B17;
> >> - case ARM64::D18: return ARM64::B18;
> >> - case ARM64::D19: return ARM64::B19;
> >> - case ARM64::D20: return ARM64::B20;
> >> - case ARM64::D21: return ARM64::B21;
> >> - case ARM64::D22: return ARM64::B22;
> >> - case ARM64::D23: return ARM64::B23;
> >> - case ARM64::D24: return ARM64::B24;
> >> - case ARM64::D25: return ARM64::B25;
> >> - case ARM64::D26: return ARM64::B26;
> >> - case ARM64::D27: return ARM64::B27;
> >> - case ARM64::D28: return ARM64::B28;
> >> - case ARM64::D29: return ARM64::B29;
> >> - case ARM64::D30: return ARM64::B30;
> >> - case ARM64::D31: return ARM64::B31;
> >> - }
> >> - // For anything else, return it unchanged.
> >> - return Reg;
> >> -}
> >> -
> >> -
> >> -static inline unsigned getDRegFromBReg(unsigned Reg) {
> >> - switch (Reg) {
> >> - case ARM64::B0: return ARM64::D0;
> >> - case ARM64::B1: return ARM64::D1;
> >> - case ARM64::B2: return ARM64::D2;
> >> - case ARM64::B3: return ARM64::D3;
> >> - case ARM64::B4: return ARM64::D4;
> >> - case ARM64::B5: return ARM64::D5;
> >> - case ARM64::B6: return ARM64::D6;
> >> - case ARM64::B7: return ARM64::D7;
> >> - case ARM64::B8: return ARM64::D8;
> >> - case ARM64::B9: return ARM64::D9;
> >> - case ARM64::B10: return ARM64::D10;
> >> - case ARM64::B11: return ARM64::D11;
> >> - case ARM64::B12: return ARM64::D12;
> >> - case ARM64::B13: return ARM64::D13;
> >> - case ARM64::B14: return ARM64::D14;
> >> - case ARM64::B15: return ARM64::D15;
> >> - case ARM64::B16: return ARM64::D16;
> >> - case ARM64::B17: return ARM64::D17;
> >> - case ARM64::B18: return ARM64::D18;
> >> - case ARM64::B19: return ARM64::D19;
> >> - case ARM64::B20: return ARM64::D20;
> >> - case ARM64::B21: return ARM64::D21;
> >> - case ARM64::B22: return ARM64::D22;
> >> - case ARM64::B23: return ARM64::D23;
> >> - case ARM64::B24: return ARM64::D24;
> >> - case ARM64::B25: return ARM64::D25;
> >> - case ARM64::B26: return ARM64::D26;
> >> - case ARM64::B27: return ARM64::D27;
> >> - case ARM64::B28: return ARM64::D28;
> >> - case ARM64::B29: return ARM64::D29;
> >> - case ARM64::B30: return ARM64::D30;
> >> - case ARM64::B31: return ARM64::D31;
> >> - }
> >> - // For anything else, return it unchanged.
> >> - return Reg;
> >> -}
> >> -
> >> -namespace ARM64CC {
> >> -
> >> -// The CondCodes constants map directly to the 4-bit encoding of the
> condition
> >> -// field for predicated instructions.
> >> -enum CondCode { // Meaning (integer) Meaning (floating-point)
> >> - EQ = 0x0, // Equal Equal
> >> - NE = 0x1, // Not equal Not equal, or unordered
> >> - CS = 0x2, // Carry set >, ==, or unordered
> >> - CC = 0x3, // Carry clear Less than
> >> - MI = 0x4, // Minus, negative Less than
> >> - PL = 0x5, // Plus, positive or zero >, ==, or unordered
> >> - VS = 0x6, // Overflow Unordered
> >> - VC = 0x7, // No overflow Not unordered
> >> - HI = 0x8, // Unsigned higher Greater than, or
> unordered
> >> - LS = 0x9, // Unsigned lower or same Less than or equal
> >> - GE = 0xa, // Greater than or equal Greater than or equal
> >> - LT = 0xb, // Less than Less than, or unordered
> >> - GT = 0xc, // Greater than Greater than
> >> - LE = 0xd, // Less than or equal <, ==, or unordered
> >> - AL = 0xe, // Always (unconditional) Always (unconditional)
> >> - NV = 0xf, // Always (unconditional) Always (unconditional)
> >> - // Note the NV exists purely to disassemble 0b1111. Execution is
> "always".
> >> - Invalid
> >> -};
> >> -
> >> -inline static const char *getCondCodeName(CondCode Code) {
> >> - switch (Code) {
> >> - default: llvm_unreachable("Unknown condition code");
> >> - case EQ: return "eq";
> >> - case NE: return "ne";
> >> - case CS: return "cs";
> >> - case CC: return "cc";
> >> - case MI: return "mi";
> >> - case PL: return "pl";
> >> - case VS: return "vs";
> >> - case VC: return "vc";
> >> - case HI: return "hi";
> >> - case LS: return "ls";
> >> - case GE: return "ge";
> >> - case LT: return "lt";
> >> - case GT: return "gt";
> >> - case LE: return "le";
> >> - case AL: return "al";
> >> - case NV: return "nv";
> >> - }
> >> -}
> >> -
> >> -inline static CondCode getInvertedCondCode(CondCode Code) {
> >> - switch (Code) {
> >> - default: llvm_unreachable("Unknown condition code");
> >> - case EQ: return NE;
> >> - case NE: return EQ;
> >> - case CS: return CC;
> >> - case CC: return CS;
> >> - case MI: return PL;
> >> - case PL: return MI;
> >> - case VS: return VC;
> >> - case VC: return VS;
> >> - case HI: return LS;
> >> - case LS: return HI;
> >> - case GE: return LT;
> >> - case LT: return GE;
> >> - case GT: return LE;
> >> - case LE: return GT;
> >> - }
> >> -}
> >> -
> >> -/// Given a condition code, return NZCV flags that would satisfy that
> condition.
> >> -/// The flag bits are in the format expected by the ccmp instructions.
> >> -/// Note that many different flag settings can satisfy a given
> condition code,
> >> -/// this function just returns one of them.
> >> -inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
> >> - // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA
> 5.5.7.
> >> - enum { N = 8, Z = 4, C = 2, V = 1 };
> >> - switch (Code) {
> >> - default: llvm_unreachable("Unknown condition code");
> >> - case EQ: return Z; // Z == 1
> >> - case NE: return 0; // Z == 0
> >> - case CS: return C; // C == 1
> >> - case CC: return 0; // C == 0
> >> - case MI: return N; // N == 1
> >> - case PL: return 0; // N == 0
> >> - case VS: return V; // V == 1
> >> - case VC: return 0; // V == 0
> >> - case HI: return C; // C == 1 && Z == 0
> >> - case LS: return 0; // C == 0 || Z == 1
> >> - case GE: return 0; // N == V
> >> - case LT: return N; // N != V
> >> - case GT: return 0; // Z == 0 && N == V
> >> - case LE: return Z; // Z == 1 || N != V
> >> - }
> >> -}
> >> -} // end namespace ARM64CC
> >> -
> >> -namespace ARM64SYS {
> >> -enum BarrierOption {
> >> - InvalidBarrier = 0xff,
> >> - OSHLD = 0x1,
> >> - OSHST = 0x2,
> >> - OSH = 0x3,
> >> - NSHLD = 0x5,
> >> - NSHST = 0x6,
> >> - NSH = 0x7,
> >> - ISHLD = 0x9,
> >> - ISHST = 0xa,
> >> - ISH = 0xb,
> >> - LD = 0xd,
> >> - ST = 0xe,
> >> - SY = 0xf
> >> -};
> >> -
> >> -inline static const char *getBarrierOptName(BarrierOption Opt) {
> >> - switch (Opt) {
> >> - default: return NULL;
> >> - case 0x1: return "oshld";
> >> - case 0x2: return "oshst";
> >> - case 0x3: return "osh";
> >> - case 0x5: return "nshld";
> >> - case 0x6: return "nshst";
> >> - case 0x7: return "nsh";
> >> - case 0x9: return "ishld";
> >> - case 0xa: return "ishst";
> >> - case 0xb: return "ish";
> >> - case 0xd: return "ld";
> >> - case 0xe: return "st";
> >> - case 0xf: return "sy";
> >> - }
> >> -}
> >> -
> >> -#define A64_SYSREG_ENC(op0,CRn,op2,CRm,op1) ((op0) << 14 | (op1) << 11
> | \
> >> - (CRn) << 7 | (CRm) << 3
> | (op2))
> >> -enum SystemRegister {
> >> - InvalidSystemReg = 0,
> >> - // Table in section 3.10.3
> >> - SPSR_EL1 = 0xc200,
> >> - SPSR_svc = SPSR_EL1,
> >> - ELR_EL1 = 0xc201,
> >> - SP_EL0 = 0xc208,
> >> - SPSel = 0xc210,
> >> - CurrentEL = 0xc212,
> >> - DAIF = 0xda11,
> >> - NZCV = 0xda10,
> >> - FPCR = 0xda20,
> >> - FPSR = 0xda21,
> >> - DSPSR = 0xda28,
> >> - DLR = 0xda29,
> >> - SPSR_EL2 = 0xe200,
> >> - SPSR_hyp = SPSR_EL2,
> >> - ELR_EL2 = 0xe201,
> >> - SP_EL1 = 0xe208,
> >> - SPSR_irq = 0xe218,
> >> - SPSR_abt = 0xe219,
> >> - SPSR_und = 0xe21a,
> >> - SPSR_fiq = 0xe21b,
> >> - SPSR_EL3 = 0xf200,
> >> - ELR_EL3 = 0xf201,
> >> - SP_EL2 = 0xf208,
> >> -
> >> -
> >> - // Table in section 3.10.8
> >> - MIDR_EL1 = 0xc000,
> >> - CTR_EL0 = 0xd801,
> >> - MPIDR_EL1 = 0xc005,
> >> - ECOIDR_EL1 = 0xc006,
> >> - DCZID_EL0 = 0xd807,
> >> - MVFR0_EL1 = 0xc018,
> >> - MVFR1_EL1 = 0xc019,
> >> - ID_AA64PFR0_EL1 = 0xc020,
> >> - ID_AA64PFR1_EL1 = 0xc021,
> >> - ID_AA64DFR0_EL1 = 0xc028,
> >> - ID_AA64DFR1_EL1 = 0xc029,
> >> - ID_AA64ISAR0_EL1 = 0xc030,
> >> - ID_AA64ISAR1_EL1 = 0xc031,
> >> - ID_AA64MMFR0_EL1 = 0xc038,
> >> - ID_AA64MMFR1_EL1 = 0xc039,
> >> - CCSIDR_EL1 = 0xc800,
> >> - CLIDR_EL1 = 0xc801,
> >> - AIDR_EL1 = 0xc807,
> >> - CSSELR_EL1 = 0xd000,
> >> - VPIDR_EL2 = 0xe000,
> >> - VMPIDR_EL2 = 0xe005,
> >> - SCTLR_EL1 = 0xc080,
> >> - SCTLR_EL2 = 0xe080,
> >> - SCTLR_EL3 = 0xf080,
> >> - ACTLR_EL1 = 0xc081,
> >> - ACTLR_EL2 = 0xe081,
> >> - ACTLR_EL3 = 0xf081,
> >> - CPACR_EL1 = 0xc082,
> >> - CPTR_EL2 = 0xe08a,
> >> - CPTR_EL3 = 0xf08a,
> >> - SCR_EL3 = 0xf088,
> >> - HCR_EL2 = 0xe088,
> >> - MDCR_EL2 = 0xe089,
> >> - MDCR_EL3 = 0xf099,
> >> - HSTR_EL2 = 0xe08b,
> >> - HACR_EL2 = 0xe08f,
> >> - TTBR0_EL1 = 0xc100,
> >> - TTBR1_EL1 = 0xc101,
> >> - TTBR0_EL2 = 0xe100,
> >> - TTBR0_EL3 = 0xf100,
> >> - VTTBR_EL2 = 0xe108,
> >> - TCR_EL1 = 0xc102,
> >> - TCR_EL2 = 0xe102,
> >> - TCR_EL3 = 0xf102,
> >> - VTCR_EL2 = 0xe10a,
> >> - ADFSR_EL1 = 0xc288,
> >> - AIFSR_EL1 = 0xc289,
> >> - ADFSR_EL2 = 0xe288,
> >> - AIFSR_EL2 = 0xe289,
> >> - ADFSR_EL3 = 0xf288,
> >> - AIFSR_EL3 = 0xf289,
> >> - ESR_EL1 = 0xc290,
> >> - ESR_EL2 = 0xe290,
> >> - ESR_EL3 = 0xf290,
> >> - FAR_EL1 = 0xc300,
> >> - FAR_EL2 = 0xe300,
> >> - FAR_EL3 = 0xf300,
> >> - HPFAR_EL2 = 0xe304,
> >> - PAR_EL1 = 0xc3a0,
> >> - MAIR_EL1 = 0xc510,
> >> - MAIR_EL2 = 0xe510,
> >> - MAIR_EL3 = 0xf510,
> >> - AMAIR_EL1 = 0xc518,
> >> - AMAIR_EL2 = 0xe518,
> >> - AMAIR_EL3 = 0xf518,
> >> - VBAR_EL1 = 0xc600,
> >> - VBAR_EL2 = 0xe600,
> >> - VBAR_EL3 = 0xf600,
> >> - RVBAR_EL1 = 0xc601,
> >> - RVBAR_EL2 = 0xe601,
> >> - RVBAR_EL3 = 0xf601,
> >> - ISR_EL1 = 0xc608,
> >> - CONTEXTIDR_EL1 = 0xc681,
> >> - TPIDR_EL0 = 0xde82,
> >> - TPIDRRO_EL0 = 0xde83,
> >> - TPIDR_EL1 = 0xc684,
> >> - TPIDR_EL2 = 0xe682,
> >> - TPIDR_EL3 = 0xf682,
> >> - TEECR32_EL1 = 0x9000,
> >> - CNTFRQ_EL0 = 0xdf00,
> >> - CNTPCT_EL0 = 0xdf01,
> >> - CNTVCT_EL0 = 0xdf02,
> >> - CNTVOFF_EL2 = 0xe703,
> >> - CNTKCTL_EL1 = 0xc708,
> >> - CNTHCTL_EL2 = 0xe708,
> >> - CNTP_TVAL_EL0 = 0xdf10,
> >> - CNTP_CTL_EL0 = 0xdf11,
> >> - CNTP_CVAL_EL0 = 0xdf12,
> >> - CNTV_TVAL_EL0 = 0xdf18,
> >> - CNTV_CTL_EL0 = 0xdf19,
> >> - CNTV_CVAL_EL0 = 0xdf1a,
> >> - CNTHP_TVAL_EL2 = 0xe710,
> >> - CNTHP_CTL_EL2 = 0xe711,
> >> - CNTHP_CVAL_EL2 = 0xe712,
> >> - CNTPS_TVAL_EL1 = 0xff10,
> >> - CNTPS_CTL_EL1 = 0xff11,
> >> - CNTPS_CVAL_EL1= 0xff12,
> >> -
> >> - PMEVCNTR0_EL0 = 0xdf40,
> >> - PMEVCNTR1_EL0 = 0xdf41,
> >> - PMEVCNTR2_EL0 = 0xdf42,
> >> - PMEVCNTR3_EL0 = 0xdf43,
> >> - PMEVCNTR4_EL0 = 0xdf44,
> >> - PMEVCNTR5_EL0 = 0xdf45,
> >> - PMEVCNTR6_EL0 = 0xdf46,
> >> - PMEVCNTR7_EL0 = 0xdf47,
> >> - PMEVCNTR8_EL0 = 0xdf48,
> >> - PMEVCNTR9_EL0 = 0xdf49,
> >> - PMEVCNTR10_EL0 = 0xdf4a,
> >> - PMEVCNTR11_EL0 = 0xdf4b,
> >> - PMEVCNTR12_EL0 = 0xdf4c,
> >> - PMEVCNTR13_EL0 = 0xdf4d,
> >> - PMEVCNTR14_EL0 = 0xdf4e,
> >> - PMEVCNTR15_EL0 = 0xdf4f,
> >> - PMEVCNTR16_EL0 = 0xdf50,
> >> - PMEVCNTR17_EL0 = 0xdf51,
> >> - PMEVCNTR18_EL0 = 0xdf52,
> >> - PMEVCNTR19_EL0 = 0xdf53,
> >> - PMEVCNTR20_EL0 = 0xdf54,
> >> - PMEVCNTR21_EL0 = 0xdf55,
> >> - PMEVCNTR22_EL0 = 0xdf56,
> >> - PMEVCNTR23_EL0 = 0xdf57,
> >> - PMEVCNTR24_EL0 = 0xdf58,
> >> - PMEVCNTR25_EL0 = 0xdf59,
> >> - PMEVCNTR26_EL0 = 0xdf5a,
> >> - PMEVCNTR27_EL0 = 0xdf5b,
> >> - PMEVCNTR28_EL0 = 0xdf5c,
> >> - PMEVCNTR29_EL0 = 0xdf5d,
> >> - PMEVCNTR30_EL0 = 0xdf5e,
> >> -
> >> - PMEVTYPER0_EL0 = 0xdf60,
> >> - PMEVTYPER1_EL0 = 0xdf61,
> >> - PMEVTYPER2_EL0 = 0xdf62,
> >> - PMEVTYPER3_EL0 = 0xdf63,
> >> - PMEVTYPER4_EL0 = 0xdf64,
> >> - PMEVTYPER5_EL0 = 0xdf65,
> >> - PMEVTYPER6_EL0 = 0xdf66,
> >> - PMEVTYPER7_EL0 = 0xdf67,
> >> - PMEVTYPER8_EL0 = 0xdf68,
> >> - PMEVTYPER9_EL0 = 0xdf69,
> >> - PMEVTYPER10_EL0 = 0xdf6a,
> >> - PMEVTYPER11_EL0 = 0xdf6b,
> >> - PMEVTYPER12_EL0 = 0xdf6c,
> >> - PMEVTYPER13_EL0 = 0xdf6d,
> >> - PMEVTYPER14_EL0 = 0xdf6e,
> >> - PMEVTYPER15_EL0 = 0xdf6f,
> >> - PMEVTYPER16_EL0 = 0xdf70,
> >> - PMEVTYPER17_EL0 = 0xdf71,
> >> - PMEVTYPER18_EL0 = 0xdf72,
> >> - PMEVTYPER19_EL0 = 0xdf73,
> >> - PMEVTYPER20_EL0 = 0xdf74,
> >> - PMEVTYPER21_EL0 = 0xdf75,
> >> - PMEVTYPER22_EL0 = 0xdf76,
> >> - PMEVTYPER23_EL0 = 0xdf77,
> >> - PMEVTYPER24_EL0 = 0xdf78,
> >> - PMEVTYPER25_EL0 = 0xdf79,
> >> - PMEVTYPER26_EL0 = 0xdf7a,
> >> - PMEVTYPER27_EL0 = 0xdf7b,
> >> - PMEVTYPER28_EL0 = 0xdf7c,
> >> - PMEVTYPER29_EL0 = 0xdf7d,
> >> - PMEVTYPER30_EL0 = 0xdf7e,
> >> -
> >> - PMCCFILTR_EL0 = 0xdf7f,
> >> -
> >> - RMR_EL3 = 0xf602,
> >> - RMR_EL2 = 0xd602,
> >> - RMR_EL1 = 0xce02,
> >> -
> >> - // Debug Architecture 5.3, Table 17.
> >> - MDCCSR_EL0 = A64_SYSREG_ENC(2, 0, 0, 1, 3),
> >> - MDCCINT_EL1 = A64_SYSREG_ENC(2, 0, 0, 2, 0),
> >> - DBGDTR_EL0 = A64_SYSREG_ENC(2, 0, 0, 4, 3),
> >> - DBGDTRRX_EL0 = A64_SYSREG_ENC(2, 0, 0, 5, 3),
> >> - DBGDTRTX_EL0 = DBGDTRRX_EL0,
> >> - DBGVCR32_EL2 = A64_SYSREG_ENC(2, 0, 0, 7, 4),
> >> - OSDTRRX_EL1 = A64_SYSREG_ENC(2, 0, 2, 0, 0),
> >> - MDSCR_EL1 = A64_SYSREG_ENC(2, 0, 2, 2, 0),
> >> - OSDTRTX_EL1 = A64_SYSREG_ENC(2, 0, 2, 3, 0),
> >> - OSECCR_EL11 = A64_SYSREG_ENC(2, 0, 2, 6, 0),
> >> -
> >> - DBGBVR0_EL1 = A64_SYSREG_ENC(2, 0, 4, 0, 0),
> >> - DBGBVR1_EL1 = A64_SYSREG_ENC(2, 0, 4, 1, 0),
> >> - DBGBVR2_EL1 = A64_SYSREG_ENC(2, 0, 4, 2, 0),
> >> - DBGBVR3_EL1 = A64_SYSREG_ENC(2, 0, 4, 3, 0),
> >> - DBGBVR4_EL1 = A64_SYSREG_ENC(2, 0, 4, 4, 0),
> >> - DBGBVR5_EL1 = A64_SYSREG_ENC(2, 0, 4, 5, 0),
> >> - DBGBVR6_EL1 = A64_SYSREG_ENC(2, 0, 4, 6, 0),
> >> - DBGBVR7_EL1 = A64_SYSREG_ENC(2, 0, 4, 7, 0),
> >> - DBGBVR8_EL1 = A64_SYSREG_ENC(2, 0, 4, 8, 0),
> >> - DBGBVR9_EL1 = A64_SYSREG_ENC(2, 0, 4, 9, 0),
> >> - DBGBVR10_EL1 = A64_SYSREG_ENC(2, 0, 4, 10, 0),
> >> - DBGBVR11_EL1 = A64_SYSREG_ENC(2, 0, 4, 11, 0),
> >> - DBGBVR12_EL1 = A64_SYSREG_ENC(2, 0, 4, 12, 0),
> >> - DBGBVR13_EL1 = A64_SYSREG_ENC(2, 0, 4, 13, 0),
> >> - DBGBVR14_EL1 = A64_SYSREG_ENC(2, 0, 4, 14, 0),
> >> - DBGBVR15_EL1 = A64_SYSREG_ENC(2, 0, 4, 15, 0),
> >> -
> >> - DBGBCR0_EL1 = A64_SYSREG_ENC(2, 0, 5, 0, 0),
> >> - DBGBCR1_EL1 = A64_SYSREG_ENC(2, 0, 5, 1, 0),
> >> - DBGBCR2_EL1 = A64_SYSREG_ENC(2, 0, 5, 2, 0),
> >> - DBGBCR3_EL1 = A64_SYSREG_ENC(2, 0, 5, 3, 0),
> >> - DBGBCR4_EL1 = A64_SYSREG_ENC(2, 0, 5, 4, 0),
> >> - DBGBCR5_EL1 = A64_SYSREG_ENC(2, 0, 5, 5, 0),
> >> - DBGBCR6_EL1 = A64_SYSREG_ENC(2, 0, 5, 6, 0),
> >> - DBGBCR7_EL1 = A64_SYSREG_ENC(2, 0, 5, 7, 0),
> >> - DBGBCR8_EL1 = A64_SYSREG_ENC(2, 0, 5, 8, 0),
> >> - DBGBCR9_EL1 = A64_SYSREG_ENC(2, 0, 5, 9, 0),
> >> - DBGBCR10_EL1 = A64_SYSREG_ENC(2, 0, 5, 10, 0),
> >> - DBGBCR11_EL1 = A64_SYSREG_ENC(2, 0, 5, 11, 0),
> >> - DBGBCR12_EL1 = A64_SYSREG_ENC(2, 0, 5, 12, 0),
> >> - DBGBCR13_EL1 = A64_SYSREG_ENC(2, 0, 5, 13, 0),
> >> - DBGBCR14_EL1 = A64_SYSREG_ENC(2, 0, 5, 14, 0),
> >> - DBGBCR15_EL1 = A64_SYSREG_ENC(2, 0, 5, 15, 0),
> >> -
> >> - DBGWVR0_EL1 = A64_SYSREG_ENC(2, 0, 6, 0, 0),
> >> - DBGWVR1_EL1 = A64_SYSREG_ENC(2, 0, 6, 1, 0),
> >> - DBGWVR2_EL1 = A64_SYSREG_ENC(2, 0, 6, 2, 0),
> >> - DBGWVR3_EL1 = A64_SYSREG_ENC(2, 0, 6, 3, 0),
> >> - DBGWVR4_EL1 = A64_SYSREG_ENC(2, 0, 6, 4, 0),
> >> - DBGWVR5_EL1 = A64_SYSREG_ENC(2, 0, 6, 5, 0),
> >> - DBGWVR6_EL1 = A64_SYSREG_ENC(2, 0, 6, 6, 0),
> >> - DBGWVR7_EL1 = A64_SYSREG_ENC(2, 0, 6, 7, 0),
> >> - DBGWVR8_EL1 = A64_SYSREG_ENC(2, 0, 6, 8, 0),
> >> - DBGWVR9_EL1 = A64_SYSREG_ENC(2, 0, 6, 9, 0),
> >> - DBGWVR10_EL1 = A64_SYSREG_ENC(2, 0, 6, 10, 0),
> >> - DBGWVR11_EL1 = A64_SYSREG_ENC(2, 0, 6, 11, 0),
> >> - DBGWVR12_EL1 = A64_SYSREG_ENC(2, 0, 6, 12, 0),
> >> - DBGWVR13_EL1 = A64_SYSREG_ENC(2, 0, 6, 13, 0),
> >> - DBGWVR14_EL1 = A64_SYSREG_ENC(2, 0, 6, 14, 0),
> >> - DBGWVR15_EL1 = A64_SYSREG_ENC(2, 0, 6, 15, 0),
> >> -
> >> - DBGWCR0_EL1 = A64_SYSREG_ENC(2, 0, 7, 0, 0),
> >> - DBGWCR1_EL1 = A64_SYSREG_ENC(2, 0, 7, 1, 0),
> >> - DBGWCR2_EL1 = A64_SYSREG_ENC(2, 0, 7, 2, 0),
> >> - DBGWCR3_EL1 = A64_SYSREG_ENC(2, 0, 7, 3, 0),
> >> - DBGWCR4_EL1 = A64_SYSREG_ENC(2, 0, 7, 4, 0),
> >> - DBGWCR5_EL1 = A64_SYSREG_ENC(2, 0, 7, 5, 0),
> >> - DBGWCR6_EL1 = A64_SYSREG_ENC(2, 0, 7, 6, 0),
> >> - DBGWCR7_EL1 = A64_SYSREG_ENC(2, 0, 7, 7, 0),
> >> - DBGWCR8_EL1 = A64_SYSREG_ENC(2, 0, 7, 8, 0),
> >> - DBGWCR9_EL1 = A64_SYSREG_ENC(2, 0, 7, 9, 0),
> >> - DBGWCR10_EL1 = A64_SYSREG_ENC(2, 0, 7, 10, 0),
> >> - DBGWCR11_EL1 = A64_SYSREG_ENC(2, 0, 7, 11, 0),
> >> - DBGWCR12_EL1 = A64_SYSREG_ENC(2, 0, 7, 12, 0),
> >> - DBGWCR13_EL1 = A64_SYSREG_ENC(2, 0, 7, 13, 0),
> >> - DBGWCR14_EL1 = A64_SYSREG_ENC(2, 0, 7, 14, 0),
> >> - DBGWCR15_EL1 = A64_SYSREG_ENC(2, 0, 7, 15, 0),
> >> -
> >> - MDRAR_EL1 = A64_SYSREG_ENC(2, 1, 0, 0, 0),
> >> - OSLAR_EL1 = A64_SYSREG_ENC(2, 1, 4, 0, 0),
> >> - OSLSR_EL1 = A64_SYSREG_ENC(2, 1, 4, 1, 0),
> >> - OSDLR_EL1 = A64_SYSREG_ENC(2, 1, 4, 3, 0),
> >> - DBGPRCR_EL1 = A64_SYSREG_ENC(2, 1, 4, 4, 0),
> >> -
> >> - DBGCLAIMSET_EL1 = A64_SYSREG_ENC(2, 7, 6, 8, 0),
> >> - DBGCLAIMCLR_EL1 = A64_SYSREG_ENC(2, 7, 6, 9, 0),
> >> - DBGAUTHSTATUS_EL1 = A64_SYSREG_ENC(2, 7, 6, 14, 0),
> >> -
> >> - DBGDEVID2 = A64_SYSREG_ENC(2, 7, 7, 0, 0),
> >> - DBGDEVID1 = A64_SYSREG_ENC(2, 7, 7, 1, 0),
> >> - DBGDEVID0 = A64_SYSREG_ENC(2, 7, 7, 2, 0),
> >> -
> >> - // The following registers are defined to allow access from AArch64
> to
> >> - // registers which are only used in the AArch32 architecture.
> >> - DACR32_EL2 = 0xe180,
> >> - IFSR32_EL2 = 0xe281,
> >> - TEEHBR32_EL1 = 0x9080,
> >> - SDER32_EL3 = 0xf089,
> >> - FPEXC32_EL2 = 0xe298,
> >> -
> >> - // Cyclone specific system registers
> >> - CPM_IOACC_CTL_EL3 = 0xff90,
> >> -
> >> - // Architectural system registers
> >> - ID_PFR0_EL1 = 0xc008,
> >> - ID_PFR1_EL1 = 0xc009,
> >> - ID_DFR0_EL1 = 0xc00a,
> >> - ID_AFR0_EL1 = 0xc00b,
> >> - ID_ISAR0_EL1 = 0xc010,
> >> - ID_ISAR1_EL1 = 0xc011,
> >> - ID_ISAR2_EL1 = 0xc012,
> >> - ID_ISAR3_EL1 = 0xc013,
> >> - ID_ISAR4_EL1 = 0xc014,
> >> - ID_ISAR5_EL1 = 0xc015,
> >> - AFSR1_EL1 = 0xc289, // note same as old AIFSR_EL1
> >> - AFSR0_EL1 = 0xc288, // note same as old ADFSR_EL1
> >> - REVIDR_EL1 = 0xc006 // note same as old ECOIDR_EL1
> >> -
> >> -};
> >> -#undef A64_SYSREG_ENC
> >> -
> >> -static inline const char *getSystemRegisterName(SystemRegister Reg) {
> >> - switch(Reg) {
> >> - default: return NULL; // Caller is responsible for handling invalid
> value.
> >> - case SPSR_EL1: return "SPSR_EL1";
> >> - case ELR_EL1: return "ELR_EL1";
> >> - case SP_EL0: return "SP_EL0";
> >> - case SPSel: return "SPSel";
> >> - case DAIF: return "DAIF";
> >> - case CurrentEL: return "CurrentEL";
> >> - case NZCV: return "NZCV";
> >> - case FPCR: return "FPCR";
> >> - case FPSR: return "FPSR";
> >> - case DSPSR: return "DSPSR";
> >> - case DLR: return "DLR";
> >> - case SPSR_EL2: return "SPSR_EL2";
> >> - case ELR_EL2: return "ELR_EL2";
> >> - case SP_EL1: return "SP_EL1";
> >> - case SPSR_irq: return "SPSR_irq";
> >> - case SPSR_abt: return "SPSR_abt";
> >> - case SPSR_und: return "SPSR_und";
> >> - case SPSR_fiq: return "SPSR_fiq";
> >> - case SPSR_EL3: return "SPSR_EL3";
> >> - case ELR_EL3: return "ELR_EL3";
> >> - case SP_EL2: return "SP_EL2";
> >> - case MIDR_EL1: return "MIDR_EL1";
> >> - case CTR_EL0: return "CTR_EL0";
> >> - case MPIDR_EL1: return "MPIDR_EL1";
> >> - case DCZID_EL0: return "DCZID_EL0";
> >> - case MVFR0_EL1: return "MVFR0_EL1";
> >> - case MVFR1_EL1: return "MVFR1_EL1";
> >> - case ID_AA64PFR0_EL1: return "ID_AA64PFR0_EL1";
> >> - case ID_AA64PFR1_EL1: return "ID_AA64PFR1_EL1";
> >> - case ID_AA64DFR0_EL1: return "ID_AA64DFR0_EL1";
> >> - case ID_AA64DFR1_EL1: return "ID_AA64DFR1_EL1";
> >> - case ID_AA64ISAR0_EL1: return "ID_AA64ISAR0_EL1";
> >> - case ID_AA64ISAR1_EL1: return "ID_AA64ISAR1_EL1";
> >> - case ID_AA64MMFR0_EL1: return "ID_AA64MMFR0_EL1";
> >> - case ID_AA64MMFR1_EL1: return "ID_AA64MMFR1_EL1";
> >> - case CCSIDR_EL1: return "CCSIDR_EL1";
> >> - case CLIDR_EL1: return "CLIDR_EL1";
> >> - case AIDR_EL1: return "AIDR_EL1";
> >> - case CSSELR_EL1: return "CSSELR_EL1";
> >> - case VPIDR_EL2: return "VPIDR_EL2";
> >> - case VMPIDR_EL2: return "VMPIDR_EL2";
> >> - case SCTLR_EL1: return "SCTLR_EL1";
> >> - case SCTLR_EL2: return "SCTLR_EL2";
> >> - case SCTLR_EL3: return "SCTLR_EL3";
> >> - case ACTLR_EL1: return "ACTLR_EL1";
> >> - case ACTLR_EL2: return "ACTLR_EL2";
> >> - case ACTLR_EL3: return "ACTLR_EL3";
> >> - case CPACR_EL1: return "CPACR_EL1";
> >> - case CPTR_EL2: return "CPTR_EL2";
> >> - case CPTR_EL3: return "CPTR_EL3";
> >> - case SCR_EL3: return "SCR_EL3";
> >> - case HCR_EL2: return "HCR_EL2";
> >> - case MDCR_EL2: return "MDCR_EL2";
> >> - case MDCR_EL3: return "MDCR_EL3";
> >> - case HSTR_EL2: return "HSTR_EL2";
> >> - case HACR_EL2: return "HACR_EL2";
> >> - case TTBR0_EL1: return "TTBR0_EL1";
> >> - case TTBR1_EL1: return "TTBR1_EL1";
> >> - case TTBR0_EL2: return "TTBR0_EL2";
> >> - case TTBR0_EL3: return "TTBR0_EL3";
> >> - case VTTBR_EL2: return "VTTBR_EL2";
> >> - case TCR_EL1: return "TCR_EL1";
> >> - case TCR_EL2: return "TCR_EL2";
> >> - case TCR_EL3: return "TCR_EL3";
> >> - case VTCR_EL2: return "VTCR_EL2";
> >> - case ADFSR_EL2: return "ADFSR_EL2";
> >> - case AIFSR_EL2: return "AIFSR_EL2";
> >> - case ADFSR_EL3: return "ADFSR_EL3";
> >> - case AIFSR_EL3: return "AIFSR_EL3";
> >> - case ESR_EL1: return "ESR_EL1";
> >> - case ESR_EL2: return "ESR_EL2";
> >> - case ESR_EL3: return "ESR_EL3";
> >> - case FAR_EL1: return "FAR_EL1";
> >> - case FAR_EL2: return "FAR_EL2";
> >> - case FAR_EL3: return "FAR_EL3";
> >> - case HPFAR_EL2: return "HPFAR_EL2";
> >> - case PAR_EL1: return "PAR_EL1";
> >> - case MAIR_EL1: return "MAIR_EL1";
> >> - case MAIR_EL2: return "MAIR_EL2";
> >> - case MAIR_EL3: return "MAIR_EL3";
> >> - case AMAIR_EL1: return "AMAIR_EL1";
> >> - case AMAIR_EL2: return "AMAIR_EL2";
> >> - case AMAIR_EL3: return "AMAIR_EL3";
> >> - case VBAR_EL1: return "VBAR_EL1";
> >> - case VBAR_EL2: return "VBAR_EL2";
> >> - case VBAR_EL3: return "VBAR_EL3";
> >> - case RVBAR_EL1: return "RVBAR_EL1";
> >> - case RVBAR_EL2: return "RVBAR_EL2";
> >> - case RVBAR_EL3: return "RVBAR_EL3";
> >> - case ISR_EL1: return "ISR_EL1";
> >> - case CONTEXTIDR_EL1: return "CONTEXTIDR_EL1";
> >> - case TPIDR_EL0: return "TPIDR_EL0";
> >> - case TPIDRRO_EL0: return "TPIDRRO_EL0";
> >> - case TPIDR_EL1: return "TPIDR_EL1";
> >> - case TPIDR_EL2: return "TPIDR_EL2";
> >> - case TPIDR_EL3: return "TPIDR_EL3";
> >> - case TEECR32_EL1: return "TEECR32_EL1";
> >> - case CNTFRQ_EL0: return "CNTFRQ_EL0";
> >> - case CNTPCT_EL0: return "CNTPCT_EL0";
> >> - case CNTVCT_EL0: return "CNTVCT_EL0";
> >> - case CNTVOFF_EL2: return "CNTVOFF_EL2";
> >> - case CNTKCTL_EL1: return "CNTKCTL_EL1";
> >> - case CNTHCTL_EL2: return "CNTHCTL_EL2";
> >> - case CNTP_TVAL_EL0: return "CNTP_TVAL_EL0";
> >> - case CNTP_CTL_EL0: return "CNTP_CTL_EL0";
> >> - case CNTP_CVAL_EL0: return "CNTP_CVAL_EL0";
> >> - case CNTV_TVAL_EL0: return "CNTV_TVAL_EL0";
> >> - case CNTV_CTL_EL0: return "CNTV_CTL_EL0";
> >> - case CNTV_CVAL_EL0: return "CNTV_CVAL_EL0";
> >> - case CNTHP_TVAL_EL2: return "CNTHP_TVAL_EL2";
> >> - case CNTHP_CTL_EL2: return "CNTHP_CTL_EL2";
> >> - case CNTHP_CVAL_EL2: return "CNTHP_CVAL_EL2";
> >> - case CNTPS_TVAL_EL1: return "CNTPS_TVAL_EL1";
> >> - case CNTPS_CTL_EL1: return "CNTPS_CTL_EL1";
> >> - case CNTPS_CVAL_EL1: return "CNTPS_CVAL_EL1";
> >> - case DACR32_EL2: return "DACR32_EL2";
> >> - case IFSR32_EL2: return "IFSR32_EL2";
> >> - case TEEHBR32_EL1: return "TEEHBR32_EL1";
> >> - case SDER32_EL3: return "SDER32_EL3";
> >> - case FPEXC32_EL2: return "FPEXC32_EL2";
> >> - case PMEVCNTR0_EL0: return "PMEVCNTR0_EL0";
> >> - case PMEVCNTR1_EL0: return "PMEVCNTR1_EL0";
> >> - case PMEVCNTR2_EL0: return "PMEVCNTR2_EL0";
> >> - case PMEVCNTR3_EL0: return "PMEVCNTR3_EL0";
> >> - case PMEVCNTR4_EL0: return "PMEVCNTR4_EL0";
> >> - case PMEVCNTR5_EL0: return "PMEVCNTR5_EL0";
> >> - case PMEVCNTR6_EL0: return "PMEVCNTR6_EL0";
> >> - case PMEVCNTR7_EL0: return "PMEVCNTR7_EL0";
> >> - case PMEVCNTR8_EL0: return "PMEVCNTR8_EL0";
> >> - case PMEVCNTR9_EL0: return "PMEVCNTR9_EL0";
> >> - case PMEVCNTR10_EL0: return "PMEVCNTR10_EL0";
> >> - case PMEVCNTR11_EL0: return "PMEVCNTR11_EL0";
> >> - case PMEVCNTR12_EL0: return "PMEVCNTR12_EL0";
> >> - case PMEVCNTR13_EL0: return "PMEVCNTR13_EL0";
> >> - case PMEVCNTR14_EL0: return "PMEVCNTR14_EL0";
> >> - case PMEVCNTR15_EL0: return "PMEVCNTR15_EL0";
> >> - case PMEVCNTR16_EL0: return "PMEVCNTR16_EL0";
> >> - case PMEVCNTR17_EL0: return "PMEVCNTR17_EL0";
> >> - case PMEVCNTR18_EL0: return "PMEVCNTR18_EL0";
> >> - case PMEVCNTR19_EL0: return "PMEVCNTR19_EL0";
> >> - case PMEVCNTR20_EL0: return "PMEVCNTR20_EL0";
> >> - case PMEVCNTR21_EL0: return "PMEVCNTR21_EL0";
> >> - case PMEVCNTR22_EL0: return "PMEVCNTR22_EL0";
> >> - case PMEVCNTR23_EL0: return "PMEVCNTR23_EL0";
> >> - case PMEVCNTR24_EL0: return "PMEVCNTR24_EL0";
> >> - case PMEVCNTR25_EL0: return "PMEVCNTR25_EL0";
> >> - case PMEVCNTR26_EL0: return "PMEVCNTR26_EL0";
> >> - case PMEVCNTR27_EL0: return "PMEVCNTR27_EL0";
> >> - case PMEVCNTR28_EL0: return "PMEVCNTR28_EL0";
> >> - case PMEVCNTR29_EL0: return "PMEVCNTR29_EL0";
> >> - case PMEVCNTR30_EL0: return "PMEVCNTR30_EL0";
> >> - case PMEVTYPER0_EL0: return "PMEVTYPER0_EL0";
> >> - case PMEVTYPER1_EL0: return "PMEVTYPER1_EL0";
> >> - case PMEVTYPER2_EL0: return "PMEVTYPER2_EL0";
> >> - case PMEVTYPER3_EL0: return "PMEVTYPER3_EL0";
> >> - case PMEVTYPER4_EL0: return "PMEVTYPER4_EL0";
> >> - case PMEVTYPER5_EL0: return "PMEVTYPER5_EL0";
> >> - case PMEVTYPER6_EL0: return "PMEVTYPER6_EL0";
> >> - case PMEVTYPER7_EL0: return "PMEVTYPER7_EL0";
> >> - case PMEVTYPER8_EL0: return "PMEVTYPER8_EL0";
> >> - case PMEVTYPER9_EL0: return "PMEVTYPER9_EL0";
> >> - case PMEVTYPER10_EL0: return "PMEVTYPER10_EL0";
> >> - case PMEVTYPER11_EL0: return "PMEVTYPER11_EL0";
> >> - case PMEVTYPER12_EL0: return "PMEVTYPER12_EL0";
> >> - case PMEVTYPER13_EL0: return "PMEVTYPER13_EL0";
> >> - case PMEVTYPER14_EL0: return "PMEVTYPER14_EL0";
> >> - case PMEVTYPER15_EL0: return "PMEVTYPER15_EL0";
> >> - case PMEVTYPER16_EL0: return "PMEVTYPER16_EL0";
> >> - case PMEVTYPER17_EL0: return "PMEVTYPER17_EL0";
> >> - case PMEVTYPER18_EL0: return "PMEVTYPER18_EL0";
> >> - case PMEVTYPER19_EL0: return "PMEVTYPER19_EL0";
> >> - case PMEVTYPER20_EL0: return "PMEVTYPER20_EL0";
> >> - case PMEVTYPER21_EL0: return "PMEVTYPER21_EL0";
> >> - case PMEVTYPER22_EL0: return "PMEVTYPER22_EL0";
> >> - case PMEVTYPER23_EL0: return "PMEVTYPER23_EL0";
> >> - case PMEVTYPER24_EL0: return "PMEVTYPER24_EL0";
> >> - case PMEVTYPER25_EL0: return "PMEVTYPER25_EL0";
> >> - case PMEVTYPER26_EL0: return "PMEVTYPER26_EL0";
> >> - case PMEVTYPER27_EL0: return "PMEVTYPER27_EL0";
> >> - case PMEVTYPER28_EL0: return "PMEVTYPER28_EL0";
> >> - case PMEVTYPER29_EL0: return "PMEVTYPER29_EL0";
> >> - case PMEVTYPER30_EL0: return "PMEVTYPER30_EL0";
> >> - case PMCCFILTR_EL0: return "PMCCFILTR_EL0";
> >> - case RMR_EL3: return "RMR_EL3";
> >> - case RMR_EL2: return "RMR_EL2";
> >> - case RMR_EL1: return "RMR_EL1";
> >> - case CPM_IOACC_CTL_EL3: return "CPM_IOACC_CTL_EL3";
> >> - case MDCCSR_EL0: return "MDCCSR_EL0";
> >> - case MDCCINT_EL1: return "MDCCINT_EL1";
> >> - case DBGDTR_EL0: return "DBGDTR_EL0";
> >> - case DBGDTRRX_EL0: return "DBGDTRRX_EL0";
> >> - case DBGVCR32_EL2: return "DBGVCR32_EL2";
> >> - case OSDTRRX_EL1: return "OSDTRRX_EL1";
> >> - case MDSCR_EL1: return "MDSCR_EL1";
> >> - case OSDTRTX_EL1: return "OSDTRTX_EL1";
> >> - case OSECCR_EL11: return "OSECCR_EL11";
> >> - case DBGBVR0_EL1: return "DBGBVR0_EL1";
> >> - case DBGBVR1_EL1: return "DBGBVR1_EL1";
> >> - case DBGBVR2_EL1: return "DBGBVR2_EL1";
> >> - case DBGBVR3_EL1: return "DBGBVR3_EL1";
> >> - case DBGBVR4_EL1: return "DBGBVR4_EL1";
> >> - case DBGBVR5_EL1: return "DBGBVR5_EL1";
> >> - case DBGBVR6_EL1: return "DBGBVR6_EL1";
> >> - case DBGBVR7_EL1: return "DBGBVR7_EL1";
> >> - case DBGBVR8_EL1: return "DBGBVR8_EL1";
> >> - case DBGBVR9_EL1: return "DBGBVR9_EL1";
> >> - case DBGBVR10_EL1: return "DBGBVR10_EL1";
> >> - case DBGBVR11_EL1: return "DBGBVR11_EL1";
> >> - case DBGBVR12_EL1: return "DBGBVR12_EL1";
> >> - case DBGBVR13_EL1: return "DBGBVR13_EL1";
> >> - case DBGBVR14_EL1: return "DBGBVR14_EL1";
> >> - case DBGBVR15_EL1: return "DBGBVR15_EL1";
> >> - case DBGBCR0_EL1: return "DBGBCR0_EL1";
> >> - case DBGBCR1_EL1: return "DBGBCR1_EL1";
> >> - case DBGBCR2_EL1: return "DBGBCR2_EL1";
> >> - case DBGBCR3_EL1: return "DBGBCR3_EL1";
> >> - case DBGBCR4_EL1: return "DBGBCR4_EL1";
> >> - case DBGBCR5_EL1: return "DBGBCR5_EL1";
> >> - case DBGBCR6_EL1: return "DBGBCR6_EL1";
> >> - case DBGBCR7_EL1: return "DBGBCR7_EL1";
> >> - case DBGBCR8_EL1: return "DBGBCR8_EL1";
> >> - case DBGBCR9_EL1: return "DBGBCR9_EL1";
> >> - case DBGBCR10_EL1: return "DBGBCR10_EL1";
> >> - case DBGBCR11_EL1: return "DBGBCR11_EL1";
> >> - case DBGBCR12_EL1: return "DBGBCR12_EL1";
> >> - case DBGBCR13_EL1: return "DBGBCR13_EL1";
> >> - case DBGBCR14_EL1: return "DBGBCR14_EL1";
> >> - case DBGBCR15_EL1: return "DBGBCR15_EL1";
> >> - case DBGWVR0_EL1: return "DBGWVR0_EL1";
> >> - case DBGWVR1_EL1: return "DBGWVR1_EL1";
> >> - case DBGWVR2_EL1: return "DBGWVR2_EL1";
> >> - case DBGWVR3_EL1: return "DBGWVR3_EL1";
> >> - case DBGWVR4_EL1: return "DBGWVR4_EL1";
> >> - case DBGWVR5_EL1: return "DBGWVR5_EL1";
> >> - case DBGWVR6_EL1: return "DBGWVR6_EL1";
> >> - case DBGWVR7_EL1: return "DBGWVR7_EL1";
> >> - case DBGWVR8_EL1: return "DBGWVR8_EL1";
> >> - case DBGWVR9_EL1: return "DBGWVR9_EL1";
> >> - case DBGWVR10_EL1: return "DBGWVR10_EL1";
> >> - case DBGWVR11_EL1: return "DBGWVR11_EL1";
> >> - case DBGWVR12_EL1: return "DBGWVR12_EL1";
> >> - case DBGWVR13_EL1: return "DBGWVR13_EL1";
> >> - case DBGWVR14_EL1: return "DBGWVR14_EL1";
> >> - case DBGWVR15_EL1: return "DBGWVR15_EL1";
> >> - case DBGWCR0_EL1: return "DBGWCR0_EL1";
> >> - case DBGWCR1_EL1: return "DBGWCR1_EL1";
> >> - case DBGWCR2_EL1: return "DBGWCR2_EL1";
> >> - case DBGWCR3_EL1: return "DBGWCR3_EL1";
> >> - case DBGWCR4_EL1: return "DBGWCR4_EL1";
> >> - case DBGWCR5_EL1: return "DBGWCR5_EL1";
> >> - case DBGWCR6_EL1: return "DBGWCR6_EL1";
> >> - case DBGWCR7_EL1: return "DBGWCR7_EL1";
> >> - case DBGWCR8_EL1: return "DBGWCR8_EL1";
> >> - case DBGWCR9_EL1: return "DBGWCR9_EL1";
> >> - case DBGWCR10_EL1: return "DBGWCR10_EL1";
> >> - case DBGWCR11_EL1: return "DBGWCR11_EL1";
> >> - case DBGWCR12_EL1: return "DBGWCR12_EL1";
> >> - case DBGWCR13_EL1: return "DBGWCR13_EL1";
> >> - case DBGWCR14_EL1: return "DBGWCR14_EL1";
> >> - case DBGWCR15_EL1: return "DBGWCR15_EL1";
> >> - case MDRAR_EL1: return "MDRAR_EL1";
> >> - case OSLAR_EL1: return "OSLAR_EL1";
> >> - case OSLSR_EL1: return "OSLSR_EL1";
> >> - case OSDLR_EL1: return "OSDLR_EL1";
> >> - case DBGPRCR_EL1: return "DBGPRCR_EL1";
> >> - case DBGCLAIMSET_EL1: return "DBGCLAIMSET_EL1";
> >> - case DBGCLAIMCLR_EL1: return "DBGCLAIMCLR_EL1";
> >> - case DBGAUTHSTATUS_EL1: return "DBGAUTHSTATUS_EL1";
> >> - case DBGDEVID2: return "DBGDEVID2";
> >> - case DBGDEVID1: return "DBGDEVID1";
> >> - case DBGDEVID0: return "DBGDEVID0";
> >> - case ID_PFR0_EL1: return "ID_PFR0_EL1";
> >> - case ID_PFR1_EL1: return "ID_PFR1_EL1";
> >> - case ID_DFR0_EL1: return "ID_DFR0_EL1";
> >> - case ID_AFR0_EL1: return "ID_AFR0_EL1";
> >> - case ID_ISAR0_EL1: return "ID_ISAR0_EL1";
> >> - case ID_ISAR1_EL1: return "ID_ISAR1_EL1";
> >> - case ID_ISAR2_EL1: return "ID_ISAR2_EL1";
> >> - case ID_ISAR3_EL1: return "ID_ISAR3_EL1";
> >> - case ID_ISAR4_EL1: return "ID_ISAR4_EL1";
> >> - case ID_ISAR5_EL1: return "ID_ISAR5_EL1";
> >> - case AFSR1_EL1: return "AFSR1_EL1";
> >> - case AFSR0_EL1: return "AFSR0_EL1";
> >> - case REVIDR_EL1: return "REVIDR_EL1";
> >> - }
> >> -}
> >> -
> >> -enum CPSRField {
> >> - InvalidCPSRField = 0xff,
> >> - cpsr_SPSel = 0x5,
> >> - cpsr_DAIFSet = 0x1e,
> >> - cpsr_DAIFClr = 0x1f
> >> -};
> >> -
> >> -static inline const char *getCPSRFieldName(CPSRField Val) {
> >> - switch(Val) {
> >> - default: assert(0 && "Invalid system register value!");
> >> - case cpsr_SPSel: return "SPSel";
> >> - case cpsr_DAIFSet: return "DAIFSet";
> >> - case cpsr_DAIFClr: return "DAIFClr";
> >> - }
> >> -}
> >> -
> >> -} // end namespace ARM64SYS
> >> -
> >> -/// Instances of this class can perform bidirectional mapping from
> random
> >> -/// identifier strings to operand encodings. For example "MSR" takes a
> named
> >> -/// system-register which must be encoded somehow and decoded for
> printing. This
> >> -/// central location means that the information for those
> transformations is not
> >> -/// duplicated and remains in sync.
> >> -///
> >> -/// FIXME: currently the algorithm is a completely unoptimised linear
> >> -/// search. Obviously this could be improved, but we would probably
> want to work
> >> -/// out just how often these instructions are emitted before working
> on it. It
> >> -/// might even be optimal to just reorder the tables for the common
> instructions
> >> -/// rather than changing the algorithm.
> >> -struct ARM64NamedImmMapper {
> >> - struct Mapping {
> >> - const char *Name;
> >> - uint32_t Value;
> >> - };
> >> -
> >> - template<int N>
> >> - ARM64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm)
> >> - : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {}
> >> -
> >> - StringRef toString(uint32_t Value, bool &Valid) const;
> >> - uint32_t fromString(StringRef Name, bool &Valid) const;
> >> -
> >> - /// Many of the instructions allow an alternative assembly form
> consisting of
> >> - /// a simple immediate. Currently the only valid forms are ranges
> [0, N) where
> >> - /// N being 0 indicates no immediate syntax-form is allowed.
> >> - bool validImm(uint32_t Value) const;
> >> -protected:
> >> - const Mapping *Pairs;
> >> - size_t NumPairs;
> >> - uint32_t TooBigImm;
> >> -};
> >> -
> >> -namespace ARM64AT {
> >> - enum ATValues {
> >> - Invalid = -1, // Op0 Op1 CRn CRm Op2
> >> - S1E1R = 0x43c0, // 01 000 0111 1000 000
> >> - S1E2R = 0x63c0, // 01 100 0111 1000 000
> >> - S1E3R = 0x73c0, // 01 110 0111 1000 000
> >> - S1E1W = 0x43c1, // 01 000 0111 1000 001
> >> - S1E2W = 0x63c1, // 01 100 0111 1000 001
> >> - S1E3W = 0x73c1, // 01 110 0111 1000 001
> >> - S1E0R = 0x43c2, // 01 000 0111 1000 010
> >> - S1E0W = 0x43c3, // 01 000 0111 1000 011
> >> - S12E1R = 0x63c4, // 01 100 0111 1000 100
> >> - S12E1W = 0x63c5, // 01 100 0111 1000 101
> >> - S12E0R = 0x63c6, // 01 100 0111 1000 110
> >> - S12E0W = 0x63c7 // 01 100 0111 1000 111
> >> - };
> >> -
> >> - struct ATMapper : ARM64NamedImmMapper {
> >> - const static Mapping ATPairs[];
> >> -
> >> - ATMapper();
> >> - };
> >> -
> >> -}
> >> -namespace ARM64DB {
> >> - enum DBValues {
> >> - Invalid = -1,
> >> - OSHLD = 0x1,
> >> - OSHST = 0x2,
> >> - OSH = 0x3,
> >> - NSHLD = 0x5,
> >> - NSHST = 0x6,
> >> - NSH = 0x7,
> >> - ISHLD = 0x9,
> >> - ISHST = 0xa,
> >> - ISH = 0xb,
> >> - LD = 0xd,
> >> - ST = 0xe,
> >> - SY = 0xf
> >> - };
> >> -
> >> - struct DBarrierMapper : ARM64NamedImmMapper {
> >> - const static Mapping DBarrierPairs[];
> >> -
> >> - DBarrierMapper();
> >> - };
> >> -}
> >> -
> >> -namespace ARM64DC {
> >> - enum DCValues {
> >> - Invalid = -1, // Op1 CRn CRm Op2
> >> - ZVA = 0x5ba1, // 01 011 0111 0100 001
> >> - IVAC = 0x43b1, // 01 000 0111 0110 001
> >> - ISW = 0x43b2, // 01 000 0111 0110 010
> >> - CVAC = 0x5bd1, // 01 011 0111 1010 001
> >> - CSW = 0x43d2, // 01 000 0111 1010 010
> >> - CVAU = 0x5bd9, // 01 011 0111 1011 001
> >> - CIVAC = 0x5bf1, // 01 011 0111 1110 001
> >> - CISW = 0x43f2 // 01 000 0111 1110 010
> >> - };
> >> -
> >> - struct DCMapper : ARM64NamedImmMapper {
> >> - const static Mapping DCPairs[];
> >> -
> >> - DCMapper();
> >> - };
> >> -
> >> -}
> >> -
> >> -namespace ARM64IC {
> >> - enum ICValues {
> >> - Invalid = -1, // Op1 CRn CRm Op2
> >> - IALLUIS = 0x0388, // 000 0111 0001 000
> >> - IALLU = 0x03a8, // 000 0111 0101 000
> >> - IVAU = 0x1ba9 // 011 0111 0101 001
> >> - };
> >> -
> >> -
> >> - struct ICMapper : ARM64NamedImmMapper {
> >> - const static Mapping ICPairs[];
> >> -
> >> - ICMapper();
> >> - };
> >> -
> >> - static inline bool NeedsRegister(ICValues Val) {
> >> - return Val == IVAU;
> >> - }
> >> -}
> >> -
> >> -namespace ARM64ISB {
> >> - enum ISBValues {
> >> - Invalid = -1,
> >> - SY = 0xf
> >> - };
> >> - struct ISBMapper : ARM64NamedImmMapper {
> >> - const static Mapping ISBPairs[];
> >> -
> >> - ISBMapper();
> >> - };
> >> -}
> >> -
> >> -namespace ARM64PRFM {
> >> - enum PRFMValues {
> >> - Invalid = -1,
> >> - PLDL1KEEP = 0x00,
> >> - PLDL1STRM = 0x01,
> >> - PLDL2KEEP = 0x02,
> >> - PLDL2STRM = 0x03,
> >> - PLDL3KEEP = 0x04,
> >> - PLDL3STRM = 0x05,
> >> - PLIL1KEEP = 0x08,
> >> - PLIL1STRM = 0x09,
> >> - PLIL2KEEP = 0x0a,
> >> - PLIL2STRM = 0x0b,
> >> - PLIL3KEEP = 0x0c,
> >> - PLIL3STRM = 0x0d,
> >> - PSTL1KEEP = 0x10,
> >> - PSTL1STRM = 0x11,
> >> - PSTL2KEEP = 0x12,
> >> - PSTL2STRM = 0x13,
> >> - PSTL3KEEP = 0x14,
> >> - PSTL3STRM = 0x15
> >> - };
> >> -
> >> - struct PRFMMapper : ARM64NamedImmMapper {
> >> - const static Mapping PRFMPairs[];
> >> -
> >> - PRFMMapper();
> >> - };
> >> -}
> >> -
> >> -namespace ARM64PState {
> >> - enum PStateValues {
> >> - Invalid = -1,
> >> - SPSel = 0x05,
> >> - DAIFSet = 0x1e,
> >> - DAIFClr = 0x1f
> >> - };
> >> -
> >> - struct PStateMapper : ARM64NamedImmMapper {
> >> - const static Mapping PStatePairs[];
> >> -
> >> - PStateMapper();
> >> - };
> >> -
> >> -}
> >> -
> >> -namespace ARM64SE {
> >> - enum ShiftExtSpecifiers {
> >> - Invalid = -1,
> >> - LSL,
> >> - MSL,
> >> - LSR,
> >> - ASR,
> >> - ROR,
> >> -
> >> - UXTB,
> >> - UXTH,
> >> - UXTW,
> >> - UXTX,
> >> -
> >> - SXTB,
> >> - SXTH,
> >> - SXTW,
> >> - SXTX
> >> - };
> >> -}
> >> -
> >> -namespace ARM64Layout {
> >> - enum VectorLayout {
> >> - Invalid = -1,
> >> - VL_8B,
> >> - VL_4H,
> >> - VL_2S,
> >> - VL_1D,
> >> -
> >> - VL_16B,
> >> - VL_8H,
> >> - VL_4S,
> >> - VL_2D,
> >> -
> >> - // Bare layout for the 128-bit vector
> >> - // (only show ".b", ".h", ".s", ".d" without vector number)
> >> - VL_B,
> >> - VL_H,
> >> - VL_S,
> >> - VL_D
> >> - };
> >> -}
> >> -
> >> -inline static const char *
> >> -ARM64VectorLayoutToString(ARM64Layout::VectorLayout Layout) {
> >> - switch (Layout) {
> >> - case ARM64Layout::VL_8B: return ".8b";
> >> - case ARM64Layout::VL_4H: return ".4h";
> >> - case ARM64Layout::VL_2S: return ".2s";
> >> - case ARM64Layout::VL_1D: return ".1d";
> >> - case ARM64Layout::VL_16B: return ".16b";
> >> - case ARM64Layout::VL_8H: return ".8h";
> >> - case ARM64Layout::VL_4S: return ".4s";
> >> - case ARM64Layout::VL_2D: return ".2d";
> >> - case ARM64Layout::VL_B: return ".b";
> >> - case ARM64Layout::VL_H: return ".h";
> >> - case ARM64Layout::VL_S: return ".s";
> >> - case ARM64Layout::VL_D: return ".d";
> >> - default: llvm_unreachable("Unknown Vector Layout");
> >> - }
> >> -}
> >> -
> >> -inline static ARM64Layout::VectorLayout
> >> -ARM64StringToVectorLayout(StringRef LayoutStr) {
> >> - return StringSwitch<ARM64Layout::VectorLayout>(LayoutStr)
> >> - .Case(".8b", ARM64Layout::VL_8B)
> >> - .Case(".4h", ARM64Layout::VL_4H)
> >> - .Case(".2s", ARM64Layout::VL_2S)
> >> - .Case(".1d", ARM64Layout::VL_1D)
> >> - .Case(".16b", ARM64Layout::VL_16B)
> >> - .Case(".8h", ARM64Layout::VL_8H)
> >> - .Case(".4s", ARM64Layout::VL_4S)
> >> - .Case(".2d", ARM64Layout::VL_2D)
> >> - .Case(".b", ARM64Layout::VL_B)
> >> - .Case(".h", ARM64Layout::VL_H)
> >> - .Case(".s", ARM64Layout::VL_S)
> >> - .Case(".d", ARM64Layout::VL_D)
> >> - .Default(ARM64Layout::Invalid);
> >> -}
> >> -
> >> -namespace ARM64SysReg {
> >> - enum SysRegROValues {
> >> - MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
> >> - DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
> >> - MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
> >> - OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
> >> - DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
> >> - PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
> >> - PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
> >> - MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
> >> - CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
> >> - CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
> >> - CTR_EL0 = 0xd801, // 11 011 0000 0000 001
> >> - MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
> >> - REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
> >> - AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
> >> - DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
> >> - ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
> >> - ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
> >> - ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
> >> - ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
> >> - ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
> >> - ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
> >> - ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
> >> - ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
> >> - ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
> >> - ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
> >> - ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
> >> - ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
> >> - ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
> >> - ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
> >> - ID_AARM64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
> >> - ID_AARM64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
> >> - ID_AARM64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
> >> - ID_AARM64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
> >> - ID_AARM64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
> >> - ID_AARM64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
> >> - ID_AARM64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
> >> - ID_AARM64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
> >> - ID_AARM64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
> >> - ID_AARM64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
> >> - MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
> >> - MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
> >> - MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
> >> - RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
> >> - RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
> >> - RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
> >> - ISR_EL1 = 0xc608, // 11 000 1100 0001 000
> >> - CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
> >> - CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
> >> -
> >> - // Trace registers
> >> - TRCSTATR = 0x8818, // 10 001 0000 0011 000
> >> - TRCIDR8 = 0x8806, // 10 001 0000 0000 110
> >> - TRCIDR9 = 0x880e, // 10 001 0000 0001 110
> >> - TRCIDR10 = 0x8816, // 10 001 0000 0010 110
> >> - TRCIDR11 = 0x881e, // 10 001 0000 0011 110
> >> - TRCIDR12 = 0x8826, // 10 001 0000 0100 110
> >> - TRCIDR13 = 0x882e, // 10 001 0000 0101 110
> >> - TRCIDR0 = 0x8847, // 10 001 0000 1000 111
> >> - TRCIDR1 = 0x884f, // 10 001 0000 1001 111
> >> - TRCIDR2 = 0x8857, // 10 001 0000 1010 111
> >> - TRCIDR3 = 0x885f, // 10 001 0000 1011 111
> >> - TRCIDR4 = 0x8867, // 10 001 0000 1100 111
> >> - TRCIDR5 = 0x886f, // 10 001 0000 1101 111
> >> - TRCIDR6 = 0x8877, // 10 001 0000 1110 111
> >> - TRCIDR7 = 0x887f, // 10 001 0000 1111 111
> >> - TRCOSLSR = 0x888c, // 10 001 0001 0001 100
> >> - TRCPDSR = 0x88ac, // 10 001 0001 0101 100
> >> - TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
> >> - TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
> >> - TRCLSR = 0x8bee, // 10 001 0111 1101 110
> >> - TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
> >> - TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
> >> - TRCDEVID = 0x8b97, // 10 001 0111 0010 111
> >> - TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
> >> - TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
> >> - TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
> >> - TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
> >> - TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
> >> - TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
> >> - TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
> >> - TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
> >> - TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
> >> - TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
> >> - TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
> >> - TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
> >> - TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
> >> -
> >> - // GICv3 registers
> >> - ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
> >> - ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
> >> - ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
> >> - ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
> >> - ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
> >> - ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
> >> - ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
> >> - ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101
> >> - };
> >> -
> >> - enum SysRegWOValues {
> >> - DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
> >> - OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
> >> - PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
> >> -
> >> - // Trace Registers
> >> - TRCOSLAR = 0x8884, // 10 001 0001 0000 100
> >> - TRCLAR = 0x8be6, // 10 001 0111 1100 110
> >> -
> >> - // GICv3 registers
> >> - ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
> >> - ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
> >> - ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
> >> - ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
> >> - ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
> >> - ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111
> >> - };
> >> -
> >> - enum SysRegValues {
> >> - Invalid = -1, // Op0 Op1 CRn CRm Op2
> >> - OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010
> >> - OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010
> >> - TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000
> >> - MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000
> >> - MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010
> >> - DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000
> >> - OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010
> >> - DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000
> >> - DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100
> >> - DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100
> >> - DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100
> >> - DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100
> >> - DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100
> >> - DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100
> >> - DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100
> >> - DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100
> >> - DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100
> >> - DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100
> >> - DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100
> >> - DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100
> >> - DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100
> >> - DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100
> >> - DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100
> >> - DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100
> >> - DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101
> >> - DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101
> >> - DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101
> >> - DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101
> >> - DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101
> >> - DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101
> >> - DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101
> >> - DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101
> >> - DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101
> >> - DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101
> >> - DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101
> >> - DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101
> >> - DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101
> >> - DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101
> >> - DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101
> >> - DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101
> >> - DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110
> >> - DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110
> >> - DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110
> >> - DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110
> >> - DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110
> >> - DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110
> >> - DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110
> >> - DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110
> >> - DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110
> >> - DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110
> >> - DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110
> >> - DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110
> >> - DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110
> >> - DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110
> >> - DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110
> >> - DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110
> >> - DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111
> >> - DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111
> >> - DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111
> >> - DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111
> >> - DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111
> >> - DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111
> >> - DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111
> >> - DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111
> >> - DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111
> >> - DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111
> >> - DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111
> >> - DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111
> >> - DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111
> >> - DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111
> >> - DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111
> >> - DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111
> >> - TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000
> >> - OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100
> >> - DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100
> >> - DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110
> >> - DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110
> >> - CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000
> >> - VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000
> >> - VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101
> >> - CPACR_EL1 = 0xc082, // 11 000 0001 0000 010
> >> - SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000
> >> - SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000
> >> - SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000
> >> - ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001
> >> - ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001
> >> - ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001
> >> - HCR_EL2 = 0xe088, // 11 100 0001 0001 000
> >> - SCR_EL3 = 0xf088, // 11 110 0001 0001 000
> >> - MDCR_EL2 = 0xe089, // 11 100 0001 0001 001
> >> - SDER32_EL3 = 0xf089, // 11 110 0001 0001 001
> >> - CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010
> >> - CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010
> >> - HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011
> >> - HACR_EL2 = 0xe08f, // 11 100 0001 0001 111
> >> - MDCR_EL3 = 0xf099, // 11 110 0001 0011 001
> >> - TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000
> >> - TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000
> >> - TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000
> >> - TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001
> >> - TCR_EL1 = 0xc102, // 11 000 0010 0000 010
> >> - TCR_EL2 = 0xe102, // 11 100 0010 0000 010
> >> - TCR_EL3 = 0xf102, // 11 110 0010 0000 010
> >> - VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000
> >> - VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010
> >> - DACR32_EL2 = 0xe180, // 11 100 0011 0000 000
> >> - SPSR_EL1 = 0xc200, // 11 000 0100 0000 000
> >> - SPSR_EL2 = 0xe200, // 11 100 0100 0000 000
> >> - SPSR_EL3 = 0xf200, // 11 110 0100 0000 000
> >> - ELR_EL1 = 0xc201, // 11 000 0100 0000 001
> >> - ELR_EL2 = 0xe201, // 11 100 0100 0000 001
> >> - ELR_EL3 = 0xf201, // 11 110 0100 0000 001
> >> - SP_EL0 = 0xc208, // 11 000 0100 0001 000
> >> - SP_EL1 = 0xe208, // 11 100 0100 0001 000
> >> - SP_EL2 = 0xf208, // 11 110 0100 0001 000
> >> - SPSel = 0xc210, // 11 000 0100 0010 000
> >> - NZCV = 0xda10, // 11 011 0100 0010 000
> >> - DAIF = 0xda11, // 11 011 0100 0010 001
> >> - CurrentEL = 0xc212, // 11 000 0100 0010 010
> >> - SPSR_irq = 0xe218, // 11 100 0100 0011 000
> >> - SPSR_abt = 0xe219, // 11 100 0100 0011 001
> >> - SPSR_und = 0xe21a, // 11 100 0100 0011 010
> >> - SPSR_fiq = 0xe21b, // 11 100 0100 0011 011
> >> - FPCR = 0xda20, // 11 011 0100 0100 000
> >> - FPSR = 0xda21, // 11 011 0100 0100 001
> >> - DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000
> >> - DLR_EL0 = 0xda29, // 11 011 0100 0101 001
> >> - IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001
> >> - AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000
> >> - AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000
> >> - AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000
> >> - AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001
> >> - AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001
> >> - AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001
> >> - ESR_EL1 = 0xc290, // 11 000 0101 0010 000
> >> - ESR_EL2 = 0xe290, // 11 100 0101 0010 000
> >> - ESR_EL3 = 0xf290, // 11 110 0101 0010 000
> >> - FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000
> >> - FAR_EL1 = 0xc300, // 11 000 0110 0000 000
> >> - FAR_EL2 = 0xe300, // 11 100 0110 0000 000
> >> - FAR_EL3 = 0xf300, // 11 110 0110 0000 000
> >> - HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100
> >> - PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000
> >> - PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000
> >> - PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001
> >> - PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010
> >> - PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011
> >> - PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101
> >> - PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000
> >> - PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001
> >> - PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010
> >> - PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000
> >> - PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001
> >> - PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010
> >> - PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011
> >> - MAIR_EL1 = 0xc510, // 11 000 1010 0010 000
> >> - MAIR_EL2 = 0xe510, // 11 100 1010 0010 000
> >> - MAIR_EL3 = 0xf510, // 11 110 1010 0010 000
> >> - AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000
> >> - AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000
> >> - AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000
> >> - VBAR_EL1 = 0xc600, // 11 000 1100 0000 000
> >> - VBAR_EL2 = 0xe600, // 11 100 1100 0000 000
> >> - VBAR_EL3 = 0xf600, // 11 110 1100 0000 000
> >> - RMR_EL1 = 0xc602, // 11 000 1100 0000 010
> >> - RMR_EL2 = 0xe602, // 11 100 1100 0000 010
> >> - RMR_EL3 = 0xf602, // 11 110 1100 0000 010
> >> - CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001
> >> - TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010
> >> - TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010
> >> - TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010
> >> - TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011
> >> - TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100
> >> - CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000
> >> - CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011
> >> - CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000
> >> - CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000
> >> - CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000
> >> - CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000
> >> - CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000
> >> - CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001
> >> - CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001
> >> - CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001
> >> - CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010
> >> - CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010
> >> - CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010
> >> - CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000
> >> - CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001
> >> - CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010
> >> - PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000
> >> - PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001
> >> - PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010
> >> - PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011
> >> - PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100
> >> - PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101
> >> - PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110
> >> - PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111
> >> - PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000
> >> - PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001
> >> - PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010
> >> - PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011
> >> - PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100
> >> - PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101
> >> - PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110
> >> - PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111
> >> - PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000
> >> - PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001
> >> - PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010
> >> - PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011
> >> - PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100
> >> - PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101
> >> - PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110
> >> - PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111
> >> - PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000
> >> - PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001
> >> - PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010
> >> - PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011
> >> - PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100
> >> - PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101
> >> - PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110
> >> - PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111
> >> - PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000
> >> - PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001
> >> - PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010
> >> - PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011
> >> - PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100
> >> - PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101
> >> - PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110
> >> - PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111
> >> - PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000
> >> - PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001
> >> - PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010
> >> - PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011
> >> - PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100
> >> - PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101
> >> - PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110
> >> - PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111
> >> - PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000
> >> - PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001
> >> - PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010
> >> - PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011
> >> - PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100
> >> - PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101
> >> - PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110
> >> - PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111
> >> - PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000
> >> - PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001
> >> - PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010
> >> - PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011
> >> - PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100
> >> - PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101
> >> - PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110
> >> -
> >> - // Trace registers
> >> - TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000
> >> - TRCPROCSELR = 0x8810, // 10 001 0000 0010 000
> >> - TRCCONFIGR = 0x8820, // 10 001 0000 0100 000
> >> - TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000
> >> - TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000
> >> - TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000
> >> - TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000
> >> - TRCTSCTLR = 0x8860, // 10 001 0000 1100 000
> >> - TRCSYNCPR = 0x8868, // 10 001 0000 1101 000
> >> - TRCCCCTLR = 0x8870, // 10 001 0000 1110 000
> >> - TRCBBCTLR = 0x8878, // 10 001 0000 1111 000
> >> - TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001
> >> - TRCQCTLR = 0x8809, // 10 001 0000 0001 001
> >> - TRCVICTLR = 0x8802, // 10 001 0000 0000 010
> >> - TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010
> >> - TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010
> >> - TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010
> >> - TRCVDCTLR = 0x8842, // 10 001 0000 1000 010
> >> - TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010
> >> - TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010
> >> - TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100
> >> - TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100
> >> - TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100
> >> - TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100
> >> - TRCSEQSTR = 0x883c, // 10 001 0000 0111 100
> >> - TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100
> >> - TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101
> >> - TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101
> >> - TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101
> >> - TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101
> >> - TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101
> >> - TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101
> >> - TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101
> >> - TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101
> >> - TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101
> >> - TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101
> >> - TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101
> >> - TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101
> >> - TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111
> >> - TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111
> >> - TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111
> >> - TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111
> >> - TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111
> >> - TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111
> >> - TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111
> >> - TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111
> >> - TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000
> >> - TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000
> >> - TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000
> >> - TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000
> >> - TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000
> >> - TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000
> >> - TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000
> >> - TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000
> >> - TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000
> >> - TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000
> >> - TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000
> >> - TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000
> >> - TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000
> >> - TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000
> >> - TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001
> >> - TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001
> >> - TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001
> >> - TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001
> >> - TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001
> >> - TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001
> >> - TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001
> >> - TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001
> >> - TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001
> >> - TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001
> >> - TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001
> >> - TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001
> >> - TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001
> >> - TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001
> >> - TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001
> >> - TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001
> >> - TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010
> >> - TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010
> >> - TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010
> >> - TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010
> >> - TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010
> >> - TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010
> >> - TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010
> >> - TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010
> >> - TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010
> >> - TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010
> >> - TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010
> >> - TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010
> >> - TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010
> >> - TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010
> >> - TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010
> >> - TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010
> >> - TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011
> >> - TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011
> >> - TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011
> >> - TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011
> >> - TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011
> >> - TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011
> >> - TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011
> >> - TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011
> >> - TRCPDCR = 0x88a4, // 10 001 0001 0100 100
> >> - TRCACVR0 = 0x8900, // 10 001 0010 0000 000
> >> - TRCACVR1 = 0x8910, // 10 001 0010 0010 000
> >> - TRCACVR2 = 0x8920, // 10 001 0010 0100 000
> >> - TRCACVR3 = 0x8930, // 10 001 0010 0110 000
> >> - TRCACVR4 = 0x8940, // 10 001 0010 1000 000
> >> - TRCACVR5 = 0x8950, // 10 001 0010 1010 000
> >> - TRCACVR6 = 0x8960, // 10 001 0010 1100 000
> >> - TRCACVR7 = 0x8970, // 10 001 0010 1110 000
> >> - TRCACVR8 = 0x8901, // 10 001 0010 0000 001
> >> - TRCACVR9 = 0x8911, // 10 001 0010 0010 001
> >> - TRCACVR10 = 0x8921, // 10 001 0010 0100 001
> >> - TRCACVR11 = 0x8931, // 10 001 0010 0110 001
> >> - TRCACVR12 = 0x8941, // 10 001 0010 1000 001
> >> - TRCACVR13 = 0x8951, // 10 001 0010 1010 001
> >> - TRCACVR14 = 0x8961, // 10 001 0010 1100 001
> >> - TRCACVR15 = 0x8971, // 10 001 0010 1110 001
> >> - TRCACATR0 = 0x8902, // 10 001 0010 0000 010
> >> - TRCACATR1 = 0x8912, // 10 001 0010 0010 010
> >> - TRCACATR2 = 0x8922, // 10 001 0010 0100 010
> >> - TRCACATR3 = 0x8932, // 10 001 0010 0110 010
> >> - TRCACATR4 = 0x8942, // 10 001 0010 1000 010
> >> - TRCACATR5 = 0x8952, // 10 001 0010 1010 010
> >> - TRCACATR6 = 0x8962, // 10 001 0010 1100 010
> >> - TRCACATR7 = 0x8972, // 10 001 0010 1110 010
> >> - TRCACATR8 = 0x8903, // 10 001 0010 0000 011
> >> - TRCACATR9 = 0x8913, // 10 001 0010 0010 011
> >> - TRCACATR10 = 0x8923, // 10 001 0010 0100 011
> >> - TRCACATR11 = 0x8933, // 10 001 0010 0110 011
> >> - TRCACATR12 = 0x8943, // 10 001 0010 1000 011
> >> - TRCACATR13 = 0x8953, // 10 001 0010 1010 011
> >> - TRCACATR14 = 0x8963, // 10 001 0010 1100 011
> >> - TRCACATR15 = 0x8973, // 10 001 0010 1110 011
> >> - TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100
> >> - TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100
> >> - TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100
> >> - TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100
> >> - TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101
> >> - TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101
> >> - TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101
> >> - TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101
> >> - TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110
> >> - TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110
> >> - TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110
> >> - TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110
> >> - TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111
> >> - TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111
> >> - TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111
> >> - TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111
> >> - TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000
> >> - TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000
> >> - TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000
> >> - TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000
> >> - TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000
> >> - TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000
> >> - TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000
> >> - TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000
> >> - TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001
> >> - TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001
> >> - TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001
> >> - TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001
> >> - TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001
> >> - TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001
> >> - TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001
> >> - TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001
> >> - TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010
> >> - TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010
> >> - TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010
> >> - TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010
> >> - TRCITCTRL = 0x8b84, // 10 001 0111 0000 100
> >> - TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110
> >> - TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110
> >> -
> >> - // GICv3 registers
> >> - ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011
> >> - ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011
> >> - ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000
> >> - ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100
> >> - ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100
> >> - ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101
> >> - ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101
> >> - ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101
> >> - ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110
> >> - ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111
> >> - ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111
> >> - ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000
> >> - ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100
> >> - ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101
> >> - ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110
> >> - ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111
> >> - ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000
> >> - ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001
> >> - ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010
> >> - ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011
> >> - ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000
> >> - ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001
> >> - ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010
> >> - ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011
> >> - ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000
> >> - ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001
> >> - ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010
> >> - ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011
> >> - ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000
> >> - ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010
> >> - ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111
> >> - ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100
> >> - ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000
> >> - ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001
> >> - ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010
> >> - ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011
> >> - ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100
> >> - ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101
> >> - ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110
> >> - ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111
> >> - ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000
> >> - ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001
> >> - ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010
> >> - ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011
> >> - ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100
> >> - ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101
> >> - ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110
> >> - ICH_LR15_EL2 = 0xe66f // 11 100 1100 1101 111
> >> - };
> >> -
> >> - // Note that these do not inherit from ARM64NamedImmMapper. This
> class is
> >> - // sufficiently different in its behaviour that I don't believe it's
> worth
> >> - // burdening the common ARM64NamedImmMapper with abstractions only
> needed in
> >> - // this one case.
> >> - struct SysRegMapper {
> >> - static const ARM64NamedImmMapper::Mapping SysRegPairs[];
> >> -
> >> - const ARM64NamedImmMapper::Mapping *InstPairs;
> >> - size_t NumInstPairs;
> >> -
> >> - SysRegMapper() {}
> >> - uint32_t fromString(StringRef Name, bool &Valid) const;
> >> - std::string toString(uint32_t Bits, bool &Valid) const;
> >> - };
> >> -
> >> - struct MSRMapper : SysRegMapper {
> >> - static const ARM64NamedImmMapper::Mapping MSRPairs[];
> >> - MSRMapper();
> >> - };
> >> -
> >> - struct MRSMapper : SysRegMapper {
> >> - static const ARM64NamedImmMapper::Mapping MRSPairs[];
> >> - MRSMapper();
> >> - };
> >> -
> >> - uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
> >> -}
> >> -
> >> -namespace ARM64TLBI {
> >> - enum TLBIValues {
> >> - Invalid = -1, // Op0 Op1 CRn CRm Op2
> >> - IPAS2E1IS = 0x6401, // 01 100 1000 0000 001
> >> - IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101
> >> - VMALLE1IS = 0x4418, // 01 000 1000 0011 000
> >> - ALLE2IS = 0x6418, // 01 100 1000 0011 000
> >> - ALLE3IS = 0x7418, // 01 110 1000 0011 000
> >> - VAE1IS = 0x4419, // 01 000 1000 0011 001
> >> - VAE2IS = 0x6419, // 01 100 1000 0011 001
> >> - VAE3IS = 0x7419, // 01 110 1000 0011 001
> >> - ASIDE1IS = 0x441a, // 01 000 1000 0011 010
> >> - VAAE1IS = 0x441b, // 01 000 1000 0011 011
> >> - ALLE1IS = 0x641c, // 01 100 1000 0011 100
> >> - VALE1IS = 0x441d, // 01 000 1000 0011 101
> >> - VALE2IS = 0x641d, // 01 100 1000 0011 101
> >> - VALE3IS = 0x741d, // 01 110 1000 0011 101
> >> - VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110
> >> - VAALE1IS = 0x441f, // 01 000 1000 0011 111
> >> - IPAS2E1 = 0x6421, // 01 100 1000 0100 001
> >> - IPAS2LE1 = 0x6425, // 01 100 1000 0100 101
> >> - VMALLE1 = 0x4438, // 01 000 1000 0111 000
> >> - ALLE2 = 0x6438, // 01 100 1000 0111 000
> >> - ALLE3 = 0x7438, // 01 110 1000 0111 000
> >> - VAE1 = 0x4439, // 01 000 1000 0111 001
> >> - VAE2 = 0x6439, // 01 100 1000 0111 001
> >> - VAE3 = 0x7439, // 01 110 1000 0111 001
> >> - ASIDE1 = 0x443a, // 01 000 1000 0111 010
> >> - VAAE1 = 0x443b, // 01 000 1000 0111 011
> >> - ALLE1 = 0x643c, // 01 100 1000 0111 100
> >> - VALE1 = 0x443d, // 01 000 1000 0111 101
> >> - VALE2 = 0x643d, // 01 100 1000 0111 101
> >> - VALE3 = 0x743d, // 01 110 1000 0111 101
> >> - VMALLS12E1 = 0x643e, // 01 100 1000 0111 110
> >> - VAALE1 = 0x443f // 01 000 1000 0111 111
> >> - };
> >> -
> >> - struct TLBIMapper : ARM64NamedImmMapper {
> >> - const static Mapping TLBIPairs[];
> >> -
> >> - TLBIMapper();
> >> - };
> >> -
> >> - static inline bool NeedsRegister(TLBIValues Val) {
> >> - switch (Val) {
> >> - case VMALLE1IS:
> >> - case ALLE2IS:
> >> - case ALLE3IS:
> >> - case ALLE1IS:
> >> - case VMALLS12E1IS:
> >> - case VMALLE1:
> >> - case ALLE2:
> >> - case ALLE3:
> >> - case ALLE1:
> >> - case VMALLS12E1:
> >> - return false;
> >> - default:
> >> - return true;
> >> - }
> >> - }
> >> -}
> >> -
> >> -namespace ARM64II {
> >> - /// Target Operand Flag enum.
> >> - enum TOF {
> >> -
> //===------------------------------------------------------------------===//
> >> - // ARM64 Specific MachineOperand flags.
> >> -
> >> - MO_NO_FLAG,
> >> -
> >> - MO_FRAGMENT = 0x7,
> >> -
> >> - /// MO_PAGE - A symbol operand with this flag represents the
> pc-relative
> >> - /// offset of the 4K page containing the symbol. This is used
> with the
> >> - /// ADRP instruction.
> >> - MO_PAGE = 1,
> >> -
> >> - /// MO_PAGEOFF - A symbol operand with this flag represents the
> offset of
> >> - /// that symbol within a 4K page. This offset is added to the
> page address
> >> - /// to produce the complete address.
> >> - MO_PAGEOFF = 2,
> >> -
> >> - /// MO_G3 - A symbol operand with this flag (granule 3) represents
> the high
> >> - /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
> >> - MO_G3 = 3,
> >> -
> >> - /// MO_G2 - A symbol operand with this flag (granule 2) represents
> the bits
> >> - /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
> >> - MO_G2 = 4,
> >> -
> >> - /// MO_G1 - A symbol operand with this flag (granule 1) represents
> the bits
> >> - /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
> >> - MO_G1 = 5,
> >> -
> >> - /// MO_G0 - A symbol operand with this flag (granule 0) represents
> the bits
> >> - /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
> >> - MO_G0 = 6,
> >> -
> >> - /// MO_GOT - This flag indicates that a symbol operand represents
> the
> >> - /// address of the GOT entry for the symbol, rather than the
> address of
> >> - /// the symbol itself.
> >> - MO_GOT = 8,
> >> -
> >> - /// MO_NC - Indicates whether the linker is expected to check the
> symbol
> >> - /// reference for overflow. For example in an ADRP/ADD pair of
> relocations
> >> - /// the ADRP usually does check, but not the ADD.
> >> - MO_NC = 0x10,
> >> -
> >> - /// MO_TLS - Indicates that the operand being accessed is some
> kind of
> >> - /// thread-local symbol. On Darwin, only one type of thread-local
> access
> >> - /// exists (pre linker-relaxation), but on ELF the TLSModel used
> for the
> >> - /// referee will affect interpretation.
> >> - MO_TLS = 0x20
> >> - };
> >> -} // end namespace ARM64II
> >> -
> >> -} // end namespace llvm
> >> -
> >> -#endif
> >>
> >> Modified:
> llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp
> (original)
> >> +++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64MCCodeEmitter.cpp Wed
> Apr 9 09:42:27 2014
> >> @@ -13,9 +13,9 @@
> >>
> >> #define DEBUG_TYPE "mccodeemitter"
> >> #include "MCTargetDesc/ARM64AddressingModes.h"
> >> -#include "MCTargetDesc/ARM64BaseInfo.h"
> >> #include "MCTargetDesc/ARM64FixupKinds.h"
> >> #include "MCTargetDesc/ARM64MCExpr.h"
> >> +#include "Utils/ARM64BaseInfo.h"
> >> #include "llvm/MC/MCCodeEmitter.h"
> >> #include "llvm/MC/MCContext.h"
> >> #include "llvm/MC/MCInst.h"
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/MCTargetDesc/CMakeLists.txt Wed Apr 9
> 09:42:27 2014
> >> @@ -1,6 +1,5 @@
> >> add_llvm_library(LLVMARM64Desc
> >> ARM64AsmBackend.cpp
> >> - ARM64BaseInfo.cpp
> >> ARM64ELFObjectWriter.cpp
> >> ARM64ELFStreamer.cpp
> >> ARM64MCAsmInfo.cpp
> >>
> >> Modified: llvm/trunk/lib/Target/ARM64/Makefile
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Makefile?rev=205867&r1=205866&r2=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/Makefile (original)
> >> +++ llvm/trunk/lib/Target/ARM64/Makefile Wed Apr 9 09:42:27 2014
> >> @@ -20,6 +20,6 @@ BUILT_SOURCES = ARM64GenRegisterInfo.inc
> >> ARM64GenFastISel.inc ARM64GenDisassemblerTables.inc \
> >> ARM64GenMCPseudoLowering.inc
> >>
> >> -DIRS = TargetInfo InstPrinter AsmParser Disassembler MCTargetDesc
> >> +DIRS = TargetInfo InstPrinter AsmParser Disassembler MCTargetDesc Utils
> >>
> >> include $(LEVEL)/Makefile.common
> >>
> >> Copied: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp (from
> r205866, llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp)
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp?p2=llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp&p1=llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.cpp&r1=205866&r2=205867&rev=205867&view=diff
> >>
> ==============================================================================
> >> (empty)
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp
> >>
> ------------------------------------------------------------------------------
> >> svn:eol-style = native
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.cpp
> >>
> ------------------------------------------------------------------------------
> >> svn:keywords = Rev Date Author URL Id
> >>
> >> Copied: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h (from
> r205866, llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h)
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h?p2=llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h&p1=llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h&r1=205866&r2=205867&rev=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h (original)
> >> +++ llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h Wed Apr 9
> 09:42:27 2014
> >> @@ -17,7 +17,9 @@
> >> #ifndef ARM64BASEINFO_H
> >> #define ARM64BASEINFO_H
> >>
> >> -#include "ARM64MCTargetDesc.h"
> >> +// FIXME: Is it easiest to fix this layering violation by moving the
> .inc
> >> +// #includes from ARM64MCTargetDesc.h to here?
> >> +#include "MCTargetDesc/ARM64MCTargetDesc.h" // For ARM64::X0 and
> friends.
> >> #include "llvm/ADT/STLExtras.h"
> >> #include "llvm/ADT/StringSwitch.h"
> >> #include "llvm/Support/ErrorHandling.h"
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h
> >>
> ------------------------------------------------------------------------------
> >> svn:eol-style = native
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/ARM64BaseInfo.h
> >>
> ------------------------------------------------------------------------------
> >> svn:keywords = Rev Date Author URL Id
> >>
> >> Added: llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt?rev=205867&view=auto
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt (added)
> >> +++ llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt Wed Apr 9
> 09:42:27 2014
> >> @@ -0,0 +1,3 @@
> >> +add_llvm_library(LLVMARM64Utils
> >> + ARM64BaseInfo.cpp
> >> + )
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt
> >>
> ------------------------------------------------------------------------------
> >> svn:eol-style = native
> >>
> >> Propchange: llvm/trunk/lib/Target/ARM64/Utils/CMakeLists.txt
> >>
> ------------------------------------------------------------------------------
> >> svn:keywords = Rev Date Author URL Id
> >>
> >> Copied: llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt (from r205866,
> llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt)
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt?p2=llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt&p1=llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt&r1=205866&r2=205867&rev=205867&view=diff
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/InstPrinter/LLVMBuild.txt (original)
> >> +++ llvm/trunk/lib/Target/ARM64/Utils/LLVMBuild.txt Wed Apr 9 09:42:27
> 2014
> >> @@ -1,4 +1,4 @@
> >> -;===- ./lib/Target/ARM64/InstPrinter/LLVMBuild.txt -------------*-
> Conf -*--===;
> >> +;===- ./lib/Target/ARM64/Utils/LLVMBuild.txt ----------------*- Conf
> -*--===;
> >> ;
> >> ; The LLVM Compiler Infrastructure
> >> ;
> >> @@ -17,8 +17,7 @@
> >>
> >> [component_0]
> >> type = Library
> >> -name = ARM64AsmPrinter
> >> +name = ARM64Utils
> >> parent = ARM64
> >> -required_libraries = MC Support
> >> +required_libraries = Support
> >> add_to_library_groups = ARM64
> >> -
> >>
> >> Added: llvm/trunk/lib/Target/ARM64/Utils/Makefile
> >> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/Utils/Makefile?rev=205867&view=auto
> >>
> ==============================================================================
> >> --- llvm/trunk/lib/Target/ARM64/Utils/Makefile (added)
> >> +++ llvm/trunk/lib/Target/ARM64/Utils/Makefile Wed Apr 9 09:42:27 2014
> >> @@ -0,0 +1,15 @@
> >> +##===- lib/Target/ARM64/Utils/Makefile -------------------*- Makefile
> -*-===##
> >> +#
> >> +# The LLVM Compiler Infrastructure
> >> +#
> >> +# This file is distributed under the University of Illinois Open Source
> >> +# License. See LICENSE.TXT for details.
> >> +#
> >>
> +##===----------------------------------------------------------------------===##
> >> +LEVEL = ../../../..
> >> +LIBRARYNAME = LLVMARM64Utils
> >> +
> >> +# Hack: we need to include 'main' ARM64 target directory to grab
> private headers
> >> +#CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
> >> +
> >> +include $(LEVEL)/Makefile.common
> >>
> >>
> >> _______________________________________________
> >> llvm-commits mailing list
> >> llvm-commits at cs.uiuc.edu
> >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
> >
> >
> > --
> > Alexander Potapenko
> > Software Engineer
> > Google Moscow
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
>
>
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>
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> Registered in England & Wales, Company No: 2557590
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> Registered in England & Wales, Company No: 2557590
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