[llvm] r205876 - [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
Bradley Smith
bradley.smith at arm.com
Wed Apr 9 07:43:11 PDT 2014
Author: brasmi01
Date: Wed Apr 9 09:43:11 2014
New Revision: 205876
URL: http://llvm.org/viewvc/llvm-project?rev=205876&view=rev
Log:
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
Modified:
llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
llvm/trunk/test/MC/ARM64/aliases.s
llvm/trunk/test/MC/ARM64/diags.s
Modified: llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp?rev=205876&r1=205875&r2=205876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp Wed Apr 9 09:43:11 2014
@@ -2516,6 +2516,12 @@ bool ARM64AsmParser::parseSysAlias(Strin
} else if (!Op.compare_lower("ipas2le1")) {
// SYS #4, C8, C4, #5
SYS_ALIAS(4, 8, 4, 5);
+ } else if (!Op.compare_lower("ipas2e1is")) {
+ // SYS #4, C8, C4, #1
+ SYS_ALIAS(4, 8, 0, 1);
+ } else if (!Op.compare_lower("ipas2le1is")) {
+ // SYS #4, C8, C4, #5
+ SYS_ALIAS(4, 8, 0, 5);
} else if (!Op.compare_lower("vmalls12e1")) {
// SYS #4, C8, C7, #6
SYS_ALIAS(4, 8, 7, 6);
@@ -2531,12 +2537,17 @@ bool ARM64AsmParser::parseSysAlias(Strin
Parser.Lex(); // Eat operand.
+ bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
+ bool HasRegister = false;
+
// Check for the optional register operand.
if (getLexer().is(AsmToken::Comma)) {
Parser.Lex(); // Eat comma.
if (Tok.isNot(AsmToken::Identifier) || parseRegister(Operands))
return TokError("expected register operand");
+
+ HasRegister = true;
}
if (getLexer().isNot(AsmToken::EndOfStatement)) {
@@ -2544,6 +2555,13 @@ bool ARM64AsmParser::parseSysAlias(Strin
return TokError("unexpected token in argument list");
}
+ if (ExpectRegister && !HasRegister) {
+ return TokError("specified " + Mnemonic + " op requires a register");
+ }
+ else if (!ExpectRegister && HasRegister) {
+ return TokError("specified " + Mnemonic + " op does not use a register");
+ }
+
Parser.Lex(); // Consume the EndOfStatement
return false;
}
Modified: llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp?rev=205876&r1=205875&r2=205876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp Wed Apr 9 09:43:11 2014
@@ -849,6 +849,20 @@ bool ARM64InstPrinter::printSysAlias(con
break;
}
break;
+ case 0:
+ switch (Op1Val) {
+ default:
+ break;
+ case 4:
+ switch (Op2Val) {
+ default:
+ break;
+ case 1: Asm = "tlbi\tipas2e1is"; break;
+ case 5: Asm = "tlbi\tipas2le1is"; break;
+ }
+ break;
+ }
+ break;
case 4:
switch (Op1Val) {
default:
Modified: llvm/trunk/test/MC/ARM64/aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/aliases.s?rev=205876&r1=205875&r2=205876&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/aliases.s (original)
+++ llvm/trunk/test/MC/ARM64/aliases.s Wed Apr 9 09:43:11 2014
@@ -412,120 +412,128 @@ foo:
; CHECK: tlbi ipas2e1
sys #4, c8, c4, #5
; CHECK: tlbi ipas2le1
+ sys #4, c8, c0, #1
+; CHECK: tlbi ipas2e1is
+ sys #4, c8, c0, #5
+; CHECK: tlbi ipas2le1is
sys #4, c8, c7, #6
; CHECK: tlbi vmalls12e1
sys #4, c8, c3, #6
; CHECK: tlbi vmalls12e1is
ic ialluis
-; CHECK: ic ialluis
+; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5]
ic iallu
-; CHECK: ic iallu
- ic ivau
-; CHECK: ic ivau
+; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5]
+ ic ivau, x0
+; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5]
- dc zva
-; CHECK: dc zva
- dc ivac
-; CHECK: dc ivac
- dc isw
-; CHECK: dc isw
- dc cvac
-; CHECK: dc cvac
- dc csw
-; CHECK: dc csw
- dc cvau
-; CHECK: dc cvau
- dc civac
-; CHECK: dc civac
- dc cisw
-; CHECK: dc cisw
+ dc zva, x0
+; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5]
+ dc ivac, x0
+; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5]
+ dc isw, x0
+; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5]
+ dc cvac, x0
+; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5]
+ dc csw, x0
+; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5]
+ dc cvau, x0
+; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5]
+ dc civac, x0
+; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5]
+ dc cisw, x0
+; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5]
- at s1e1r
-; CHECK: at s1e1r
- at s1e2r
-; CHECK: at s1e2r
- at s1e3r
-; CHECK: at s1e3r
- at s1e1w
-; CHECK: at s1e1w
- at s1e2w
-; CHECK: at s1e2w
- at s1e3w
-; CHECK: at s1e3w
- at s1e0r
-; CHECK: at s1e0r
- at s1e0w
-; CHECK: at s1e0w
- at s12e1r
-; CHECK: at s12e1r
- at s12e1w
-; CHECK: at s12e1w
- at s12e0r
-; CHECK: at s12e0r
- at s12e0w
-; CHECK: at s12e0w
+ at s1e1r, x0
+; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5]
+ at s1e2r, x0
+; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5]
+ at s1e3r, x0
+; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5]
+ at s1e1w, x0
+; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5]
+ at s1e2w, x0
+; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5]
+ at s1e3w, x0
+; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5]
+ at s1e0r, x0
+; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5]
+ at s1e0w, x0
+; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5]
+ at s12e1r, x0
+; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5]
+ at s12e1w, x0
+; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5]
+ at s12e0r, x0
+; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5]
+ at s12e0w, x0
+; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5]
tlbi vmalle1is
-; CHECK: tlbi vmalle1is
+; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5]
tlbi alle2is
-; CHECK: tlbi alle2is
+; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5]
tlbi alle3is
-; CHECK: tlbi alle3is
- tlbi vae1is
-; CHECK: tlbi vae1is
- tlbi vae2is
-; CHECK: tlbi vae2is
- tlbi vae3is
-; CHECK: tlbi vae3is
- tlbi aside1is
-; CHECK: tlbi aside1is
- tlbi vaae1is
-; CHECK: tlbi vaae1is
+; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5]
+ tlbi vae1is, x0
+; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5]
+ tlbi vae2is, x0
+; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5]
+ tlbi vae3is, x0
+; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5]
+ tlbi aside1is, x0
+; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5]
+ tlbi vaae1is, x0
+; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5]
tlbi alle1is
-; CHECK: tlbi alle1is
- tlbi vale1is
-; CHECK: tlbi vale1is
- tlbi vaale1is
-; CHECK: tlbi vaale1is
+; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5]
+ tlbi vale1is, x0
+; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5]
+ tlbi vaale1is, x0
+; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5]
tlbi vmalle1
-; CHECK: tlbi vmalle1
+; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5]
tlbi alle2
-; CHECK: tlbi alle2
- tlbi vale2is
-; CHECK: tlbi vale2is
- tlbi vale3is
-; CHECK: tlbi vale3is
+; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5]
+ tlbi vale2is, x0
+; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5]
+ tlbi vale3is, x0
+; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5]
tlbi alle3
-; CHECK: tlbi alle3
- tlbi vae1
-; CHECK: tlbi vae1
- tlbi vae2
-; CHECK: tlbi vae2
- tlbi vae3
-; CHECK: tlbi vae3
- tlbi aside1
-; CHECK: tlbi aside1
- tlbi vaae1
-; CHECK: tlbi vaae1
+; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5]
+ tlbi vae1, x0
+; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5]
+ tlbi vae2, x0
+; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5]
+ tlbi vae3, x0
+; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5]
+ tlbi aside1, x0
+; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5]
+ tlbi vaae1, x0
+; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5]
tlbi alle1
-; CHECK: tlbi alle1
- tlbi vale1
-; CHECK: tlbi vale1
- tlbi vale2
-; CHECK: tlbi vale2
- tlbi vale3
-; CHECK: tlbi vale3
- tlbi vaale1
-; CHECK: tlbi vaale1
- tlbi ipas2e1, x10
-; CHECK: tlbi ipas2e1, x10
- tlbi ipas2le1, x1
-; CHECK: tlbi ipas2le1, x1
+; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5
+ tlbi vale1, x0
+; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5]
+ tlbi vale2, x0
+; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5]
+ tlbi vale3, x0
+; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5]
+ tlbi vaale1, x0
+; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5]
+ tlbi ipas2e1, x0
+; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5]
+ tlbi ipas2le1, x0
+; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5]
+ tlbi ipas2e1is, x0
+; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5]
+ tlbi ipas2le1is, x0
+; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5]
tlbi vmalls12e1
-; CHECK: tlbi vmalls12e1
+; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5]
tlbi vmalls12e1is
-; CHECK: tlbi vmalls12e1is
+; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5]
;-----------------------------------------------------------------------------
; 5.8.5 Vector Arithmetic aliases
Modified: llvm/trunk/test/MC/ARM64/diags.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diags.s?rev=205876&r1=205875&r2=205876&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (original)
+++ llvm/trunk/test/MC/ARM64/diags.s Wed Apr 9 09:43:11 2014
@@ -240,3 +240,103 @@ b.c #0x4
; CHECK-ERRORS: error: invalid condition code
; CHECK-ERRORS: b.c #0x4
; CHECK-ERRORS: ^
+
+ic ialluis, x0
+; CHECK-ERRORS: error: specified ic op does not use a register
+ic iallu, x0
+; CHECK-ERRORS: error: specified ic op does not use a register
+ic ivau
+; CHECK-ERRORS: error: specified ic op requires a register
+
+dc zva
+; CHECK-ERRORS: error: specified dc op requires a register
+dc ivac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc isw
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cvac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc csw
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cvau
+; CHECK-ERRORS: error: specified dc op requires a register
+dc civac
+; CHECK-ERRORS: error: specified dc op requires a register
+dc cisw
+; CHECK-ERRORS: error: specified dc op requires a register
+
+at s1e1r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e2r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e3r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e1w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e2w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e3w
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e0r
+; CHECK-ERRORS: error: specified at op requires a register
+at s1e0w
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e1r
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e1w
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e0r
+; CHECK-ERRORS: error: specified at op requires a register
+at s12e0w
+; CHECK-ERRORS: error: specified at op requires a register
+
+tlbi vmalle1is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi vmalle1, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle1is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle2is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle3is, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle1, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle2, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi alle3, x0
+; CHECK-ERRORS: error: specified tlbi op does not use a register
+tlbi vae1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae2is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae3is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi aside1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaae1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaale1is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale2is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale3is
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae2
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vae3
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi aside1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vaae1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale1
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale2
+; CHECK-ERRORS: error: specified tlbi op requires a register
+tlbi vale3
+; CHECK-ERRORS: error: specified tlbi op requires a register
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