[llvm] r205732 - R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies

[Tom Stellard]

Author: tstellar
Date: Mon Apr  7 14:45:45 2014
New Revision: 205732

URL: http://llvm.org/viewvc/llvm-project?rev=205732&view=rev
Log:
R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies

Modified:
    llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
    llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll

Modified: llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp?rev=205732&r1=205731&r2=205732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp Mon Apr  7 14:45:45 2014
@@ -256,6 +256,16 @@ bool SIFixSGPRCopies::runOnMachineFuncti
         TII->moveToVALU(MI);
         break;
       }
+      case AMDGPU::INSERT_SUBREG: {
+        const TargetRegisterClass *DstRC, *SrcRC;
+        DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
+        SrcRC = MRI.getRegClass(MI.getOperand(1).getReg());
+        if (!TRI->isSGPRClass(DstRC) || !TRI->hasVGPRs(SrcRC))
+          break;
+        DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
+        DEBUG(MI.print(dbgs()));
+        TII->moveToVALU(MI);
+      }
       }
     }
   }

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=205732&r1=205731&r2=205732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Mon Apr  7 14:45:45 2014
@@ -516,6 +516,7 @@ unsigned SIInstrInfo::getVALUOp(const Ma
   case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
   case AMDGPU::COPY: return AMDGPU::COPY;
   case AMDGPU::PHI: return AMDGPU::PHI;
+  case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
   case AMDGPU::S_MOV_B32:
     return MI.getOperand(1).isReg() ?
            AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
@@ -996,6 +997,7 @@ void SIInstrInfo::moveToVALU(MachineInst
     case AMDGPU::COPY:
     case AMDGPU::PHI:
     case AMDGPU::REG_SEQUENCE:
+    case AMDGPU::INSERT_SUBREG:
       if (RI.hasVGPRs(NewDstRC))
         continue;
       NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);

Modified: llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll?rev=205732&r1=205731&r2=205732&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll (original)
+++ llvm/trunk/test/CodeGen/R600/insert_vector_elt.ll Mon Apr  7 14:45:45 2014
@@ -173,3 +173,29 @@ define void @dynamic_insertelement_v16i8
   store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16
   ret void
 }
+
+; This test requires handling INSERT_SUBREG in SIFixSGPRCopies.  Check that
+; the compiler doesn't crash.
+; SI-LABEL: @insert_split_bb
+define void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) {
+entry:
+  %0 = insertelement <2 x i32> undef, i32 %a, i32 0
+  %1 = icmp eq i32 %a, 0
+  br i1 %1, label %if, label %else
+
+if:
+  %2 = load i32 addrspace(1)* %in
+  %3 = insertelement <2 x i32> %0, i32 %2, i32 1
+  br label %endif
+
+else:
+  %4 = getelementptr i32 addrspace(1)* %in, i32 1
+  %5 = load i32 addrspace(1)* %4
+  %6 = insertelement <2 x i32> %0, i32 %5, i32 1
+  br label %endif
+
+endif:
+  %7 = phi <2 x i32> [%3, %if], [%6, %else]
+  store <2 x i32> %7, <2 x i32> addrspace(1)* %out
+  ret void
+}