[PATCH] 'CSE' of ADRP instructions used for load/store addressing

[Jiangning Liu]

Hi Zhaoshi,

Thanks for your experiment!

I finally got time to look into ARM64 back-end, and now I think ARM64
introduced a so-called LOH(Link Optimization Hint) to mark each instruction
in the pattern "adrp + add + ld/st" as I mentioned above, so finally ARM64
intends to expose all of them to linker and ask link time optimization to
remove redundant adrp and fuse add into ld/st as mentioned in file
ARM64CollectLOH.cpp. Note that here the link time optimization is different
from the LLVM LTO, which is based on LLVM IR. And I don't see APPLE has
upstreamed the linker using LOH info. Correct me, if I'm wrong, please!

Therefore, the test case I added would definitely fail for current ARM64
solution.

I think link time optimization is good, but it is not the most common
scenario for end-user to use compiler, so the solution I gave should be
still be quite meaningful.

Thanks,
-Jiangning



2014-04-03 6:45 GMT+08:00 Zhaoshi <zhaoshiz at codeaurora.org>:

> Hi,
>
> We applied this patch and are evaluating its performance. However, it only
> works for AArch64. The test case added by this patch failed on ARM64.
> Jiangning, can you take a look?
>
> Thanks,
> Zhaoshi
>
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu
> [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Rafael Espíndola
> Sent: Tuesday, April 01, 2014 08:35
> To: reviews+D3223+public+8a3946e1568d2bfb at llvm-reviews.chandlerc.com
> Cc: llvm-commits
> Subject: Re: [PATCH] 'CSE' of ADRP instructions used for load/store
> addressing
>
> On 1 April 2014 03:52, Jiangning Liu <liujiangning1 at gmail.com> wrote:
> >
> >   Hi Rafael,
> >
> >   No. I didn't enable global-merge-on-external by default, so you have to
> use -global-merge-on-external instead.
>
> OK. The main thing is using opt instead of llc.
>
> Cheers,
> Rafael
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>
>


-- 
Thanks,
-Jiangning
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