[llvm] r205524 - PR19320:

[Stepan Dyatkovskiy]

Author: dyatkovskiy
Date: Thu Apr  3 06:29:15 2014
New Revision: 205524

URL: http://llvm.org/viewvc/llvm-project?rev=205524&view=rev
Log:
PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.


Added:
    llvm/trunk/test/MC/ARM/ldrd-strd-gnu-sp.s
Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=205524&r1=205523&r2=205524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Apr  3 06:29:15 2014
@@ -5408,11 +5408,16 @@ bool ARMAsmParser::ParseInstruction(Pars
       Operands.size() == 4) {
     ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
     assert(Op->isReg() && "expected register argument");
-    assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
-                                    &MRI->getRegClass(ARM::GPRPairRegClassID))
-           && "expected register pair");
+
+    unsigned SuperReg = MRI->getMatchingSuperReg(
+        Op->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
+
+    assert(SuperReg && "expected register pair");
+
+    unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
+
     Operands.insert(Operands.begin() + 3,
-                    ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
+                    ARMOperand::CreateReg(PairedReg, Op->getStartLoc(),
                                           Op->getEndLoc()));
   }
 

Added: llvm/trunk/test/MC/ARM/ldrd-strd-gnu-sp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldrd-strd-gnu-sp.s?rev=205524&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/ldrd-strd-gnu-sp.s (added)
+++ llvm/trunk/test/MC/ARM/ldrd-strd-gnu-sp.s Thu Apr  3 06:29:15 2014
@@ -0,0 +1,9 @@
+// PR19320
+// RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
+.text
+
+// CHECK: ldrd	r12, sp, [r0, #32]      @ encoding: [0xd0,0xc2,0xc0,0xe1]
+        ldrd    r12, [r0, #32]
+
+// CHECK: strd	r12, sp, [r0, #32]      @ encoding: [0xf0,0xc2,0xc0,0xe1]
+        strd    r12, [r0, #32]