[llvm] r205302 - ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.

[Tim Northover]

Author: tnorthover
Date: Tue Apr  1 07:22:37 2014
New Revision: 205302

URL: http://llvm.org/viewvc/llvm-project?rev=205302&view=rev
Log:
ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.

Modified:
    llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
    llvm/trunk/test/CodeGen/ARM64/vmul.ll

Modified: llvm/trunk/include/llvm/IR/IntrinsicsARM64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsARM64.td?rev=205302&r1=205301&r2=205302&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsARM64.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsARM64.td Tue Apr  1 07:22:37 2014
@@ -74,8 +74,7 @@ let TargetPrefix = "arm64" in {  // All
                 [IntrNoMem]>;
   class AdvSIMD_2VectorArg_Long_Intrinsic
     : Intrinsic<[llvm_anyvector_ty],
-                [LLVMTruncatedType<0>,
-                 LLVMTruncatedType<0>],
+                [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
                 [IntrNoMem]>;
   class AdvSIMD_2VectorArg_Wide_Intrinsic
     : Intrinsic<[llvm_anyvector_ty],
@@ -178,6 +177,11 @@ let Properties = [IntrNoMem] in {
   def int_arm64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
   def int_arm64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 
+  // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
+  // it with a v16i8.
+  def int_arm64_neon_pmull64 :
+        Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
+
   // Vector Extending Multiply
   def int_arm64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic;
 

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td?rev=205302&r1=205301&r2=205302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td Tue Apr  1 07:22:37 2014
@@ -2726,6 +2726,13 @@ defm USUBL   : SIMDLongThreeVectorBHS<1,
 defm USUBW   : SIMDWideThreeVectorBHS<   1, 0b0011, "usubw",
                  BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
 
+// Patterns for 64-bit pmull
+def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
+          (PMULLv1i64 V64:$Rn, V64:$Rm)>;
+def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
+                                  (vector_extract (v2i64 V128:$Rm), (i64 1))),
+          (PMULLv2i64 V128:$Rn, V128:$Rm)>;
+
 // CodeGen patterns for addhn and subhn instructions, which can actually be
 // written in LLVM IR without too much difficulty.
 

Modified: llvm/trunk/test/CodeGen/ARM64/vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmul.ll?rev=205302&r1=205301&r2=205302&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vmul.ll Tue Apr  1 07:22:37 2014
@@ -1983,3 +1983,21 @@ define i64 @sqdmlsl_d(i32 %A, i32 %B, i6
   %tmp5 = call i64 @llvm.arm64.neon.sqsub.i64(i64 %C, i64 %tmp4)
   ret i64 %tmp5
 }
+
+define <16 x i8> @test_pmull_64(i64 %l, i64 %r) nounwind {
+; CHECK-LABEL: test_pmull_64:
+; CHECK: pmull.1q
+  %val = call <16 x i8> @llvm.arm64.neon.pmull64(i64 %l, i64 %r)
+  ret <16 x i8> %val
+}
+
+define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind {
+; CHECK-LABEL: test_pmull_high_64:
+; CHECK: pmull2.1q
+  %l_hi = extractelement <2 x i64> %l, i32 1
+  %r_hi = extractelement <2 x i64> %r, i32 1
+  %val = call <16 x i8> @llvm.arm64.neon.pmull64(i64 %l_hi, i64 %r_hi)
+  ret <16 x i8> %val
+}
+
+declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64)