[llvm] r205207 - ARM64: add patterns for scalar sqdmlal & sqdmlsl.

[Tim Northover]

Author: tnorthover
Date: Mon Mar 31 10:46:38 2014
New Revision: 205207

URL: http://llvm.org/viewvc/llvm-project?rev=205207&view=rev
Log:
ARM64: add patterns for scalar sqdmlal & sqdmlsl.

Modified:
    llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
    llvm/trunk/test/CodeGen/ARM64/vmul.ll

Modified: llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td?rev=205207&r1=205206&r2=205207&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM64/ARM64InstrInfo.td Mon Mar 31 10:46:38 2014
@@ -2525,6 +2525,15 @@ defm SQDMULL  : SIMDThreeScalarMixedHS<0
 defm SQDMLAL  : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
 defm SQDMLSL  : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
 
+def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
+                   (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
+                                                        (i32 FPR32:$Rm))))),
+          (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
+                   (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
+                                                        (i32 FPR32:$Rm))))),
+          (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
+
 //===----------------------------------------------------------------------===//
 // Advanced SIMD two scalar instructions.
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/ARM64/vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmul.ll?rev=205207&r1=205206&r2=205207&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmul.ll (original)
+++ llvm/trunk/test/CodeGen/ARM64/vmul.ll Mon Mar 31 10:46:38 2014
@@ -1967,3 +1967,19 @@ define <1 x double> @test_fdiv_v1f64(<1
   %prod = fdiv <1 x double> %L, %R
   ret <1 x double> %prod
 }
+
+define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind {
+;CHECK-LABEL: sqdmlal_d:
+;CHECK: sqdmlal
+  %tmp4 = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %A, i32 %B)
+  %tmp5 = call i64 @llvm.arm64.neon.sqadd.i64(i64 %C, i64 %tmp4)
+  ret i64 %tmp5
+}
+
+define i64 @sqdmlsl_d(i32 %A, i32 %B, i64 %C) nounwind {
+;CHECK-LABEL: sqdmlsl_d:
+;CHECK: sqdmlsl
+  %tmp4 = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %A, i32 %B)
+  %tmp5 = call i64 @llvm.arm64.neon.sqsub.i64(i64 %C, i64 %tmp4)
+  ret i64 %tmp5
+}