[llvm] r185966 - Reapply an improved version of r180816/180817.
Nico Weber
thakis at chromium.org
Sat Mar 29 16:07:16 PDT 2014
Hi Adrian,
r185966 lets clang optimize out the this pointer with asan even with -O0.
Is that intentional?
(sorry about replying to the digest, I don't subscribe to llvm-commits.)
Thanks,
Nico
ps: Repro, at r185965 and r185966:
$ cat test.cc
class A {
public:
int f(int a) {
d = a;
int b = 4 * a;
return b;
}
int d;
};
int main() {
A a;
return a.f(53);
}
$ ~/src/llvm-build/bin/clang++ test.cc -g -fsanitize=address -O0
$ lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
Breakpoint 1: where = a.out`main + 263 at test.cc:13, address =
0x0000000100000aa7
(lldb) run
Process 8465 launched: '/Users/thakis/src/chrome/src/a.out' (x86_64)
Process 8465 stopped
* thread #1: tid = 0x2cb858, 0x00007fff5fc01028 dyld`_dyld_start, stop
reason = exec
frame #0: 0x00007fff5fc01028 dyld`_dyld_start
dyld`_dyld_start:
-> 0x7fff5fc01028: popq %rdi
0x7fff5fc01029: pushq $0
0x7fff5fc0102b: movq %rsp, %rbp
0x7fff5fc0102e: andq $-16, %rsp
(lldb) c
Process 8465 resuming
Process 8465 stopped
* thread #1: tid = 0x2cb858, 0x0000000100000aa7 a.out`main + 263 at
test.cc:13, queue = 'com.apple.main-thread, stop reason = breakpoint 1.1
frame #0: 0x0000000100000aa7 a.out`main + 263 at test.cc:13
10
11 int main() {
12 A a;
-> 13 return a.f(53);
14 }
(lldb) s
Process 8465 stopped
* thread #1: tid = 0x2cb858, 0x0000000100000ce2
a.out`A::f(this=0x00007fff5fbff980, a=53) + 402 at test.cc:4, queue =
'com.apple.main-thread, stop reason = step in
frame #0: 0x0000000100000ce2 a.out`A::f(this=0x00007fff5fbff980, a=53)
+ 402 at test.cc:4
1 class A {
2 public:
3 int f(int a) {
-> 4 d = a;
5 int b = 4 * a;
6 return b;
7 }
(lldb) ^DQuitting LLDB will kill one or more processes. Do you really want
to proceed: [Y/n]
Nicos-MacBook-Pro:src thakis$ ~/src/llvm-build/bin/clang++ --version
clang version 3.4 (185965)
Target: x86_64-apple-darwin13.1.0
Thread model: posix
# Note how the this pointer is fine at r185965
$ ~/src/llvm-build/bin/clang++ test.cc -g -fsanitize=address -O0
$ lldb a.out
Current executable set to 'a.out' (x86_64).
(lldb) b main
Breakpoint 1: where = a.out`main + 263 at test.cc:13, address =
0x0000000100000aa7
(lldb) r
Process 8945 launched: '/Users/thakis/src/chrome/src/a.out' (x86_64)
Process 8945 stopped
* thread #1: tid = 0x2cbd36, 0x00007fff5fc01028 dyld`_dyld_start, stop
reason = exec
frame #0: 0x00007fff5fc01028 dyld`_dyld_start
dyld`_dyld_start:
-> 0x7fff5fc01028: popq %rdi
0x7fff5fc01029: pushq $0
0x7fff5fc0102b: movq %rsp, %rbp
0x7fff5fc0102e: andq $-16, %rsp
(lldb) c
Process 8945 resuming
Process 8945 stopped
* thread #1: tid = 0x2cbd36, 0x0000000100000aa7 a.out`main + 263 at
test.cc:13, queue = 'com.apple.main-thread, stop reason = breakpoint 1.1
frame #0: 0x0000000100000aa7 a.out`main + 263 at test.cc:13
10
11 int main() {
12 A a;
-> 13 return a.f(53);
14 }
(lldb) s
Process 8945 stopped
* thread #1: tid = 0x2cbd36, 0x0000000100000ce2
a.out`A::f(this=<unavailable>, a=<unavailable>) + 402 at test.cc:4, queue =
'com.apple.main-thread, stop reason = step in
frame #0: 0x0000000100000ce2 a.out`A::f(this=<unavailable>,
a=<unavailable>) + 402 at test.cc:4
1 class A {
2 public:
3 int f(int a) {
-> 4 d = a;
5 int b = 4 * a;
6 return b;
7 }
(lldb) ^DQuitting LLDB will kill one or more processes. Do you really want
to proceed: [Y/n]
Nicos-MacBook-Pro:src thakis$ ~/src/llvm-build/bin/clang++ --version
clang version 3.4 (185966)
Target: x86_64-apple-darwin13.1.0
Thread model: posix
# Note that the this pointer is now optimized out
On Tue, Jul 9, 2013 at 1:54 PM, <llvm-commits-request at cs.uiuc.edu> wrote:
> Send llvm-commits mailing list submissions to
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>
> Today's Topics:
>
> 1. [llvm] r185960 - WidenVecRes_BUILD_VECTOR must use the first
> operand's type (Hal Finkel)
> 2. [llvm] r185961 - Appease Atom buildbot after r185956
> (explicitly turn on AVX) (Stephen Lin)
> 3. Re: [llvm] r185961 - Appease Atom buildbot after r185956
> (explicitly turn on AVX) (Stephen Lin)
> 4. [llvm] r185962 - Appease buildbots after r185956: just set
> -mcpu explicitly, as it should have been from the beginning.
> (Stephen Lin)
> 5. Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit
> conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is
> derived from T. (David Blaikie)
> 6. [llvm] r185963 - Added "mode: c++" to FastISel.h header.
> (Michael Gottesman)
> 7. Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit
> conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is
> derived from T. (Chandler Carruth)
> 8. [llvm] r185964 - Fixed up the comments in FastISel.h so that
> they conform to the LLVM style guide. (Michael Gottesman)
> 9. [llvm] r185966 - Reapply an improved version of
> r180816/180817. (Adrian Prantl)
> 10. Re: [llvm-commits] [llvm] r159203 - in /llvm/trunk:
> lib/Target/ARM/ARMAsmPrinter.cpp
> lib/Target/CellSPU/SPUAsmPrinter.cpp
> lib/Target/Hexagon/HexagonAsmPrinter.cpp
> lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> lib/Target/PowerPC/PPCAsmPrinter.cpp
> lib/Target/Sparc/SparcAsmPrinter.cpp
> lib/Target/X86/X86AsmPrinter.cpp
> lib/Target/XCore/XCoreAsmPrinter.cpp
> test/CodeGen/Generic/asm-large-immediate.ll (Aaron Ballman)
> 11. [PATCH] Allow FMAs in safe math mode in some cases when one
> operand of the fmul is either exactly 0.0 or exactly 1.0.
> (Stephen Lin)
> 12. Re: [PATCH] [Object] Split the ELF interface into 3 parts.
> (Michael Spencer)
>
>
> ----------------------------------------------------------------------
>
> Message: 1
> Date: Tue, 09 Jul 2013 18:55:11 -0000
> From: Hal Finkel <hfinkel at anl.gov>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185960 - WidenVecRes_BUILD_VECTOR must use the first
> operand's type
> Message-ID: <20130709185511.504AE2A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: hfinkel
> Date: Tue Jul 9 13:55:10 2013
> New Revision: 185960
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185960&view=rev
> Log:
> WidenVecRes_BUILD_VECTOR must use the first operand's type
>
> Because integer BUILD_VECTOR operands may have a larger type than the
> result's
> vector element type, and all operands must have the same type, when
> widening a
> BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type,
> but
> rather must use the type of the existing operands.
>
> Another bug found by llvm-stress.
>
> Added:
> llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=185960&r1=185959&r2=185960&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jul 9
> 13:55:10 2013
> @@ -1872,7 +1872,10 @@ SDValue DAGTypeLegalizer::WidenVecRes_BU
> SDLoc dl(N);
> // Build a vector with undefined for the new nodes.
> EVT VT = N->getValueType(0);
> - EVT EltVT = VT.getVectorElementType();
> +
> + // Integer BUILD_VECTOR operands may be larger than the node's vector
> element
> + // type. The UNDEFs need to have the same type as the existing operands.
> + EVT EltVT = N->getOperand(0).getValueType();
> unsigned NumElts = VT.getVectorNumElements();
>
> EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
>
> Added: llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll?rev=185960&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll (added)
> +++ llvm/trunk/test/CodeGen/PowerPC/bv-widen-undef.ll Tue Jul 9 13:55:10
> 2013
> @@ -0,0 +1,23 @@
> +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
> +target triple = "powerpc64-unknown-linux-gnu"
> +
> +define void @autogen_SD4357(i8) {
> +BB:
> + br label %CF
> +
> +CF: ; preds = %CF, %BB
> + br i1 undef, label %CF, label %CF77
> +
> +CF77: ; preds = %CF81, %CF77,
> %CF
> + %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8
> -1>, <2 x i32> <i32 0, i32 undef>
> + br i1 undef, label %CF77, label %CF80
> +
> +CF80: ; preds = %CF80, %CF77
> + %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1>
> + %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000,
> 0xM00000000000000000000000000000000
> + br i1 %Cmp24, label %CF80, label %CF81
> +
> +CF81: ; preds = %CF80
> + %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0
> + br label %CF77
> +}
>
>
>
>
> ------------------------------
>
> Message: 2
> Date: Tue, 09 Jul 2013 18:55:52 -0000
> From: Stephen Lin <stephenwlin at gmail.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185961 - Appease Atom buildbot after r185956
> (explicitly turn on AVX)
> Message-ID: <20130709185552.EB1D62A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: stephenwlin
> Date: Tue Jul 9 13:55:52 2013
> New Revision: 185961
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185961&view=rev
> Log:
> Appease Atom buildbot after r185956 (explicitly turn on AVX)
>
> Modified:
> llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
>
> Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9
> 13:55:52 2013
> @@ -1,5 +1,5 @@
> ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s
> | FileCheck %s --check-prefix=CHECK-NOFMA
> +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin
> < %s | FileCheck %s --check-prefix=CHECK-NOFMA
>
> ; CHECK: fmafunc
> define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float>
> %c) {
>
> Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9
> 13:55:52 2013
> @@ -1,5 +1,5 @@
> ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s
> | FileCheck %s --check-prefix=CHECK-NOFMA
> +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin
> < %s | FileCheck %s --check-prefix=CHECK-NOFMA
>
> ; CHECK: fmafunc
> define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x
> float> %c) {
>
>
>
>
> ------------------------------
>
> Message: 3
> Date: Tue, 9 Jul 2013 12:00:32 -0700
> From: Stephen Lin <stephenwlin at gmail.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm] r185961 - Appease Atom buildbot after r185956
> (explicitly turn on AVX)
> Message-ID:
> <
> CAP2HvmDNKK8Euu+r19KPDOvH2oDg_+i2-wdzvzMa1iMEvk3QHQ at mail.gmail.com>
> Content-Type: text/plain; charset=UTF-8
>
> Sorry for all the broken bots, I copied and pasted a test line and
> didn't notice it wasn't setting the cpu explicitly (everything passed
> on my dev machine because it has +avx,-fma,-fma4)
> Stephen
>
> On Tue, Jul 9, 2013 at 11:55 AM, Stephen Lin <stephenwlin at gmail.com>
> wrote:
> > Author: stephenwlin
> > Date: Tue Jul 9 13:55:52 2013
> > New Revision: 185961
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=185961&view=rev
> > Log:
> > Appease Atom buildbot after r185956 (explicitly turn on AVX)
> >
> > Modified:
> > llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> > llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
> >
> > Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)
> > +++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9
> 13:55:52 2013
> > @@ -1,5 +1,5 @@
> > ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> > -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin <
> %s | FileCheck %s --check-prefix=CHECK-NOFMA
> > +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
> >
> > ; CHECK: fmafunc
> > define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float>
> %c) {
> >
> > Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185961&r1=185960&r2=185961&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)
> > +++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9
> 13:55:52 2013
> > @@ -1,5 +1,5 @@
> > ; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> > -; RUN: llc -march=x86 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin <
> %s | FileCheck %s --check-prefix=CHECK-NOFMA
> > +; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
> >
> > ; CHECK: fmafunc
> > define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x
> float> %c) {
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> ------------------------------
>
> Message: 4
> Date: Tue, 09 Jul 2013 19:27:10 -0000
> From: Stephen Lin <stephenwlin at gmail.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185962 - Appease buildbots after r185956: just set
> -mcpu explicitly, as it should have been from the beginning.
> Message-ID: <20130709192710.83C4C2A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: stephenwlin
> Date: Tue Jul 9 14:27:10 2013
> New Revision: 185962
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185962&view=rev
> Log:
> Appease buildbots after r185956: just set -mcpu explicitly, as it should
> have been from the beginning.
>
> Modified:
> llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
>
> Modified: llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/extended-fma-contraction.ll Tue Jul 9
> 14:27:10 2013
> @@ -1,5 +1,5 @@
> -; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> -; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin
> < %s | FileCheck %s --check-prefix=CHECK-NOFMA
> +; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s
> +; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
>
> ; CHECK: fmafunc
> define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float>
> %c) {
>
> Modified: llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll?rev=185962&r1=185961&r2=185962&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/wide-fma-contraction.ll Tue Jul 9
> 14:27:10 2013
> @@ -1,5 +1,5 @@
> -; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s |
> FileCheck %s
> -; RUN: llc -march=x86 -mattr=+avx,-fma,-fma4 -mtriple=x86_64-apple-darwin
> < %s | FileCheck %s --check-prefix=CHECK-NOFMA
> +; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s
> +; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4
> -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
>
> ; CHECK: fmafunc
> define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x
> float> %c) {
>
>
>
>
> ------------------------------
>
> Message: 5
> Date: Tue, 9 Jul 2013 12:37:11 -0700
> From: David Blaikie <dblaikie at gmail.com>
> To: Argyrios Kyrtzidis <akyrtzi at gmail.com>
> Cc: "llvm-commits at cs.uiuc.edu" <llvm-commits at cs.uiuc.edu>
> Subject: Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit
> conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is
> derived from T.
> Message-ID:
> <
> CAENS6EuF7cSYBNfSJp03r89+ooc_ypQjn7vB_7qcxqKsBgjrzQ at mail.gmail.com>
> Content-Type: text/plain; charset=ISO-8859-1
>
> On Tue, Jul 9, 2013 at 11:48 AM, Argyrios Kyrtzidis <akyrtzi at gmail.com>
> wrote:
> > On Jul 8, 2013, at 7:37 PM, David Blaikie <dblaikie at gmail.com> wrote:
> >
> >> On Mon, Jul 8, 2013 at 7:31 PM, Argyrios Kyrtzidis <akyrtzi at gmail.com>
> wrote:
> >>> On Jul 8, 2013, at 5:31 PM, David Blaikie <dblaikie at gmail.com> wrote:
> >>>
> >>>> On Mon, Jul 8, 2013 at 5:08 PM, Argyrios Kyrtzidis <akyrtzi at gmail.com>
> wrote:
> >>>>> On Jul 8, 2013, at 4:05 PM, David Blaikie <dblaikie at gmail.com>
> wrote:
> >>>>>
> >>>>> On Mon, Jul 8, 2013 at 2:51 PM, Argyrios Kyrtzidis <
> akyrtzi at gmail.com>
> >>>>> wrote:
> >>>>>
> >>>>> On Jul 8, 2013, at 12:47 PM, David Blaikie <dblaikie at gmail.com>
> wrote:
> >>>>>
> >>>>> On Mon, Jul 8, 2013 at 12:12 PM, Argyrios Kyrtzidis <
> akyrtzi at gmail.com>
> >>>>> wrote:
> >>>>>
> >>>>> Author: akirtzidis
> >>>>> Date: Mon Jul 8 14:12:01 2013
> >>>>> New Revision: 185851
> >>>>>
> >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=185851&view=rev
> >>>>> Log:
> >>>>> [ADT/NullablePtr] Allow implicit conversion of NullablePtr<OtherT> ->
> >>>>> NullablePtr<T> if OtherT is derived from T.
> >>>>>
> >>>>>
> >>>>> Might be nicer to do this for any case where SrcT* is implicitly
> >>>>> convertible DestT* (such as adding cv qualifiers or converting to
> >>>>> void*).
> >>>>>
> >>>>>
> >>>>> cv qualifiers look like are working, void* is not.
> >>>>> In general, we need to add the equivalent of C++11's is_convertible
> to
> >>>>> "llvm/Support/type_traits.h" and use it here.
> >>>>>
> >>>>>
> >>>>> Shall we do that then?
> >>>>>
> >>>>> (your current implementation also disables this ctor for
> NullablePtr's
> >>>>> of non-class type (NullablePtr<int> for example), I think... that
> >>>>> seems unreasonable)
> >>>>>
> >>>>>
> >>>>> Feel free to enhance it :-)
> >>>>
> >>>> Alternatively, this code doesn't seem to have any uses inside the llvm
> >>>> codebase (at least not clang, llvm, compiler-rt, libcxx - maybe in
> >>>> lldb?) nor any tests. Should we just remove it instead? (I assume you
> >>>> have a use-case, or you wouldn't've been motivated to update it - is
> >>>> that use case somewhere in the llvm project (broadly, across all
> >>>> subprojects) or out of tree?)
> >>>
> >>> It is used out of tree.
> >>
> >> It might be more suitable for it to live along with the code that's
> >> consuming it, I'd imagine. (that'd be my preference, at least - though
> >> if it's really necessary for it to be here, it should probably at
> >> least have unit tests)
> >
> > Unit tests for this are overkill IMO,
>
> Even if it's just compile tests to check that some of the examples I
> gave work correctly/as expected, that doesn't seem unreasonable to me
> (if only to enshrine/document the intended semantics).
>
> > we could just start using it in new llvm/clang APIs.
>
> That it's been in the codebase for 2 years & still (?) has zero uses
> seems to indicate that that might not be desired & should probably
> just be removed.
>
> >
> >>
> >> - David
> >>
> >>>
> >>>>
> >>>> - David
> >>>>
> >>>>>
> >>>>> -Argyrios
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>> Modified:
> >>>>> llvm/trunk/include/llvm/ADT/NullablePtr.h
> >>>>>
> >>>>> Modified: llvm/trunk/include/llvm/ADT/NullablePtr.h
> >>>>> URL:
> >>>>>
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/NullablePtr.h?rev=185851&r1=185850&r2=185851&view=diff
> >>>>>
> ==============================================================================
> >>>>> --- llvm/trunk/include/llvm/ADT/NullablePtr.h (original)
> >>>>> +++ llvm/trunk/include/llvm/ADT/NullablePtr.h Mon Jul 8 14:12:01
> 2013
> >>>>> @@ -14,6 +14,7 @@
> >>>>> #ifndef LLVM_ADT_NULLABLEPTR_H
> >>>>> #define LLVM_ADT_NULLABLEPTR_H
> >>>>>
> >>>>> +#include "llvm/Support/type_traits.h"
> >>>>> #include <cassert>
> >>>>> #include <cstddef>
> >>>>>
> >>>>> @@ -25,8 +26,17 @@ namespace llvm {
> >>>>> template<class T>
> >>>>> class NullablePtr {
> >>>>> T *Ptr;
> >>>>> + struct PlaceHolder {};
> >>>>> +
> >>>>> public:
> >>>>> NullablePtr(T *P = 0) : Ptr(P) {}
> >>>>> +
> >>>>> + template<typename OtherT>
> >>>>> + NullablePtr(NullablePtr<OtherT> Other,
> >>>>> + typename enable_if<
> >>>>> + is_base_of<T, OtherT>,
> >>>>> + PlaceHolder
> >>>>> + >::type = PlaceHolder()) : Ptr(Other.getPtrOrNull())
> {}
> >>>>>
> >>>>> bool isNull() const { return Ptr == 0; }
> >>>>> bool isNonNull() const { return Ptr != 0; }
> >>>>>
> >>>>>
> >>>>> _______________________________________________
> >>>>> llvm-commits mailing list
> >>>>> llvm-commits at cs.uiuc.edu
> >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >>>>>
> >>>>>
> >>>
> >
>
>
> ------------------------------
>
> Message: 6
> Date: Tue, 09 Jul 2013 20:00:25 -0000
> From: Michael Gottesman <mgottesman at apple.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185963 - Added "mode: c++" to FastISel.h header.
> Message-ID: <20130709200025.826872A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: mgottesman
> Date: Tue Jul 9 15:00:25 2013
> New Revision: 185963
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185963&view=rev
> Log:
> Added "mode: c++" to FastISel.h header.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/FastISel.h
>
> Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185963&r1=185962&r2=185963&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Jul 9 15:00:25 2013
> @@ -1,4 +1,4 @@
> -//===-- FastISel.h - Definition of the FastISel class
> ---------------------===//
> +//===-- FastISel.h - Definition of the FastISel class ---*- mode: c++;
> -*--===//
> //
> // The LLVM Compiler Infrastructure
> //
>
>
>
>
> ------------------------------
>
> Message: 7
> Date: Tue, 9 Jul 2013 13:02:34 -0700
> From: Chandler Carruth <chandlerc at google.com>
> To: Argyrios Kyrtzidis <akyrtzi at gmail.com>
> Cc: "llvm-commits at cs.uiuc.edu" <llvm-commits at cs.uiuc.edu>
> Subject: Re: [llvm] r185851 - [ADT/NullablePtr] Allow implicit
> conversion of NullablePtr<OtherT> -> NullablePtr<T> if OtherT is
> derived from T.
> Message-ID:
> <CAGCO0Kj+=8ODzR1EBFkgS+FEBgXW6030v=
> h_au25kWPELSjfpg at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> On Tue, Jul 9, 2013 at 11:48 AM, Argyrios Kyrtzidis <akyrtzi at gmail.com
> >wrote:
>
> > >>> Alternatively, this code doesn't seem to have any uses inside the
> llvm
> > >>> codebase (at least not clang, llvm, compiler-rt, libcxx - maybe in
> > >>> lldb?) nor any tests. Should we just remove it instead? (I assume you
> > >>> have a use-case, or you wouldn't've been motivated to update it - is
> > >>> that use case somewhere in the llvm project (broadly, across all
> > >>> subprojects) or out of tree?)
> > >>
> > >> It is used out of tree.
> > >
> > > It might be more suitable for it to live along with the code that's
> > > consuming it, I'd imagine. (that'd be my preference, at least - though
> > > if it's really necessary for it to be here, it should probably at
> > > least have unit tests)
> >
> > Unit tests for this are overkill IMO, we could just start using it in new
> > llvm/clang APIs.
>
>
> I think one of two things need to happen here:
>
> 1) We move this code to live with the out-of-tree consumers so that the
> open source project isn't maintaining and carrying forward untested and
> unused code paths, or
> 2) We make a conscious decision to consistently recommend the use of this
> type as part of APIs in LLVM, Clang, and other projects.
>
> As to why I would prefer #1 over #2: I don't (yet) buy the utility of this.
> Instead, I prefer the simple rule: pointers are nullable, references are
> not, and to use them for those purposes.
>
> Yes, there is a challenge of re-binding a never-null pointer member of a
> class, but the fact that this utility for addressing that problem has
> gotten so little adoption makes me feel that this isn't a big problem, and
> we already have sufficient tools to address it (such as assert()s around
> mutation operations).
>
> My 2 cents.
> -Chandler
> -------------- next part --------------
> An HTML attachment was scrubbed...
> URL: <
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20130709/55ef46cd/attachment-0001.html
> >
>
> ------------------------------
>
> Message: 8
> Date: Tue, 09 Jul 2013 20:08:46 -0000
> From: Michael Gottesman <mgottesman at apple.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185964 - Fixed up the comments in FastISel.h so that
> they conform to the LLVM style guide.
> Message-ID: <20130709200846.8FF102A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: mgottesman
> Date: Tue Jul 9 15:08:46 2013
> New Revision: 185964
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185964&view=rev
> Log:
> Fixed up the comments in FastISel.h so that they conform to the LLVM style
> guide.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/FastISel.h
>
> Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=185964&r1=185963&r2=185964&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Jul 9 15:08:46 2013
> @@ -6,9 +6,10 @@
> // License. See LICENSE.TXT for details.
> //
>
> //===----------------------------------------------------------------------===//
> -//
> -// This file defines the FastISel class.
> -//
> +///
> +/// \file
> +/// This file defines the FastISel class.
> +///
>
> //===----------------------------------------------------------------------===//
>
> #ifndef LLVM_CODEGEN_FASTISEL_H
> @@ -41,9 +42,8 @@ class TargetRegisterInfo;
> class User;
> class Value;
>
> -/// FastISel - This is a fast-path instruction selection class that
> -/// generates poor code and doesn't support illegal types or non-trivial
> -/// lowering, but runs quickly.
> +/// This is a fast-path instruction selection class that generates poor
> code and
> +/// doesn't support illegal types or non-trivial lowering, but runs
> quickly.
> class FastISel {
> protected:
> DenseMap<const Value *, unsigned> LocalValueMap;
> @@ -59,99 +59,92 @@ protected:
> const TargetRegisterInfo &TRI;
> const TargetLibraryInfo *LibInfo;
>
> - /// The position of the last instruction for materializing constants
> - /// for use in the current block. It resets to EmitStartPt when it
> - /// makes sense (for example, it's usually profitable to avoid function
> - /// calls between the definition and the use)
> + /// The position of the last instruction for materializing constants
> for use
> + /// in the current block. It resets to EmitStartPt when it makes sense
> (for
> + /// example, it's usually profitable to avoid function calls between the
> + /// definition and the use)
> MachineInstr *LastLocalValue;
>
> - /// The top most instruction in the current block that is allowed for
> - /// emitting local variables. LastLocalValue resets to EmitStartPt when
> - /// it makes sense (for example, on function calls)
> + /// The top most instruction in the current block that is allowed for
> emitting
> + /// local variables. LastLocalValue resets to EmitStartPt when it makes
> sense
> + /// (for example, on function calls)
> MachineInstr *EmitStartPt;
>
> public:
> - /// getLastLocalValue - Return the position of the last instruction
> - /// emitted for materializing constants for use in the current block.
> + /// Return the position of the last instruction emitted for
> materializing
> + /// constants for use in the current block.
> MachineInstr *getLastLocalValue() { return LastLocalValue; }
>
> - /// setLastLocalValue - Update the position of the last instruction
> - /// emitted for materializing constants for use in the current block.
> + /// Update the position of the last instruction emitted for
> materializing
> + /// constants for use in the current block.
> void setLastLocalValue(MachineInstr *I) {
> EmitStartPt = I;
> LastLocalValue = I;
> }
>
> - /// startNewBlock - Set the current block to which generated machine
> - /// instructions will be appended, and clear the local CSE map.
> - ///
> + /// Set the current block to which generated machine instructions will
> be
> + /// appended, and clear the local CSE map.
> void startNewBlock();
>
> - /// getCurDebugLoc() - Return current debug location information.
> + /// Return current debug location information.
> DebugLoc getCurDebugLoc() const { return DL; }
>
> - /// LowerArguments - Do "fast" instruction selection for function
> arguments
> - /// and append machine instructions to the current block. Return true if
> - /// it is successful.
> + /// Do "fast" instruction selection for function arguments and append
> machine
> + /// instructions to the current block. Return true if it is successful.
> bool LowerArguments();
>
> - /// SelectInstruction - Do "fast" instruction selection for the given
> - /// LLVM IR instruction, and append generated machine instructions to
> - /// the current block. Return true if selection was successful.
> - ///
> + /// Do "fast" instruction selection for the given LLVM IR instruction,
> and
> + /// append generated machine instructions to the current block. Return
> true if
> + /// selection was successful.
> bool SelectInstruction(const Instruction *I);
>
> - /// SelectOperator - Do "fast" instruction selection for the given
> - /// LLVM IR operator (Instruction or ConstantExpr), and append
> - /// generated machine instructions to the current block. Return true
> - /// if selection was successful.
> - ///
> + /// Do "fast" instruction selection for the given LLVM IR operator
> + /// (Instruction or ConstantExpr), and append generated machine
> instructions
> + /// to the current block. Return true if selection was successful.
> bool SelectOperator(const User *I, unsigned Opcode);
>
> - /// getRegForValue - Create a virtual register and arrange for it to
> - /// be assigned the value for the given LLVM value.
> + /// Create a virtual register and arrange for it to be assigned the
> value for
> + /// the given LLVM value.
> unsigned getRegForValue(const Value *V);
>
> - /// lookUpRegForValue - Look up the value to see if its value is already
> - /// cached in a register. It may be defined by instructions across
> blocks or
> - /// defined locally.
> + /// Look up the value to see if its value is already cached in a
> register. It
> + /// may be defined by instructions across blocks or defined locally.
> unsigned lookUpRegForValue(const Value *V);
>
> - /// getRegForGEPIndex - This is a wrapper around getRegForValue that
> also
> - /// takes care of truncating or sign-extending the given getelementptr
> - /// index value.
> + /// This is a wrapper around getRegForValue that also takes care of
> truncating
> + /// or sign-extending the given getelementptr index value.
> std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
>
> - /// \brief We're checking to see if we can fold \p LI into \p FoldInst.
> - /// Note that we could have a sequence where multiple LLVM IR
> instructions
> - /// are folded into the same machineinstr. For example we could have:
> + /// \brief We're checking to see if we can fold \p LI into \p FoldInst.
> Note
> + /// that we could have a sequence where multiple LLVM IR instructions
> are
> + /// folded into the same machineinstr. For example we could have:
> + ///
> /// A: x = load i32 *P
> /// B: y = icmp A, 42
> /// C: br y, ...
> ///
> - /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know
> - /// about "B" (and any other folded instructions) because it is between
> - /// A and C.
> + /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know
> about "B"
> + /// (and any other folded instructions) because it is between A and C.
> ///
> /// If we succeed folding, return true.
> - ///
> bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
>
> - /// \brief The specified machine instr operand is a vreg, and that
> - /// vreg is being provided by the specified load instruction. If
> possible,
> - /// try to fold the load as an operand to the instruction, returning
> true if
> + /// \brief The specified machine instr operand is a vreg, and that vreg
> is
> + /// being provided by the specified load instruction. If possible, try
> to
> + /// fold the load as an operand to the instruction, returning true if
> /// possible.
> + ///
> /// This method should be implemented by targets.
> virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned
> /*OpNo*/,
> const LoadInst * /*LI*/) {
> return false;
> }
>
> - /// recomputeInsertPt - Reset InsertPt to prepare for inserting
> instructions
> - /// into the current block.
> + /// Reset InsertPt to prepare for inserting instructions into the
> current
> + /// block.
> void recomputeInsertPt();
>
> - /// removeDeadCode - Remove all dead instructions between the I and E.
> + /// Remove all dead instructions between the I and E.
> void removeDeadCode(MachineBasicBlock::iterator I,
> MachineBasicBlock::iterator E);
>
> @@ -160,11 +153,11 @@ public:
> DebugLoc DL;
> };
>
> - /// enterLocalValueArea - Prepare InsertPt to begin inserting
> instructions
> - /// into the local value area and return the old insert position.
> + /// Prepare InsertPt to begin inserting instructions into the local
> value area
> + /// and return the old insert position.
> SavePoint enterLocalValueArea();
>
> - /// leaveLocalValueArea - Reset InsertPt to the given old insert
> position.
> + /// Reset InsertPt to the given old insert position.
> void leaveLocalValueArea(SavePoint Old);
>
> virtual ~FastISel();
> @@ -173,69 +166,59 @@ protected:
> explicit FastISel(FunctionLoweringInfo &funcInfo,
> const TargetLibraryInfo *libInfo);
>
> - /// TargetSelectInstruction - This method is called by
> target-independent
> - /// code when the normal FastISel process fails to select an
> instruction.
> - /// This gives targets a chance to emit code for anything that doesn't
> - /// fit into FastISel's framework. It returns true if it was successful.
> - ///
> + /// This method is called by target-independent code when the normal
> FastISel
> + /// process fails to select an instruction. This gives targets a
> chance to
> + /// emit code for anything that doesn't fit into FastISel's framework.
> It
> + /// returns true if it was successful.
> virtual bool
> TargetSelectInstruction(const Instruction *I) = 0;
>
> - /// FastLowerArguments - This method is called by target-independent
> code to
> - /// do target specific argument lowering. It returns true if it was
> - /// successful.
> + /// This method is called by target-independent code to do target
> specific
> + /// argument lowering. It returns true if it was successful.
> virtual bool FastLowerArguments();
>
> - /// FastEmit_r - This method is called by target-independent code
> - /// to request that an instruction with the given type and opcode
> - /// be emitted.
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type and opcode be emitted.
> virtual unsigned FastEmit_(MVT VT,
> MVT RetVT,
> unsigned Opcode);
>
> - /// FastEmit_r - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// register operand be emitted.
> - ///
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and register operand be
> emitted.
> virtual unsigned FastEmit_r(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> unsigned Op0, bool Op0IsKill);
>
> - /// FastEmit_rr - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// register operands be emitted.
> - ///
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and register operands be
> emitted.
> virtual unsigned FastEmit_rr(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> unsigned Op0, bool Op0IsKill,
> unsigned Op1, bool Op1IsKill);
>
> - /// FastEmit_ri - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// register and immediate operands be emitted.
> - ///
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and register and immediate
> + /// operands be emitted.
> virtual unsigned FastEmit_ri(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> unsigned Op0, bool Op0IsKill,
> uint64_t Imm);
>
> - /// FastEmit_rf - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// register and floating-point immediate operands be emitted.
> - ///
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and register and
> floating-point
> + /// immediate operands be emitted.
> virtual unsigned FastEmit_rf(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> unsigned Op0, bool Op0IsKill,
> const ConstantFP *FPImm);
>
> - /// FastEmit_rri - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// register and immediate operands be emitted.
> - ///
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and register and immediate
> + /// operands be emitted.
> virtual unsigned FastEmit_rri(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> @@ -243,142 +226,130 @@ protected:
> unsigned Op1, bool Op1IsKill,
> uint64_t Imm);
>
> - /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first
> tries
> - /// to emit an instruction with an immediate operand using FastEmit_ri.
> - /// If that fails, it materializes the immediate into a register and try
> - /// FastEmit_rr instead.
> + /// \brief This method is a wrapper of FastEmit_ri.
> + ///
> + /// It first tries to emit an instruction with an immediate operand
> using
> + /// FastEmit_ri. If that fails, it materializes the immediate into a
> register
> + /// and try FastEmit_rr instead.
> unsigned FastEmit_ri_(MVT VT,
> unsigned Opcode,
> unsigned Op0, bool Op0IsKill,
> uint64_t Imm, MVT ImmType);
>
> - /// FastEmit_i - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// immediate operand be emitted.
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and immediate operand be
> emitted.
> virtual unsigned FastEmit_i(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> uint64_t Imm);
>
> - /// FastEmit_f - This method is called by target-independent code
> - /// to request that an instruction with the given type, opcode, and
> - /// floating-point immediate operand be emitted.
> + /// This method is called by target-independent code to request that an
> + /// instruction with the given type, opcode, and floating-point
> immediate
> + /// operand be emitted.
> virtual unsigned FastEmit_f(MVT VT,
> MVT RetVT,
> unsigned Opcode,
> const ConstantFP *FPImm);
>
> - /// FastEmitInst_ - Emit a MachineInstr with no operands and a
> - /// result register in the given register class.
> - ///
> + /// Emit a MachineInstr with no operands and a result register in the
> given
> + /// register class.
> unsigned FastEmitInst_(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC);
>
> - /// FastEmitInst_r - Emit a MachineInstr with one register operand
> - /// and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with one register operand and a result register
> in the
> + /// given register class.
> unsigned FastEmitInst_r(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill);
>
> - /// FastEmitInst_rr - Emit a MachineInstr with two register operands
> - /// and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with two register operands and a result
> register in
> + /// the given register class.
> unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> unsigned Op1, bool Op1IsKill);
>
> - /// FastEmitInst_rrr - Emit a MachineInstr with three register operands
> - /// and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with three register operands and a result
> register in
> + /// the given register class.
> unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> unsigned Op1, bool Op1IsKill,
> unsigned Op2, bool Op2IsKill);
>
> - /// FastEmitInst_ri - Emit a MachineInstr with a register operand,
> - /// an immediate, and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with a register operand, an immediate, and a
> result
> + /// register in the given register class.
> unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> uint64_t Imm);
>
> - /// FastEmitInst_rii - Emit a MachineInstr with one register operand
> - /// and two immediate operands.
> - ///
> + /// Emit a MachineInstr with one register operand and two immediate
> operands.
> unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> uint64_t Imm1, uint64_t Imm2);
>
> - /// FastEmitInst_rf - Emit a MachineInstr with two register operands
> - /// and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with two register operands and a result
> register in
> + /// the given register class.
> unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> const ConstantFP *FPImm);
>
> - /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
> - /// an immediate, and a result register in the given register class.
> - ///
> + /// Emit a MachineInstr with two register operands, an immediate, and a
> result
> + /// register in the given register class.
> unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> unsigned Op1, bool Op1IsKill,
> uint64_t Imm);
>
> - /// FastEmitInst_rrii - Emit a MachineInstr with two register operands,
> - /// two immediates operands, and a result register in the given register
> - /// class.
> + /// Emit a MachineInstr with two register operands, two immediates
> operands,
> + /// and a result register in the given register class.
> unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
> const TargetRegisterClass *RC,
> unsigned Op0, bool Op0IsKill,
> unsigned Op1, bool Op1IsKill,
> uint64_t Imm1, uint64_t Imm2);
>
> - /// FastEmitInst_i - Emit a MachineInstr with a single immediate
> - /// operand, and a result register in the given register class.
> + /// Emit a MachineInstr with a single immediate operand, and a result
> register
> + /// in the given register class.
> unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
> const TargetRegisterClass *RC,
> uint64_t Imm);
>
> - /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
> + /// Emit a MachineInstr with a two immediate operands.
> unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
> const TargetRegisterClass *RC,
> uint64_t Imm1, uint64_t Imm2);
>
> - /// FastEmitInst_extractsubreg - Emit a MachineInstr for an
> extract_subreg
> - /// from a specified index of a superregister to a specified type.
> + /// Emit a MachineInstr for an extract_subreg from a specified index of
> a
> + /// superregister to a specified type.
> unsigned FastEmitInst_extractsubreg(MVT RetVT,
> unsigned Op0, bool Op0IsKill,
> uint32_t Idx);
>
> - /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
> - /// with all but the least significant bit set to zero.
> + /// Emit MachineInstrs to compute the value of Op with all but the least
> + /// significant bit set to zero.
> unsigned FastEmitZExtFromI1(MVT VT,
> unsigned Op0, bool Op0IsKill);
>
> - /// FastEmitBranch - Emit an unconditional branch to the given block,
> - /// unless it is the immediate (fall-through) successor, and update
> - /// the CFG.
> + /// Emit an unconditional branch to the given block, unless it is the
> + /// immediate (fall-through) successor, and update the CFG.
> void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
>
> void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
>
> unsigned createResultReg(const TargetRegisterClass *RC);
>
> - /// TargetMaterializeConstant - Emit a constant in a register using
> - /// target-specific logic, such as constant pool loads.
> + /// Emit a constant in a register using target-specific logic, such as
> + /// constant pool loads.
> virtual unsigned TargetMaterializeConstant(const Constant* C) {
> return 0;
> }
>
> - /// TargetMaterializeAlloca - Emit an alloca address in a register using
> - /// target-specific logic.
> + /// Emit an alloca address in a register using target-specific logic.
> virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
> return 0;
> }
> @@ -404,25 +375,26 @@ private:
>
> bool SelectInsertValue(const User *I);
>
> - /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor
> blocks.
> + /// \brief Handle PHI nodes in successor blocks.
> + ///
> /// Emit code to ensure constants are copied into registers when needed.
> /// Remember the virtual registers that need to be added to the Machine
> PHI
> - /// nodes as input. We cannot just directly add them, because expansion
> - /// might result in multiple MBB's for one BB. As such, the start of
> the
> - /// BB might correspond to a different MBB than the end.
> + /// nodes as input. We cannot just directly add them, because
> expansion might
> + /// result in multiple MBB's for one BB. As such, the start of the BB
> might
> + /// correspond to a different MBB than the end.
> bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
>
> - /// materializeRegForValue - Helper for getRegForVale. This function is
> - /// called when the value isn't already available in a register and must
> - /// be materialized with new instructions.
> + /// Helper for getRegForVale. This function is called when the value
> isn't
> + /// already available in a register and must be materialized with new
> + /// instructions.
> unsigned materializeRegForValue(const Value *V, MVT VT);
>
> - /// flushLocalValueMap - clears LocalValueMap and moves the area for the
> - /// new local variables to the beginning of the block. It helps to avoid
> - /// spilling cached variables across heavy instructions like calls.
> + /// Clears LocalValueMap and moves the area for the new local variables
> to the
> + /// beginning of the block. It helps to avoid spilling cached variables
> across
> + /// heavy instructions like calls.
> void flushLocalValueMap();
>
> - /// hasTrivialKill - Test whether the given value has exactly one use.
> + /// Test whether the given value has exactly one use.
> bool hasTrivialKill(const Value *V) const;
> };
>
>
>
>
>
> ------------------------------
>
> Message: 9
> Date: Tue, 09 Jul 2013 20:28:37 -0000
> From: Adrian Prantl <aprantl at apple.com>
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r185966 - Reapply an improved version of
> r180816/180817.
> Message-ID: <20130709202838.5B2422A6C029 at llvm.org>
> Content-Type: text/plain; charset="utf-8"
>
> Author: adrian
> Date: Tue Jul 9 15:28:37 2013
> New Revision: 185966
>
> URL: http://llvm.org/viewvc/llvm-project?rev=185966&view=rev
> Log:
> Reapply an improved version of r180816/180817.
>
> Change the informal convention of DBG_VALUE machine instructions so that
> we can express a register-indirect address with an offset of 0.
> The old convention was that a DBG_VALUE is a register-indirect value if
> the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE
> is register-indirect if the first operand is a register and the second
> operand is an immediate. For plain register values the combination reg,
> reg is used. MachineInstrBuilder::BuildMI knows how to build the new
> DBG_VALUES.
>
> rdar://problem/13658587
>
> Added:
> llvm/trunk/test/DebugInfo/X86/vla.ll
> Modified:
> llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
> llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
> llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
> llvm/trunk/lib/CodeGen/RegAllocFast.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/test/CodeGen/X86/dbg-value-range.ll
> llvm/trunk/test/DebugInfo/X86/op_deref.ll
> llvm/trunk/test/DebugInfo/X86/parameters.ll
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Tue Jul 9
> 15:28:37 2013
> @@ -335,6 +335,51 @@ inline MachineInstrBuilder BuildMI(Machi
> return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
> }
>
> +/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
> +/// for either a value in a register or a register-indirect+offset
> +/// address. The convention is that a DBG_VALUE is indirect iff the
> +/// second operand is an immediate.
> +///
> +inline MachineInstrBuilder BuildMI(MachineFunction &MF,
> + DebugLoc DL,
> + const MCInstrDesc &MCID,
> + bool IsIndirect,
> + unsigned Reg,
> + unsigned Offset,
> + const MDNode *MD) {
> + if (IsIndirect)
> + return BuildMI(MF, DL, MCID)
> + .addReg(Reg, RegState::Debug)
> + .addImm(Offset)
> + .addMetadata(MD);
> + else {
> + assert(Offset == 0 && "A direct address cannot have an offset.");
> + return BuildMI(MF, DL, MCID)
> + .addReg(Reg, RegState::Debug)
> + .addReg(0U, RegState::Debug)
> + .addMetadata(MD);
> + }
> +}
> +
> +/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
> +/// for either a value in a register or a register-indirect+offset
> +/// address and inserts it at position I.
> +///
> +inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> + MachineBasicBlock::iterator I,
> + DebugLoc DL,
> + const MCInstrDesc &MCID,
> + bool IsIndirect,
> + unsigned Reg,
> + unsigned Offset,
> + const MDNode *MD) {
> + MachineFunction &MF = *BB.getParent();
> + MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);
> + BB.insert(I, MI);
> + return MachineInstrBuilder(MF, MI);
> +}
> +
> +
> inline unsigned getDefRegState(bool B) {
> return B ? RegState::Define : 0;
> }
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jul 9 15:28:37
> 2013
> @@ -570,8 +570,10 @@ static bool emitDebugValueComment(const
> }
> OS << V.getName() << " <- ";
>
> - int64_t Offset = MI->getOperand(1).getImm();
> - bool Deref = false;
> + // The second operand is only an offset if it's an immediate.
> + bool Deref = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
> + int64_t Offset = Deref ? MI->getOperand(1).getImm() : 0;
> +
> // Register or immediate value. Register 0 means undef.
> if (MI->getOperand(0).isFPImm()) {
> APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());
> @@ -595,8 +597,6 @@ static bool emitDebugValueComment(const
> unsigned Reg;
> if (MI->getOperand(0).isReg()) {
> Reg = MI->getOperand(0).getReg();
> - Deref = Offset != 0; // FIXME: use a better sentinel value so that
> deref
> - // of a reg with a zero offset is valid
> } else {
> assert(MI->getOperand(0).isFI() && "Unknown operand type");
> const TargetFrameLowering *TFI = AP.TM.getFrameLowering();
> @@ -616,10 +616,9 @@ static bool emitDebugValueComment(const
> OS << AP.TM.getRegisterInfo()->getName(Reg);
> }
>
> - if (Offset)
> - OS << '+' << Offset;
> if (Deref)
> - OS << ']';
> + OS << '+' << Offset << ']';
> +
> // NOTE: Want this comment at start of line, don't emit with AddComment.
> AP.OutStreamer.EmitRawText(OS.str());
> return true;
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue Jul 9
> 15:28:37 2013
> @@ -1563,8 +1563,9 @@ DIE *CompileUnit::constructVariableDIE(D
> assert(DVInsn->getNumOperands() == 3);
> if (DVInsn->getOperand(0).isReg()) {
> const MachineOperand RegOp = DVInsn->getOperand(0);
> - if (int64_t Offset = DVInsn->getOperand(1).getImm()) {
> - MachineLocation Location(RegOp.getReg(), Offset);
> + // If the second operand is an immedieate, this is an indirect
> value.
> + if (DVInsn->getOperand(1).isImm()) {
> + MachineLocation Location(RegOp.getReg(),
> DVInsn->getOperand(1).getImm());
> addVariableAddress(*DV, VariableDie, Location);
> } else if (RegOp.getReg())
> addVariableAddress(*DV, VariableDie,
> MachineLocation(RegOp.getReg()));
>
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jul 9 15:28:37
> 2013
> @@ -1184,7 +1184,8 @@ static bool isDbgValueInDefinedReg(const
> assert(MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!");
> return MI->getNumOperands() == 3 &&
> MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
> - MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0;
> + (MI->getOperand(1).isImm() ||
> + (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() ==
> 0U));
> }
>
> // Get .debug_loc entry for the instruction range starting at MI.
> @@ -1195,12 +1196,11 @@ static DotDebugLocEntry getDebugLocEntry
> const MDNode *Var = MI->getOperand(MI->getNumOperands() -
> 1).getMetadata();
>
> assert(MI->getNumOperands() == 3);
> - if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) {
> + if (MI->getOperand(0).isReg()) {
> MachineLocation MLoc;
> - // TODO: Currently an offset of 0 in a DBG_VALUE means
> - // we need to generate a direct register value.
> - // There is no way to specify an indirect value with offset 0.
> - if (MI->getOperand(1).getImm() == 0)
> + // If the second operand is an immediate, this is a
> + // register-indirect address.
> + if (!MI->getOperand(1).isImm())
> MLoc.set(MI->getOperand(0).getReg());
> else
> MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
>
> Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Jul 9 15:28:37 2013
> @@ -108,6 +108,7 @@ class LDVImpl;
> class UserValue {
> const MDNode *variable; ///< The debug info variable we are part of.
> unsigned offset; ///< Byte offset into variable.
> + bool IsIndirect; ///< true if this is a register-indirect+offset
> value.
> DebugLoc dl; ///< The debug location for the variable. This
> is
> ///< used by dwarf writer to find lexical scope.
> UserValue *leader; ///< Equivalence class leader.
> @@ -134,9 +135,10 @@ class UserValue {
>
> public:
> /// UserValue - Create a new UserValue.
> - UserValue(const MDNode *var, unsigned o, DebugLoc L,
> + UserValue(const MDNode *var, unsigned o, bool i, DebugLoc L,
> LocMap::Allocator &alloc)
> - : variable(var), offset(o), dl(L), leader(this), next(0),
> locInts(alloc)
> + : variable(var), offset(o), IsIndirect(i), dl(L), leader(this),
> + next(0), locInts(alloc)
> {}
>
> /// getLeader - Get the leader of this value's equivalence class.
> @@ -299,7 +301,8 @@ class LDVImpl {
> UVMap userVarMap;
>
> /// getUserValue - Find or create a UserValue.
> - UserValue *getUserValue(const MDNode *Var, unsigned Offset, DebugLoc
> DL);
> + UserValue *getUserValue(const MDNode *Var, unsigned Offset,
> + bool IsIndirect, DebugLoc DL);
>
> /// lookupVirtReg - Find the EC leader for VirtReg or null.
> UserValue *lookupVirtReg(unsigned VirtReg);
> @@ -414,7 +417,7 @@ void UserValue::mapVirtRegs(LDVImpl *LDV
> }
>
> UserValue *LDVImpl::getUserValue(const MDNode *Var, unsigned Offset,
> - DebugLoc DL) {
> + bool IsIndirect, DebugLoc DL) {
> UserValue *&Leader = userVarMap[Var];
> if (Leader) {
> UserValue *UV = Leader->getLeader();
> @@ -424,7 +427,7 @@ UserValue *LDVImpl::getUserValue(const M
> return UV;
> }
>
> - UserValue *UV = new UserValue(Var, Offset, DL, allocator);
> + UserValue *UV = new UserValue(Var, Offset, IsIndirect, DL, allocator);
> userValues.push_back(UV);
> Leader = UserValue::merge(Leader, UV);
> return UV;
> @@ -445,15 +448,17 @@ UserValue *LDVImpl::lookupVirtReg(unsign
> bool LDVImpl::handleDebugValue(MachineInstr *MI, SlotIndex Idx) {
> // DBG_VALUE loc, offset, variable
> if (MI->getNumOperands() != 3 ||
> - !MI->getOperand(1).isImm() || !MI->getOperand(2).isMetadata()) {
> + !(MI->getOperand(1).isReg() || MI->getOperand(1).isImm()) ||
> + !MI->getOperand(2).isMetadata()) {
> DEBUG(dbgs() << "Can't handle " << *MI);
> return false;
> }
>
> // Get or create the UserValue for (variable,offset).
> - unsigned Offset = MI->getOperand(1).getImm();
> + bool IsIndirect = MI->getOperand(1).isImm();
> + unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
> const MDNode *Var = MI->getOperand(2).getMetadata();
> - UserValue *UV = getUserValue(Var, Offset, MI->getDebugLoc());
> + UserValue *UV = getUserValue(Var, Offset, IsIndirect,
> MI->getDebugLoc());
> UV->addDef(Idx, MI->getOperand(0));
> return true;
> }
> @@ -921,8 +926,12 @@ void UserValue::insertDebugValue(Machine
> MachineOperand &Loc = locations[LocNo];
> ++NumInsertedDebugValues;
>
> - BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
> - .addOperand(Loc).addImm(offset).addMetadata(variable);
> + if (Loc.isReg())
> + BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
> + IsIndirect, Loc.getReg(), offset, variable);
> + else
> + BuildMI(*MBB, I, findDebugLoc(), TII.get(TargetOpcode::DBG_VALUE))
> + .addOperand(Loc).addImm(offset).addMetadata(variable);
> }
>
> void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jul 9 15:28:37 2013
> @@ -298,7 +298,8 @@ void RAFast::spillVirtReg(MachineBasicBl
> for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
> MachineInstr *DBG = LRIDbgValues[li];
> const MDNode *MDPtr = DBG->getOperand(2).getMetadata();
> - int64_t Offset = DBG->getOperand(1).getImm();
> + bool IsIndirect = DBG->getOperand(1).isImm(); // Register-indirect
> value?
> + int64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0;
> DebugLoc DL;
> if (MI == MBB->end()) {
> // If MI is at basic block end then use last instruction's
> location.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Jul 9 15:28:37
> 2013
> @@ -612,11 +612,13 @@ bool FastISel::SelectCall(const User *I)
> return true;
> }
>
> + unsigned Offset = 0;
> Optional<MachineOperand> Op;
> if (const Argument *Arg = dyn_cast<Argument>(Address))
> // Some arguments' frame index is recorded during argument lowering.
> - if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
> - Op = MachineOperand::CreateFI(FI);
> + Offset = FuncInfo.getArgumentFrameIndex(Arg);
> + if (Offset)
> + Op = MachineOperand::CreateFI(Offset);
> if (!Op)
> if (unsigned Reg = lookUpRegForValue(Address))
> Op = MachineOperand::CreateReg(Reg, false);
> @@ -638,12 +640,16 @@ bool FastISel::SelectCall(const User *I)
> Op =
> MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
> false);
>
> - if (Op && Op->isReg())
> - Op->setIsDebug(true);
> -
> if (Op)
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> - TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
> + if (Op->isReg()) {
> + Op->setIsDebug(true);
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> + TII.get(TargetOpcode::DBG_VALUE),
> + /* IsIndirect */
> DI->getAddress()->getType()->isPointerTy(),
> + Op->getReg(), Offset, DI->getVariable());
> + } else
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
> +
> TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
> .addMetadata(DI->getVariable());
> else
> // We can't yet handle anything else here because it would require
> @@ -676,9 +682,9 @@ bool FastISel::SelectCall(const User *I)
> .addFPImm(CF).addImm(DI->getOffset())
> .addMetadata(DI->getVariable());
> } else if (unsigned Reg = lookUpRegForValue(V)) {
> - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
> - .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
> - .addMetadata(DI->getVariable());
> + bool IsIndirect = DI->getOffset() != 0;
> + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, IsIndirect,
> + Reg, DI->getOffset(), DI->getVariable());
> } else {
> // We can't yet handle anything else here because it would require
> // generating code, thus altering codegen because of debug info.
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Jul 9
> 15:28:37 2013
> @@ -678,7 +678,13 @@ InstrEmitter::EmitDbgValue(SDDbgValue *S
> MIB.addReg(0U);
> }
>
> - MIB.addImm(Offset).addMetadata(MDPtr);
> + if (Offset != 0) // Indirect addressing.
> + MIB.addImm(Offset);
> + else
> + MIB.addReg(0U, RegState::Debug);
> +
> + MIB.addMetadata(MDPtr);
> +
> return &*MIB;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jul 9
> 15:28:37 2013
> @@ -4422,11 +4422,15 @@ SelectionDAGBuilder::EmitFuncArgumentDbg
> return false;
>
> if (Op->isReg())
> - Op->setIsDebug();
> -
> - FuncInfo.ArgDbgValues.push_back(
> + FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
> +
> TII->get(TargetOpcode::DBG_VALUE),
> + /* IsIndirect */ Offset != 0,
> + Op->getReg(), Offset,
> Variable));
> + else
> + FuncInfo.ArgDbgValues.push_back(
> BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
> .addOperand(*Op).addImm(Offset).addMetadata(Variable));
> +
> return true;
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Jul 9
> 15:28:37 2013
> @@ -421,12 +421,13 @@ bool SelectionDAGISel::runOnMachineFunct
> MachineBasicBlock::iterator InsertPos = Def;
> const MDNode *Variable =
> MI->getOperand(MI->getNumOperands()-1).getMetadata();
> - unsigned Offset = MI->getOperand(1).getImm();
> + bool IsIndirect = MI->getOperand(1).isImm();
> + unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
> // Def is never a terminator here, so it is ok to increment
> InsertPos.
> BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
> - TII.get(TargetOpcode::DBG_VALUE))
> - .addReg(LDI->second, RegState::Debug)
> - .addImm(Offset).addMetadata(Variable);
> + TII.get(TargetOpcode::DBG_VALUE),
> + IsIndirect,
> + LDI->second, Offset, Variable);
>
> // If this vreg is directly copied into an exported register then
> // that COPY instructions also need DBG_VALUE, if it is the only
> @@ -445,9 +446,10 @@ bool SelectionDAGISel::runOnMachineFunct
> if (CopyUseMI) {
> MachineInstr *NewMI =
> BuildMI(*MF, CopyUseMI->getDebugLoc(),
> - TII.get(TargetOpcode::DBG_VALUE))
> - .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
> - .addImm(Offset).addMetadata(Variable);
> + TII.get(TargetOpcode::DBG_VALUE),
> + IsIndirect,
> + CopyUseMI->getOperand(0).getReg(),
> + Offset, Variable);
> MachineBasicBlock::iterator Pos = CopyUseMI;
> EntryMBB->insertAfter(Pos, NewMI);
> }
>
> Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Tue Jul 9 15:28:37 2013
> @@ -40,7 +40,7 @@ declare void @llvm.dbg.value(metadata, i
> !21 = metadata !{metadata !6, metadata !11}
> !22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"}
>
> -; Check that variable bar:b value range is appropriately trucated in
> debug info.
> +; Check that variable bar:b value range is appropriately truncated in
> debug info.
> ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'
> ; Here Ltmp7 is the end of the location range.
>
> @@ -54,7 +54,7 @@ declare void @llvm.dbg.value(metadata, i
> ;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}
> ;CHECK-NEXT: .short Lset
> ;CHECK-NEXT: Ltmp
> -;CHECK-NEXT: .byte 85
> +;CHECK-NEXT: .byte 85 ## DW_OP_reg
> ;CHECK-NEXT: Ltmp
> ;CHECK-NEXT: .quad 0
> ;CHECK-NEXT: .quad 0
>
> Modified: llvm/trunk/test/DebugInfo/X86/op_deref.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/op_deref.ll?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/X86/op_deref.ll (original)
> +++ llvm/trunk/test/DebugInfo/X86/op_deref.ll Tue Jul 9 15:28:37 2013
> @@ -1,10 +1,16 @@
> ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj
> -; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
> +; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
> -check-prefix=DW-CHECK
>
> -; CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
> +; DW-CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000067] = "vla")
> ; FIXME: The location here needs to be fixed, but llvm-dwarfdump doesn't
> handle
> ; DW_AT_location lists yet.
> -; CHECK: DW_AT_location [DW_FORM_data4] (0x00000000)
> +; DW-CHECK: DW_AT_location [DW_FORM_data4]
> (0x00000000)
> +
> +; Unfortunately llvm-dwarfdump can't unparse a list of DW_AT_locations
> +; right now, so we check the asm output:
> +; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm |
> FileCheck %s -check-prefix=ASM-CHECK
> +; vla should have a register-indirect address at one point.
> +; ASM-CHECK: DEBUG_VALUE: vla <- [RCX+0]
>
> define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {
> entry:
>
> Modified: llvm/trunk/test/DebugInfo/X86/parameters.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/parameters.ll?rev=185966&r1=185965&r2=185966&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/X86/parameters.ll (original)
> +++ llvm/trunk/test/DebugInfo/X86/parameters.ll Tue Jul 9 15:28:37 2013
> @@ -24,9 +24,9 @@
>
> ; CHECK: debug_info contents
> ; CHECK: DW_AT_name{{.*}} = "f"
> -; 0x74 is DW_OP_breg0 + 4, showing that the parameter is accessed
> indirectly
> +; 0x74 is DW_OP_breg4, showing that the parameter is accessed indirectly
> ; (with a zero offset) from the register parameter
> -; CHECK: DW_AT_location{{.*}}(<0x02> 74 00 )
> +; CHECK: DW_AT_location{{.*}}(<0x0{{.}}> 74 00
>
> ; CHECK: DW_AT_name{{.*}} = "g"
> ; CHECK: DW_AT_location{{.*}}([[G_LOC:0x[0-9]*]])
>
> Added: llvm/trunk/test/DebugInfo/X86/vla.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/vla.ll?rev=185966&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/X86/vla.ll (added)
> +++ llvm/trunk/test/DebugInfo/X86/vla.ll Tue Jul 9 15:28:37 2013
> @@ -0,0 +1,104 @@
> +; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - |
> FileCheck %s
> +; Ensure that we generate a breg+0 location for the variable length array
> a.
> +; CHECK: ##DEBUG_VALUE: vla:a <- [RDX+0]
> +; rdar://problem/13658587
> +;
> +; generated from:
> +;
> +; int vla(int n) {
> +; int a[n];
> +; a[0] = 42;
> +; return a[n-1];
> +; }
> +;
> +; int main(int argc, char** argv) {
> +; return vla(argc);
> +; }
> +
> +; ModuleID = 'vla.c'
> +target datalayout =
> "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
> +target triple = "x86_64-apple-macosx10.8.0"
> +
> +; Function Attrs: nounwind ssp uwtable
> +define i32 @vla(i32 %n) nounwind ssp uwtable {
> +entry:
> + %n.addr = alloca i32, align 4
> + %saved_stack = alloca i8*
> + %cleanup.dest.slot = alloca i32
> + store i32 %n, i32* %n.addr, align 4
> + call void @llvm.dbg.declare(metadata !{i32* %n.addr}, metadata !15),
> !dbg !16
> + %0 = load i32* %n.addr, align 4, !dbg !17
> + %1 = zext i32 %0 to i64, !dbg !17
> + %2 = call i8* @llvm.stacksave(), !dbg !17
> + store i8* %2, i8** %saved_stack, !dbg !17
> + %vla = alloca i32, i64 %1, align 16, !dbg !17
> + call void @llvm.dbg.declare(metadata !{i32* %vla}, metadata !18), !dbg
> !17
> + %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22
> + store i32 42, i32* %arrayidx, align 4, !dbg !22
> + %3 = load i32* %n.addr, align 4, !dbg !23
> + %sub = sub nsw i32 %3, 1, !dbg !23
> + %idxprom = sext i32 %sub to i64, !dbg !23
> + %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
> + %4 = load i32* %arrayidx1, align 4, !dbg !23
> + store i32 1, i32* %cleanup.dest.slot
> + %5 = load i8** %saved_stack, !dbg !24
> + call void @llvm.stackrestore(i8* %5), !dbg !24
> + ret i32 %4, !dbg !23
> +}
> +
> +; Function Attrs: nounwind readnone
> +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
> +
> +; Function Attrs: nounwind
> +declare i8* @llvm.stacksave() nounwind
> +
> +; Function Attrs: nounwind
> +declare void @llvm.stackrestore(i8*) nounwind
> +
> +; Function Attrs: nounwind ssp uwtable
> +define i32 @main(i32 %argc, i8** %argv) nounwind ssp uwtable {
> +entry:
> + %retval = alloca i32, align 4
> + %argc.addr = alloca i32, align 4
> + %argv.addr = alloca i8**, align 8
> + store i32 0, i32* %retval
> + store i32 %argc, i32* %argc.addr, align 4
> + call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !25),
> !dbg !26
> + store i8** %argv, i8*** %argv.addr, align 8
> + call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata
> !27), !dbg !26
> + %0 = load i32* %argc.addr, align 4, !dbg !28
> + %call = call i32 @vla(i32 %0), !dbg !28
> + ret i32 %call, !dbg !28
> +}
> +
> +!llvm.dbg.cu = !{!0}
> +
> +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version
> 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata
> !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ]
> [/vla.c] [DW_LANG_C99]
> +!1 = metadata !{metadata !"vla.c", metadata !""}
> +!2 = metadata !{i32 0}
> +!3 = metadata !{metadata !4, metadata !9}
> +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"vla",
> metadata !"vla", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32
> 0, i32 0, null, i32 256, i1 false, i32 (i32)* @vla, null, null, metadata
> !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [vla]
> +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ]
> [/vla.c]
> +!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64
> 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [
> DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
> +!7 = metadata !{metadata !8, metadata !8}
> +!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32,
> i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32,
> align 32, offset 0, enc DW_ATE_signed]
> +!9 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main",
> metadata !"main", metadata !"", i32 7, metadata !10, i1 false, i1 true, i32
> 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null,
> metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
> +!10 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0,
> i64 0, i64 0, i32 0, null, metadata !11, i32 0, i32 0} ; [
> DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
> +!11 = metadata !{metadata !8, metadata !8, metadata !12}
> +!12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64
> 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64,
> align 64, offset 0] [from ]
> +!13 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64
> 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64,
> align 64, offset 0] [from char]
> +!14 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8,
> i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8,
> align 8, offset 0, enc DW_ATE_signed_char]
> +!15 = metadata !{i32 786689, metadata !4, metadata !"n", metadata !5, i32
> 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [n] [line 1]
> +!16 = metadata !{i32 1, i32 0, metadata !4, null}
> +!17 = metadata !{i32 2, i32 0, metadata !4, null}
> +!18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32
> 2, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2]
> +!19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64
> 32, i32 0, i32 0, metadata !8, metadata !20, i32 0, i32 0} ; [
> DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
> +!20 = metadata !{metadata !21}
> +!21 = metadata !{i32 786465, i64 0, i64 -1} ; [
> DW_TAG_subrange_type ] [unbounded]
> +!22 = metadata !{i32 3, i32 0, metadata !4, null}
> +!23 = metadata !{i32 4, i32 0, metadata !4, null}
> +!24 = metadata !{i32 5, i32 0, metadata !4, null}
> +!25 = metadata !{i32 786689, metadata !9, metadata !"argc", metadata !5,
> i32 16777223, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc]
> [line 7]
> +!26 = metadata !{i32 7, i32 0, metadata !9, null}
> +!27 = metadata !{i32 786689, metadata !9, metadata !"argv", metadata !5,
> i32 33554439, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv]
> [line 7]
> +!28 = metadata !{i32 8, i32 0, metadata !9, null}
>
>
>
>
> ------------------------------
>
> Message: 10
> Date: Tue, 9 Jul 2013 16:31:40 -0400
> From: Aaron Ballman <aaron at aaronballman.com>
> To: Jack Carter <jcarter at mips.com>, Richard Osborne <richard at xmos.com>
> Cc: llvm-commits <llvm-commits at cs.uiuc.edu>
> Subject: Re: [llvm-commits] [llvm] r159203 - in /llvm/trunk:
> lib/Target/ARM/ARMAsmPrinter.cpp
> lib/Target/CellSPU/SPUAsmPrinter.cpp
> lib/Target/Hexagon/HexagonAsmPrinter.cpp
> lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> lib/Target/PowerPC/PPCAsmPrinter.cpp
> lib/Target/Sparc/SparcAsmPrinter.cpp
> lib/Target/X86/X86AsmPrinter.cpp
> lib/Target/XCore/XCoreAsmPrinter.cpp
> test/CodeGen/Generic/asm-large-immediate.ll
> Message-ID:
> <CAAt6xTuK8S2dpMA4Yep7gDnNquMF+s4HDSprKuJPu2x=
> p78uxw at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> I realize this commit is ancient, but I found something that was kind
> of suspect while doing some code spelunking. This code has some
> incorrect indentation, where it is indented at the same level as a
> secondary if statement, but it should not be. So when ExtraCode[0] !=
> 0, the printOperand call is never made in two places (detailed below).
> What's more, this code adds switch statements with no case labels
> (just a default).
>
> I've attached a patch that I believe is what the original patch was
> intending, but since I don't understand the original intent, I'm
> looking for eyeballs.
>
> Thanks!
>
> ~Aaron
>
> On Tue, Jun 26, 2012 at 9:49 AM, Jack Carter <jcarter at mips.com> wrote:
> > Author: jacksprat
> > Date: Tue Jun 26 08:49:27 2012
> > New Revision: 159203
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=159203&view=rev
> > Log:
> > There are a number of generic inline asm operand modifiers that
> > up to r158925 were handled as processor specific. Making them
> > generic and putting tests for these modifiers in the CodeGen/Generic
> > directory caused a number of targets to fail.
> >
> > This commit addresses that problem by having the targets call
> > the generic routine for generic modifiers that they don't currently
> > have explicit code for.
> >
> > For now only generic print operands 'c' and 'n' are supported.vi
> >
> >
> > Affected files:
> >
> > test/CodeGen/Generic/asm-large-immediate.ll
> > lib/Target/PowerPC/PPCAsmPrinter.cpp
> > lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> > lib/Target/ARM/ARMAsmPrinter.cpp
> > lib/Target/XCore/XCoreAsmPrinter.cpp
> > lib/Target/X86/X86AsmPrinter.cpp
> > lib/Target/Hexagon/HexagonAsmPrinter.cpp
> > lib/Target/CellSPU/SPUAsmPrinter.cpp
> > lib/Target/Sparc/SparcAsmPrinter.cpp
> > lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> > lib/Target/Mips/MipsAsmPrinter.cpp
> >
> > MSP430 isn't represented because it did not even run with
> > the long existing 'c' modifier and it was not apparent what
> > needs to be done to get it inline asm ready.
> >
> > Contributer: Jack Carter
> >
> >
> > Modified:
> > llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> > llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
> > llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
> > llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> > llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> > llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
> > llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
> > llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
> > llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> > llvm/trunk/test/CodeGen/Generic/asm-large-immediate.ll
> >
> > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jun 26 08:49:27 2012
> > @@ -422,7 +422,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant,
> ExtraCode, O);
> > case 'a': // Print as a memory address.
> > if (MI->getOperand(OpNum).isReg()) {
> > O << "["
> >
> > Modified: llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/CellSPU/SPUAsmPrinter.cpp Tue Jun 26 08:49:27
> 2012
> > @@ -301,7 +301,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > case 'L': // Write second word of DImode reference.
> > // Verify that this operand has two consecutive registers.
> > if (!MI->getOperand(OpNo).isReg() ||
> >
> > Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Tue Jun 26
> 08:49:27 2012
> > @@ -133,7 +133,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, OS);
> > case 'c': // Don't print "$" before a global var name or constant.
> > // Hexagon never has a prefix.
> > printOperand(MI, OpNo, OS);
> >
> > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Tue Jun 26
> 08:49:27 2012
> > @@ -200,7 +200,13 @@
> > unsigned AsmVariant,const char *ExtraCode, raw_ostream
> &O) {
> > // Does this asm operand have a single letter operand modifier?
> > if (ExtraCode && ExtraCode[0])
> > - return true; // Unknown modifier.
> > + if (ExtraCode[1] != 0) return true; // Unknown modifier.
> > +
> > + switch (ExtraCode[0]) {
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > + }
>
> Here.
>
> >
> > printOperand(MI, OpNo, O);
> > return false;
> >
> > Modified: llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp Tue Jun 26 08:49:27
> 2012
> > @@ -1914,7 +1914,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > case 'r':
> > break;
> > }
> >
> > Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Tue Jun 26 08:49:27
> 2012
> > @@ -248,7 +248,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > case 'c': // Don't print "$" before a global var name or constant.
> > break; // PPC never has a prefix.
> > case 'L': // Write second word of DImode reference.
> >
> > Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Tue Jun 26 08:49:27
> 2012
> > @@ -187,7 +187,9 @@
> > if (ExtraCode[1] != 0) return true; // Unknown modifier.
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > case 'r':
> > break;
> > }
> >
> > Modified: llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp Tue Jun 26 08:49:27 2012
> > @@ -407,7 +407,9 @@
> > const MachineOperand &MO = MI->getOperand(OpNo);
> >
> > switch (ExtraCode[0]) {
> > - default: return true; // Unknown modifier.
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > case 'a': // This is an address. Currently only 'i' and 'r' are
> expected.
> > if (MO.isImm()) {
> > O << MO.getImm();
> >
> > Modified: llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
> > +++ llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp Tue Jun 26 08:49:27
> 2012
> > @@ -260,7 +260,17 @@
> > bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned
> OpNo,
> > unsigned AsmVariant,const char
> *ExtraCode,
> > raw_ostream &O) {
> > - printOperand(MI, OpNo, O);
> > + // Does this asm operand have a single letter operand modifier?
> > + if (ExtraCode && ExtraCode[0])
> > + if (ExtraCode[1] != 0) return true; // Unknown modifier.
> > +
> > + switch (ExtraCode[0]) {
> > + default:
> > + // See if this is a generic print operand
> > + return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant,
> ExtraCode, O);
> > + }
>
> Here.
>
> > +
> > +printOperand(MI, OpNo, O);
> > return false;
> > }
> >
> >
> > Modified: llvm/trunk/test/CodeGen/Generic/asm-large-immediate.ll
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/asm-large-immediate.ll?rev=159203&r1=159202&r2=159203&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/test/CodeGen/Generic/asm-large-immediate.ll (original)
> > +++ llvm/trunk/test/CodeGen/Generic/asm-large-immediate.ll Tue Jun 26
> 08:49:27 2012
> > @@ -1,8 +1,5 @@
> > ; RUN: llc < %s | FileCheck %s
> >
> > -; FIXME: Seek around r158932 to r158946.
> > -; XFAIL: powerpc
> > -
> > define void @test() {
> > entry:
> > ; CHECK: /* result: 68719476738 */
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> -------------- next part --------------
> A non-text attachment was scrubbed...
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> URL: <
> http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20130709/f6d745f2/attachment-0001.obj
> >
>
> ------------------------------
>
> Message: 11
> Date: Tue, 9 Jul 2013 13:44:04 -0700
> From: Stephen Lin <swlin at post.harvard.edu>
> To: llvm-commits at cs.uiuc.edu
> Subject: [PATCH] Allow FMAs in safe math mode in some cases when one
> operand of the fmul is either exactly 0.0 or exactly 1.0.
> Message-ID:
> <CAP2HvmCa5QaJ0R6p5NgCJQ1b2K=
> iVW0iSDcX6S-ipDG2uESbBw at mail.gmail.com>
> Content-Type: text/plain; charset="utf-8"
>
> Hi,
>
> The attached patch allows FMAs to be formed in DAGCombiner even
> without unsafe math mode when one operand is known to be either 0.0 or
> 1.0 exactly (this is safe because no rounding occurs in the fmul step,
> and behavior on all limit case inputs is preserved, as far as I can
> tell.)
>
> This allows formation of FMAs in cases like the following:
>
> extern bool f;
>
> double foo(bool a, double b, double c, double d, double e) {
> return (b * double(a) + c) + (d * (1.0 - double(a)) + e);
> }
>
> The intent of this patch is to address a subset of the issues which
> required r181216 to be partially reverted (tracked as PR16164)
> although there are still many other cases affected by that patch which
> are not resolved.
>
> Unfortunately, due to SelectionDAG limitations, this transformation
> will only be done if the input can be determined to be zero or one
> with information only in the same basic block, so depending on
> optimization settings and phase ordering, will fail in cases like the
> following:
>
> extern bool f;
>
> double foo(bool a, double b, double c, double d, double e) {
> if (a)
> return b * double(a) + c;
> else
> return d * (1.0 - double(a)) + e;
> }
>
> Please let me know if you have any feedback.
>
> Thanks,
> Stephen
> -------------- next part --------------
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> http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20130709/a52fd550/attachment-0001.obj
> >
>
> ------------------------------
>
> Message: 12
> Date: Tue, 9 Jul 2013 13:53:59 -0700
> From: Michael Spencer <bigcheesegs at gmail.com>
> To: rafael.espindola at gmail.com, silvas at purdue.edu,
> bigcheesegs at gmail.com
> Cc: llvm-commits at cs.uiuc.edu, shankarke at gmail.com
> Subject: Re: [PATCH] [Object] Split the ELF interface into 3 parts.
> Message-ID:
> <20783f8f7220d6fad53635848701e4d5 at llvm-reviews.chandlerc.com>
> Content-Type: text/plain; charset="utf-8"
>
> Address review comments.
>
> Hi rafael, silvas,
>
> http://llvm-reviews.chandlerc.com/D1033
>
> CHANGE SINCE LAST DIFF
> http://llvm-reviews.chandlerc.com/D1033?vs=2549&id=2733#toc
>
> Files:
> include/llvm/Object/ELF.h
> include/llvm/Object/ELFObjectFile.h
> include/llvm/Object/ELFTypes.h
> include/llvm/Object/RelocVisitor.h
> lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
> lib/MC/MCObjectSymbolizer.cpp
> lib/Object/ELFObjectFile.cpp
> lib/Target/X86/MCTargetDesc/X86ELFRelocationInfo.cpp
> tools/llvm-objdump/ELFDump.cpp
> tools/llvm-readobj/ELFDumper.cpp
> tools/yaml2obj/yaml2elf.cpp
> -------------- next part --------------
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> http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20130709/8dab5898/attachment.bin
> >
>
> ------------------------------
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> End of llvm-commits Digest, Vol 109, Issue 44
> *********************************************
>
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