[llvm] r205090 - ARM64: initial backend import
Tim Northover
tnorthover at apple.com
Sat Mar 29 03:18:15 PDT 2014
Added: llvm/trunk/test/CodeGen/ARM64/vext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vext.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vext.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vext.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,464 @@
+; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
+
+define void @test_vext_s8() nounwind ssp {
+ ; CHECK-LABEL: test_vext_s8:
+ ; CHECK: {{ext.8.*#1}}
+ %xS8x8 = alloca <8 x i8>, align 8
+ %__a = alloca <8 x i8>, align 8
+ %__b = alloca <8 x i8>, align 8
+ %tmp = load <8 x i8>* %xS8x8, align 8
+ store <8 x i8> %tmp, <8 x i8>* %__a, align 8
+ %tmp1 = load <8 x i8>* %xS8x8, align 8
+ store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
+ %tmp2 = load <8 x i8>* %__a, align 8
+ %tmp3 = load <8 x i8>* %__b, align 8
+ %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
+ store <8 x i8> %vext, <8 x i8>* %xS8x8, align 8
+ ret void
+}
+
+define void @test_vext_u8() nounwind ssp {
+ ; CHECK-LABEL: test_vext_u8:
+ ; CHECK: {{ext.8.*#2}}
+ %xU8x8 = alloca <8 x i8>, align 8
+ %__a = alloca <8 x i8>, align 8
+ %__b = alloca <8 x i8>, align 8
+ %tmp = load <8 x i8>* %xU8x8, align 8
+ store <8 x i8> %tmp, <8 x i8>* %__a, align 8
+ %tmp1 = load <8 x i8>* %xU8x8, align 8
+ store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
+ %tmp2 = load <8 x i8>* %__a, align 8
+ %tmp3 = load <8 x i8>* %__b, align 8
+ %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
+ store <8 x i8> %vext, <8 x i8>* %xU8x8, align 8
+ ret void
+}
+
+define void @test_vext_p8() nounwind ssp {
+ ; CHECK-LABEL: test_vext_p8:
+ ; CHECK: {{ext.8.*#3}}
+ %xP8x8 = alloca <8 x i8>, align 8
+ %__a = alloca <8 x i8>, align 8
+ %__b = alloca <8 x i8>, align 8
+ %tmp = load <8 x i8>* %xP8x8, align 8
+ store <8 x i8> %tmp, <8 x i8>* %__a, align 8
+ %tmp1 = load <8 x i8>* %xP8x8, align 8
+ store <8 x i8> %tmp1, <8 x i8>* %__b, align 8
+ %tmp2 = load <8 x i8>* %__a, align 8
+ %tmp3 = load <8 x i8>* %__b, align 8
+ %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ store <8 x i8> %vext, <8 x i8>* %xP8x8, align 8
+ ret void
+}
+
+define void @test_vext_s16() nounwind ssp {
+ ; CHECK-LABEL: test_vext_s16:
+ ; CHECK: {{ext.8.*#2}}
+ %xS16x4 = alloca <4 x i16>, align 8
+ %__a = alloca <4 x i16>, align 8
+ %__b = alloca <4 x i16>, align 8
+ %tmp = load <4 x i16>* %xS16x4, align 8
+ store <4 x i16> %tmp, <4 x i16>* %__a, align 8
+ %tmp1 = load <4 x i16>* %xS16x4, align 8
+ store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
+ %tmp2 = load <4 x i16>* %__a, align 8
+ %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
+ %tmp4 = load <4 x i16>* %__b, align 8
+ %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
+ %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ store <4 x i16> %vext, <4 x i16>* %xS16x4, align 8
+ ret void
+}
+
+define void @test_vext_u16() nounwind ssp {
+ ; CHECK-LABEL: test_vext_u16:
+ ; CHECK: {{ext.8.*#4}}
+ %xU16x4 = alloca <4 x i16>, align 8
+ %__a = alloca <4 x i16>, align 8
+ %__b = alloca <4 x i16>, align 8
+ %tmp = load <4 x i16>* %xU16x4, align 8
+ store <4 x i16> %tmp, <4 x i16>* %__a, align 8
+ %tmp1 = load <4 x i16>* %xU16x4, align 8
+ store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
+ %tmp2 = load <4 x i16>* %__a, align 8
+ %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
+ %tmp4 = load <4 x i16>* %__b, align 8
+ %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
+ %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+ store <4 x i16> %vext, <4 x i16>* %xU16x4, align 8
+ ret void
+}
+
+define void @test_vext_p16() nounwind ssp {
+ ; CHECK-LABEL: test_vext_p16:
+ ; CHECK: {{ext.8.*#6}}
+ %xP16x4 = alloca <4 x i16>, align 8
+ %__a = alloca <4 x i16>, align 8
+ %__b = alloca <4 x i16>, align 8
+ %tmp = load <4 x i16>* %xP16x4, align 8
+ store <4 x i16> %tmp, <4 x i16>* %__a, align 8
+ %tmp1 = load <4 x i16>* %xP16x4, align 8
+ store <4 x i16> %tmp1, <4 x i16>* %__b, align 8
+ %tmp2 = load <4 x i16>* %__a, align 8
+ %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8>
+ %tmp4 = load <4 x i16>* %__b, align 8
+ %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16>
+ %vext = shufflevector <4 x i16> %tmp6, <4 x i16> %tmp7, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ store <4 x i16> %vext, <4 x i16>* %xP16x4, align 8
+ ret void
+}
+
+define void @test_vext_s32() nounwind ssp {
+ ; CHECK-LABEL: test_vext_s32:
+ ; CHECK: {{ext.8.*#4}}
+ %xS32x2 = alloca <2 x i32>, align 8
+ %__a = alloca <2 x i32>, align 8
+ %__b = alloca <2 x i32>, align 8
+ %tmp = load <2 x i32>* %xS32x2, align 8
+ store <2 x i32> %tmp, <2 x i32>* %__a, align 8
+ %tmp1 = load <2 x i32>* %xS32x2, align 8
+ store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
+ %tmp2 = load <2 x i32>* %__a, align 8
+ %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
+ %tmp4 = load <2 x i32>* %__b, align 8
+ %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
+ %vext = shufflevector <2 x i32> %tmp6, <2 x i32> %tmp7, <2 x i32> <i32 1, i32 2>
+ store <2 x i32> %vext, <2 x i32>* %xS32x2, align 8
+ ret void
+}
+
+define void @test_vext_u32() nounwind ssp {
+ ; CHECK-LABEL: test_vext_u32:
+ ; CHECK: {{ext.8.*#4}}
+ %xU32x2 = alloca <2 x i32>, align 8
+ %__a = alloca <2 x i32>, align 8
+ %__b = alloca <2 x i32>, align 8
+ %tmp = load <2 x i32>* %xU32x2, align 8
+ store <2 x i32> %tmp, <2 x i32>* %__a, align 8
+ %tmp1 = load <2 x i32>* %xU32x2, align 8
+ store <2 x i32> %tmp1, <2 x i32>* %__b, align 8
+ %tmp2 = load <2 x i32>* %__a, align 8
+ %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8>
+ %tmp4 = load <2 x i32>* %__b, align 8
+ %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32>
+ %vext = shufflevector <2 x i32> %tmp6, <2 x i32> %tmp7, <2 x i32> <i32 1, i32 2>
+ store <2 x i32> %vext, <2 x i32>* %xU32x2, align 8
+ ret void
+}
+
+define void @test_vext_f32() nounwind ssp {
+ ; CHECK-LABEL: test_vext_f32:
+ ; CHECK: {{ext.8.*#4}}
+ %xF32x2 = alloca <2 x float>, align 8
+ %__a = alloca <2 x float>, align 8
+ %__b = alloca <2 x float>, align 8
+ %tmp = load <2 x float>* %xF32x2, align 8
+ store <2 x float> %tmp, <2 x float>* %__a, align 8
+ %tmp1 = load <2 x float>* %xF32x2, align 8
+ store <2 x float> %tmp1, <2 x float>* %__b, align 8
+ %tmp2 = load <2 x float>* %__a, align 8
+ %tmp3 = bitcast <2 x float> %tmp2 to <8 x i8>
+ %tmp4 = load <2 x float>* %__b, align 8
+ %tmp5 = bitcast <2 x float> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <2 x float>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <2 x float>
+ %vext = shufflevector <2 x float> %tmp6, <2 x float> %tmp7, <2 x i32> <i32 1, i32 2>
+ store <2 x float> %vext, <2 x float>* %xF32x2, align 8
+ ret void
+}
+
+define void @test_vext_s64() nounwind ssp {
+ ; CHECK-LABEL: test_vext_s64:
+ ; CHECK_FIXME: {{ext.8.*#1}}
+ ; this just turns into a load of the second element
+ %xS64x1 = alloca <1 x i64>, align 8
+ %__a = alloca <1 x i64>, align 8
+ %__b = alloca <1 x i64>, align 8
+ %tmp = load <1 x i64>* %xS64x1, align 8
+ store <1 x i64> %tmp, <1 x i64>* %__a, align 8
+ %tmp1 = load <1 x i64>* %xS64x1, align 8
+ store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
+ %tmp2 = load <1 x i64>* %__a, align 8
+ %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
+ %tmp4 = load <1 x i64>* %__b, align 8
+ %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
+ %vext = shufflevector <1 x i64> %tmp6, <1 x i64> %tmp7, <1 x i32> <i32 1>
+ store <1 x i64> %vext, <1 x i64>* %xS64x1, align 8
+ ret void
+}
+
+define void @test_vext_u64() nounwind ssp {
+ ; CHECK-LABEL: test_vext_u64:
+ ; CHECK_FIXME: {{ext.8.*#1}}
+ ; this is turned into a simple load of the 2nd element
+ %xU64x1 = alloca <1 x i64>, align 8
+ %__a = alloca <1 x i64>, align 8
+ %__b = alloca <1 x i64>, align 8
+ %tmp = load <1 x i64>* %xU64x1, align 8
+ store <1 x i64> %tmp, <1 x i64>* %__a, align 8
+ %tmp1 = load <1 x i64>* %xU64x1, align 8
+ store <1 x i64> %tmp1, <1 x i64>* %__b, align 8
+ %tmp2 = load <1 x i64>* %__a, align 8
+ %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8>
+ %tmp4 = load <1 x i64>* %__b, align 8
+ %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8>
+ %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64>
+ %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64>
+ %vext = shufflevector <1 x i64> %tmp6, <1 x i64> %tmp7, <1 x i32> <i32 1>
+ store <1 x i64> %vext, <1 x i64>* %xU64x1, align 8
+ ret void
+}
+
+define void @test_vextq_s8() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_s8:
+ ; CHECK: {{ext.16.*#4}}
+ %xS8x16 = alloca <16 x i8>, align 16
+ %__a = alloca <16 x i8>, align 16
+ %__b = alloca <16 x i8>, align 16
+ %tmp = load <16 x i8>* %xS8x16, align 16
+ store <16 x i8> %tmp, <16 x i8>* %__a, align 16
+ %tmp1 = load <16 x i8>* %xS8x16, align 16
+ store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
+ %tmp2 = load <16 x i8>* %__a, align 16
+ %tmp3 = load <16 x i8>* %__b, align 16
+ %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
+ store <16 x i8> %vext, <16 x i8>* %xS8x16, align 16
+ ret void
+}
+
+define void @test_vextq_u8() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_u8:
+ ; CHECK: {{ext.16.*#5}}
+ %xU8x16 = alloca <16 x i8>, align 16
+ %__a = alloca <16 x i8>, align 16
+ %__b = alloca <16 x i8>, align 16
+ %tmp = load <16 x i8>* %xU8x16, align 16
+ store <16 x i8> %tmp, <16 x i8>* %__a, align 16
+ %tmp1 = load <16 x i8>* %xU8x16, align 16
+ store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
+ %tmp2 = load <16 x i8>* %__a, align 16
+ %tmp3 = load <16 x i8>* %__b, align 16
+ %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
+ store <16 x i8> %vext, <16 x i8>* %xU8x16, align 16
+ ret void
+}
+
+define void @test_vextq_p8() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_p8:
+ ; CHECK: {{ext.16.*#6}}
+ %xP8x16 = alloca <16 x i8>, align 16
+ %__a = alloca <16 x i8>, align 16
+ %__b = alloca <16 x i8>, align 16
+ %tmp = load <16 x i8>* %xP8x16, align 16
+ store <16 x i8> %tmp, <16 x i8>* %__a, align 16
+ %tmp1 = load <16 x i8>* %xP8x16, align 16
+ store <16 x i8> %tmp1, <16 x i8>* %__b, align 16
+ %tmp2 = load <16 x i8>* %__a, align 16
+ %tmp3 = load <16 x i8>* %__b, align 16
+ %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21>
+ store <16 x i8> %vext, <16 x i8>* %xP8x16, align 16
+ ret void
+}
+
+define void @test_vextq_s16() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_s16:
+ ; CHECK: {{ext.16.*#14}}
+ %xS16x8 = alloca <8 x i16>, align 16
+ %__a = alloca <8 x i16>, align 16
+ %__b = alloca <8 x i16>, align 16
+ %tmp = load <8 x i16>* %xS16x8, align 16
+ store <8 x i16> %tmp, <8 x i16>* %__a, align 16
+ %tmp1 = load <8 x i16>* %xS16x8, align 16
+ store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
+ %tmp2 = load <8 x i16>* %__a, align 16
+ %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
+ %tmp4 = load <8 x i16>* %__b, align 16
+ %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
+ %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14>
+ store <8 x i16> %vext, <8 x i16>* %xS16x8, align 16
+ ret void
+}
+
+define void @test_vextq_u16() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_u16:
+ ; CHECK: {{ext.16.*#8}}
+ %xU16x8 = alloca <8 x i16>, align 16
+ %__a = alloca <8 x i16>, align 16
+ %__b = alloca <8 x i16>, align 16
+ %tmp = load <8 x i16>* %xU16x8, align 16
+ store <8 x i16> %tmp, <8 x i16>* %__a, align 16
+ %tmp1 = load <8 x i16>* %xU16x8, align 16
+ store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
+ %tmp2 = load <8 x i16>* %__a, align 16
+ %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
+ %tmp4 = load <8 x i16>* %__b, align 16
+ %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
+ %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+ store <8 x i16> %vext, <8 x i16>* %xU16x8, align 16
+ ret void
+}
+
+define void @test_vextq_p16() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_p16:
+ ; CHECK: {{ext.16.*#10}}
+ %xP16x8 = alloca <8 x i16>, align 16
+ %__a = alloca <8 x i16>, align 16
+ %__b = alloca <8 x i16>, align 16
+ %tmp = load <8 x i16>* %xP16x8, align 16
+ store <8 x i16> %tmp, <8 x i16>* %__a, align 16
+ %tmp1 = load <8 x i16>* %xP16x8, align 16
+ store <8 x i16> %tmp1, <8 x i16>* %__b, align 16
+ %tmp2 = load <8 x i16>* %__a, align 16
+ %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8>
+ %tmp4 = load <8 x i16>* %__b, align 16
+ %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16>
+ %vext = shufflevector <8 x i16> %tmp6, <8 x i16> %tmp7, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12>
+ store <8 x i16> %vext, <8 x i16>* %xP16x8, align 16
+ ret void
+}
+
+define void @test_vextq_s32() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_s32:
+ ; CHECK: {{ext.16.*#4}}
+ %xS32x4 = alloca <4 x i32>, align 16
+ %__a = alloca <4 x i32>, align 16
+ %__b = alloca <4 x i32>, align 16
+ %tmp = load <4 x i32>* %xS32x4, align 16
+ store <4 x i32> %tmp, <4 x i32>* %__a, align 16
+ %tmp1 = load <4 x i32>* %xS32x4, align 16
+ store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
+ %tmp2 = load <4 x i32>* %__a, align 16
+ %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
+ %tmp4 = load <4 x i32>* %__b, align 16
+ %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
+ %vext = shufflevector <4 x i32> %tmp6, <4 x i32> %tmp7, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ store <4 x i32> %vext, <4 x i32>* %xS32x4, align 16
+ ret void
+}
+
+define void @test_vextq_u32() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_u32:
+ ; CHECK: {{ext.16.*#8}}
+ %xU32x4 = alloca <4 x i32>, align 16
+ %__a = alloca <4 x i32>, align 16
+ %__b = alloca <4 x i32>, align 16
+ %tmp = load <4 x i32>* %xU32x4, align 16
+ store <4 x i32> %tmp, <4 x i32>* %__a, align 16
+ %tmp1 = load <4 x i32>* %xU32x4, align 16
+ store <4 x i32> %tmp1, <4 x i32>* %__b, align 16
+ %tmp2 = load <4 x i32>* %__a, align 16
+ %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8>
+ %tmp4 = load <4 x i32>* %__b, align 16
+ %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32>
+ %vext = shufflevector <4 x i32> %tmp6, <4 x i32> %tmp7, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+ store <4 x i32> %vext, <4 x i32>* %xU32x4, align 16
+ ret void
+}
+
+define void @test_vextq_f32() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_f32:
+ ; CHECK: {{ext.16.*#12}}
+ %xF32x4 = alloca <4 x float>, align 16
+ %__a = alloca <4 x float>, align 16
+ %__b = alloca <4 x float>, align 16
+ %tmp = load <4 x float>* %xF32x4, align 16
+ store <4 x float> %tmp, <4 x float>* %__a, align 16
+ %tmp1 = load <4 x float>* %xF32x4, align 16
+ store <4 x float> %tmp1, <4 x float>* %__b, align 16
+ %tmp2 = load <4 x float>* %__a, align 16
+ %tmp3 = bitcast <4 x float> %tmp2 to <16 x i8>
+ %tmp4 = load <4 x float>* %__b, align 16
+ %tmp5 = bitcast <4 x float> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <4 x float>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <4 x float>
+ %vext = shufflevector <4 x float> %tmp6, <4 x float> %tmp7, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
+ store <4 x float> %vext, <4 x float>* %xF32x4, align 16
+ ret void
+}
+
+define void @test_vextq_s64() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_s64:
+ ; CHECK: {{ext.16.*#8}}
+ %xS64x2 = alloca <2 x i64>, align 16
+ %__a = alloca <2 x i64>, align 16
+ %__b = alloca <2 x i64>, align 16
+ %tmp = load <2 x i64>* %xS64x2, align 16
+ store <2 x i64> %tmp, <2 x i64>* %__a, align 16
+ %tmp1 = load <2 x i64>* %xS64x2, align 16
+ store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
+ %tmp2 = load <2 x i64>* %__a, align 16
+ %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
+ %tmp4 = load <2 x i64>* %__b, align 16
+ %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
+ %vext = shufflevector <2 x i64> %tmp6, <2 x i64> %tmp7, <2 x i32> <i32 1, i32 2>
+ store <2 x i64> %vext, <2 x i64>* %xS64x2, align 16
+ ret void
+}
+
+define void @test_vextq_u64() nounwind ssp {
+ ; CHECK-LABEL: test_vextq_u64:
+ ; CHECK: {{ext.16.*#8}}
+ %xU64x2 = alloca <2 x i64>, align 16
+ %__a = alloca <2 x i64>, align 16
+ %__b = alloca <2 x i64>, align 16
+ %tmp = load <2 x i64>* %xU64x2, align 16
+ store <2 x i64> %tmp, <2 x i64>* %__a, align 16
+ %tmp1 = load <2 x i64>* %xU64x2, align 16
+ store <2 x i64> %tmp1, <2 x i64>* %__b, align 16
+ %tmp2 = load <2 x i64>* %__a, align 16
+ %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8>
+ %tmp4 = load <2 x i64>* %__b, align 16
+ %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8>
+ %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64>
+ %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64>
+ %vext = shufflevector <2 x i64> %tmp6, <2 x i64> %tmp7, <2 x i32> <i32 1, i32 2>
+ store <2 x i64> %vext, <2 x i64>* %xU64x2, align 16
+ ret void
+}
+
+; shuffles with an undef second operand can use an EXT also so long as the
+; indices wrap and stay sequential.
+; rdar://12051674
+define <16 x i8> @vext1(<16 x i8> %_a) nounwind {
+; CHECK-LABEL: vext1:
+; CHECK: ext.16b v0, v0, v0, #8
+ %vext = shufflevector <16 x i8> %_a, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <16 x i8> %vext
+}
+
+; <rdar://problem/12212062>
+define <2 x i64> @vext2(<2 x i64> %p0, <2 x i64> %p1) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: vext2:
+; CHECK: ext.16b v1, v1, v1, #8
+; CHECK: ext.16b v0, v0, v0, #8
+; CHECK: add.2d v0, v0, v1
+ %t0 = shufflevector <2 x i64> %p1, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+ %t1 = shufflevector <2 x i64> %p0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+ %t2 = add <2 x i64> %t1, %t0
+ ret <2 x i64> %t2
+}
Added: llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vfloatintrinsics.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,375 @@
+; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
+
+;;; Float vectors
+
+%v2f32 = type <2 x float>
+; CHECK: test_v2f32.sqrt:
+define %v2f32 @test_v2f32.sqrt(%v2f32 %a) {
+ ; CHECK: fsqrt.2s
+ %1 = call %v2f32 @llvm.sqrt.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.powi:
+define %v2f32 @test_v2f32.powi(%v2f32 %a, i32 %b) {
+ ; CHECK: pow
+ %1 = call %v2f32 @llvm.powi.v2f32(%v2f32 %a, i32 %b)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.sin:
+define %v2f32 @test_v2f32.sin(%v2f32 %a) {
+ ; CHECK: sin
+ %1 = call %v2f32 @llvm.sin.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.cos:
+define %v2f32 @test_v2f32.cos(%v2f32 %a) {
+ ; CHECK: cos
+ %1 = call %v2f32 @llvm.cos.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.pow:
+define %v2f32 @test_v2f32.pow(%v2f32 %a, %v2f32 %b) {
+ ; CHECK: pow
+ %1 = call %v2f32 @llvm.pow.v2f32(%v2f32 %a, %v2f32 %b)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.exp:
+define %v2f32 @test_v2f32.exp(%v2f32 %a) {
+ ; CHECK: exp
+ %1 = call %v2f32 @llvm.exp.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.exp2:
+define %v2f32 @test_v2f32.exp2(%v2f32 %a) {
+ ; CHECK: exp
+ %1 = call %v2f32 @llvm.exp2.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.log:
+define %v2f32 @test_v2f32.log(%v2f32 %a) {
+ ; CHECK: log
+ %1 = call %v2f32 @llvm.log.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.log10:
+define %v2f32 @test_v2f32.log10(%v2f32 %a) {
+ ; CHECK: log
+ %1 = call %v2f32 @llvm.log10.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.log2:
+define %v2f32 @test_v2f32.log2(%v2f32 %a) {
+ ; CHECK: log
+ %1 = call %v2f32 @llvm.log2.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.fma:
+define %v2f32 @test_v2f32.fma(%v2f32 %a, %v2f32 %b, %v2f32 %c) {
+ ; CHECK: fma
+ %1 = call %v2f32 @llvm.fma.v2f32(%v2f32 %a, %v2f32 %b, %v2f32 %c)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.fabs:
+define %v2f32 @test_v2f32.fabs(%v2f32 %a) {
+ ; CHECK: fabs
+ %1 = call %v2f32 @llvm.fabs.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.floor:
+define %v2f32 @test_v2f32.floor(%v2f32 %a) {
+ ; CHECK: frintm.2s
+ %1 = call %v2f32 @llvm.floor.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.ceil:
+define %v2f32 @test_v2f32.ceil(%v2f32 %a) {
+ ; CHECK: frintp.2s
+ %1 = call %v2f32 @llvm.ceil.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.trunc:
+define %v2f32 @test_v2f32.trunc(%v2f32 %a) {
+ ; CHECK: frintz.2s
+ %1 = call %v2f32 @llvm.trunc.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.rint:
+define %v2f32 @test_v2f32.rint(%v2f32 %a) {
+ ; CHECK: frintx.2s
+ %1 = call %v2f32 @llvm.rint.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+; CHECK: test_v2f32.nearbyint:
+define %v2f32 @test_v2f32.nearbyint(%v2f32 %a) {
+ ; CHECK: frinti.2s
+ %1 = call %v2f32 @llvm.nearbyint.v2f32(%v2f32 %a)
+ ret %v2f32 %1
+}
+
+declare %v2f32 @llvm.sqrt.v2f32(%v2f32) #0
+declare %v2f32 @llvm.powi.v2f32(%v2f32, i32) #0
+declare %v2f32 @llvm.sin.v2f32(%v2f32) #0
+declare %v2f32 @llvm.cos.v2f32(%v2f32) #0
+declare %v2f32 @llvm.pow.v2f32(%v2f32, %v2f32) #0
+declare %v2f32 @llvm.exp.v2f32(%v2f32) #0
+declare %v2f32 @llvm.exp2.v2f32(%v2f32) #0
+declare %v2f32 @llvm.log.v2f32(%v2f32) #0
+declare %v2f32 @llvm.log10.v2f32(%v2f32) #0
+declare %v2f32 @llvm.log2.v2f32(%v2f32) #0
+declare %v2f32 @llvm.fma.v2f32(%v2f32, %v2f32, %v2f32) #0
+declare %v2f32 @llvm.fabs.v2f32(%v2f32) #0
+declare %v2f32 @llvm.floor.v2f32(%v2f32) #0
+declare %v2f32 @llvm.ceil.v2f32(%v2f32) #0
+declare %v2f32 @llvm.trunc.v2f32(%v2f32) #0
+declare %v2f32 @llvm.rint.v2f32(%v2f32) #0
+declare %v2f32 @llvm.nearbyint.v2f32(%v2f32) #0
+
+;;;
+
+%v4f32 = type <4 x float>
+; CHECK: test_v4f32.sqrt:
+define %v4f32 @test_v4f32.sqrt(%v4f32 %a) {
+ ; CHECK: fsqrt.4s
+ %1 = call %v4f32 @llvm.sqrt.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.powi:
+define %v4f32 @test_v4f32.powi(%v4f32 %a, i32 %b) {
+ ; CHECK: pow
+ %1 = call %v4f32 @llvm.powi.v4f32(%v4f32 %a, i32 %b)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.sin:
+define %v4f32 @test_v4f32.sin(%v4f32 %a) {
+ ; CHECK: sin
+ %1 = call %v4f32 @llvm.sin.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.cos:
+define %v4f32 @test_v4f32.cos(%v4f32 %a) {
+ ; CHECK: cos
+ %1 = call %v4f32 @llvm.cos.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.pow:
+define %v4f32 @test_v4f32.pow(%v4f32 %a, %v4f32 %b) {
+ ; CHECK: pow
+ %1 = call %v4f32 @llvm.pow.v4f32(%v4f32 %a, %v4f32 %b)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.exp:
+define %v4f32 @test_v4f32.exp(%v4f32 %a) {
+ ; CHECK: exp
+ %1 = call %v4f32 @llvm.exp.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.exp2:
+define %v4f32 @test_v4f32.exp2(%v4f32 %a) {
+ ; CHECK: exp
+ %1 = call %v4f32 @llvm.exp2.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.log:
+define %v4f32 @test_v4f32.log(%v4f32 %a) {
+ ; CHECK: log
+ %1 = call %v4f32 @llvm.log.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.log10:
+define %v4f32 @test_v4f32.log10(%v4f32 %a) {
+ ; CHECK: log
+ %1 = call %v4f32 @llvm.log10.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.log2:
+define %v4f32 @test_v4f32.log2(%v4f32 %a) {
+ ; CHECK: log
+ %1 = call %v4f32 @llvm.log2.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.fma:
+define %v4f32 @test_v4f32.fma(%v4f32 %a, %v4f32 %b, %v4f32 %c) {
+ ; CHECK: fma
+ %1 = call %v4f32 @llvm.fma.v4f32(%v4f32 %a, %v4f32 %b, %v4f32 %c)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.fabs:
+define %v4f32 @test_v4f32.fabs(%v4f32 %a) {
+ ; CHECK: fabs
+ %1 = call %v4f32 @llvm.fabs.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.floor:
+define %v4f32 @test_v4f32.floor(%v4f32 %a) {
+ ; CHECK: frintm.4s
+ %1 = call %v4f32 @llvm.floor.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.ceil:
+define %v4f32 @test_v4f32.ceil(%v4f32 %a) {
+ ; CHECK: frintp.4s
+ %1 = call %v4f32 @llvm.ceil.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.trunc:
+define %v4f32 @test_v4f32.trunc(%v4f32 %a) {
+ ; CHECK: frintz.4s
+ %1 = call %v4f32 @llvm.trunc.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.rint:
+define %v4f32 @test_v4f32.rint(%v4f32 %a) {
+ ; CHECK: frintx.4s
+ %1 = call %v4f32 @llvm.rint.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+; CHECK: test_v4f32.nearbyint:
+define %v4f32 @test_v4f32.nearbyint(%v4f32 %a) {
+ ; CHECK: frinti.4s
+ %1 = call %v4f32 @llvm.nearbyint.v4f32(%v4f32 %a)
+ ret %v4f32 %1
+}
+
+declare %v4f32 @llvm.sqrt.v4f32(%v4f32) #0
+declare %v4f32 @llvm.powi.v4f32(%v4f32, i32) #0
+declare %v4f32 @llvm.sin.v4f32(%v4f32) #0
+declare %v4f32 @llvm.cos.v4f32(%v4f32) #0
+declare %v4f32 @llvm.pow.v4f32(%v4f32, %v4f32) #0
+declare %v4f32 @llvm.exp.v4f32(%v4f32) #0
+declare %v4f32 @llvm.exp2.v4f32(%v4f32) #0
+declare %v4f32 @llvm.log.v4f32(%v4f32) #0
+declare %v4f32 @llvm.log10.v4f32(%v4f32) #0
+declare %v4f32 @llvm.log2.v4f32(%v4f32) #0
+declare %v4f32 @llvm.fma.v4f32(%v4f32, %v4f32, %v4f32) #0
+declare %v4f32 @llvm.fabs.v4f32(%v4f32) #0
+declare %v4f32 @llvm.floor.v4f32(%v4f32) #0
+declare %v4f32 @llvm.ceil.v4f32(%v4f32) #0
+declare %v4f32 @llvm.trunc.v4f32(%v4f32) #0
+declare %v4f32 @llvm.rint.v4f32(%v4f32) #0
+declare %v4f32 @llvm.nearbyint.v4f32(%v4f32) #0
+
+;;; Double vector
+
+%v2f64 = type <2 x double>
+; CHECK: test_v2f64.sqrt:
+define %v2f64 @test_v2f64.sqrt(%v2f64 %a) {
+ ; CHECK: fsqrt.2d
+ %1 = call %v2f64 @llvm.sqrt.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.powi:
+define %v2f64 @test_v2f64.powi(%v2f64 %a, i32 %b) {
+ ; CHECK: pow
+ %1 = call %v2f64 @llvm.powi.v2f64(%v2f64 %a, i32 %b)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.sin:
+define %v2f64 @test_v2f64.sin(%v2f64 %a) {
+ ; CHECK: sin
+ %1 = call %v2f64 @llvm.sin.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.cos:
+define %v2f64 @test_v2f64.cos(%v2f64 %a) {
+ ; CHECK: cos
+ %1 = call %v2f64 @llvm.cos.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.pow:
+define %v2f64 @test_v2f64.pow(%v2f64 %a, %v2f64 %b) {
+ ; CHECK: pow
+ %1 = call %v2f64 @llvm.pow.v2f64(%v2f64 %a, %v2f64 %b)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.exp:
+define %v2f64 @test_v2f64.exp(%v2f64 %a) {
+ ; CHECK: exp
+ %1 = call %v2f64 @llvm.exp.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.exp2:
+define %v2f64 @test_v2f64.exp2(%v2f64 %a) {
+ ; CHECK: exp
+ %1 = call %v2f64 @llvm.exp2.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.log:
+define %v2f64 @test_v2f64.log(%v2f64 %a) {
+ ; CHECK: log
+ %1 = call %v2f64 @llvm.log.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.log10:
+define %v2f64 @test_v2f64.log10(%v2f64 %a) {
+ ; CHECK: log
+ %1 = call %v2f64 @llvm.log10.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.log2:
+define %v2f64 @test_v2f64.log2(%v2f64 %a) {
+ ; CHECK: log
+ %1 = call %v2f64 @llvm.log2.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.fma:
+define %v2f64 @test_v2f64.fma(%v2f64 %a, %v2f64 %b, %v2f64 %c) {
+ ; CHECK: fma
+ %1 = call %v2f64 @llvm.fma.v2f64(%v2f64 %a, %v2f64 %b, %v2f64 %c)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.fabs:
+define %v2f64 @test_v2f64.fabs(%v2f64 %a) {
+ ; CHECK: fabs
+ %1 = call %v2f64 @llvm.fabs.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.floor:
+define %v2f64 @test_v2f64.floor(%v2f64 %a) {
+ ; CHECK: frintm.2d
+ %1 = call %v2f64 @llvm.floor.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.ceil:
+define %v2f64 @test_v2f64.ceil(%v2f64 %a) {
+ ; CHECK: frintp.2d
+ %1 = call %v2f64 @llvm.ceil.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.trunc:
+define %v2f64 @test_v2f64.trunc(%v2f64 %a) {
+ ; CHECK: frintz.2d
+ %1 = call %v2f64 @llvm.trunc.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.rint:
+define %v2f64 @test_v2f64.rint(%v2f64 %a) {
+ ; CHECK: frintx.2d
+ %1 = call %v2f64 @llvm.rint.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+; CHECK: test_v2f64.nearbyint:
+define %v2f64 @test_v2f64.nearbyint(%v2f64 %a) {
+ ; CHECK: frinti.2d
+ %1 = call %v2f64 @llvm.nearbyint.v2f64(%v2f64 %a)
+ ret %v2f64 %1
+}
+
+declare %v2f64 @llvm.sqrt.v2f64(%v2f64) #0
+declare %v2f64 @llvm.powi.v2f64(%v2f64, i32) #0
+declare %v2f64 @llvm.sin.v2f64(%v2f64) #0
+declare %v2f64 @llvm.cos.v2f64(%v2f64) #0
+declare %v2f64 @llvm.pow.v2f64(%v2f64, %v2f64) #0
+declare %v2f64 @llvm.exp.v2f64(%v2f64) #0
+declare %v2f64 @llvm.exp2.v2f64(%v2f64) #0
+declare %v2f64 @llvm.log.v2f64(%v2f64) #0
+declare %v2f64 @llvm.log10.v2f64(%v2f64) #0
+declare %v2f64 @llvm.log2.v2f64(%v2f64) #0
+declare %v2f64 @llvm.fma.v2f64(%v2f64, %v2f64, %v2f64) #0
+declare %v2f64 @llvm.fabs.v2f64(%v2f64) #0
+declare %v2f64 @llvm.floor.v2f64(%v2f64) #0
+declare %v2f64 @llvm.ceil.v2f64(%v2f64) #0
+declare %v2f64 @llvm.trunc.v2f64(%v2f64) #0
+declare %v2f64 @llvm.rint.v2f64(%v2f64) #0
+declare %v2f64 @llvm.nearbyint.v2f64(%v2f64) #0
+
+attributes #0 = { nounwind readonly }
Added: llvm/trunk/test/CodeGen/ARM64/vhadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vhadd.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vhadd.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vhadd.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,249 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: shadd8b:
+;CHECK: shadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: shadd16b:
+;CHECK: shadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.shadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: shadd4h:
+;CHECK: shadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.shadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: shadd8h:
+;CHECK: shadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.shadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: shadd2s:
+;CHECK: shadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.shadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: shadd4s:
+;CHECK: shadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.shadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uhadd8b:
+;CHECK: uhadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uhadd16b:
+;CHECK: uhadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uhadd4h:
+;CHECK: uhadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uhadd8h:
+;CHECK: uhadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uhadd2s:
+;CHECK: uhadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @uhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uhadd4s:
+;CHECK: uhadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.shadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.shadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.shadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.shadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.shadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: srhadd8b:
+;CHECK: srhadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.srhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: srhadd16b:
+;CHECK: srhadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.srhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: srhadd4h:
+;CHECK: srhadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.srhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: srhadd8h:
+;CHECK: srhadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.srhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: srhadd2s:
+;CHECK: srhadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.srhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: srhadd4s:
+;CHECK: srhadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.srhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: urhadd8b:
+;CHECK: urhadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.urhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: urhadd16b:
+;CHECK: urhadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.urhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: urhadd4h:
+;CHECK: urhadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.urhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: urhadd8h:
+;CHECK: urhadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.urhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: urhadd2s:
+;CHECK: urhadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.urhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @urhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: urhadd4s:
+;CHECK: urhadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.urhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.urhadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.urhadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.urhadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.srhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.srhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.urhadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.urhadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vhsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vhsub.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vhsub.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vhsub.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,125 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: shsub8b:
+;CHECK: shsub.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: shsub16b:
+;CHECK: shsub.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: shsub4h:
+;CHECK: shsub.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: shsub8h:
+;CHECK: shsub.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: shsub2s:
+;CHECK: shsub.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: shsub4s:
+;CHECK: shsub.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uhsub8b:
+;CHECK: uhsub.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uhsub16b:
+;CHECK: uhsub.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uhsub4h:
+;CHECK: uhsub.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uhsub8h:
+;CHECK: uhsub.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uhsub2s:
+;CHECK: uhsub.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uhsub4s:
+;CHECK: uhsub.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.shsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.shsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.shsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uhsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uhsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uhsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.shsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.shsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.shsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uhsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uhsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uhsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/virtual_base.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/virtual_base.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/virtual_base.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/virtual_base.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,51 @@
+; RUN: llc < %s -O3 -march arm64 | FileCheck %s
+; <rdar://13463602>
+
+%struct.Counter_Struct = type { i64, i64 }
+%struct.Bicubic_Patch_Struct = type { %struct.Method_Struct*, i32, %struct.Object_Struct*, %struct.Texture_Struct*, %struct.Interior_Struct*, %struct.Object_Struct*, %struct.Object_Struct*, %struct.Bounding_Box_Struct, i64, i32, i32, i32, [4 x [4 x [3 x double]]], [3 x double], double, double, %struct.Bezier_Node_Struct* }
+%struct.Method_Struct = type { i32 (%struct.Object_Struct*, %struct.Ray_Struct*, %struct.istack_struct*)*, i32 (double*, %struct.Object_Struct*)*, void (double*, %struct.Object_Struct*, %struct.istk_entry*)*, i8* (%struct.Object_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, double*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*, %struct.Transform_Struct*)*, void (%struct.Object_Struct*)*, void (%struct.Object_Struct*)* }
+%struct.Object_Struct = type { %struct.Method_Struct*, i32, %struct.Object_Struct*, %struct.Texture_Struct*, %struct.Interior_Struct*, %struct.Object_Struct*, %struct.Object_Struct*, %struct.Bounding_Box_Struct, i64 }
+%struct.Texture_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.9, %struct.Texture_Struct*, %struct.Pigment_Struct*, %struct.Tnormal_Struct*, %struct.Finish_Struct*, %struct.Texture_Struct*, i32 }
+%struct.Warps_Struct = type { i16, %struct.Warps_Struct* }
+%struct.Pattern_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.6 }
+%struct.Blend_Map_Struct = type { i16, i16, i16, i64, %struct.Blend_Map_Entry* }
+%struct.Blend_Map_Entry = type { float, i8, %union.anon }
+%union.anon = type { [2 x double], [8 x i8] }
+%union.anon.6 = type { %struct.anon.7 }
+%struct.anon.7 = type { float, [3 x double] }
+%union.anon.9 = type { %struct.anon.10 }
+%struct.anon.10 = type { float, [3 x double] }
+%struct.Pigment_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.0, [5 x float] }
+%union.anon.0 = type { %struct.anon }
+%struct.anon = type { float, [3 x double] }
+%struct.Tnormal_Struct = type { i16, i16, i16, i32, float, float, float, %struct.Warps_Struct*, %struct.Pattern_Struct*, %struct.Blend_Map_Struct*, %union.anon.3, float }
+%union.anon.3 = type { %struct.anon.4 }
+%struct.anon.4 = type { float, [3 x double] }
+%struct.Finish_Struct = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, [3 x float], [3 x float] }
+%struct.Interior_Struct = type { i64, i32, float, float, float, float, float, %struct.Media_Struct* }
+%struct.Media_Struct = type { i32, i32, i32, i32, i32, double, double, i32, i32, i32, i32, [5 x float], [5 x float], [5 x float], [5 x float], double, double, double, double*, %struct.Pigment_Struct*, %struct.Media_Struct* }
+%struct.Bounding_Box_Struct = type { [3 x float], [3 x float] }
+%struct.Ray_Struct = type { [3 x double], [3 x double], i32, [100 x %struct.Interior_Struct*] }
+%struct.istack_struct = type { %struct.istack_struct*, %struct.istk_entry*, i32 }
+%struct.istk_entry = type { double, [3 x double], [3 x double], %struct.Object_Struct*, i32, i32, double, double, i8* }
+%struct.Transform_Struct = type { [4 x [4 x double]], [4 x [4 x double]] }
+%struct.Bezier_Node_Struct = type { i32, [3 x double], double, i32, i8* }
+
+define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) {
+; CHECK: Precompute_Patch_Values
+; CHECK: ldr [[VAL:x[0-9]+]], [x0, #288]
+; CHECK-NEXT: str [[VAL]], [sp, #232]
+; CHECK-NEXT: ldr [[VAL2:q[0-9]+]], [x0, #272]
+; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216]
+entry:
+ %Control_Points = alloca [16 x [3 x double]], align 8
+ %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0
+ %tmp14 = bitcast double* %arraydecay5.3.1 to i8*
+ %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0
+ %tmp15 = bitcast double* %arraydecay11.3.1 to i8*
+ call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i32 1, i1 false)
+ ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1)
Added: llvm/trunk/test/CodeGen/ARM64/vmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmax.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmax.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vmax.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,679 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: smax_8b:
+;CHECK: smax.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: smax_16b:
+;CHECK: smax.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: smax_4h:
+;CHECK: smax.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: smax_8h:
+;CHECK: smax.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: smax_2s:
+;CHECK: smax.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @smax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: smax_4s:
+;CHECK: smax.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.smax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.smax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.smax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: umax_8b:
+;CHECK: umax.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.umax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: umax_16b:
+;CHECK: umax.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.umax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: umax_4h:
+;CHECK: umax.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.umax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: umax_8h:
+;CHECK: umax.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.umax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: umax_2s:
+;CHECK: umax.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.umax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @umax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: umax_4s:
+;CHECK: umax.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.umax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.umax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.umax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.umax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.umax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: smin_8b:
+;CHECK: smin.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.smin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: smin_16b:
+;CHECK: smin.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.smin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: smin_4h:
+;CHECK: smin.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.smin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: smin_8h:
+;CHECK: smin.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.smin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: smin_2s:
+;CHECK: smin.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.smin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @smin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: smin_4s:
+;CHECK: smin.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.smin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.smin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.smin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.smin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.smin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.smin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: umin_8b:
+;CHECK: umin.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: umin_16b:
+;CHECK: umin.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: umin_4h:
+;CHECK: umin.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: umin_8h:
+;CHECK: umin.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: umin_2s:
+;CHECK: umin.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @umin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: umin_4s:
+;CHECK: umin.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.umin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.umin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.umin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.umin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.umin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: smaxp_8b:
+;CHECK: smaxp.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: smaxp_16b:
+;CHECK: smaxp.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.smaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: smaxp_4h:
+;CHECK: smaxp.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.smaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: smaxp_8h:
+;CHECK: smaxp.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.smaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: smaxp_2s:
+;CHECK: smaxp.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.smaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @smaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: smaxp_4s:
+;CHECK: smaxp.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.smaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.smaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.smaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.smaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.smaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.smaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.smaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: umaxp_8b:
+;CHECK: umaxp.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.umaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: umaxp_16b:
+;CHECK: umaxp.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.umaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: umaxp_4h:
+;CHECK: umaxp.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.umaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: umaxp_8h:
+;CHECK: umaxp.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.umaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: umaxp_2s:
+;CHECK: umaxp.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.umaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @umaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: umaxp_4s:
+;CHECK: umaxp.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.umaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.umaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.umaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.umaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.umaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sminp_8b:
+;CHECK: sminp.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sminp_16b:
+;CHECK: sminp.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sminp_4h:
+;CHECK: sminp.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sminp_8h:
+;CHECK: sminp.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sminp_2s:
+;CHECK: sminp.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @sminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sminp_4s:
+;CHECK: sminp.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.sminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uminp_8b:
+;CHECK: uminp.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uminp_16b:
+;CHECK: uminp.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uminp_4h:
+;CHECK: uminp.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uminp_8h:
+;CHECK: uminp.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uminp_2s:
+;CHECK: uminp.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @uminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uminp_4s:
+;CHECK: uminp.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.uminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <16 x i8> @llvm.arm64.neon.uminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+
+define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmax_2s:
+;CHECK: fmax.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fmax.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmax_4s:
+;CHECK: fmax.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fmax.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fmax_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmax_2d:
+;CHECK: fmax.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fmax.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fmax.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmax.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmax.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmaxp_2s:
+;CHECK: fmaxp.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fmaxp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmaxp_4s:
+;CHECK: fmaxp.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fmaxp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fmaxp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmaxp_2d:
+;CHECK: fmaxp.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fmaxp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fmaxp.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmaxp.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmaxp.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmin_2s:
+;CHECK: fmin.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fmin.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmin_4s:
+;CHECK: fmin.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fmin.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fmin_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmin_2d:
+;CHECK: fmin.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fmin.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fmin.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmin.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmin.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fminp_2s:
+;CHECK: fminp.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fminp_4s:
+;CHECK: fminp.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fminp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fminp_2d:
+;CHECK: fminp.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fminp.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fminp.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fminp.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fminnmp_2s:
+;CHECK: fminnmp.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fminnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fminnmp_4s:
+;CHECK: fminnmp.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fminnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fminnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fminnmp_2d:
+;CHECK: fminnmp.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fminnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fminnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fminnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fminnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmaxnmp_2s:
+;CHECK: fmaxnmp.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fmaxnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmaxnmp_4s:
+;CHECK: fmaxnmp.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fmaxnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fmaxnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmaxnmp_2d:
+;CHECK: fmaxnmp.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fmaxnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fmaxnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmaxnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmaxnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vminmaxnm.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,68 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
+; CHECK: fmaxnm.2s v0, v0, v1
+; CHECK: ret
+ %vmaxnm2.i = tail call <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
+ ret <2 x float> %vmaxnm2.i
+}
+
+define <4 x float> @f2(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
+; CHECK: fmaxnm.4s v0, v0, v1
+; CHECK: ret
+ %vmaxnm2.i = tail call <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
+ ret <4 x float> %vmaxnm2.i
+}
+
+define <2 x double> @f3(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
+; CHECK: fmaxnm.2d v0, v0, v1
+; CHECK: ret
+ %vmaxnm2.i = tail call <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
+ ret <2 x double> %vmaxnm2.i
+}
+
+define <2 x float> @f4(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
+; CHECK: fminnm.2s v0, v0, v1
+; CHECK: ret
+ %vminnm2.i = tail call <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
+ ret <2 x float> %vminnm2.i
+}
+
+define <4 x float> @f5(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
+; CHECK: fminnm.4s v0, v0, v1
+; CHECK: ret
+ %vminnm2.i = tail call <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
+ ret <4 x float> %vminnm2.i
+}
+
+define <2 x double> @f6(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
+; CHECK: fminnm.2d v0, v0, v1
+; CHECK: ret
+ %vminnm2.i = tail call <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
+ ret <2 x double> %vminnm2.i
+}
+
+declare <2 x double> @llvm.arm64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x float> @llvm.arm64.neon.fminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x float> @llvm.arm64.neon.fmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
+
+
+define double @test_fmaxnmv(<2 x double> %in) {
+; CHECK-LABEL: test_fmaxnmv:
+; CHECK: fmaxnmp.2d d0, v0
+ %max = call double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
+ ret double %max
+}
+
+define double @test_fminnmv(<2 x double> %in) {
+; CHECK-LABEL: test_fminnmv:
+; CHECK: fminnmp.2d d0, v0
+ %min = call double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double> %in)
+ ret double %min
+}
+
+declare double @llvm.arm64.neon.fmaxnmv.f64.v2f64(<2 x double>)
+declare double @llvm.arm64.neon.fminnmv.f64.v2f64(<2 x double>)
Added: llvm/trunk/test/CodeGen/ARM64/vmovn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmovn.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmovn.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vmovn.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,242 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
+;CHECK-LABEL: xtn8b:
+;CHECK-NOT: ld1
+;CHECK: xtn.8b v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = trunc <8 x i16> %A to <8 x i8>
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @xtn4h(<4 x i32> %A) nounwind {
+;CHECK-LABEL: xtn4h:
+;CHECK-NOT: ld1
+;CHECK: xtn.4h v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = trunc <4 x i32> %A to <4 x i16>
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @xtn2s(<2 x i64> %A) nounwind {
+;CHECK-LABEL: xtn2s:
+;CHECK-NOT: ld1
+;CHECK: xtn.2s v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = trunc <2 x i64> %A to <2 x i32>
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
+;CHECK-LABEL: xtn2_16b:
+;CHECK-NOT: ld1
+;CHECK: xtn2.16b v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = trunc <8 x i16> %A to <8 x i8>
+ %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
+;CHECK-LABEL: xtn2_8h:
+;CHECK-NOT: ld1
+;CHECK: xtn2.8h v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = trunc <4 x i32> %A to <4 x i16>
+ %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
+;CHECK-LABEL: xtn2_4s:
+;CHECK-NOT: ld1
+;CHECK: xtn2.4s v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = trunc <2 x i64> %A to <2 x i32>
+ %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind {
+;CHECK-LABEL: sqxtn8b:
+;CHECK-NOT: ld1
+;CHECK: sqxtn.8b v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind {
+;CHECK-LABEL: sqxtn4h:
+;CHECK-NOT: ld1
+;CHECK: sqxtn.4h v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind {
+;CHECK-LABEL: sqxtn2s:
+;CHECK-NOT: ld1
+;CHECK: sqxtn.2s v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
+;CHECK-LABEL: sqxtn2_16b:
+;CHECK-NOT: ld1
+;CHECK: sqxtn2.16b v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
+ %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
+;CHECK-LABEL: sqxtn2_8h:
+;CHECK-NOT: ld1
+;CHECK: sqxtn2.8h v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
+ %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
+;CHECK-LABEL: sqxtn2_4s:
+;CHECK-NOT: ld1
+;CHECK: sqxtn2.4s v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
+ %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone
+
+define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind {
+;CHECK-LABEL: uqxtn8b:
+;CHECK-NOT: ld1
+;CHECK: uqxtn.8b v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind {
+;CHECK-LABEL: uqxtn4h:
+;CHECK-NOT: ld1
+;CHECK: uqxtn.4h v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind {
+;CHECK-LABEL: uqxtn2s:
+;CHECK-NOT: ld1
+;CHECK: uqxtn.2s v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
+;CHECK-LABEL: uqxtn2_16b:
+;CHECK-NOT: ld1
+;CHECK: uqxtn2.16b v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
+ %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
+;CHECK-LABEL: uqxtn2_8h:
+;CHECK-NOT: ld1
+;CHECK: uqxtn2.8h v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
+ %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
+;CHECK-LABEL: uqxtn2_4s:
+;CHECK-NOT: ld1
+;CHECK: uqxtn2.4s v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
+ %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+declare <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone
+
+define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind {
+;CHECK-LABEL: sqxtun8b:
+;CHECK-NOT: ld1
+;CHECK: sqxtun.8b v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind {
+;CHECK-LABEL: sqxtun4h:
+;CHECK-NOT: ld1
+;CHECK: sqxtun.4h v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind {
+;CHECK-LABEL: sqxtun2s:
+;CHECK-NOT: ld1
+;CHECK: sqxtun.2s v0, v0
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
+;CHECK-LABEL: sqxtun2_16b:
+;CHECK-NOT: ld1
+;CHECK: sqxtun2.16b v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
+ %res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
+;CHECK-LABEL: sqxtun2_8h:
+;CHECK-NOT: ld1
+;CHECK: sqxtun2.8h v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
+ %res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
+;CHECK-LABEL: sqxtun2_4s:
+;CHECK-NOT: ld1
+;CHECK: sqxtun2.4s v0, v1
+;CHECK-NEXT: ret
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
+ %res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone
+
Added: llvm/trunk/test/CodeGen/ARM64/vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vmul.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vmul.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vmul.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,1969 @@
+; RUN: llc -asm-verbose=false < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+
+define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: smull8h:
+;CHECK: smull.8h
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: smull4s:
+;CHECK: smull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @smull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: smull2d:
+;CHECK: smull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: umull8h:
+;CHECK: umull.8h
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: umull4s:
+;CHECK: umull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @umull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: umull2d:
+;CHECK: umull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmull4s:
+;CHECK: sqdmull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmull2d:
+;CHECK: sqdmull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmull2_4s:
+;CHECK: sqdmull2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqdmull2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmull2_2d:
+;CHECK: sqdmull2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+
+declare <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
+
+define <8 x i16> @pmull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: pmull8h:
+;CHECK: pmull.8h
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+declare <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
+
+define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_4h:
+;CHECK: sqdmulh.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_8h:
+;CHECK: sqdmulh.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_2s:
+;CHECK: sqdmulh.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_4s:
+;CHECK: sqdmulh.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define i32 @sqdmulh_1s(i32* %A, i32* %B) nounwind {
+;CHECK-LABEL: sqdmulh_1s:
+;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
+ %tmp1 = load i32* %A
+ %tmp2 = load i32* %B
+ %tmp3 = call i32 @llvm.arm64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2)
+ ret i32 %tmp3
+}
+
+declare <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare i32 @llvm.arm64.neon.sqdmulh.i32(i32, i32) nounwind readnone
+
+define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_4h:
+;CHECK: sqrdmulh.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_8h:
+;CHECK: sqrdmulh.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_2s:
+;CHECK: sqrdmulh.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_4s:
+;CHECK: sqrdmulh.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define i32 @sqrdmulh_1s(i32* %A, i32* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_1s:
+;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}}
+ %tmp1 = load i32* %A
+ %tmp2 = load i32* %B
+ %tmp3 = call i32 @llvm.arm64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2)
+ ret i32 %tmp3
+}
+
+declare <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare i32 @llvm.arm64.neon.sqrdmulh.i32(i32, i32) nounwind readnone
+
+define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmulx_2s:
+;CHECK: fmulx.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmulx_4s:
+;CHECK: fmulx.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @fmulx_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmulx_2d:
+;CHECK: fmulx.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: smlal4s:
+;CHECK: smlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: smlal2d:
+;CHECK: smlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: smlsl4s:
+;CHECK: smlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @smlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: smlsl2d:
+;CHECK: smlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+declare <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
+declare <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
+
+define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlal4s:
+;CHECK: sqdmlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlal2d:
+;CHECK: sqdmlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlal2_4s:
+;CHECK: sqdmlal2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlal2_2d:
+;CHECK: sqdmlal2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl4s:
+;CHECK: sqdmlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl2d:
+;CHECK: sqdmlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl2_4s:
+;CHECK: sqdmlsl2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4)
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl2_2d:
+;CHECK: sqdmlsl2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4)
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: umlal4s:
+;CHECK: umlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: umlal2d:
+;CHECK: umlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: umlsl4s:
+;CHECK: umlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: umlsl2d:
+;CHECK: umlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
+;CHECK-LABEL: fmla_2s:
+;CHECK: fmla.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = load <2 x float>* %C
+ %tmp4 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3)
+ ret <2 x float> %tmp4
+}
+
+define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
+;CHECK-LABEL: fmla_4s:
+;CHECK: fmla.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = load <4 x float>* %C
+ %tmp4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3)
+ ret <4 x float> %tmp4
+}
+
+define <2 x double> @fmla_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
+;CHECK-LABEL: fmla_2d:
+;CHECK: fmla.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = load <2 x double>* %C
+ %tmp4 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3)
+ ret <2 x double> %tmp4
+}
+
+declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
+;CHECK-LABEL: fmls_2s:
+;CHECK: fmls.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = load <2 x float>* %C
+ %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
+ %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp4, <2 x float> %tmp3)
+ ret <2 x float> %tmp5
+}
+
+define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
+;CHECK-LABEL: fmls_4s:
+;CHECK: fmls.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = load <4 x float>* %C
+ %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
+ %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp4, <4 x float> %tmp3)
+ ret <4 x float> %tmp5
+}
+
+define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
+;CHECK-LABEL: fmls_2d:
+;CHECK: fmls.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = load <2 x double>* %C
+ %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
+ %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp4, <2 x double> %tmp3)
+ ret <2 x double> %tmp5
+}
+
+define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
+;CHECK-LABEL: fmls_commuted_neg_2s:
+;CHECK: fmls.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = load <2 x float>* %C
+ %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2
+ %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3)
+ ret <2 x float> %tmp5
+}
+
+define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
+;CHECK-LABEL: fmls_commuted_neg_4s:
+;CHECK: fmls.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = load <4 x float>* %C
+ %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2
+ %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3)
+ ret <4 x float> %tmp5
+}
+
+define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind {
+;CHECK-LABEL: fmls_commuted_neg_2d:
+;CHECK: fmls.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = load <2 x double>* %C
+ %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2
+ %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3)
+ ret <2 x double> %tmp5
+}
+
+define <2 x float> @fmls_indexed_2s(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {
+;CHECK-LABEL: fmls_indexed_2s:
+;CHECK: fmls.2s
+entry:
+ %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %c
+ %lane = shufflevector <2 x float> %b, <2 x float> undef, <2 x i32> zeroinitializer
+ %fmls1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %0, <2 x float> %lane, <2 x float> %a)
+ ret <2 x float> %fmls1
+}
+
+define <4 x float> @fmls_indexed_4s(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone ssp {
+;CHECK-LABEL: fmls_indexed_4s:
+;CHECK: fmls.4s
+entry:
+ %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
+ %lane = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
+ %fmls1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %lane, <4 x float> %a)
+ ret <4 x float> %fmls1
+}
+
+define <2 x double> @fmls_indexed_2d(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone ssp {
+;CHECK-LABEL: fmls_indexed_2d:
+;CHECK: fmls.2d
+entry:
+ %0 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %c
+ %lane = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer
+ %fmls1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %lane, <2 x double> %a)
+ ret <2 x double> %fmls1
+}
+
+define <2 x float> @fmla_indexed_scalar_2s(<2 x float> %a, <2 x float> %b, float %c) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: fmla_indexed_scalar_2s:
+; CHECK-NEXT: fmla.2s
+; CHECK-NEXT: ret
+ %v1 = insertelement <2 x float> undef, float %c, i32 0
+ %v2 = insertelement <2 x float> %v1, float %c, i32 1
+ %fmla1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %v1, <2 x float> %b, <2 x float> %a) nounwind
+ ret <2 x float> %fmla1
+}
+
+define <4 x float> @fmla_indexed_scalar_4s(<4 x float> %a, <4 x float> %b, float %c) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: fmla_indexed_scalar_4s:
+; CHECK-NEXT: fmla.4s
+; CHECK-NEXT: ret
+ %v1 = insertelement <4 x float> undef, float %c, i32 0
+ %v2 = insertelement <4 x float> %v1, float %c, i32 1
+ %v3 = insertelement <4 x float> %v2, float %c, i32 2
+ %v4 = insertelement <4 x float> %v3, float %c, i32 3
+ %fmla1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %v4, <4 x float> %b, <4 x float> %a) nounwind
+ ret <4 x float> %fmla1
+}
+
+define <2 x double> @fmla_indexed_scalar_2d(<2 x double> %a, <2 x double> %b, double %c) nounwind readnone ssp {
+; CHECK-LABEL: fmla_indexed_scalar_2d:
+; CHECK-NEXT: fmla.2d
+; CHECK-NEXT: ret
+entry:
+ %v1 = insertelement <2 x double> undef, double %c, i32 0
+ %v2 = insertelement <2 x double> %v1, double %c, i32 1
+ %fmla1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %v2, <2 x double> %b, <2 x double> %a) nounwind
+ ret <2 x double> %fmla1
+}
+
+define <4 x i16> @mul_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: mul_4h:
+;CHECK-NOT: dup
+;CHECK: mul.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = mul <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @mul_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: mul_8h:
+;CHECK-NOT: dup
+;CHECK: mul.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = mul <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @mul_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: mul_2s:
+;CHECK-NOT: dup
+;CHECK: mul.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = mul <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @mul_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: mul_4s:
+;CHECK-NOT: dup
+;CHECK: mul.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = mul <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @mul_2d(<2 x i64> %A, <2 x i64> %B) nounwind {
+; CHECK-LABEL: mul_2d:
+; CHECK: mul
+; CHECK: mul
+ %tmp1 = mul <2 x i64> %A, %B
+ ret <2 x i64> %tmp1
+}
+
+define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmul_lane_2s:
+;CHECK-NOT: dup
+;CHECK: fmul.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = fmul <2 x float> %tmp1, %tmp3
+ ret <2 x float> %tmp4
+}
+
+define <4 x float> @fmul_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmul_lane_4s:
+;CHECK-NOT: dup
+;CHECK: fmul.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = fmul <4 x float> %tmp1, %tmp3
+ ret <4 x float> %tmp4
+}
+
+define <2 x double> @fmul_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmul_lane_2d:
+;CHECK-NOT: dup
+;CHECK: fmul.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = fmul <2 x double> %tmp1, %tmp3
+ ret <2 x double> %tmp4
+}
+
+define float @fmul_lane_s(float %A, <4 x float> %vec) nounwind {
+;CHECK-LABEL: fmul_lane_s:
+;CHECK-NOT: dup
+;CHECK: fmul.s s0, s0, v1[3]
+ %B = extractelement <4 x float> %vec, i32 3
+ %res = fmul float %A, %B
+ ret float %res
+}
+
+define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind {
+;CHECK-LABEL: fmul_lane_d:
+;CHECK-NOT: dup
+;CHECK: fmul.d d0, d0, v1[1]
+ %B = extractelement <2 x double> %vec, i32 1
+ %res = fmul double %A, %B
+ ret double %res
+}
+
+
+
+define <2 x float> @fmulx_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: fmulx_lane_2s:
+;CHECK-NOT: dup
+;CHECK: fmulx.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x float> @llvm.arm64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp3)
+ ret <2 x float> %tmp4
+}
+
+define <4 x float> @fmulx_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: fmulx_lane_4s:
+;CHECK-NOT: dup
+;CHECK: fmulx.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x float> @llvm.arm64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp3)
+ ret <4 x float> %tmp4
+}
+
+define <2 x double> @fmulx_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: fmulx_lane_2d:
+;CHECK-NOT: dup
+;CHECK: fmulx.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x double> @llvm.arm64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp3)
+ ret <2 x double> %tmp4
+}
+
+define <4 x i16> @sqdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_lane_4h:
+;CHECK-NOT: dup
+;CHECK: sqdmulh.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i16> @llvm.arm64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
+ ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @sqdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_lane_8h:
+;CHECK-NOT: dup
+;CHECK: sqdmulh.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <8 x i16> @llvm.arm64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @sqdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_lane_2s:
+;CHECK-NOT: dup
+;CHECK: sqdmulh.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i32> @llvm.arm64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @sqdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmulh_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmulh.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define i32 @sqdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind {
+;CHECK-LABEL: sqdmulh_lane_1s:
+;CHECK-NOT: dup
+;CHECK: sqdmulh.s s0, {{s[0-9]+}}, {{v[0-9]+}}[1]
+ %tmp1 = extractelement <4 x i32> %B, i32 1
+ %tmp2 = call i32 @llvm.arm64.neon.sqdmulh.i32(i32 %A, i32 %tmp1)
+ ret i32 %tmp2
+}
+
+define <4 x i16> @sqrdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_lane_4h:
+;CHECK-NOT: dup
+;CHECK: sqrdmulh.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i16> @llvm.arm64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3)
+ ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @sqrdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_lane_8h:
+;CHECK-NOT: dup
+;CHECK: sqrdmulh.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <8 x i16> @llvm.arm64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3)
+ ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @sqrdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_lane_2s:
+;CHECK-NOT: dup
+;CHECK: sqrdmulh.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i32> @llvm.arm64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3)
+ ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @sqrdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrdmulh_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqrdmulh.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define i32 @sqrdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind {
+;CHECK-LABEL: sqrdmulh_lane_1s:
+;CHECK-NOT: dup
+;CHECK: sqrdmulh.s s0, {{s[0-9]+}}, {{v[0-9]+}}[1]
+ %tmp1 = extractelement <4 x i32> %B, i32 1
+ %tmp2 = call i32 @llvm.arm64.neon.sqrdmulh.i32(i32 %A, i32 %tmp1)
+ ret i32 %tmp2
+}
+
+define <4 x i32> @sqdmull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmull_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @sqdmull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmull_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqdmull2_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmull2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @sqdmull2_lane_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqdmull2_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmull2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i64> %tmp4
+}
+
+define <4 x i32> @umull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: umull_lane_4s:
+;CHECK-NOT: dup
+;CHECK: umull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @umull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: umull_lane_2d:
+;CHECK-NOT: dup
+;CHECK: umull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <4 x i32> @smull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: smull_lane_4s:
+;CHECK-NOT: dup
+;CHECK: smull.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3)
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @smull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: smull_lane_2d:
+;CHECK-NOT: dup
+;CHECK: smull.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp4 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3)
+ ret <2 x i64> %tmp4
+}
+
+define <4 x i32> @smlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: smlal_lane_4s:
+;CHECK-NOT: dup
+;CHECK: smlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = add <4 x i32> %tmp3, %tmp5
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @smlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: smlal_lane_2d:
+;CHECK-NOT: dup
+;CHECK: smlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = add <2 x i64> %tmp3, %tmp5
+ ret <2 x i64> %tmp6
+}
+
+define <4 x i32> @sqdmlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlal_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @sqdmlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlal_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
+ ret <2 x i64> %tmp6
+}
+
+define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlal2_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmlal2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp6 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @sqdmlal2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlal2_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmlal2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp6 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
+ ret <2 x i64> %tmp6
+}
+
+define i32 @sqdmlal_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
+;CHECK-LABEL: sqdmlal_lane_1s:
+;CHECK: sqdmlal.4s
+ %lhs = insertelement <4 x i16> undef, i16 %B, i32 0
+ %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+ %prod.vec = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)
+ %prod = extractelement <4 x i32> %prod.vec, i32 0
+ %res = call i32 @llvm.arm64.neon.sqadd.i32(i32 %A, i32 %prod)
+ ret i32 %res
+}
+declare i32 @llvm.arm64.neon.sqadd.i32(i32, i32)
+
+define i32 @sqdmlsl_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind {
+;CHECK-LABEL: sqdmlsl_lane_1s:
+;CHECK: sqdmlsl.4s
+ %lhs = insertelement <4 x i16> undef, i16 %B, i32 0
+ %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+ %prod.vec = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)
+ %prod = extractelement <4 x i32> %prod.vec, i32 0
+ %res = call i32 @llvm.arm64.neon.sqsub.i32(i32 %A, i32 %prod)
+ ret i32 %res
+}
+declare i32 @llvm.arm64.neon.sqsub.i32(i32, i32)
+
+define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
+;CHECK-LABEL: sqdmlal_lane_1d:
+;CHECK: sqdmlal.s
+ %rhs = extractelement <2 x i32> %C, i32 1
+ %prod = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
+ %res = call i64 @llvm.arm64.neon.sqadd.i64(i64 %A, i64 %prod)
+ ret i64 %res
+}
+declare i64 @llvm.arm64.neon.sqdmulls.scalar(i32, i32)
+declare i64 @llvm.arm64.neon.sqadd.i64(i64, i64)
+
+define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind {
+;CHECK-LABEL: sqdmlsl_lane_1d:
+;CHECK: sqdmlsl.s
+ %rhs = extractelement <2 x i32> %C, i32 1
+ %prod = call i64 @llvm.arm64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)
+ %res = call i64 @llvm.arm64.neon.sqsub.i64(i64 %A, i64 %prod)
+ ret i64 %res
+}
+declare i64 @llvm.arm64.neon.sqsub.i64(i64, i64)
+
+
+define <4 x i32> @umlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: umlal_lane_4s:
+;CHECK-NOT: dup
+;CHECK: umlal.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = add <4 x i32> %tmp3, %tmp5
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @umlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: umlal_lane_2d:
+;CHECK-NOT: dup
+;CHECK: umlal.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = add <2 x i64> %tmp3, %tmp5
+ ret <2 x i64> %tmp6
+}
+
+
+define <4 x i32> @smlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: smlsl_lane_4s:
+;CHECK-NOT: dup
+;CHECK: smlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = sub <4 x i32> %tmp3, %tmp5
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @smlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: smlsl_lane_2d:
+;CHECK-NOT: dup
+;CHECK: smlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = sub <2 x i64> %tmp3, %tmp5
+ ret <2 x i64> %tmp6
+}
+
+define <4 x i32> @sqdmlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @sqdmlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
+ ret <2 x i64> %tmp6
+}
+
+define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl2_lane_4s:
+;CHECK-NOT: dup
+;CHECK: sqdmlsl2.4s
+ %load1 = load <8 x i16>* %A
+ %load2 = load <8 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ %tmp6 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5)
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: sqdmlsl2_lane_2d:
+;CHECK-NOT: dup
+;CHECK: sqdmlsl2.2d
+ %load1 = load <4 x i32>* %A
+ %load2 = load <4 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ %tmp6 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5)
+ ret <2 x i64> %tmp6
+}
+
+define <4 x i32> @umlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind {
+;CHECK-LABEL: umlsl_lane_4s:
+;CHECK-NOT: dup
+;CHECK: umlsl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = load <4 x i32>* %C
+ %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4)
+ %tmp6 = sub <4 x i32> %tmp3, %tmp5
+ ret <4 x i32> %tmp6
+}
+
+define <2 x i64> @umlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind {
+;CHECK-LABEL: umlsl_lane_2d:
+;CHECK-NOT: dup
+;CHECK: umlsl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = load <2 x i64>* %C
+ %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1>
+ %tmp5 = call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4)
+ %tmp6 = sub <2 x i64> %tmp3, %tmp5
+ ret <2 x i64> %tmp6
+}
+
+; Scalar FMULX
+define float @fmulxs(float %a, float %b) nounwind {
+; CHECK-LABEL: fmulxs:
+; CHECKNEXT: fmulx s0, s0, s1
+ %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
+; CHECKNEXT: ret
+ ret float %fmulx.i
+}
+
+define double @fmulxd(double %a, double %b) nounwind {
+; CHECK-LABEL: fmulxd:
+; CHECKNEXT: fmulx d0, d0, d1
+ %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
+; CHECKNEXT: ret
+ ret double %fmulx.i
+}
+
+define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind {
+; CHECK-LABEL: fmulxs_lane:
+; CHECKNEXT: fmulx.s s0, s0, v1[3]
+ %b = extractelement <4 x float> %vec, i32 3
+ %fmulx.i = tail call float @llvm.arm64.neon.fmulx.f32(float %a, float %b) nounwind
+; CHECKNEXT: ret
+ ret float %fmulx.i
+}
+
+define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind {
+; CHECK-LABEL: fmulxd_lane:
+; CHECKNEXT: fmulx d0, d0, v1[1]
+ %b = extractelement <2 x double> %vec, i32 1
+ %fmulx.i = tail call double @llvm.arm64.neon.fmulx.f64(double %a, double %b) nounwind
+; CHECKNEXT: ret
+ ret double %fmulx.i
+}
+
+declare double @llvm.arm64.neon.fmulx.f64(double, double) nounwind readnone
+declare float @llvm.arm64.neon.fmulx.f32(float, float) nounwind readnone
+
+
+define <8 x i16> @smull2_8h_simple(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: smull2_8h_simple:
+; CHECK-NEXT: smull2.8h v0, v0, v1
+; CHECK-NEXT: ret
+ %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %2 = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %3 = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %1, <8 x i8> %2) #2
+ ret <8 x i16> %3
+}
+
+define <8 x i16> @foo0(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: foo0:
+; CHECK: smull2.8h v0, v0, v1
+ %tmp = bitcast <16 x i8> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>
+ %tmp2 = bitcast <16 x i8> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>
+ %vmull.i.i = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
+ ret <8 x i16> %vmull.i.i
+}
+
+define <4 x i32> @foo1(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: foo1:
+; CHECK: smull2.4s v0, v0, v1
+ %tmp = bitcast <8 x i16> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ ret <4 x i32> %vmull2.i.i
+}
+
+define <2 x i64> @foo2(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: foo2:
+; CHECK: smull2.2d v0, v0, v1
+ %tmp = bitcast <4 x i32> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ ret <2 x i64> %vmull2.i.i
+}
+
+define <8 x i16> @foo3(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: foo3:
+; CHECK: umull2.8h v0, v0, v1
+ %tmp = bitcast <16 x i8> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>
+ %tmp2 = bitcast <16 x i8> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>
+ %vmull.i.i = tail call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
+ ret <8 x i16> %vmull.i.i
+}
+
+define <4 x i32> @foo4(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: foo4:
+; CHECK: umull2.4s v0, v0, v1
+ %tmp = bitcast <8 x i16> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ ret <4 x i32> %vmull2.i.i
+}
+
+define <2 x i64> @foo5(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: foo5:
+; CHECK: umull2.2d v0, v0, v1
+ %tmp = bitcast <4 x i32> %a to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ ret <2 x i64> %vmull2.i.i
+}
+
+define <4 x i32> @foo6(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo6:
+; CHECK-NEXT: smull2.4s v0, v1, v2[1]
+; CHECK-NEXT: ret
+entry:
+ %0 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>
+ %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind
+ ret <4 x i32> %vmull2.i
+}
+
+define <2 x i64> @foo7(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo7:
+; CHECK-NEXT: smull2.2d v0, v1, v2[1]
+; CHECK-NEXT: ret
+entry:
+ %0 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>
+ %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+ %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind
+ ret <2 x i64> %vmull2.i
+}
+
+define <4 x i32> @foo8(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo8:
+; CHECK-NEXT: umull2.4s v0, v1, v2[1]
+; CHECK-NEXT: ret
+entry:
+ %0 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>
+ %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind
+ ret <4 x i32> %vmull2.i
+}
+
+define <2 x i64> @foo9(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
+; CHECK-LABEL: foo9:
+; CHECK-NEXT: umull2.2d v0, v1, v2[1]
+; CHECK-NEXT: ret
+entry:
+ %0 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>
+ %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+ %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind
+ ret <2 x i64> %vmull2.i
+}
+
+define <8 x i16> @bar0(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind {
+; CHECK-LABEL: bar0:
+; CHECK: smlal2.8h v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <16 x i8> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
+ %tmp2 = bitcast <16 x i8> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>
+ %vmull.i.i.i = tail call <8 x i16> @llvm.arm64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
+ %add.i = add <8 x i16> %vmull.i.i.i, %a
+ ret <8 x i16> %add.i
+}
+
+define <4 x i32> @bar1(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind {
+; CHECK-LABEL: bar1:
+; CHECK: smlal2.4s v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>
+ %vmull2.i.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ %add.i = add <4 x i32> %vmull2.i.i.i, %a
+ ret <4 x i32> %add.i
+}
+
+define <2 x i64> @bar2(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind {
+; CHECK-LABEL: bar2:
+; CHECK: smlal2.2d v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>
+ %vmull2.i.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ %add.i = add <2 x i64> %vmull2.i.i.i, %a
+ ret <2 x i64> %add.i
+}
+
+define <8 x i16> @bar3(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind {
+; CHECK-LABEL: bar3:
+; CHECK: umlal2.8h v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <16 x i8> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>
+ %tmp2 = bitcast <16 x i8> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>
+ %vmull.i.i.i = tail call <8 x i16> @llvm.arm64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp3) nounwind
+ %add.i = add <8 x i16> %vmull.i.i.i, %a
+ ret <8 x i16> %add.i
+}
+
+define <4 x i32> @bar4(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind {
+; CHECK-LABEL: bar4:
+; CHECK: umlal2.4s v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>
+ %vmull2.i.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ %add.i = add <4 x i32> %vmull2.i.i.i, %a
+ ret <4 x i32> %add.i
+}
+
+define <2 x i64> @bar5(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind {
+; CHECK-LABEL: bar5:
+; CHECK: umlal2.2d v0, v1, v2
+; CHECK-NEXT: ret
+
+ %tmp = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %c to <2 x i64>
+ %shuffle.i3.i.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>
+ %vmull2.i.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ %add.i = add <2 x i64> %vmull2.i.i.i, %a
+ ret <2 x i64> %add.i
+}
+
+define <4 x i32> @mlal2_1(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind {
+; CHECK-LABEL: mlal2_1:
+; CHECK: smlal2.4s v0, v1, v2[3]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
+ %tmp = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %shuffle to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ %add = add <4 x i32> %vmull2.i.i, %a
+ ret <4 x i32> %add
+}
+
+define <2 x i64> @mlal2_2(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind {
+; CHECK-LABEL: mlal2_2:
+; CHECK: smlal2.2d v0, v1, v2[1]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %tmp = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %shuffle to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ %add = add <2 x i64> %vmull2.i.i, %a
+ ret <2 x i64> %add
+}
+
+define <4 x i32> @mlal2_4(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind {
+; CHECK-LABEL: mlal2_4:
+; CHECK: umlal2.4s v0, v1, v2[2]
+; CHECK-NEXT: ret
+
+ %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+ %tmp = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %tmp2 = bitcast <8 x i16> %shuffle to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) nounwind
+ %add = add <4 x i32> %vmull2.i.i, %a
+ ret <4 x i32> %add
+}
+
+define <2 x i64> @mlal2_5(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind {
+; CHECK-LABEL: mlal2_5:
+; CHECK: umlal2.2d v0, v1, v2[0]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> zeroinitializer
+ %tmp = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %tmp, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %tmp2 = bitcast <4 x i32> %shuffle to <2 x i64>
+ %shuffle.i3.i = shufflevector <2 x i64> %tmp2, <2 x i64> undef, <1 x i32> <i32 1>
+ %tmp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) nounwind
+ %add = add <2 x i64> %vmull2.i.i, %a
+ ret <2 x i64> %add
+}
+
+; rdar://12328502
+define <2 x double> @vmulq_n_f64(<2 x double> %x, double %y) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: vmulq_n_f64:
+; CHECK-NOT: dup.2d
+; CHECK: fmul.2d v0, v0, v1[0]
+ %vecinit.i = insertelement <2 x double> undef, double %y, i32 0
+ %vecinit1.i = insertelement <2 x double> %vecinit.i, double %y, i32 1
+ %mul.i = fmul <2 x double> %vecinit1.i, %x
+ ret <2 x double> %mul.i
+}
+
+define <4 x float> @vmulq_n_f32(<4 x float> %x, float %y) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: vmulq_n_f32:
+; CHECK-NOT: dup.4s
+; CHECK: fmul.4s v0, v0, v1[0]
+ %vecinit.i = insertelement <4 x float> undef, float %y, i32 0
+ %vecinit1.i = insertelement <4 x float> %vecinit.i, float %y, i32 1
+ %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %y, i32 2
+ %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %y, i32 3
+ %mul.i = fmul <4 x float> %vecinit3.i, %x
+ ret <4 x float> %mul.i
+}
+
+define <2 x float> @vmul_n_f32(<2 x float> %x, float %y) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: vmul_n_f32:
+; CHECK-NOT: dup.2s
+; CHECK: fmul.2s v0, v0, v1[0]
+ %vecinit.i = insertelement <2 x float> undef, float %y, i32 0
+ %vecinit1.i = insertelement <2 x float> %vecinit.i, float %y, i32 1
+ %mul.i = fmul <2 x float> %vecinit1.i, %x
+ ret <2 x float> %mul.i
+}
+
+define <4 x i16> @vmla_laneq_s16_test(<4 x i16> %a, <4 x i16> %b, <8 x i16> %c) nounwind readnone ssp {
+entry:
+; CHECK: vmla_laneq_s16_test
+; CHECK-NOT: ext
+; CHECK: mla.4h v0, v1, v2[6]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
+ %mul = mul <4 x i16> %shuffle, %b
+ %add = add <4 x i16> %mul, %a
+ ret <4 x i16> %add
+}
+
+define <2 x i32> @vmla_laneq_s32_test(<2 x i32> %a, <2 x i32> %b, <4 x i32> %c) nounwind readnone ssp {
+entry:
+; CHECK: vmla_laneq_s32_test
+; CHECK-NOT: ext
+; CHECK: mla.2s v0, v1, v2[3]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 3, i32 3>
+ %mul = mul <2 x i32> %shuffle, %b
+ %add = add <2 x i32> %mul, %a
+ ret <2 x i32> %add
+}
+
+define <4 x i32> @vmull_laneq_s16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {
+entry:
+; CHECK: vmull_laneq_s16_test
+; CHECK-NOT: ext
+; CHECK: smull.4s v0, v0, v1[6]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
+ %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #2
+ ret <4 x i32> %vmull2.i
+}
+
+define <2 x i64> @vmull_laneq_s32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+; CHECK: vmull_laneq_s32_test
+; CHECK-NOT: ext
+; CHECK: smull.2d v0, v0, v1[2]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>
+ %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #2
+ ret <2 x i64> %vmull2.i
+}
+define <4 x i32> @vmull_laneq_u16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {
+entry:
+; CHECK: vmull_laneq_u16_test
+; CHECK-NOT: ext
+; CHECK: umull.4s v0, v0, v1[6]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>
+ %vmull2.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #2
+ ret <4 x i32> %vmull2.i
+}
+
+define <2 x i64> @vmull_laneq_u32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {
+entry:
+; CHECK: vmull_laneq_u32_test
+; CHECK-NOT: ext
+; CHECK: umull.2d v0, v0, v1[2]
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>
+ %vmull2.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #2
+ ret <2 x i64> %vmull2.i
+}
+
+define <4 x i32> @vmull_high_n_s16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {
+entry:
+; CHECK: vmull_high_n_s16_test
+; CHECK-NOT: ext
+; CHECK: smull2.4s
+; CHECK-NEXT: ret
+ %conv = trunc i32 %d to i16
+ %0 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 3
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind
+ ret <4 x i32> %vmull2.i.i
+}
+
+define <2 x i64> @vmull_high_n_s32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {
+entry:
+; CHECK: vmull_high_n_s32_test
+; CHECK-NOT: ext
+; CHECK: smull2.2d
+; CHECK-NEXT: ret
+ %0 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 0
+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 1
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind
+ ret <2 x i64> %vmull2.i.i
+}
+
+define <4 x i32> @vmull_high_n_u16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {
+entry:
+; CHECK: vmull_high_n_u16_test
+; CHECK-NOT: ext
+; CHECK: umull2.4s
+; CHECK-NEXT: ret
+ %conv = trunc i32 %d to i16
+ %0 = bitcast <8 x i16> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>
+ %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 3
+ %vmull2.i.i = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind
+ ret <4 x i32> %vmull2.i.i
+}
+
+define <2 x i64> @vmull_high_n_u32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {
+entry:
+; CHECK: vmull_high_n_u32_test
+; CHECK-NOT: ext
+; CHECK: umull2.2d
+; CHECK-NEXT: ret
+ %0 = bitcast <4 x i32> %b to <2 x i64>
+ %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>
+ %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>
+ %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 0
+ %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 1
+ %vmull2.i.i = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind
+ ret <2 x i64> %vmull2.i.i
+}
+
+define <4 x i32> @vmul_built_dup_test(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: vmul_built_dup_test:
+; CHECK-NOT: ins
+; CHECK-NOT: dup
+; CHECK: mul.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[1]
+ %vget_lane = extractelement <4 x i32> %b, i32 1
+ %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 3
+ %prod = mul <4 x i32> %a, %vecinit3.i
+ ret <4 x i32> %prod
+}
+
+define <4 x i16> @vmul_built_dup_fromsmall_test(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: vmul_built_dup_fromsmall_test:
+; CHECK-NOT: ins
+; CHECK-NOT: dup
+; CHECK: mul.4h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[3]
+ %vget_lane = extractelement <4 x i16> %b, i32 3
+ %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ %prod = mul <4 x i16> %a, %vecinit3.i
+ ret <4 x i16> %prod
+}
+
+define <8 x i16> @vmulq_built_dup_fromsmall_test(<8 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: vmulq_built_dup_fromsmall_test:
+; CHECK-NOT: ins
+; CHECK-NOT: dup
+; CHECK: mul.8h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0]
+ %vget_lane = extractelement <4 x i16> %b, i32 0
+ %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 0
+ %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 1
+ %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 2
+ %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 3
+ %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 4
+ %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 5
+ %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 6
+ %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 7
+ %prod = mul <8 x i16> %a, %vecinit7.i
+ ret <8 x i16> %prod
+}
+
+define <2 x i64> @mull_from_two_extracts(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: mull_from_two_extracts:
+; CHECK-NOT: ext
+; CHECK: sqdmull2.2d
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @mlal_from_two_extracts(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: mlal_from_two_extracts:
+; CHECK-NOT: ext
+; CHECK: sqdmlal2.2d
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
+ %sum = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)
+ ret <2 x i64> %sum
+}
+
+define <2 x i64> @mull_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
+; CHECK-LABEL: mull_from_extract_dup:
+; CHECK-NOT: ext
+; CHECK: sqdmull2.2d
+ %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
+ %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
+ ret <2 x i64> %res
+}
+
+define <8 x i16> @pmull_from_extract_dup(<16 x i8> %lhs, i8 %rhs) {
+; CHECK-LABEL: pmull_from_extract_dup:
+; CHECK-NOT: ext
+; CHECK: pmull2.8h
+ %rhsvec.0 = insertelement <8 x i8> undef, i8 %rhs, i32 0
+ %rhsvec = shufflevector <8 x i8> %rhsvec.0, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+
+ %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+
+ %res = tail call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) nounwind
+ ret <8 x i16> %res
+}
+
+define <8 x i16> @pmull_from_extract_duplane(<16 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK-LABEL: pmull_from_extract_duplane:
+; CHECK-NOT: ext
+; CHECK: pmull2.8h
+
+ %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %rhs.high = shufflevector <8 x i8> %rhs, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+
+ %res = tail call <8 x i16> @llvm.arm64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) nounwind
+ ret <8 x i16> %res
+}
+
+define <2 x i64> @sqdmull_from_extract_duplane(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: sqdmull_from_extract_duplane:
+; CHECK-NOT: ext
+; CHECK: sqdmull2.2d
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @sqdmlal_from_extract_duplane(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: sqdmlal_from_extract_duplane:
+; CHECK-NOT: ext
+; CHECK: sqdmlal2.2d
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
+ %sum = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)
+ ret <2 x i64> %sum
+}
+
+define <2 x i64> @umlal_from_extract_duplane(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK-LABEL: umlal_from_extract_duplane:
+; CHECK-NOT: ext
+; CHECK: umlal2.2d
+
+ %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>
+
+ %res = tail call <2 x i64> @llvm.arm64.neon.umull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind
+ %sum = add <2 x i64> %accum, %res
+ ret <2 x i64> %sum
+}
+
+define float @scalar_fmla_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {
+; CHECK-LABEL: scalar_fmla_from_extract_v4f32:
+; CHECK: fmla.s s0, s1, v2[3]
+ %rhs = extractelement <4 x float> %rvec, i32 3
+ %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
+ ret float %res
+}
+
+define float @scalar_fmla_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {
+; CHECK-LABEL: scalar_fmla_from_extract_v2f32:
+; CHECK: fmla.s s0, s1, v2[1]
+ %rhs = extractelement <2 x float> %rvec, i32 1
+ %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
+ ret float %res
+}
+
+define float @scalar_fmls_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {
+; CHECK-LABEL: scalar_fmls_from_extract_v4f32:
+; CHECK: fmls.s s0, s1, v2[3]
+ %rhs.scal = extractelement <4 x float> %rvec, i32 3
+ %rhs = fsub float -0.0, %rhs.scal
+ %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
+ ret float %res
+}
+
+define float @scalar_fmls_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {
+; CHECK-LABEL: scalar_fmls_from_extract_v2f32:
+; CHECK: fmls.s s0, s1, v2[1]
+ %rhs.scal = extractelement <2 x float> %rvec, i32 1
+ %rhs = fsub float -0.0, %rhs.scal
+ %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)
+ ret float %res
+}
+
+declare float @llvm.fma.f32(float, float, float)
+
+define double @scalar_fmla_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {
+; CHECK-LABEL: scalar_fmla_from_extract_v2f64:
+; CHECK: fmla.d d0, d1, v2[1]
+ %rhs = extractelement <2 x double> %rvec, i32 1
+ %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)
+ ret double %res
+}
+
+define double @scalar_fmls_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {
+; CHECK-LABEL: scalar_fmls_from_extract_v2f64:
+; CHECK: fmls.d d0, d1, v2[1]
+ %rhs.scal = extractelement <2 x double> %rvec, i32 1
+ %rhs = fsub double -0.0, %rhs.scal
+ %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)
+ ret double %res
+}
+
+declare double @llvm.fma.f64(double, double, double)
+
+define <2 x float> @fmls_with_fneg_before_extract_v2f32(<2 x float> %accum, <2 x float> %lhs, <4 x float> %rhs) {
+; CHECK-LABEL: fmls_with_fneg_before_extract_v2f32:
+; CHECK: fmls.2s v0, v1, v2[3]
+ %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs
+ %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <2 x i32> <i32 3, i32 3>
+ %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)
+ ret <2 x float> %res
+}
+
+define <2 x float> @fmls_with_fneg_before_extract_v2f32_1(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) {
+; CHECK-LABEL: fmls_with_fneg_before_extract_v2f32_1:
+; CHECK: fmls.2s v0, v1, v2[1]
+ %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs
+ %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+ %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)
+ ret <2 x float> %res
+}
+
+define <4 x float> @fmls_with_fneg_before_extract_v4f32(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) {
+; CHECK-LABEL: fmls_with_fneg_before_extract_v4f32:
+; CHECK: fmls.4s v0, v1, v2[3]
+ %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs
+ %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+ %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)
+ ret <4 x float> %res
+}
+
+define <4 x float> @fmls_with_fneg_before_extract_v4f32_1(<4 x float> %accum, <4 x float> %lhs, <2 x float> %rhs) {
+; CHECK-LABEL: fmls_with_fneg_before_extract_v4f32_1:
+; CHECK: fmls.4s v0, v1, v2[1]
+ %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs
+ %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+ %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)
+ ret <4 x float> %res
+}
+
+define <2 x double> @fmls_with_fneg_before_extract_v2f64(<2 x double> %accum, <2 x double> %lhs, <2 x double> %rhs) {
+; CHECK-LABEL: fmls_with_fneg_before_extract_v2f64:
+; CHECK: fmls.2d v0, v1, v2[1]
+ %rhs_neg = fsub <2 x double> <double -0.0, double -0.0>, %rhs
+ %splat = shufflevector <2 x double> %rhs_neg, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+ %res = call <2 x double> @llvm.fma.v2f64(<2 x double> %lhs, <2 x double> %splat, <2 x double> %accum)
+ ret <2 x double> %res
+}
+
+define <1 x double> @test_fmul_v1f64(<1 x double> %L, <1 x double> %R) nounwind {
+; CHECK-LABEL: test_fmul_v1f64:
+; CHECK: fmul
+ %prod = fmul <1 x double> %L, %R
+ ret <1 x double> %prod
+}
+
+define <1 x double> @test_fdiv_v1f64(<1 x double> %L, <1 x double> %R) nounwind {
+; CHECK-LABEL: test_fdiv_v1f64:
+; CHECK-LABEL: fdiv
+ %prod = fdiv <1 x double> %L, %R
+ ret <1 x double> %prod
+}
Added: llvm/trunk/test/CodeGen/ARM64/volatile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/volatile.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/volatile.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/volatile.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,27 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s
+define i64 @normal_load(i64* nocapture %bar) nounwind readonly {
+; CHECK: normal_load
+; CHECK: ldp
+; CHECK-NEXT: add
+; CHECK-NEXT: ret
+ %add.ptr = getelementptr inbounds i64* %bar, i64 1
+ %tmp = load i64* %add.ptr, align 8
+ %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
+ %tmp1 = load i64* %add.ptr1, align 8
+ %add = add nsw i64 %tmp1, %tmp
+ ret i64 %add
+}
+
+define i64 @volatile_load(i64* nocapture %bar) nounwind {
+; CHECK: volatile_load
+; CHECK: ldr
+; CHECK-NEXT: ldr
+; CHECK-NEXT: add
+; CHECK-NEXT: ret
+ %add.ptr = getelementptr inbounds i64* %bar, i64 1
+ %tmp = load volatile i64* %add.ptr, align 8
+ %add.ptr1 = getelementptr inbounds i64* %bar, i64 2
+ %tmp1 = load volatile i64* %add.ptr1, align 8
+ %add = add nsw i64 %tmp1, %tmp
+ ret i64 %add
+}
Added: llvm/trunk/test/CodeGen/ARM64/vqadd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vqadd.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vqadd.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vqadd.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,300 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sqadd8b:
+;CHECK: sqadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqadd4h:
+;CHECK: sqadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqadd2s:
+;CHECK: sqadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uqadd8b:
+;CHECK: uqadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uqadd4h:
+;CHECK: uqadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uqadd2s:
+;CHECK: uqadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sqadd16b:
+;CHECK: sqadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqadd8h:
+;CHECK: sqadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqadd4s:
+;CHECK: sqadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: sqadd2d:
+;CHECK: sqadd.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uqadd16b:
+;CHECK: uqadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uqadd8h:
+;CHECK: uqadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uqadd4s:
+;CHECK: uqadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @uqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: uqadd2d:
+;CHECK: uqadd.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.sqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.uqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.sqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: usqadd8b:
+;CHECK: usqadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: usqadd4h:
+;CHECK: usqadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: usqadd2s:
+;CHECK: usqadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: usqadd16b:
+;CHECK: usqadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: usqadd8h:
+;CHECK: usqadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: usqadd4s:
+;CHECK: usqadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: usqadd2d:
+;CHECK: usqadd.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.usqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: suqadd8b:
+;CHECK: suqadd.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: suqadd4h:
+;CHECK: suqadd.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: suqadd2s:
+;CHECK: suqadd.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: suqadd16b:
+;CHECK: suqadd.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: suqadd8h:
+;CHECK: suqadd.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: suqadd4s:
+;CHECK: suqadd.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: suqadd2d:
+;CHECK: suqadd.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <1 x i64> @suqadd_d(<1 x i64> %l, <1 x i64> %r) nounwind {
+; CHECK-LABEL: suqadd_d:
+; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
+ %sum = call <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64> %l, <1 x i64> %r)
+ ret <1 x i64> %sum
+}
+
+declare <8 x i8> @llvm.arm64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vqsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vqsub.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vqsub.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vqsub.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,147 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sqsub8b:
+;CHECK: sqsub.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqsub4h:
+;CHECK: sqsub.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqsub2s:
+;CHECK: sqsub.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uqsub8b:
+;CHECK: uqsub.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uqsub4h:
+;CHECK: uqsub.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uqsub2s:
+;CHECK: uqsub.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sqsub16b:
+;CHECK: sqsub.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqsub8h:
+;CHECK: sqsub.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqsub4s:
+;CHECK: sqsub.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: sqsub2d:
+;CHECK: sqsub.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uqsub16b:
+;CHECK: uqsub.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uqsub8h:
+;CHECK: uqsub.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uqsub4s:
+;CHECK: uqsub.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: uqsub2d:
+;CHECK: uqsub.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.sqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uqsub.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqsub.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqsub.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.uqsub.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.sqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uqsub.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uqsub.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uqsub.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.uqsub.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vselect.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vselect.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vselect.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+;CHECK: @func63
+;CHECK: cmeq.4h v0, v0, v1
+;CHECK: sshll.4s v0, v0, #0
+;CHECK: bsl.16b v0, v2, v3
+;CHECK: str q0, [x0]
+;CHECK: ret
+
+%T0_63 = type <4 x i16>
+%T1_63 = type <4 x i32>
+%T2_63 = type <4 x i1>
+define void @func63(%T1_63* %out, %T0_63 %v0, %T0_63 %v1, %T1_63 %v2, %T1_63 %v3) {
+ %cond = icmp eq %T0_63 %v0, %v1
+ %r = select %T2_63 %cond, %T1_63 %v2, %T1_63 %v3
+ store %T1_63 %r, %T1_63* %out
+ ret void
+}
Added: llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vsetcc_fp.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -asm-verbose=false | FileCheck %s
+define <2 x i32> @fcmp_one(<2 x float> %x, <2 x float> %y) nounwind optsize readnone {
+; CHECK-LABEL: fcmp_one:
+; CHECK-NEXT: fcmgt.2s [[REG:v[0-9]+]], v0, v1
+; CHECK-NEXT: fcmgt.2s [[REG2:v[0-9]+]], v1, v0
+; CHECK-NEXT: orr.8b v0, [[REG2]], [[REG]]
+; CHECK-NEXT: ret
+ %tmp = fcmp one <2 x float> %x, %y
+ %or = sext <2 x i1> %tmp to <2 x i32>
+ ret <2 x i32> %or
+}
Added: llvm/trunk/test/CodeGen/ARM64/vshift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshift.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshift.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vshift.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,1909 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -enable-misched=false | FileCheck %s
+
+define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sqshl8b:
+;CHECK: sqshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqshl4h:
+;CHECK: sqshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqshl2s:
+;CHECK: sqshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uqshl8b:
+;CHECK: uqshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uqshl4h:
+;CHECK: uqshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uqshl2s:
+;CHECK: uqshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sqshl16b:
+;CHECK: sqshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqshl8h:
+;CHECK: sqshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqshl4s:
+;CHECK: sqshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: sqshl2d:
+;CHECK: sqshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uqshl16b:
+;CHECK: uqshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uqshl8h:
+;CHECK: uqshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uqshl4s:
+;CHECK: uqshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @uqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: uqshl2d:
+;CHECK: uqshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.sqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.uqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: srshl8b:
+;CHECK: srshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: srshl4h:
+;CHECK: srshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: srshl2s:
+;CHECK: srshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: urshl8b:
+;CHECK: urshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: urshl4h:
+;CHECK: urshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: urshl2s:
+;CHECK: urshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: srshl16b:
+;CHECK: srshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: srshl8h:
+;CHECK: srshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: srshl4s:
+;CHECK: srshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: srshl2d:
+;CHECK: srshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: urshl16b:
+;CHECK: urshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: urshl8h:
+;CHECK: urshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: urshl4s:
+;CHECK: urshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @urshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: urshl2d:
+;CHECK: urshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.srshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.urshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sqrshl8b:
+;CHECK: sqrshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrshl4h:
+;CHECK: sqrshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrshl2s:
+;CHECK: sqrshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: uqrshl8b:
+;CHECK: uqrshl.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: uqrshl4h:
+;CHECK: uqrshl.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: uqrshl2s:
+;CHECK: uqrshl.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sqrshl16b:
+;CHECK: sqrshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sqrshl8h:
+;CHECK: sqrshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sqrshl4s:
+;CHECK: sqrshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: sqrshl2d:
+;CHECK: sqrshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: uqrshl16b:
+;CHECK: uqrshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: uqrshl8h:
+;CHECK: uqrshl.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: uqrshl4s:
+;CHECK: uqrshl.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @uqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: uqrshl2d:
+;CHECK: uqrshl.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.sqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <8 x i8> @llvm.arm64.neon.uqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.uqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.sqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.uqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.uqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.uqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: urshr8b:
+;CHECK: urshr.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: urshr4h:
+;CHECK: urshr.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: urshr2s:
+;CHECK: urshr.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: urshr16b:
+;CHECK: urshr.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: urshr8h:
+;CHECK: urshr.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: urshr4s:
+;CHECK: urshr.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: urshr2d:
+;CHECK: urshr.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: srshr8b:
+;CHECK: srshr.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: srshr4h:
+;CHECK: srshr.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: srshr2s:
+;CHECK: srshr.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: srshr16b:
+;CHECK: srshr.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: srshr8h:
+;CHECK: srshr.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: srshr4s:
+;CHECK: srshr.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: srshr2d:
+;CHECK: srshr.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: sqshlu8b:
+;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshlu4h:
+;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshlu2s:
+;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: sqshlu16b:
+;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshlu8h:
+;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshlu4s:
+;CHECK: sqshlu.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqshlu2d(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshlu2d:
+;CHECK: sqshlu.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.sqshlu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqshlu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqshlu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.sqshlu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.sqshlu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.sqshlu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.sqshlu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
+
+define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: rshrn8b:
+;CHECK: rshrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: rshrn4h:
+;CHECK: rshrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: rshrn2s:
+;CHECK: rshrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: rshrn16b:
+;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: rshrn8h:
+;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @rshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: rshrn4s:
+;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare <8 x i8> @llvm.arm64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.rshrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: shrn8b:
+;CHECK: shrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: shrn4h:
+;CHECK: shrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: shrn2s:
+;CHECK: shrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: shrn16b:
+;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: shrn8h:
+;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @shrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: shrn4s:
+;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare <8 x i8> @llvm.arm64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @sqshrn1s(i64 %A) nounwind {
+; CHECK-LABEL: sqshrn1s:
+; CHECK: sqshrn {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.sqshrn.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshrn8b:
+;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshrn4h:
+;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshrn2s:
+;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+
+define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshrn16b:
+;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshrn8h:
+;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @sqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshrn4s:
+;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.sqshrn.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @sqshrun1s(i64 %A) nounwind {
+; CHECK-LABEL: sqshrun1s:
+; CHECK: sqshrun {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.sqshrun.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshrun8b:
+;CHECK: sqshrun.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshrun4h:
+;CHECK: sqshrun.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshrun2s:
+;CHECK: sqshrun.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshrun16b:
+;CHECK: sqshrun2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshrun8h:
+;CHECK: sqshrun2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @sqshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshrun4s:
+;CHECK: sqshrun2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.sqshrun.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.sqshrun.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqshrun.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqshrun.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @sqrshrn1s(i64 %A) nounwind {
+; CHECK-LABEL: sqrshrn1s:
+; CHECK: sqrshrn {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.sqrshrn.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqrshrn8b:
+;CHECK: sqrshrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqrshrn4h:
+;CHECK: sqrshrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqrshrn2s:
+;CHECK: sqrshrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqrshrn16b:
+;CHECK: sqrshrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqrshrn8h:
+;CHECK: sqrshrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @sqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqrshrn4s:
+;CHECK: sqrshrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.sqrshrn.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.sqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @sqrshrun1s(i64 %A) nounwind {
+; CHECK-LABEL: sqrshrun1s:
+; CHECK: sqrshrun {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.sqrshrun.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqrshrun8b:
+;CHECK: sqrshrun.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqrshrun4h:
+;CHECK: sqrshrun.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqrshrun2s:
+;CHECK: sqrshrun.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqrshrun16b:
+;CHECK: sqrshrun2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqrshrun8h:
+;CHECK: sqrshrun2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @sqrshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqrshrun4s:
+;CHECK: sqrshrun2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.sqrshrun.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.sqrshrun.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.sqrshrun.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.sqrshrun.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @uqrshrn1s(i64 %A) nounwind {
+; CHECK-LABEL: uqrshrn1s:
+; CHECK: uqrshrn {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.uqrshrn.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: uqrshrn8b:
+;CHECK: uqrshrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: uqrshrn4h:
+;CHECK: uqrshrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: uqrshrn2s:
+;CHECK: uqrshrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: uqrshrn16b:
+;CHECK: uqrshrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: uqrshrn8h:
+;CHECK: uqrshrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @uqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: uqrshrn4s:
+;CHECK: uqrshrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.uqrshrn.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.uqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define i32 @uqshrn1s(i64 %A) nounwind {
+; CHECK-LABEL: uqshrn1s:
+; CHECK: uqshrn {{s[0-9]+}}, d0, #1
+ %tmp = call i32 @llvm.arm64.neon.uqshrn.i32(i64 %A, i32 1)
+ ret i32 %tmp
+}
+
+define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: uqshrn8b:
+;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: uqshrn4h:
+;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: uqshrn2s:
+;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind {
+;CHECK-LABEL: uqshrn16b:
+;CHECK: uqshrn2.16b v0, {{v[0-9]+}}, #1
+ %out = load <8 x i8>* %ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
+ %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind {
+;CHECK-LABEL: uqshrn8h:
+;CHECK: uqshrn2.8h v0, {{v[0-9]+}}, #1
+ %out = load <4 x i16>* %ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
+ %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @uqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind {
+;CHECK-LABEL: uqshrn4s:
+;CHECK: uqshrn2.4s v0, {{v[0-9]+}}, #1
+ %out = load <2 x i32>* %ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
+ %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %tmp4
+}
+
+declare i32 @llvm.arm64.neon.uqshrn.i32(i64, i32) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.uqshrn.v8i8(<8 x i16>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.uqshrn.v4i16(<4 x i32>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readnone
+
+define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: ushll8h:
+;CHECK: ushll.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
+ %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: ushll4s:
+;CHECK: ushll.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
+ %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: ushll2d:
+;CHECK: ushll.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
+ %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: ushll2_8h:
+;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1
+ %load1 = load <16 x i8>* %A
+ %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
+ %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: ushll2_4s:
+;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1
+ %load1 = load <8 x i16>* %A
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
+ %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: ushll2_2d:
+;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1
+ %load1 = load <4 x i32>* %A
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
+ %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: sshll8h:
+;CHECK: sshll.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
+ %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: sshll4s:
+;CHECK: sshll.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
+ %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: sshll2d:
+;CHECK: sshll.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
+ %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: sshll2_8h:
+;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1
+ %load1 = load <16 x i8>* %A
+ %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
+ %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sshll2_4s:
+;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1
+ %load1 = load <8 x i16>* %A
+ %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
+ %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sshll2_2d:
+;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1
+ %load1 = load <4 x i32>* %A
+ %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
+ %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: sqshli8b:
+;CHECK: sqshl.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshli4h:
+;CHECK: sqshl.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshli2s:
+;CHECK: sqshl.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: sqshli16b:
+;CHECK: sqshl.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: sqshli8h:
+;CHECK: sqshl.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: sqshli4s:
+;CHECK: sqshl.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: sqshli2d:
+;CHECK: sqshl.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind {
+;CHECK-LABEL: uqshli8b:
+;CHECK: uqshl.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind {
+;CHECK-LABEL: uqshli4h:
+;CHECK: uqshl.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: uqshli2s:
+;CHECK: uqshl.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind {
+;CHECK-LABEL: uqshli16b:
+;CHECK: uqshl.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind {
+;CHECK-LABEL: uqshli8h:
+;CHECK: uqshl.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: uqshli4s:
+;CHECK: uqshl.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind {
+;CHECK-LABEL: uqshli2d:
+;CHECK: uqshl.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
+ ret <2 x i64> %tmp3
+}
+
+define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: ursra8b:
+;CHECK: ursra.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ %tmp4 = load <8 x i8>* %B
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: ursra4h:
+;CHECK: ursra.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
+ %tmp4 = load <4 x i16>* %B
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: ursra2s:
+;CHECK: ursra.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
+ %tmp4 = load <2 x i32>* %B
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: ursra16b:
+;CHECK: ursra.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ %tmp4 = load <16 x i8>* %B
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: ursra8h:
+;CHECK: ursra.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
+ %tmp4 = load <8 x i16>* %B
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: ursra4s:
+;CHECK: ursra.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
+ %tmp4 = load <4 x i32>* %B
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: ursra2d:
+;CHECK: ursra.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
+ %tmp4 = load <2 x i64>* %B
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: srsra8b:
+;CHECK: srsra.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ %tmp4 = load <8 x i8>* %B
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: srsra4h:
+;CHECK: srsra.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
+ %tmp4 = load <4 x i16>* %B
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: srsra2s:
+;CHECK: srsra.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
+ %tmp4 = load <2 x i32>* %B
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: srsra16b:
+;CHECK: srsra.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
+ %tmp4 = load <16 x i8>* %B
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: srsra8h:
+;CHECK: srsra.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
+ %tmp4 = load <8 x i16>* %B
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: srsra4s:
+;CHECK: srsra.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
+ %tmp4 = load <4 x i32>* %B
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: srsra2d:
+;CHECK: srsra.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
+ %tmp4 = load <2 x i64>* %B
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: usra8b:
+;CHECK: usra.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp4 = load <8 x i8>* %B
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: usra4h:
+;CHECK: usra.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
+ %tmp4 = load <4 x i16>* %B
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: usra2s:
+;CHECK: usra.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
+ %tmp4 = load <2 x i32>* %B
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: usra16b:
+;CHECK: usra.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp4 = load <16 x i8>* %B
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: usra8h:
+;CHECK: usra.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp4 = load <8 x i16>* %B
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: usra4s:
+;CHECK: usra.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = load <4 x i32>* %B
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: usra2d:
+;CHECK: usra.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp4 = load <2 x i64>* %B
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: ssra8b:
+;CHECK: ssra.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp4 = load <8 x i8>* %B
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: ssra4h:
+;CHECK: ssra.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
+ %tmp4 = load <4 x i16>* %B
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: ssra2s:
+;CHECK: ssra.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>
+ %tmp4 = load <2 x i32>* %B
+ %tmp5 = add <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: ssra16b:
+;CHECK: ssra.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp4 = load <16 x i8>* %B
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: ssra8h:
+;CHECK: ssra.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp4 = load <8 x i16>* %B
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: ssra4s:
+;CHECK: ssra.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp4 = load <4 x i32>* %B
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @ssra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: ssra2d:
+;CHECK: ssra.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp4 = load <2 x i64>* %B
+ %tmp5 = add <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i8> @shr_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: shr_orr8b:
+;CHECK: shr.8b v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>* %A
+ %tmp4 = load <8 x i8>* %B
+ %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp5 = or <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @shr_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: shr_orr4h:
+;CHECK: shr.4h v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>* %A
+ %tmp4 = load <4 x i16>* %B
+ %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
+ %tmp5 = or <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @shr_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: shr_orr2s:
+;CHECK: shr.2s v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>* %A
+ %tmp4 = load <2 x i32>* %B
+ %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
+ %tmp5 = or <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @shr_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: shr_orr16b:
+;CHECK: shr.16b v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>* %A
+ %tmp4 = load <16 x i8>* %B
+ %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp5 = or <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @shr_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: shr_orr8h:
+;CHECK: shr.8h v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp4 = load <8 x i16>* %B
+ %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp5 = or <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @shr_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: shr_orr4s:
+;CHECK: shr.4s v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp4 = load <4 x i32>* %B
+ %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = or <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @shr_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: shr_orr2d:
+;CHECK: shr.2d v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp4 = load <2 x i64>* %B
+ %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp5 = or <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i8> @shl_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: shl_orr8b:
+;CHECK: shl.8b v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <8 x i8>* %A
+ %tmp4 = load <8 x i8>* %B
+ %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp5 = or <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @shl_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: shl_orr4h:
+;CHECK: shl.4h v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <4 x i16>* %A
+ %tmp4 = load <4 x i16>* %B
+ %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
+ %tmp5 = or <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @shl_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: shl_orr2s:
+;CHECK: shl.2s v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.8b
+;CHECK-NEXT: ret
+ %tmp1 = load <2 x i32>* %A
+ %tmp4 = load <2 x i32>* %B
+ %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>
+ %tmp5 = or <2 x i32> %tmp3, %tmp4
+ ret <2 x i32> %tmp5
+}
+
+define <16 x i8> @shl_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: shl_orr16b:
+;CHECK: shl.16b v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <16 x i8>* %A
+ %tmp4 = load <16 x i8>* %B
+ %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %tmp5 = or <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @shl_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: shl_orr8h:
+;CHECK: shl.8h v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <8 x i16>* %A
+ %tmp4 = load <8 x i16>* %B
+ %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+ %tmp5 = or <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @shl_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: shl_orr4s:
+;CHECK: shl.4s v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <4 x i32>* %A
+ %tmp4 = load <4 x i32>* %B
+ %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
+ %tmp5 = or <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @shl_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: shl_orr2d:
+;CHECK: shl.2d v0, {{v[0-9]+}}, #1
+;CHECK-NEXT: orr.16b
+;CHECK-NEXT: ret
+ %tmp1 = load <2 x i64>* %A
+ %tmp4 = load <2 x i64>* %B
+ %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>
+ %tmp5 = or <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @shll(<8 x i8> %in) {
+; CHECK-LABEL: shll:
+; CHECK: shll.8h v0, {{v[0-9]+}}, #8
+ %ext = zext <8 x i8> %in to <8 x i16>
+ %res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @shll_high(<8 x i16> %in) {
+; CHECK-LABEL: shll_high
+; CHECK: shll2.4s v0, {{v[0-9]+}}, #16
+ %extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext = zext <4 x i16> %extract to <4 x i32>
+ %res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>
+ ret <4 x i32> %res
+}
+
+define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: sli8b:
+;CHECK: sli.8b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: sli4h:
+;CHECK: sli.4h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: sli2s:
+;CHECK: sli.2s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)
+ ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind {
+;CHECK-LABEL: sli1d:
+;CHECK: sli d0, {{d[0-9]+}}, #1
+ %tmp1 = load <1 x i64>* %A
+ %tmp2 = load <1 x i64>* %B
+ %tmp3 = call <1 x i64> @llvm.arm64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)
+ ret <1 x i64> %tmp3
+}
+
+define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: sli16b:
+;CHECK: sli.16b v0, {{v[0-9]+}}, #1
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = call <16 x i8> @llvm.arm64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)
+ ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: sli8h:
+;CHECK: sli.8h v0, {{v[0-9]+}}, #1
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)
+ ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: sli4s:
+;CHECK: sli.4s v0, {{v[0-9]+}}, #1
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)
+ ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sli2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: sli2d:
+;CHECK: sli.2d v0, {{v[0-9]+}}, #1
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)
+ ret <2 x i64> %tmp3
+}
+
+declare <8 x i8> @llvm.arm64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone
+declare <2 x i32> @llvm.arm64.neon.vsli.v2i32(<2 x i32>, <2 x i32>, i32) nounwind readnone
+declare <1 x i64> @llvm.arm64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) nounwind readnone
+
+declare <16 x i8> @llvm.arm64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwind readnone
+declare <8 x i16> @llvm.arm64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone
+declare <2 x i64> @llvm.arm64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vshr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshr.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshr.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vshr.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,49 @@
+; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
+
+define <8 x i16> @testShiftRightArith_v8i16(<8 x i16> %a, <8 x i16> %b) #0 {
+; CHECK-LABEL: testShiftRightArith_v8i16:
+; CHECK: neg.8h [[REG1:v[0-9]+]], [[REG1]]
+; CHECK-NEXT: sshl.8h [[REG2:v[0-9]+]], [[REG2]], [[REG1]]
+
+entry:
+ %a.addr = alloca <8 x i16>, align 16
+ %b.addr = alloca <8 x i16>, align 16
+ store <8 x i16> %a, <8 x i16>* %a.addr, align 16
+ store <8 x i16> %b, <8 x i16>* %b.addr, align 16
+ %0 = load <8 x i16>* %a.addr, align 16
+ %1 = load <8 x i16>* %b.addr, align 16
+ %shr = ashr <8 x i16> %0, %1
+ ret <8 x i16> %shr
+}
+
+define <4 x i32> @testShiftRightArith_v4i32(<4 x i32> %a, <4 x i32> %b) #0 {
+; CHECK-LABEL: testShiftRightArith_v4i32:
+; CHECK: neg.4s [[REG3:v[0-9]+]], [[REG3]]
+; CHECK-NEXT: sshl.4s [[REG4:v[0-9]+]], [[REG4]], [[REG3]]
+entry:
+ %a.addr = alloca <4 x i32>, align 32
+ %b.addr = alloca <4 x i32>, align 32
+ store <4 x i32> %a, <4 x i32>* %a.addr, align 32
+ store <4 x i32> %b, <4 x i32>* %b.addr, align 32
+ %0 = load <4 x i32>* %a.addr, align 32
+ %1 = load <4 x i32>* %b.addr, align 32
+ %shr = ashr <4 x i32> %0, %1
+ ret <4 x i32> %shr
+}
+
+define <8 x i16> @testShiftRightLogical(<8 x i16> %a, <8 x i16> %b) #0 {
+; CHECK: testShiftRightLogical
+; CHECK: neg.8h [[REG5:v[0-9]+]], [[REG5]]
+; CHECK-NEXT: ushl.8h [[REG6:v[0-9]+]], [[REG6]], [[REG5]]
+entry:
+ %a.addr = alloca <8 x i16>, align 16
+ %b.addr = alloca <8 x i16>, align 16
+ store <8 x i16> %a, <8 x i16>* %a.addr, align 16
+ store <8 x i16> %b, <8 x i16>* %b.addr, align 16
+ %0 = load <8 x i16>* %a.addr, align 16
+ %1 = load <8 x i16>* %b.addr, align 16
+ %shr = lshr <8 x i16> %0, %1
+ ret <8 x i16> %shr
+}
+
+attributes #0 = { nounwind }
Added: llvm/trunk/test/CodeGen/ARM64/vshuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vshuffle.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vshuffle.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vshuffle.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,115 @@
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
+
+
+; The mask:
+; CHECK: lCPI0_0:
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 255 ; 0xff
+; The second vector is legalized to undef and the elements of the first vector
+; are used instead.
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 4 ; 0x4
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 0 ; 0x0
+; CHECK: test1
+; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0
+; CHECK: movi.8h v[[REG1:[0-9]+]], #1, lsl #8
+; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+define <8 x i1> @test1() {
+entry:
+ %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
+ i1 7>,
+ <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
+ i1 7>,
+ <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
+ i32 12, i32 14, i32 0>
+ ret <8 x i1> %Shuff
+}
+
+; CHECK: lCPI1_0:
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 10 ; 0xa
+; CHECK: .byte 12 ; 0xc
+; CHECK: .byte 14 ; 0xe
+; CHECK: .byte 0 ; 0x0
+; CHECK: test2
+; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI1_0 at PAGEOFF]
+; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_1 at PAGE
+; CHECK: ldr q[[REG1:[0-9]+]], [x[[REG2]], lCPI1_1 at PAGEOFF]
+; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+define <8 x i1>@test2() {
+bb:
+ %Shuff = shufflevector <8 x i1> zeroinitializer,
+ <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
+ <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
+ i32 0>
+ ret <8 x i1> %Shuff
+}
+
+; CHECK: lCPI2_0:
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 10 ; 0xa
+; CHECK: .byte 12 ; 0xc
+; CHECK: .byte 14 ; 0xe
+; CHECK: .byte 0 ; 0x0
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 255 ; 0xff
+; CHECK: .byte 10 ; 0xa
+; CHECK: .byte 12 ; 0xc
+; CHECK: .byte 14 ; 0xe
+; CHECK: .byte 0 ; 0x0
+; CHECK: test3
+; CHECK: adrp x[[REG3:[0-9]+]], lCPI2_0 at PAGE
+; CHECK: ldr q[[REG0:[0-9]+]], [x[[REG3]], lCPI2_0 at PAGEOFF]
+; CHECK: movi.2d v[[REG1:[0-9]+]], #0000000000000000
+; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]]
+define <16 x i1> @test3(i1* %ptr, i32 %v) {
+bb:
+ %Shuff = shufflevector <16 x i1> zeroinitializer, <16 x i1> undef,
+ <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
+ i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
+ i32 14, i32 0>
+ ret <16 x i1> %Shuff
+}
+; CHECK: lCPI3_1:
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 1 ; 0x1
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 18 ; 0x12
+; CHECK: .byte 10 ; 0xa
+; CHECK: .byte 12 ; 0xc
+; CHECK: .byte 14 ; 0xe
+; CHECK: .byte 0 ; 0x0
+; CHECK: .byte 2 ; 0x2
+; CHECK: .byte 31 ; 0x1f
+; CHECK: .byte 6 ; 0x6
+; CHECK: .byte 30 ; 0x1e
+; CHECK: .byte 10 ; 0xa
+; CHECK: .byte 12 ; 0xc
+; CHECK: .byte 14 ; 0xe
+; CHECK: .byte 0 ; 0x0
+; CHECK: _test4:
+; CHECK: ldr q[[REG1:[0-9]+]]
+; CHECK: movi.2d v[[REG0:[0-9]+]], #0000000000000000
+; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_1 at PAGE
+; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_1 at PAGEOFF]
+; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG0]], v[[REG1]] }, v[[REG2]]
+define <16 x i1> @test4(i1* %ptr, i32 %v) {
+bb:
+ %Shuff = shufflevector <16 x i1> zeroinitializer,
+ <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
+ i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
+ <16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
+ i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
+ ret <16 x i1> %Shuff
+}
Added: llvm/trunk/test/CodeGen/ARM64/vsqrt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsqrt.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsqrt.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vsqrt.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,177 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: frecps_2s:
+;CHECK: frecps.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: frecps_4s:
+;CHECK: frecps.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @frecps_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: frecps_2d:
+;CHECK: frecps.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+
+define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind {
+;CHECK-LABEL: frsqrts_2s:
+;CHECK: frsqrts.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp2 = load <2 x float>* %B
+ %tmp3 = call <2 x float> @llvm.arm64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: frsqrts_4s:
+;CHECK: frsqrts.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = call <4 x float> @llvm.arm64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @frsqrts_2d(<2 x double>* %A, <2 x double>* %B) nounwind {
+;CHECK-LABEL: frsqrts_2d:
+;CHECK: frsqrts.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp2 = load <2 x double>* %B
+ %tmp3 = call <2 x double> @llvm.arm64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.frsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.frsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.frsqrts.v2f64(<2 x double>, <2 x double>) nounwind readnone
+
+define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind {
+;CHECK-LABEL: frecpe_2s:
+;CHECK: frecpe.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp3 = call <2 x float> @llvm.arm64.neon.frecpe.v2f32(<2 x float> %tmp1)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind {
+;CHECK-LABEL: frecpe_4s:
+;CHECK: frecpe.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp3 = call <4 x float> @llvm.arm64.neon.frecpe.v4f32(<4 x float> %tmp1)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind {
+;CHECK-LABEL: frecpe_2d:
+;CHECK: frecpe.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp3 = call <2 x double> @llvm.arm64.neon.frecpe.v2f64(<2 x double> %tmp1)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.frecpe.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.frecpe.v4f32(<4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.frecpe.v2f64(<2 x double>) nounwind readnone
+
+define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind {
+;CHECK-LABEL: frsqrte_2s:
+;CHECK: frsqrte.2s
+ %tmp1 = load <2 x float>* %A
+ %tmp3 = call <2 x float> @llvm.arm64.neon.frsqrte.v2f32(<2 x float> %tmp1)
+ ret <2 x float> %tmp3
+}
+
+define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind {
+;CHECK-LABEL: frsqrte_4s:
+;CHECK: frsqrte.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp3 = call <4 x float> @llvm.arm64.neon.frsqrte.v4f32(<4 x float> %tmp1)
+ ret <4 x float> %tmp3
+}
+
+define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind {
+;CHECK-LABEL: frsqrte_2d:
+;CHECK: frsqrte.2d
+ %tmp1 = load <2 x double>* %A
+ %tmp3 = call <2 x double> @llvm.arm64.neon.frsqrte.v2f64(<2 x double> %tmp1)
+ ret <2 x double> %tmp3
+}
+
+declare <2 x float> @llvm.arm64.neon.frsqrte.v2f32(<2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm64.neon.frsqrte.v4f32(<4 x float>) nounwind readnone
+declare <2 x double> @llvm.arm64.neon.frsqrte.v2f64(<2 x double>) nounwind readnone
+
+define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: urecpe_2s:
+;CHECK: urecpe.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.urecpe.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @urecpe_4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: urecpe_4s:
+;CHECK: urecpe.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.urecpe.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp3
+}
+
+declare <2 x i32> @llvm.arm64.neon.urecpe.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone
+
+define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind {
+;CHECK-LABEL: ursqrte_2s:
+;CHECK: ursqrte.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
+ ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @ursqrte_4s(<4 x i32>* %A) nounwind {
+;CHECK-LABEL: ursqrte_4s:
+;CHECK: ursqrte.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp3 = call <4 x i32> @llvm.arm64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
+ ret <4 x i32> %tmp3
+}
+
+declare <2 x i32> @llvm.arm64.neon.ursqrte.v2i32(<2 x i32>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.ursqrte.v4i32(<4 x i32>) nounwind readnone
+
+define float @f1(float %a, float %b) nounwind readnone optsize ssp {
+; CHECK-LABEL: f1:
+; CHECK: frsqrts s0, s0, s1
+; CHECK-NEXT: ret
+ %vrsqrtss.i = tail call float @llvm.arm64.neon.frsqrts.f32(float %a, float %b) nounwind
+ ret float %vrsqrtss.i
+}
+
+define double @f2(double %a, double %b) nounwind readnone optsize ssp {
+; CHECK-LABEL: f2:
+; CHECK: frsqrts d0, d0, d1
+; CHECK-NEXT: ret
+ %vrsqrtsd.i = tail call double @llvm.arm64.neon.frsqrts.f64(double %a, double %b) nounwind
+ ret double %vrsqrtsd.i
+}
+
+declare double @llvm.arm64.neon.frsqrts.f64(double, double) nounwind readnone
+declare float @llvm.arm64.neon.frsqrts.f32(float, float) nounwind readnone
Added: llvm/trunk/test/CodeGen/ARM64/vsra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsra.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsra.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vsra.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,142 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: vsras8:
+;CHECK: ssra.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: vsras16:
+;CHECK: ssra.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: vsras32:
+;CHECK: ssra.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 >
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: vsraQs8:
+;CHECK: ssra.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: vsraQs16:
+;CHECK: ssra.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: vsraQs32:
+;CHECK: ssra.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: vsraQs64:
+;CHECK: ssra.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 >
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: vsrau8:
+;CHECK: usra.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ %tmp4 = add <8 x i8> %tmp1, %tmp3
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: vsrau16:
+;CHECK: usra.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 >
+ %tmp4 = add <4 x i16> %tmp1, %tmp3
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: vsrau32:
+;CHECK: usra.2s
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 >
+ %tmp4 = add <2 x i32> %tmp1, %tmp3
+ ret <2 x i32> %tmp4
+}
+
+
+define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: vsraQu8:
+;CHECK: usra.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
+ %tmp4 = add <16 x i8> %tmp1, %tmp3
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: vsraQu16:
+;CHECK: usra.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
+ %tmp4 = add <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: vsraQu32:
+;CHECK: usra.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 >
+ %tmp4 = add <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: vsraQu64:
+;CHECK: usra.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 >
+ %tmp4 = add <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
Added: llvm/trunk/test/CodeGen/ARM64/vsub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/vsub.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/vsub.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/vsub.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,417 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: subhn8b:
+;CHECK: subhn.8b
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: subhn4h:
+;CHECK: subhn.4h
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @subhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: subhn2s:
+;CHECK: subhn.2s
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @subhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
+;CHECK-LABEL: subhn2_16b:
+;CHECK: subhn.8b
+;CHECK-NEXT: subhn2.16b
+ %vsubhn2.i = tail call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
+ %vsubhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
+ %res = shufflevector <8 x i8> %vsubhn2.i, <8 x i8> %vsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @subhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
+;CHECK-LABEL: subhn2_8h:
+;CHECK: subhn.4h
+;CHECK-NEXT: subhn2.8h
+ %vsubhn2.i = tail call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
+ %vsubhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
+ %res = shufflevector <4 x i16> %vsubhn2.i, <4 x i16> %vsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @subhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
+;CHECK-LABEL: subhn2_4s:
+;CHECK: subhn.2s
+;CHECK-NEXT: subhn2.4s
+ %vsubhn2.i = tail call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
+ %vsubhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
+ %res = shufflevector <2 x i32> %vsubhn2.i, <2 x i32> %vsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+declare <2 x i32> @llvm.arm64.neon.subhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.subhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.subhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: rsubhn8b:
+;CHECK: rsubhn.8b
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
+ ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: rsubhn4h:
+;CHECK: rsubhn.4h
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
+ ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @rsubhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind {
+;CHECK-LABEL: rsubhn2s:
+;CHECK: rsubhn.2s
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i64>* %B
+ %tmp3 = call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
+ ret <2 x i32> %tmp3
+}
+
+define <16 x i8> @rsubhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind {
+;CHECK-LABEL: rsubhn2_16b:
+;CHECK: rsubhn.8b
+;CHECK-NEXT: rsubhn2.16b
+ %vrsubhn2.i = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
+ %vrsubhn_high2.i = tail call <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
+ %res = shufflevector <8 x i8> %vrsubhn2.i, <8 x i8> %vrsubhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @rsubhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind {
+;CHECK-LABEL: rsubhn2_8h:
+;CHECK: rsubhn.4h
+;CHECK-NEXT: rsubhn2.8h
+ %vrsubhn2.i = tail call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
+ %vrsubhn_high3.i = tail call <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind
+ %res = shufflevector <4 x i16> %vrsubhn2.i, <4 x i16> %vrsubhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @rsubhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind {
+;CHECK-LABEL: rsubhn2_4s:
+;CHECK: rsubhn.2s
+;CHECK-NEXT: rsubhn2.4s
+ %vrsubhn2.i = tail call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
+ %vrsubhn_high3.i = tail call <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind
+ %res = shufflevector <2 x i32> %vrsubhn2.i, <2 x i32> %vrsubhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %res
+}
+
+declare <2 x i32> @llvm.arm64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
+declare <4 x i16> @llvm.arm64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+declare <8 x i8> @llvm.arm64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+
+define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: ssubl8h:
+;CHECK: ssubl.8h
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
+ %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+ %tmp5 = sub <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: ssubl4s:
+;CHECK: ssubl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
+ %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: ssubl2d:
+;CHECK: ssubl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
+ %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: ssubl2_8h:
+;CHECK: ssubl2.8h
+ %tmp1 = load <16 x i8>* %A
+ %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext1 = sext <8 x i8> %high1 to <8 x i16>
+
+ %tmp2 = load <16 x i8>* %B
+ %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext2 = sext <8 x i8> %high2 to <8 x i16>
+
+ %res = sub <8 x i16> %ext1, %ext2
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: ssubl2_4s:
+;CHECK: ssubl2.4s
+ %tmp1 = load <8 x i16>* %A
+ %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext1 = sext <4 x i16> %high1 to <4 x i32>
+
+ %tmp2 = load <8 x i16>* %B
+ %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext2 = sext <4 x i16> %high2 to <4 x i32>
+
+ %res = sub <4 x i32> %ext1, %ext2
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: ssubl2_2d:
+;CHECK: ssubl2.2d
+ %tmp1 = load <4 x i32>* %A
+ %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext1 = sext <2 x i32> %high1 to <2 x i64>
+
+ %tmp2 = load <4 x i32>* %B
+ %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext2 = sext <2 x i32> %high2 to <2 x i64>
+
+ %res = sub <2 x i64> %ext1, %ext2
+ ret <2 x i64> %res
+}
+
+define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: usubl8h:
+;CHECK: usubl.8h
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
+ %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+ %tmp5 = sub <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: usubl4s:
+;CHECK: usubl.4s
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
+ %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+ %tmp5 = sub <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: usubl2d:
+;CHECK: usubl.2d
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
+ %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+ %tmp5 = sub <2 x i64> %tmp3, %tmp4
+ ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: usubl2_8h:
+;CHECK: usubl2.8h
+ %tmp1 = load <16 x i8>* %A
+ %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext1 = zext <8 x i8> %high1 to <8 x i16>
+
+ %tmp2 = load <16 x i8>* %B
+ %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext2 = zext <8 x i8> %high2 to <8 x i16>
+
+ %res = sub <8 x i16> %ext1, %ext2
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: usubl2_4s:
+;CHECK: usubl2.4s
+ %tmp1 = load <8 x i16>* %A
+ %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext1 = zext <4 x i16> %high1 to <4 x i32>
+
+ %tmp2 = load <8 x i16>* %B
+ %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext2 = zext <4 x i16> %high2 to <4 x i32>
+
+ %res = sub <4 x i32> %ext1, %ext2
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: usubl2_2d:
+;CHECK: usubl2.2d
+ %tmp1 = load <4 x i32>* %A
+ %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext1 = zext <2 x i32> %high1 to <2 x i64>
+
+ %tmp2 = load <4 x i32>* %B
+ %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext2 = zext <2 x i32> %high2 to <2 x i64>
+
+ %res = sub <2 x i64> %ext1, %ext2
+ ret <2 x i64> %res
+}
+
+define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: ssubw8h:
+;CHECK: ssubw.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
+ %tmp4 = sub <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: ssubw4s:
+;CHECK: ssubw.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
+ %tmp4 = sub <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: ssubw2d:
+;CHECK: ssubw.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
+ %tmp4 = sub <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: ssubw2_8h:
+;CHECK: ssubw2.8h
+ %tmp1 = load <8 x i16>* %A
+
+ %tmp2 = load <16 x i8>* %B
+ %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext2 = sext <8 x i8> %high2 to <8 x i16>
+
+ %res = sub <8 x i16> %tmp1, %ext2
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: ssubw2_4s:
+;CHECK: ssubw2.4s
+ %tmp1 = load <4 x i32>* %A
+
+ %tmp2 = load <8 x i16>* %B
+ %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext2 = sext <4 x i16> %high2 to <4 x i32>
+
+ %res = sub <4 x i32> %tmp1, %ext2
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: ssubw2_2d:
+;CHECK: ssubw2.2d
+ %tmp1 = load <2 x i64>* %A
+
+ %tmp2 = load <4 x i32>* %B
+ %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext2 = sext <2 x i32> %high2 to <2 x i64>
+
+ %res = sub <2 x i64> %tmp1, %ext2
+ ret <2 x i64> %res
+}
+
+define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: usubw8h:
+;CHECK: usubw.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
+ %tmp4 = sub <8 x i16> %tmp1, %tmp3
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: usubw4s:
+;CHECK: usubw.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
+ %tmp4 = sub <4 x i32> %tmp1, %tmp3
+ ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind {
+;CHECK-LABEL: usubw2d:
+;CHECK: usubw.2d
+ %tmp1 = load <2 x i64>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
+ %tmp4 = sub <2 x i64> %tmp1, %tmp3
+ ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: usubw2_8h:
+;CHECK: usubw2.8h
+ %tmp1 = load <8 x i16>* %A
+
+ %tmp2 = load <16 x i8>* %B
+ %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %ext2 = zext <8 x i8> %high2 to <8 x i16>
+
+ %res = sub <8 x i16> %tmp1, %ext2
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: usubw2_4s:
+;CHECK: usubw2.4s
+ %tmp1 = load <4 x i32>* %A
+
+ %tmp2 = load <8 x i16>* %B
+ %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+ %ext2 = zext <4 x i16> %high2 to <4 x i32>
+
+ %res = sub <4 x i32> %tmp1, %ext2
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @usubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: usubw2_2d:
+;CHECK: usubw2.2d
+ %tmp1 = load <2 x i64>* %A
+
+ %tmp2 = load <4 x i32>* %B
+ %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+ %ext2 = zext <2 x i32> %high2 to <2 x i64>
+
+ %res = sub <2 x i64> %tmp1, %ext2
+ ret <2 x i64> %res
+}
Added: llvm/trunk/test/CodeGen/ARM64/weak-reference.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/weak-reference.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/weak-reference.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/weak-reference.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
+
+ at x = extern_weak global i32
+
+define i32 @fn() nounwind ssp {
+; CHECK-LABEL: fn:
+; CHECK: .weak_reference
+ %val = load i32* @x, align 4
+ ret i32 %val
+}
Added: llvm/trunk/test/CodeGen/ARM64/xaluo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/xaluo.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/xaluo.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/xaluo.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,524 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s
+
+;
+; Get the actual value of the overflow bit.
+;
+define i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: saddo.i32
+; CHECK: adds w8, w0, w1
+; CHECK-NEXT: csinc w0, wzr, wzr, vc
+ %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: saddo.i64
+; CHECK: adds x8, x0, x1
+; CHECK-NEXT: csinc w0, wzr, wzr, vc
+ %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: uaddo.i32
+; CHECK: adds w8, w0, w1
+; CHECK-NEXT: csinc w0, wzr, wzr, cc
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: uaddo.i64
+; CHECK: adds x8, x0, x1
+; CHECK-NEXT: csinc w0, wzr, wzr, cc
+ %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+define i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: ssubo.i32
+; CHECK: subs w8, w0, w1
+; CHECK-NEXT: csinc w0, wzr, wzr, vc
+ %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: ssubo.i64
+; CHECK: subs x8, x0, x1
+; CHECK-NEXT: csinc w0, wzr, wzr, vc
+ %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: usubo.i32
+; CHECK: subs w8, w0, w1
+; CHECK-NEXT: csinc w0, wzr, wzr, cs
+ %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: usubo.i64
+; CHECK: subs x8, x0, x1
+; CHECK-NEXT: csinc w0, wzr, wzr, cs
+ %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+define i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: smulo.i32
+; CHECK: smull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: cmp w9, w8, asr #31
+; CHECK-NEXT: csinc w0, wzr, wzr, eq
+ %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: smulo.i64
+; CHECK: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: cmp x9, x8, asr #63
+; CHECK-NEXT: csinc w0, wzr, wzr, eq
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+define i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
+entry:
+; CHECK-LABEL: umulo.i32
+; CHECK: umull x8, w0, w1
+; CHECK-NEXT: cmp xzr, x8, lsr #32
+; CHECK-NEXT: csinc w0, wzr, wzr, eq
+ %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ store i32 %val, i32* %res
+ ret i1 %obit
+}
+
+define i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
+entry:
+; CHECK-LABEL: umulo.i64
+; CHECK: umulh x8, x0, x1
+; CHECK-NEXT: cmp xzr, x8
+; CHECK-NEXT: csinc w8, wzr, wzr, eq
+; CHECK-NEXT: mul x9, x0, x1
+ %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ store i64 %val, i64* %res
+ ret i1 %obit
+}
+
+
+;
+; Check the use of the overflow bit in combination with a select instruction.
+;
+define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: saddo.select.i32
+; CHECK: cmn w0, w1
+; CHECK-NEXT: csel w0, w0, w1, vs
+ %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: saddo.select.i64
+; CHECK: cmn x0, x1
+; CHECK-NEXT: csel x0, x0, x1, vs
+ %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: uaddo.select.i32
+; CHECK: cmn w0, w1
+; CHECK-NEXT: csel w0, w0, w1, cs
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: uaddo.select.i64
+; CHECK: cmn x0, x1
+; CHECK-NEXT: csel x0, x0, x1, cs
+ %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: ssubo.select.i32
+; CHECK: cmp w0, w1
+; CHECK-NEXT: csel w0, w0, w1, vs
+ %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: ssubo.select.i64
+; CHECK: cmp x0, x1
+; CHECK-NEXT: csel x0, x0, x1, vs
+ %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: usubo.select.i32
+; CHECK: cmp w0, w1
+; CHECK-NEXT: csel w0, w0, w1, cc
+ %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: usubo.select.i64
+; CHECK: cmp x0, x1
+; CHECK-NEXT: csel x0, x0, x1, cc
+ %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: smulo.select.i32
+; CHECK: smull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: cmp w9, w8, asr #31
+; CHECK-NEXT: csel w0, w0, w1, ne
+ %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: smulo.select.i64
+; CHECK: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: cmp x9, x8, asr #63
+; CHECK-NEXT: csel x0, x0, x1, ne
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: umulo.select.i32
+; CHECK: umull x8, w0, w1
+; CHECK-NEXT: cmp xzr, x8, lsr #32
+; CHECK-NEXT: csel w0, w0, w1, ne
+ %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
+ %obit = extractvalue {i32, i1} %t, 1
+ %ret = select i1 %obit, i32 %v1, i32 %v2
+ ret i32 %ret
+}
+
+define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: umulo.select.i64
+; CHECK: umulh x8, x0, x1
+; CHECK-NEXT: cmp xzr, x8
+; CHECK-NEXT: csel x0, x0, x1, ne
+ %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
+ %obit = extractvalue {i64, i1} %t, 1
+ %ret = select i1 %obit, i64 %v1, i64 %v2
+ ret i64 %ret
+}
+
+
+;
+; Check the use of the overflow bit in combination with a branch instruction.
+;
+define i1 @saddo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: saddo.br.i32
+; CHECK: cmn w0, w1
+; CHECK-NEXT: b.vc
+ %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @saddo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: saddo.br.i64
+; CHECK: cmn x0, x1
+; CHECK-NEXT: b.vc
+ %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: uaddo.br.i32
+; CHECK: cmn w0, w1
+; CHECK-NEXT: b.cc
+ %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: uaddo.br.i64
+; CHECK: cmn x0, x1
+; CHECK-NEXT: b.cc
+ %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: ssubo.br.i32
+; CHECK: cmp w0, w1
+; CHECK-NEXT: b.vc
+ %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: ssubo.br.i64
+; CHECK: cmp x0, x1
+; CHECK-NEXT: b.vc
+ %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @usubo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: usubo.br.i32
+; CHECK: cmp w0, w1
+; CHECK-NEXT: b.cs
+ %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @usubo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: usubo.br.i64
+; CHECK: cmp x0, x1
+; CHECK-NEXT: b.cs
+ %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @smulo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: smulo.br.i32
+; CHECK: smull x8, w0, w1
+; CHECK-NEXT: lsr x9, x8, #32
+; CHECK-NEXT: cmp w9, w8, asr #31
+; CHECK-NEXT: b.eq
+ %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @smulo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: smulo.br.i64
+; CHECK: mul x8, x0, x1
+; CHECK-NEXT: smulh x9, x0, x1
+; CHECK-NEXT: cmp x9, x8, asr #63
+; CHECK-NEXT: b.eq
+ %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @umulo.br.i32(i32 %v1, i32 %v2) {
+entry:
+; CHECK-LABEL: umulo.br.i32
+; CHECK: umull x8, w0, w1
+; CHECK-NEXT: cmp xzr, x8, lsr #32
+; CHECK-NEXT: b.eq
+ %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
+ %val = extractvalue {i32, i1} %t, 0
+ %obit = extractvalue {i32, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+define i1 @umulo.br.i64(i64 %v1, i64 %v2) {
+entry:
+; CHECK-LABEL: umulo.br.i64
+; CHECK: umulh x8, x0, x1
+; CHECK-NEXT: cbz
+ %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
+ %val = extractvalue {i64, i1} %t, 0
+ %obit = extractvalue {i64, i1} %t, 1
+ br i1 %obit, label %overflow, label %continue
+
+overflow:
+ ret i1 false
+
+continue:
+ ret i1 true
+}
+
+declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
+declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
+declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
+declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
+declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
+declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
+declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
+
Added: llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/zero-cycle-regmov.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
+; rdar://12254953
+
+define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind ssp {
+entry:
+; CHECK-LABEL: t:
+; CHECK: mov x0, [[REG1:x[0-9]+]]
+; CHECK: mov x1, [[REG2:x[0-9]+]]
+; CHECK: bl _foo
+; CHECK: mov x0, [[REG1]]
+; CHECK: mov x1, [[REG2]]
+ %call = call i32 @foo(i32 %c, i32 %d) nounwind
+ %call1 = call i32 @foo(i32 %c, i32 %d) nounwind
+ unreachable
+}
+
+declare i32 @foo(i32, i32)
Added: llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/zero-cycle-zeroing.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,49 @@
+; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
+; rdar://11481771
+; rdar://13713797
+
+define void @t1() nounwind ssp {
+entry:
+; CHECK-LABEL: t1:
+; CHECK-NOT: fmov
+; CHECK: movi.2d v0, #0000000000000000
+; CHECK: movi.2d v1, #0000000000000000
+; CHECK: movi.2d v2, #0000000000000000
+; CHECK: movi.2d v3, #0000000000000000
+ tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind
+ ret void
+}
+
+define void @t2() nounwind ssp {
+entry:
+; CHECK-LABEL: t2:
+; CHECK-NOT: mov w0, wzr
+; CHECK: movz w0, #0
+; CHECK: movz w1, #0
+ tail call void @bari(i32 0, i32 0) nounwind
+ ret void
+}
+
+define void @t3() nounwind ssp {
+entry:
+; CHECK-LABEL: t3:
+; CHECK-NOT: mov x0, xzr
+; CHECK: movz x0, #0
+; CHECK: movz x1, #0
+ tail call void @barl(i64 0, i64 0) nounwind
+ ret void
+}
+
+define void @t4() nounwind ssp {
+; CHECK-LABEL: t4:
+; CHECK-NOT: fmov
+; CHECK: movi.2d v0, #0000000000000000
+; CHECK: movi.2d v1, #0000000000000000
+ tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
+ ret void
+}
+
+declare void @bar(double, double, double, double)
+declare void @bari(i32, i32)
+declare void @barl(i64, i64)
+declare void @barf(float, float)
Added: llvm/trunk/test/CodeGen/ARM64/zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zext.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zext.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/zext.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm64 | FileCheck %s
+
+define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK-LABEL: foo:
+; CHECK: add w0, w1, w0
+; CHECK: ret
+ %add = add i32 %b, %a
+ %conv = zext i32 %add to i64
+ ret i64 %conv
+}
Added: llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/zextload-unscaled.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,40 @@
+; RUN: llc -march=arm64 < %s | FileCheck %s
+
+ at var32 = global i32 0
+
+define void @test_zextloadi1_unscaled(i1* %base) {
+; CHECK-LABEL: test_zextloadi1_unscaled:
+; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
+
+ %addr = getelementptr i1* %base, i32 -7
+ %val = load i1* %addr, align 1
+
+ %extended = zext i1 %val to i32
+ store i32 %extended, i32* @var32, align 4
+ ret void
+}
+
+define void @test_zextloadi8_unscaled(i8* %base) {
+; CHECK-LABEL: test_zextloadi8_unscaled:
+; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7]
+
+ %addr = getelementptr i8* %base, i32 -7
+ %val = load i8* %addr, align 1
+
+ %extended = zext i8 %val to i32
+ store i32 %extended, i32* @var32, align 4
+ ret void
+}
+
+define void @test_zextloadi16_unscaled(i16* %base) {
+; CHECK-LABEL: test_zextloadi16_unscaled:
+; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14]
+
+ %addr = getelementptr i16* %base, i32 -7
+ %val = load i16* %addr, align 2
+
+ %extended = zext i16 %val to i32
+ store i32 %extended, i32* @var32, align 4
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/ARM64/zip.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/zip.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM64/zip.ll (added)
+++ llvm/trunk/test/CodeGen/ARM64/zip.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,107 @@
+; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+
+define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: vzipi8:
+;CHECK: zip1.8b
+;CHECK: zip2.8b
+;CHECK-NEXT: add.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+;CHECK-LABEL: vzipi16:
+;CHECK: zip1.4h
+;CHECK: zip2.4h
+;CHECK-NEXT: add.4h
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = add <4 x i16> %tmp3, %tmp4
+ ret <4 x i16> %tmp5
+}
+
+define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: vzipQi8:
+;CHECK: zip1.16b
+;CHECK: zip2.16b
+;CHECK-NEXT: add.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+;CHECK-LABEL: vzipQi16:
+;CHECK: zip1.8h
+;CHECK: zip2.8h
+;CHECK-NEXT: add.8h
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+ %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
+ %tmp5 = add <8 x i16> %tmp3, %tmp4
+ ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+;CHECK-LABEL: vzipQi32:
+;CHECK: zip1.4s
+;CHECK: zip2.4s
+;CHECK-NEXT: add.4s
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = add <4 x i32> %tmp3, %tmp4
+ ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
+;CHECK-LABEL: vzipQf:
+;CHECK: zip1.4s
+;CHECK: zip2.4s
+;CHECK-NEXT: fadd.4s
+ %tmp1 = load <4 x float>* %A
+ %tmp2 = load <4 x float>* %B
+ %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
+ %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
+ %tmp5 = fadd <4 x float> %tmp3, %tmp4
+ ret <4 x float> %tmp5
+}
+
+; Undef shuffle indices should not prevent matching to VZIP:
+
+define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+;CHECK-LABEL: vzipi8_undef:
+;CHECK: zip1.8b
+;CHECK: zip2.8b
+;CHECK-NEXT: add.8b
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11>
+ %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15>
+ %tmp5 = add <8 x i8> %tmp3, %tmp4
+ ret <8 x i8> %tmp5
+}
+
+define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+;CHECK-LABEL: vzipQi8_undef:
+;CHECK: zip1.16b
+;CHECK: zip2.16b
+;CHECK-NEXT: add.16b
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+ %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31>
+ %tmp5 = add <16 x i8> %tmp3, %tmp4
+ ret <16 x i8> %tmp5
+}
Added: llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/DebugInfo/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,4 @@
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
+
Added: llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll (added)
+++ llvm/trunk/test/DebugInfo/ARM64/struct_by_value.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,68 @@
+; A by-value struct is a register-indirect value (breg).
+; RUN: llc %s -filetype=asm -o - | FileCheck %s
+
+; CHECK: DW_OP_breg0
+
+; rdar://problem/13658587
+;
+; Generated from
+;
+; struct five
+; {
+; int a;
+; int b;
+; int c;
+; int d;
+; int e;
+; };
+;
+; int
+; return_five_int (struct five f)
+; {
+; return f.a;
+; }
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
+target triple = "arm64-apple-ios3.0.0"
+
+%struct.five = type { i32, i32, i32, i32, i32 }
+
+; Function Attrs: nounwind ssp
+define i32 @return_five_int(%struct.five* %f) #0 {
+entry:
+ call void @llvm.dbg.declare(metadata !{%struct.five* %f}, metadata !17), !dbg !18
+ %a = getelementptr inbounds %struct.five* %f, i32 0, i32 0, !dbg !19
+ %0 = load i32* %a, align 4, !dbg !19
+ ret i32 %0, !dbg !19
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+attributes #0 = { nounwind ssp }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!16, !20}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"LLVM version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [struct_by_value.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"struct_by_value.c", metadata !""}
+!2 = metadata !{}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"return_five_int", metadata !"return_five_int", metadata !"", i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%struct.five*)* @return_five_int, null, null, metadata !2, i32 14} ; [ DW_TAG_subprogram ] [line 13] [def] [scope 14] [return_five_int]
+!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [struct_by_value.c]
+!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !9}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786451, metadata !1, null, metadata !"five", i32 1, i64 160, i64 32, i32 0, i32 0, null, metadata !10, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [five] [line 1, size 160, align 32, offset 0] [def] [from ]
+!10 = metadata !{metadata !11, metadata !12, metadata !13, metadata !14, metadata !15}
+!11 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"a", i32 3, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_member ] [a] [line 3, size 32, align 32, offset 0] [from int]
+!12 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"b", i32 4, i64 32, i64 32, i64 32, i32 0, metadata !8} ; [ DW_TAG_member ] [b] [line 4, size 32, align 32, offset 32] [from int]
+!13 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"c", i32 5, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] [c] [line 5, size 32, align 32, offset 64] [from int]
+!14 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"d", i32 6, i64 32, i64 32, i64 96, i32 0, metadata !8} ; [ DW_TAG_member ] [d] [line 6, size 32, align 32, offset 96] [from int]
+!15 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"e", i32 7, i64 32, i64 32, i64 128, i32 0, metadata !8} ; [ DW_TAG_member ] [e] [line 7, size 32, align 32, offset 128] [from int]
+!16 = metadata !{i32 2, metadata !"Dwarf Version", i32 2}
+!17 = metadata !{i32 786689, metadata !4, metadata !"f", metadata !5, i32 16777229, metadata !9, i32 8192, i32 0} ; [ DW_TAG_arg_variable ] [f] [line 13]
+!18 = metadata !{i32 13, i32 0, metadata !4, null}
+!19 = metadata !{i32 16, i32 0, metadata !4, null}
+!20 = metadata !{i32 1, metadata !"Debug Info Version", i32 1}
Added: llvm/trunk/test/MC/ARM64/advsimd.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/advsimd.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/advsimd.s (added)
+++ llvm/trunk/test/MC/ARM64/advsimd.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,1997 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s
+
+foo:
+
+ abs.8b v0, v0
+ abs.16b v0, v0
+ abs.4h v0, v0
+ abs.8h v0, v0
+ abs.2s v0, v0
+ abs.4s v0, v0
+
+; CHECK: abs.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x0e]
+; CHECK: abs.16b v0, v0 ; encoding: [0x00,0xb8,0x20,0x4e]
+; CHECK: abs.4h v0, v0 ; encoding: [0x00,0xb8,0x60,0x0e]
+; CHECK: abs.8h v0, v0 ; encoding: [0x00,0xb8,0x60,0x4e]
+; CHECK: abs.2s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x0e]
+; CHECK: abs.4s v0, v0 ; encoding: [0x00,0xb8,0xa0,0x4e]
+
+ add.8b v0, v0, v0
+ add.16b v0, v0, v0
+ add.4h v0, v0, v0
+ add.8h v0, v0, v0
+ add.2s v0, v0, v0
+ add.4s v0, v0, v0
+ add.2d v0, v0, v0
+
+; CHECK: add.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x0e]
+; CHECK: add.16b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x4e]
+; CHECK: add.4h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x0e]
+; CHECK: add.8h v0, v0, v0 ; encoding: [0x00,0x84,0x60,0x4e]
+; CHECK: add.2s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x0e]
+; CHECK: add.4s v0, v0, v0 ; encoding: [0x00,0x84,0xa0,0x4e]
+; CHECK: add.2d v0, v0, v0 ; encoding: [0x00,0x84,0xe0,0x4e]
+
+ add d1, d2, d3
+
+; CHECK: add d1, d2, d3 ; encoding: [0x41,0x84,0xe3,0x5e]
+
+ addhn.8b v0, v0, v0
+ addhn2.16b v0, v0, v0
+ addhn.4h v0, v0, v0
+ addhn2.8h v0, v0, v0
+ addhn.2s v0, v0, v0
+ addhn2.4s v0, v0, v0
+
+; CHECK: addhn.8b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x0e]
+; CHECK: addhn2.16b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x4e]
+; CHECK: addhn.4h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x0e]
+; CHECK: addhn2.8h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x4e]
+; CHECK: addhn.2s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x0e]
+; CHECK: addhn2.4s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x4e]
+
+ addp.8b v0, v0, v0
+ addp.16b v0, v0, v0
+ addp.4h v0, v0, v0
+ addp.8h v0, v0, v0
+ addp.2s v0, v0, v0
+ addp.4s v0, v0, v0
+ addp.2d v0, v0, v0
+
+; CHECK: addp.8b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x0e]
+; CHECK: addp.16b v0, v0, v0 ; encoding: [0x00,0xbc,0x20,0x4e]
+; CHECK: addp.4h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x0e]
+; CHECK: addp.8h v0, v0, v0 ; encoding: [0x00,0xbc,0x60,0x4e]
+; CHECK: addp.2s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x0e]
+; CHECK: addp.4s v0, v0, v0 ; encoding: [0x00,0xbc,0xa0,0x4e]
+; CHECK: addp.2d v0, v0, v0 ; encoding: [0x00,0xbc,0xe0,0x4e]
+
+ addp.2d d0, v0
+
+; CHECK: addp.2d d0, v0 ; encoding: [0x00,0xb8,0xf1,0x5e]
+
+ addv.8b b0, v0
+ addv.16b b0, v0
+ addv.4h h0, v0
+ addv.8h h0, v0
+ addv.4s s0, v0
+
+; CHECK: addv.8b b0, v0 ; encoding: [0x00,0xb8,0x31,0x0e]
+; CHECK: addv.16b b0, v0 ; encoding: [0x00,0xb8,0x31,0x4e]
+; CHECK: addv.4h h0, v0 ; encoding: [0x00,0xb8,0x71,0x0e]
+; CHECK: addv.8h h0, v0 ; encoding: [0x00,0xb8,0x71,0x4e]
+; CHECK: addv.4s s0, v0 ; encoding: [0x00,0xb8,0xb1,0x4e]
+
+
+; INS/DUP
+ dup.2d v0, x3
+ dup.4s v0, w3
+ dup.2s v0, w3
+ dup.8h v0, w3
+ dup.4h v0, w3
+ dup.16b v0, w3
+ dup.8b v0, w3
+
+ dup v1.2d, x3
+ dup v2.4s, w4
+ dup v3.2s, w5
+ dup v4.8h, w6
+ dup v5.4h, w7
+ dup v6.16b, w8
+ dup v7.8b, w9
+
+; CHECK: dup.2d v0, x3 ; encoding: [0x60,0x0c,0x08,0x4e]
+; CHECK: dup.4s v0, w3 ; encoding: [0x60,0x0c,0x04,0x4e]
+; CHECK: dup.2s v0, w3 ; encoding: [0x60,0x0c,0x04,0x0e]
+; CHECK: dup.8h v0, w3 ; encoding: [0x60,0x0c,0x02,0x4e]
+; CHECK: dup.4h v0, w3 ; encoding: [0x60,0x0c,0x02,0x0e]
+; CHECK: dup.16b v0, w3 ; encoding: [0x60,0x0c,0x01,0x4e]
+; CHECK: dup.8b v0, w3 ; encoding: [0x60,0x0c,0x01,0x0e]
+
+; CHECK: dup.2d v1, x3 ; encoding: [0x61,0x0c,0x08,0x4e]
+; CHECK: dup.4s v2, w4 ; encoding: [0x82,0x0c,0x04,0x4e]
+; CHECK: dup.2s v3, w5 ; encoding: [0xa3,0x0c,0x04,0x0e]
+; CHECK: dup.8h v4, w6 ; encoding: [0xc4,0x0c,0x02,0x4e]
+; CHECK: dup.4h v5, w7 ; encoding: [0xe5,0x0c,0x02,0x0e]
+; CHECK: dup.16b v6, w8 ; encoding: [0x06,0x0d,0x01,0x4e]
+; CHECK: dup.8b v7, w9 ; encoding: [0x27,0x0d,0x01,0x0e]
+
+ dup.2d v0, v3[1]
+ dup.2s v0, v3[1]
+ dup.4s v0, v3[1]
+ dup.4h v0, v3[1]
+ dup.8h v0, v3[1]
+ dup.8b v0, v3[1]
+ dup.16b v0, v3[1]
+
+ dup v7.2d, v9.d[1]
+ dup v6.2s, v8.s[1]
+ dup v5.4s, v7.s[2]
+ dup v4.4h, v6.h[3]
+ dup v3.8h, v5.h[4]
+ dup v2.8b, v4.b[5]
+ dup v1.16b, v3.b[6]
+
+; CHECK: dup.2d v0, v3[1] ; encoding: [0x60,0x04,0x18,0x4e]
+; CHECK: dup.2s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x0e]
+; CHECK: dup.4s v0, v3[1] ; encoding: [0x60,0x04,0x0c,0x4e]
+; CHECK: dup.4h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x0e]
+; CHECK: dup.8h v0, v3[1] ; encoding: [0x60,0x04,0x06,0x4e]
+; CHECK: dup.8b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x0e]
+; CHECK: dup.16b v0, v3[1] ; encoding: [0x60,0x04,0x03,0x4e]
+
+; CHECK: dup.2d v7, v9[1] ; encoding: [0x27,0x05,0x18,0x4e]
+; CHECK: dup.2s v6, v8[1] ; encoding: [0x06,0x05,0x0c,0x0e]
+; CHECK: dup.4s v5, v7[2] ; encoding: [0xe5,0x04,0x14,0x4e]
+; CHECK: dup.4h v4, v6[3] ; encoding: [0xc4,0x04,0x0e,0x0e]
+; CHECK: dup.8h v3, v5[4] ; encoding: [0xa3,0x04,0x12,0x4e]
+; CHECK: dup.8b v2, v4[5] ; encoding: [0x82,0x04,0x0b,0x0e]
+; CHECK: dup.16b v1, v3[6] ; encoding: [0x61,0x04,0x0d,0x4e]
+
+ dup b3, v4[1]
+ dup h3, v4[1]
+ dup s3, v4[1]
+ dup d3, v4[1]
+ dup b3, v4.b[1]
+ dup h3, v4.h[1]
+ dup s3, v4.s[1]
+ dup d3, v4.d[1]
+
+ mov b3, v4[1]
+ mov h3, v4[1]
+ mov s3, v4[1]
+ mov d3, v4[1]
+ mov b3, v4.b[1]
+ mov h3, v4.h[1]
+ mov s3, v4.s[1]
+ mov d3, v4.d[1]
+
+; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
+; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
+; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
+; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
+; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
+; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
+; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
+; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
+
+; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
+; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
+; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
+; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
+; CHECK: mov b3, v4[1] ; encoding: [0x83,0x04,0x03,0x5e]
+; CHECK: mov h3, v4[1] ; encoding: [0x83,0x04,0x06,0x5e]
+; CHECK: mov s3, v4[1] ; encoding: [0x83,0x04,0x0c,0x5e]
+; CHECK: mov d3, v4[1] ; encoding: [0x83,0x04,0x18,0x5e]
+
+ smov.s x3, v2[2]
+ smov x3, v2.s[2]
+ umov.s w3, v2[2]
+ umov w3, v2.s[2]
+ umov.d x3, v2[1]
+ umov x3, v2.d[1]
+
+; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e]
+; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e]
+; CHECK: umov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e]
+; CHECK: umov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e]
+; CHECK: umov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e]
+; CHECK: umov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e]
+
+ ; MOV aliases for UMOV instructions above
+
+ mov.s w2, v3[3]
+ mov w5, v7.s[2]
+ mov.d x11, v13[1]
+ mov x17, v19.d[0]
+
+; CHECK: umov.s w2, v3[3] ; encoding: [0x62,0x3c,0x1c,0x0e]
+; CHECK: umov.s w5, v7[2] ; encoding: [0xe5,0x3c,0x14,0x0e]
+; CHECK: umov.d x11, v13[1] ; encoding: [0xab,0x3d,0x18,0x4e]
+; CHECK: umov.d x17, v19[0] ; encoding: [0x71,0x3e,0x08,0x4e]
+
+ ins.d v2[1], x5
+ ins.s v2[1], w5
+ ins.h v2[1], w5
+ ins.b v2[1], w5
+
+ ins v2.d[1], x5
+ ins v2.s[1], w5
+ ins v2.h[1], w5
+ ins v2.b[1], w5
+
+; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
+; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
+; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
+
+; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]
+; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]
+; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]
+
+ ins.d v2[1], v15[1]
+ ins.s v2[1], v15[1]
+ ins.h v2[1], v15[1]
+ ins.b v2[1], v15[1]
+
+ ins v2.d[1], v15.d[0]
+ ins v2.s[3], v15.s[2]
+ ins v2.h[7], v15.h[3]
+ ins v2.b[10], v15.b[5]
+
+; CHECK: ins.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]
+; CHECK: ins.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]
+; CHECK: ins.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]
+; CHECK: ins.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]
+
+; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
+; CHECK: ins.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]
+; CHECK: ins.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]
+; CHECK: ins.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]
+
+; MOV aliases for the above INS instructions.
+ mov.d v2[1], x5
+ mov.s v3[1], w6
+ mov.h v4[1], w7
+ mov.b v5[1], w8
+
+ mov v9.d[1], x2
+ mov v8.s[1], w3
+ mov v7.h[1], w4
+ mov v6.b[1], w5
+
+ mov.d v1[1], v10[1]
+ mov.s v2[1], v11[1]
+ mov.h v7[1], v12[1]
+ mov.b v8[1], v15[1]
+
+ mov v2.d[1], v15.d[0]
+ mov v7.s[3], v16.s[2]
+ mov v8.h[7], v17.h[3]
+ mov v9.b[10], v18.b[5]
+
+; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]
+; CHECK: ins.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]
+; CHECK: ins.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]
+; CHECK: ins.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]
+; CHECK: ins.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]
+; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]
+; CHECK: ins.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]
+; CHECK: ins.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]
+; CHECK: ins.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]
+; CHECK: ins.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]
+; CHECK: ins.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]
+; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]
+; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]
+; CHECK: ins.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]
+; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]
+; CHECK: ins.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]
+
+
+ and.8b v0, v0, v0
+ and.16b v0, v0, v0
+
+; CHECK: and.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x0e]
+; CHECK: and.16b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x4e]
+
+ bic.8b v0, v0, v0
+
+; CHECK: bic.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x0e]
+
+ cmeq.8b v0, v0, v0
+ cmge.8b v0, v0, v0
+ cmgt.8b v0, v0, v0
+ cmhi.8b v0, v0, v0
+ cmhs.8b v0, v0, v0
+ cmtst.8b v0, v0, v0
+ fabd.2s v0, v0, v0
+ facge.2s v0, v0, v0
+ facgt.2s v0, v0, v0
+ faddp.2s v0, v0, v0
+ fadd.2s v0, v0, v0
+ fcmeq.2s v0, v0, v0
+ fcmge.2s v0, v0, v0
+ fcmgt.2s v0, v0, v0
+ fdiv.2s v0, v0, v0
+ fmaxnmp.2s v0, v0, v0
+ fmaxnm.2s v0, v0, v0
+ fmaxp.2s v0, v0, v0
+ fmax.2s v0, v0, v0
+ fminnmp.2s v0, v0, v0
+ fminnm.2s v0, v0, v0
+ fminp.2s v0, v0, v0
+ fmin.2s v0, v0, v0
+ fmla.2s v0, v0, v0
+ fmls.2s v0, v0, v0
+ fmulx.2s v0, v0, v0
+ fmul.2s v0, v0, v0
+ fmulx d2, d3, d1
+ fmulx s2, s3, s1
+ frecps.2s v0, v0, v0
+ frsqrts.2s v0, v0, v0
+ fsub.2s v0, v0, v0
+ mla.8b v0, v0, v0
+ mls.8b v0, v0, v0
+ mul.8b v0, v0, v0
+ pmul.8b v0, v0, v0
+ saba.8b v0, v0, v0
+ sabd.8b v0, v0, v0
+ shadd.8b v0, v0, v0
+ shsub.8b v0, v0, v0
+ smaxp.8b v0, v0, v0
+ smax.8b v0, v0, v0
+ sminp.8b v0, v0, v0
+ smin.8b v0, v0, v0
+ sqadd.8b v0, v0, v0
+ sqdmulh.4h v0, v0, v0
+ sqrdmulh.4h v0, v0, v0
+ sqrshl.8b v0, v0, v0
+ sqshl.8b v0, v0, v0
+ sqsub.8b v0, v0, v0
+ srhadd.8b v0, v0, v0
+ srshl.8b v0, v0, v0
+ sshl.8b v0, v0, v0
+ sub.8b v0, v0, v0
+ uaba.8b v0, v0, v0
+ uabd.8b v0, v0, v0
+ uhadd.8b v0, v0, v0
+ uhsub.8b v0, v0, v0
+ umaxp.8b v0, v0, v0
+ umax.8b v0, v0, v0
+ uminp.8b v0, v0, v0
+ umin.8b v0, v0, v0
+ uqadd.8b v0, v0, v0
+ uqrshl.8b v0, v0, v0
+ uqshl.8b v0, v0, v0
+ uqsub.8b v0, v0, v0
+ urhadd.8b v0, v0, v0
+ urshl.8b v0, v0, v0
+ ushl.8b v0, v0, v0
+
+; CHECK: cmeq.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x2e]
+; CHECK: cmge.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x0e]
+; CHECK: cmgt.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x0e]
+; CHECK: cmhi.8b v0, v0, v0 ; encoding: [0x00,0x34,0x20,0x2e]
+; CHECK: cmhs.8b v0, v0, v0 ; encoding: [0x00,0x3c,0x20,0x2e]
+; CHECK: cmtst.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x0e]
+; CHECK: fabd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x2e]
+; CHECK: facge.2s v0, v0, v0 ; encoding: [0x00,0xec,0x20,0x2e]
+; CHECK: facgt.2s v0, v0, v0 ; encoding: [0x00,0xec,0xa0,0x2e]
+; CHECK: faddp.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x2e]
+; CHECK: fadd.2s v0, v0, v0 ; encoding: [0x00,0xd4,0x20,0x0e]
+; CHECK: fcmeq.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x0e]
+; CHECK: fcmge.2s v0, v0, v0 ; encoding: [0x00,0xe4,0x20,0x2e]
+; CHECK: fcmgt.2s v0, v0, v0 ; encoding: [0x00,0xe4,0xa0,0x2e]
+; CHECK: fdiv.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x2e]
+; CHECK: fmaxnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x2e]
+; CHECK: fmaxnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0x20,0x0e]
+; CHECK: fmaxp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x2e]
+; CHECK: fmax.2s v0, v0, v0 ; encoding: [0x00,0xf4,0x20,0x0e]
+; CHECK: fminnmp.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x2e]
+; CHECK: fminnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x0e]
+; CHECK: fminp.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x2e]
+; CHECK: fmin.2s v0, v0, v0 ; encoding: [0x00,0xf4,0xa0,0x0e]
+; CHECK: fmla.2s v0, v0, v0 ; encoding: [0x00,0xcc,0x20,0x0e]
+; CHECK: fmls.2s v0, v0, v0 ; encoding: [0x00,0xcc,0xa0,0x0e]
+; CHECK: fmulx.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x0e]
+
+; CHECK: fmul.2s v0, v0, v0 ; encoding: [0x00,0xdc,0x20,0x2e]
+; CHECK: fmulx d2, d3, d1 ; encoding: [0x62,0xdc,0x61,0x5e]
+; CHECK: fmulx s2, s3, s1 ; encoding: [0x62,0xdc,0x21,0x5e]
+; CHECK: frecps.2s v0, v0, v0 ; encoding: [0x00,0xfc,0x20,0x0e]
+; CHECK: frsqrts.2s v0, v0, v0 ; encoding: [0x00,0xfc,0xa0,0x0e]
+; CHECK: fsub.2s v0, v0, v0 ; encoding: [0x00,0xd4,0xa0,0x0e]
+; CHECK: mla.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x0e]
+; CHECK: mls.8b v0, v0, v0 ; encoding: [0x00,0x94,0x20,0x2e]
+; CHECK: mul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x0e]
+; CHECK: pmul.8b v0, v0, v0 ; encoding: [0x00,0x9c,0x20,0x2e]
+; CHECK: saba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x0e]
+; CHECK: sabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x0e]
+; CHECK: shadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x0e]
+; CHECK: shsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x0e]
+; CHECK: smaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x0e]
+; CHECK: smax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x0e]
+; CHECK: sminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x0e]
+; CHECK: smin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x0e]
+; CHECK: sqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x0e]
+; CHECK: sqdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x0e]
+; CHECK: sqrdmulh.4h v0, v0, v0 ; encoding: [0x00,0xb4,0x60,0x2e]
+; CHECK: sqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x0e]
+; CHECK: sqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x0e]
+; CHECK: sqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x0e]
+; CHECK: srhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x0e]
+; CHECK: srshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x0e]
+; CHECK: sshl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x0e]
+; CHECK: sub.8b v0, v0, v0 ; encoding: [0x00,0x84,0x20,0x2e]
+; CHECK: uaba.8b v0, v0, v0 ; encoding: [0x00,0x7c,0x20,0x2e]
+; CHECK: uabd.8b v0, v0, v0 ; encoding: [0x00,0x74,0x20,0x2e]
+; CHECK: uhadd.8b v0, v0, v0 ; encoding: [0x00,0x04,0x20,0x2e]
+; CHECK: uhsub.8b v0, v0, v0 ; encoding: [0x00,0x24,0x20,0x2e]
+; CHECK: umaxp.8b v0, v0, v0 ; encoding: [0x00,0xa4,0x20,0x2e]
+; CHECK: umax.8b v0, v0, v0 ; encoding: [0x00,0x64,0x20,0x2e]
+; CHECK: uminp.8b v0, v0, v0 ; encoding: [0x00,0xac,0x20,0x2e]
+; CHECK: umin.8b v0, v0, v0 ; encoding: [0x00,0x6c,0x20,0x2e]
+; CHECK: uqadd.8b v0, v0, v0 ; encoding: [0x00,0x0c,0x20,0x2e]
+; CHECK: uqrshl.8b v0, v0, v0 ; encoding: [0x00,0x5c,0x20,0x2e]
+; CHECK: uqshl.8b v0, v0, v0 ; encoding: [0x00,0x4c,0x20,0x2e]
+; CHECK: uqsub.8b v0, v0, v0 ; encoding: [0x00,0x2c,0x20,0x2e]
+; CHECK: urhadd.8b v0, v0, v0 ; encoding: [0x00,0x14,0x20,0x2e]
+; CHECK: urshl.8b v0, v0, v0 ; encoding: [0x00,0x54,0x20,0x2e]
+; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
+
+ bif.8b v0, v0, v0
+ bit.8b v0, v0, v0
+ bsl.8b v0, v0, v0
+ eor.8b v0, v0, v0
+ orn.8b v0, v0, v0
+ orr.8b v0, v0, v0
+
+; CHECK: bif.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x2e]
+; CHECK: bit.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x2e]
+; CHECK: bsl.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x2e]
+; CHECK: eor.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x2e]
+; CHECK: orn.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x0e]
+; CHECK: orr.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e]
+
+ sadalp.4h v0, v0
+ sadalp.8h v0, v0
+ sadalp.2s v0, v0
+ sadalp.4s v0, v0
+ sadalp.1d v0, v0
+ sadalp.2d v0, v0
+
+; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e]
+; CHECK: sadalp.8h v0, v0 ; encoding: [0x00,0x68,0x20,0x4e]
+; CHECK: sadalp.2s v0, v0 ; encoding: [0x00,0x68,0x60,0x0e]
+; CHECK: sadalp.4s v0, v0 ; encoding: [0x00,0x68,0x60,0x4e]
+; CHECK: sadalp.1d v0, v0 ; encoding: [0x00,0x68,0xa0,0x0e]
+; CHECK: sadalp.2d v0, v0 ; encoding: [0x00,0x68,0xa0,0x4e]
+
+ cls.8b v0, v0
+ clz.8b v0, v0
+ cnt.8b v0, v0
+ fabs.2s v0, v0
+ fneg.2s v0, v0
+ frecpe.2s v0, v0
+ frinta.2s v0, v0
+ frintx.2s v0, v0
+ frinti.2s v0, v0
+ frintm.2s v0, v0
+ frintn.2s v0, v0
+ frintp.2s v0, v0
+ frintz.2s v0, v0
+ frsqrte.2s v0, v0
+ fsqrt.2s v0, v0
+ neg.8b v0, v0
+ not.8b v0, v0
+ rbit.8b v0, v0
+ rev16.8b v0, v0
+ rev32.8b v0, v0
+ rev64.8b v0, v0
+ sadalp.4h v0, v0
+ saddlp.4h v0, v0
+ scvtf.2s v0, v0
+ sqabs.8b v0, v0
+ sqneg.8b v0, v0
+ sqxtn.8b v0, v0
+ sqxtun.8b v0, v0
+ suqadd.8b v0, v0
+ uadalp.4h v0, v0
+ uaddlp.4h v0, v0
+ ucvtf.2s v0, v0
+ uqxtn.8b v0, v0
+ urecpe.2s v0, v0
+ ursqrte.2s v0, v0
+ usqadd.8b v0, v0
+ xtn.8b v0, v0
+ shll.8h v1, v2, #8
+ shll.4s v3, v4, #16
+ shll.2d v5, v6, #32
+ shll2.8h v7, v8, #8
+ shll2.4s v9, v10, #16
+ shll2.2d v11, v12, #32
+ shll v1.8h, v2.8b, #8
+ shll v1.4s, v2.4h, #16
+ shll v1.2d, v2.2s, #32
+ shll2 v1.8h, v2.16b, #8
+ shll2 v1.4s, v2.8h, #16
+ shll2 v1.2d, v2.4s, #32
+
+; CHECK: cls.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x0e]
+; CHECK: clz.8b v0, v0 ; encoding: [0x00,0x48,0x20,0x2e]
+; CHECK: cnt.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x0e]
+; CHECK: fabs.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x0e]
+; CHECK: fneg.2s v0, v0 ; encoding: [0x00,0xf8,0xa0,0x2e]
+; CHECK: frecpe.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x0e]
+; CHECK: frinta.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x2e]
+; CHECK: frintx.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x2e]
+; CHECK: frinti.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x2e]
+; CHECK: frintm.2s v0, v0 ; encoding: [0x00,0x98,0x21,0x0e]
+; CHECK: frintn.2s v0, v0 ; encoding: [0x00,0x88,0x21,0x0e]
+; CHECK: frintp.2s v0, v0 ; encoding: [0x00,0x88,0xa1,0x0e]
+; CHECK: frintz.2s v0, v0 ; encoding: [0x00,0x98,0xa1,0x0e]
+; CHECK: frsqrte.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x2e]
+; CHECK: fsqrt.2s v0, v0 ; encoding: [0x00,0xf8,0xa1,0x2e]
+; CHECK: neg.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x2e]
+; CHECK: not.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x2e]
+; CHECK: rbit.8b v0, v0 ; encoding: [0x00,0x58,0x60,0x2e]
+; CHECK: rev16.8b v0, v0 ; encoding: [0x00,0x18,0x20,0x0e]
+; CHECK: rev32.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x2e]
+; CHECK: rev64.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x0e]
+; CHECK: sadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x0e]
+; CHECK: saddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x0e]
+; CHECK: scvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x0e]
+; CHECK: sqabs.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x0e]
+; CHECK: sqneg.8b v0, v0 ; encoding: [0x00,0x78,0x20,0x2e]
+; CHECK: sqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x0e]
+; CHECK: sqxtun.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x2e]
+; CHECK: suqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x0e]
+; CHECK: uadalp.4h v0, v0 ; encoding: [0x00,0x68,0x20,0x2e]
+; CHECK: uaddlp.4h v0, v0 ; encoding: [0x00,0x28,0x20,0x2e]
+; CHECK: ucvtf.2s v0, v0 ; encoding: [0x00,0xd8,0x21,0x2e]
+; CHECK: uqxtn.8b v0, v0 ; encoding: [0x00,0x48,0x21,0x2e]
+; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
+; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
+; CHECK: usqadd.8b v0, v0 ; encoding: [0x00,0x38,0x20,0x2e]
+; CHECK: xtn.8b v0, v0 ; encoding: [0x00,0x28,0x21,0x0e]
+; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e]
+; CHECK: shll.4s v3, v4, #16 ; encoding: [0x83,0x38,0x61,0x2e]
+; CHECK: shll.2d v5, v6, #32 ; encoding: [0xc5,0x38,0xa1,0x2e]
+; CHECK: shll2.8h v7, v8, #8 ; encoding: [0x07,0x39,0x21,0x6e]
+; CHECK: shll2.4s v9, v10, #16 ; encoding: [0x49,0x39,0x61,0x6e]
+; CHECK: shll2.2d v11, v12, #32 ; encoding: [0x8b,0x39,0xa1,0x6e]
+; CHECK: shll.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x2e]
+; CHECK: shll.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x2e]
+; CHECK: shll.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x2e]
+; CHECK: shll2.8h v1, v2, #8 ; encoding: [0x41,0x38,0x21,0x6e]
+; CHECK: shll2.4s v1, v2, #16 ; encoding: [0x41,0x38,0x61,0x6e]
+; CHECK: shll2.2d v1, v2, #32 ; encoding: [0x41,0x38,0xa1,0x6e]
+
+
+ cmeq.8b v0, v0, #0
+ cmeq.16b v0, v0, #0
+ cmeq.4h v0, v0, #0
+ cmeq.8h v0, v0, #0
+ cmeq.2s v0, v0, #0
+ cmeq.4s v0, v0, #0
+ cmeq.2d v0, v0, #0
+
+; CHECK: cmeq.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x0e]
+; CHECK: cmeq.16b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x4e]
+; CHECK: cmeq.4h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x0e]
+; CHECK: cmeq.8h v0, v0, #0 ; encoding: [0x00,0x98,0x60,0x4e]
+; CHECK: cmeq.2s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x0e]
+; CHECK: cmeq.4s v0, v0, #0 ; encoding: [0x00,0x98,0xa0,0x4e]
+; CHECK: cmeq.2d v0, v0, #0 ; encoding: [0x00,0x98,0xe0,0x4e]
+
+ cmge.8b v0, v0, #0
+ cmgt.8b v0, v0, #0
+ cmle.8b v0, v0, #0
+ cmlt.8b v0, v0, #0
+ fcmeq.2s v0, v0, #0
+ fcmge.2s v0, v0, #0
+ fcmgt.2s v0, v0, #0
+ fcmle.2s v0, v0, #0
+ fcmlt.2s v0, v0, #0
+
+; ARM verbose mode aliases
+ cmlt v8.8b, v14.8b, #0
+ cmlt v8.16b, v14.16b, #0
+ cmlt v8.4h, v14.4h, #0
+ cmlt v8.8h, v14.8h, #0
+ cmlt v8.2s, v14.2s, #0
+ cmlt v8.4s, v14.4s, #0
+ cmlt v8.2d, v14.2d, #0
+
+; CHECK: cmge.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x2e]
+; CHECK: cmgt.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x0e]
+; CHECK: cmle.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x2e]
+; CHECK: cmlt.8b v0, v0, #0 ; encoding: [0x00,0xa8,0x20,0x0e]
+; CHECK: fcmeq.2s v0, v0, #0 ; encoding: [0x00,0xd8,0xa0,0x0e]
+; CHECK: fcmge.2s v0, v0, #0 ; encoding: [0x00,0xc8,0xa0,0x2e]
+; CHECK: fcmgt.2s v0, v0, #0 ; encoding: [0x00,0xc8,0xa0,0x0e]
+; CHECK: fcmle.2s v0, v0, #0 ; encoding: [0x00,0xd8,0xa0,0x2e]
+; CHECK: fcmlt.2s v0, v0, #0 ; encoding: [0x00,0xe8,0xa0,0x0e]
+; CHECK: cmlt.8b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x0e]
+; CHECK: cmlt.16b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x4e]
+; CHECK: cmlt.4h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x0e]
+; CHECK: cmlt.8h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x4e]
+; CHECK: cmlt.2s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x0e]
+; CHECK: cmlt.4s v8, v14, #0 ; encoding: [0xc8,0xa9,0xa0,0x4e]
+; CHECK: cmlt.2d v8, v14, #0 ; encoding: [0xc8,0xa9,0xe0,0x4e]
+
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD Floating-point <-> Integer Conversions
+;===-------------------------------------------------------------------------===
+
+ fcvtas.2s v0, v0
+ fcvtas.4s v0, v0
+ fcvtas.2d v0, v0
+ fcvtas s0, s0
+ fcvtas d0, d0
+
+; CHECK: fcvtas.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x0e]
+; CHECK: fcvtas.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x4e]
+; CHECK: fcvtas.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x4e]
+; CHECK: fcvtas s0, s0 ; encoding: [0x00,0xc8,0x21,0x5e]
+; CHECK: fcvtas d0, d0 ; encoding: [0x00,0xc8,0x61,0x5e]
+
+ fcvtau.2s v0, v0
+ fcvtau.4s v0, v0
+ fcvtau.2d v0, v0
+ fcvtau s0, s0
+ fcvtau d0, d0
+
+; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
+; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
+; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
+; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
+; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
+
+ fcvtl v1.4s, v5.4h
+ fcvtl v2.2d, v6.2s
+ fcvtl2 v3.4s, v7.8h
+ fcvtl2 v4.2d, v8.4s
+
+; CHECK: fcvtl v1.4s, v5.4h ; encoding: [0xa1,0x78,0x21,0x0e]
+; CHECK: fcvtl v2.2d, v6.2s ; encoding: [0xc2,0x78,0x61,0x0e]
+; CHECK: fcvtl2 v3.4s, v7.8h ; encoding: [0xe3,0x78,0x21,0x4e]
+; CHECK: fcvtl2 v4.2d, v8.4s ; encoding: [0x04,0x79,0x61,0x4e]
+
+ fcvtms.2s v0, v0
+ fcvtms.4s v0, v0
+ fcvtms.2d v0, v0
+ fcvtms s0, s0
+ fcvtms d0, d0
+
+; CHECK: fcvtms.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x0e]
+; CHECK: fcvtms.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x4e]
+; CHECK: fcvtms.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x4e]
+; CHECK: fcvtms s0, s0 ; encoding: [0x00,0xb8,0x21,0x5e]
+; CHECK: fcvtms d0, d0 ; encoding: [0x00,0xb8,0x61,0x5e]
+
+ fcvtmu.2s v0, v0
+ fcvtmu.4s v0, v0
+ fcvtmu.2d v0, v0
+ fcvtmu s0, s0
+ fcvtmu d0, d0
+
+; CHECK: fcvtmu.2s v0, v0 ; encoding: [0x00,0xb8,0x21,0x2e]
+; CHECK: fcvtmu.4s v0, v0 ; encoding: [0x00,0xb8,0x21,0x6e]
+; CHECK: fcvtmu.2d v0, v0 ; encoding: [0x00,0xb8,0x61,0x6e]
+; CHECK: fcvtmu s0, s0 ; encoding: [0x00,0xb8,0x21,0x7e]
+; CHECK: fcvtmu d0, d0 ; encoding: [0x00,0xb8,0x61,0x7e]
+
+ fcvtns.2s v0, v0
+ fcvtns.4s v0, v0
+ fcvtns.2d v0, v0
+ fcvtns s0, s0
+ fcvtns d0, d0
+
+; CHECK: fcvtns.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x0e]
+; CHECK: fcvtns.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x4e]
+; CHECK: fcvtns.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x4e]
+; CHECK: fcvtns s0, s0 ; encoding: [0x00,0xa8,0x21,0x5e]
+; CHECK: fcvtns d0, d0 ; encoding: [0x00,0xa8,0x61,0x5e]
+
+ fcvtnu.2s v0, v0
+ fcvtnu.4s v0, v0
+ fcvtnu.2d v0, v0
+ fcvtnu s0, s0
+ fcvtnu d0, d0
+
+; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e]
+; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e]
+; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e]
+; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e]
+; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
+
+ fcvtn v2.4h, v4.4s
+ fcvtn v3.2s, v5.2d
+ fcvtn2 v4.8h, v6.4s
+ fcvtn2 v5.4s, v7.2d
+ fcvtxn v6.2s, v9.2d
+ fcvtxn2 v7.4s, v8.2d
+
+; CHECK: fcvtn v2.4h, v4.4s ; encoding: [0x82,0x68,0x21,0x0e]
+; CHECK: fcvtn v3.2s, v5.2d ; encoding: [0xa3,0x68,0x61,0x0e]
+; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e]
+; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e]
+; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
+; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e]
+
+ fcvtps.2s v0, v0
+ fcvtps.4s v0, v0
+ fcvtps.2d v0, v0
+ fcvtps s0, s0
+ fcvtps d0, d0
+
+; CHECK: fcvtps.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x0e]
+; CHECK: fcvtps.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x4e]
+; CHECK: fcvtps.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x4e]
+; CHECK: fcvtps s0, s0 ; encoding: [0x00,0xa8,0xa1,0x5e]
+; CHECK: fcvtps d0, d0 ; encoding: [0x00,0xa8,0xe1,0x5e]
+
+ fcvtpu.2s v0, v0
+ fcvtpu.4s v0, v0
+ fcvtpu.2d v0, v0
+ fcvtpu s0, s0
+ fcvtpu d0, d0
+
+; CHECK: fcvtpu.2s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x2e]
+; CHECK: fcvtpu.4s v0, v0 ; encoding: [0x00,0xa8,0xa1,0x6e]
+; CHECK: fcvtpu.2d v0, v0 ; encoding: [0x00,0xa8,0xe1,0x6e]
+; CHECK: fcvtpu s0, s0 ; encoding: [0x00,0xa8,0xa1,0x7e]
+; CHECK: fcvtpu d0, d0 ; encoding: [0x00,0xa8,0xe1,0x7e]
+
+ fcvtzs.2s v0, v0
+ fcvtzs.4s v0, v0
+ fcvtzs.2d v0, v0
+ fcvtzs s0, s0
+ fcvtzs d0, d0
+
+; CHECK: fcvtzs.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x0e]
+; CHECK: fcvtzs.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x4e]
+; CHECK: fcvtzs.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x4e]
+; CHECK: fcvtzs s0, s0 ; encoding: [0x00,0xb8,0xa1,0x5e]
+; CHECK: fcvtzs d0, d0 ; encoding: [0x00,0xb8,0xe1,0x5e]
+
+ fcvtzu.2s v0, v0
+ fcvtzu.4s v0, v0
+ fcvtzu.2d v0, v0
+ fcvtzu s0, s0
+ fcvtzu d0, d0
+
+; CHECK: fcvtzu.2s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x2e]
+; CHECK: fcvtzu.4s v0, v0 ; encoding: [0x00,0xb8,0xa1,0x6e]
+; CHECK: fcvtzu.2d v0, v0 ; encoding: [0x00,0xb8,0xe1,0x6e]
+; CHECK: fcvtzu s0, s0 ; encoding: [0x00,0xb8,0xa1,0x7e]
+; CHECK: fcvtzu d0, d0 ; encoding: [0x00,0xb8,0xe1,0x7e]
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD modified immediate instructions
+;===-------------------------------------------------------------------------===
+
+ bic.2s v0, #1
+ bic.2s v0, #1, lsl #0
+ bic.2s v0, #1, lsl #8
+ bic.2s v0, #1, lsl #16
+ bic.2s v0, #1, lsl #24
+
+; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f]
+; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f]
+; CHECK: bic.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f]
+; CHECK: bic.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f]
+; CHECK: bic.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f]
+
+ bic.4h v0, #1
+ bic.4h v0, #1, lsl #0
+ bic.4h v0, #1, lsl #8
+
+; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f]
+; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f]
+; CHECK: bic.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f]
+
+ bic.4s v0, #1
+ bic.4s v0, #1, lsl #0
+ bic.4s v0, #1, lsl #8
+ bic.4s v0, #1, lsl #16
+ bic.4s v0, #1, lsl #24
+
+; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f]
+; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f]
+; CHECK: bic.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f]
+; CHECK: bic.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f]
+; CHECK: bic.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f]
+
+ bic.8h v0, #1
+ bic.8h v0, #1, lsl #0
+ bic.8h v0, #1, lsl #8
+
+; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f]
+; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f]
+; CHECK: bic.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f]
+
+ fmov.2d v0, #1.250000e-01
+
+; CHECK: fmov.2d v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x6f]
+
+ fmov.2s v0, #1.250000e-01
+ fmov.4s v0, #1.250000e-01
+
+; CHECK: fmov.2s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x0f]
+; CHECK: fmov.4s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x4f]
+
+ orr.2s v0, #1
+ orr.2s v0, #1, lsl #0
+ orr.2s v0, #1, lsl #8
+ orr.2s v0, #1, lsl #16
+ orr.2s v0, #1, lsl #24
+
+; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f]
+; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f]
+; CHECK: orr.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f]
+; CHECK: orr.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f]
+; CHECK: orr.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f]
+
+ orr.4h v0, #1
+ orr.4h v0, #1, lsl #0
+ orr.4h v0, #1, lsl #8
+
+; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f]
+; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f]
+; CHECK: orr.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f]
+
+ orr.4s v0, #1
+ orr.4s v0, #1, lsl #0
+ orr.4s v0, #1, lsl #8
+ orr.4s v0, #1, lsl #16
+ orr.4s v0, #1, lsl #24
+
+; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f]
+; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f]
+; CHECK: orr.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f]
+; CHECK: orr.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f]
+; CHECK: orr.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f]
+
+ orr.8h v0, #1
+ orr.8h v0, #1, lsl #0
+ orr.8h v0, #1, lsl #8
+
+; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f]
+; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f]
+; CHECK: orr.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f]
+
+ movi d0, #0x000000000000ff
+ movi.2d v0, #0x000000000000ff
+
+; CHECK: movi d0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x2f]
+; CHECK: movi.2d v0, #0x000000000000ff ; encoding: [0x20,0xe4,0x00,0x6f]
+
+ movi.2s v0, #1
+ movi.2s v0, #1, lsl #0
+ movi.2s v0, #1, lsl #8
+ movi.2s v0, #1, lsl #16
+ movi.2s v0, #1, lsl #24
+
+; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f]
+; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f]
+; CHECK: movi.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f]
+; CHECK: movi.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f]
+; CHECK: movi.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f]
+
+ movi.4s v0, #1
+ movi.4s v0, #1, lsl #0
+ movi.4s v0, #1, lsl #8
+ movi.4s v0, #1, lsl #16
+ movi.4s v0, #1, lsl #24
+
+; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f]
+; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f]
+; CHECK: movi.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f]
+; CHECK: movi.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f]
+; CHECK: movi.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f]
+
+ movi.4h v0, #1
+ movi.4h v0, #1, lsl #0
+ movi.4h v0, #1, lsl #8
+
+; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f]
+; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f]
+; CHECK: movi.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f]
+
+ movi.8h v0, #1
+ movi.8h v0, #1, lsl #0
+ movi.8h v0, #1, lsl #8
+
+; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f]
+; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f]
+; CHECK: movi.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f]
+
+ movi.2s v0, #1, msl #8
+ movi.2s v0, #1, msl #16
+ movi.4s v0, #1, msl #8
+ movi.4s v0, #1, msl #16
+
+; CHECK: movi.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f]
+; CHECK: movi.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f]
+; CHECK: movi.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f]
+; CHECK: movi.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f]
+
+ movi.8b v0, #1
+ movi.16b v0, #1
+
+; CHECK: movi.8b v0, #1 ; encoding: [0x20,0xe4,0x00,0x0f]
+; CHECK: movi.16b v0, #1 ; encoding: [0x20,0xe4,0x00,0x4f]
+
+ mvni.2s v0, #1
+ mvni.2s v0, #1, lsl #0
+ mvni.2s v0, #1, lsl #8
+ mvni.2s v0, #1, lsl #16
+ mvni.2s v0, #1, lsl #24
+
+; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f]
+; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f]
+; CHECK: mvni.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f]
+; CHECK: mvni.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f]
+; CHECK: mvni.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f]
+
+ mvni.4s v0, #1
+ mvni.4s v0, #1, lsl #0
+ mvni.4s v0, #1, lsl #8
+ mvni.4s v0, #1, lsl #16
+ mvni.4s v0, #1, lsl #24
+
+; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f]
+; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f]
+; CHECK: mvni.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f]
+; CHECK: mvni.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f]
+; CHECK: mvni.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f]
+
+ mvni.4h v0, #1
+ mvni.4h v0, #1, lsl #0
+ mvni.4h v0, #1, lsl #8
+
+; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f]
+; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f]
+; CHECK: mvni.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f]
+
+ mvni.8h v0, #1
+ mvni.8h v0, #1, lsl #0
+ mvni.8h v0, #1, lsl #8
+
+; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f]
+; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f]
+; CHECK: mvni.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f]
+
+ mvni.2s v0, #1, msl #8
+ mvni.2s v0, #1, msl #16
+ mvni.4s v0, #1, msl #8
+ mvni.4s v0, #1, msl #16
+
+; CHECK: mvni.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f]
+; CHECK: mvni.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f]
+; CHECK: mvni.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f]
+; CHECK: mvni.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f]
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD scalar x index
+;===-------------------------------------------------------------------------===
+
+ fmla.s s0, s0, v0[3]
+ fmla.d d0, d0, v0[1]
+ fmls.s s0, s0, v0[3]
+ fmls.d d0, d0, v0[1]
+ fmulx.s s0, s0, v0[3]
+ fmulx.d d0, d0, v0[1]
+ fmul.s s0, s0, v0[3]
+ fmul.d d0, d0, v0[1]
+ sqdmlal.h s0, h0, v0[7]
+ sqdmlal.s d0, s0, v0[3]
+ sqdmlsl.h s0, h0, v0[7]
+ sqdmulh.h h0, h0, v0[7]
+ sqdmulh.s s0, s0, v0[3]
+ sqdmull.h s0, h0, v0[7]
+ sqdmull.s d0, s0, v0[3]
+ sqrdmulh.h h0, h0, v0[7]
+ sqrdmulh.s s0, s0, v0[3]
+
+; CHECK: fmla.s s0, s0, v0[3] ; encoding: [0x00,0x18,0xa0,0x5f]
+; CHECK: fmla.d d0, d0, v0[1] ; encoding: [0x00,0x18,0xc0,0x5f]
+; CHECK: fmls.s s0, s0, v0[3] ; encoding: [0x00,0x58,0xa0,0x5f]
+; CHECK: fmls.d d0, d0, v0[1] ; encoding: [0x00,0x58,0xc0,0x5f]
+; CHECK: fmulx.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x7f]
+; CHECK: fmulx.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x7f]
+; CHECK: fmul.s s0, s0, v0[3] ; encoding: [0x00,0x98,0xa0,0x5f]
+; CHECK: fmul.d d0, d0, v0[1] ; encoding: [0x00,0x98,0xc0,0x5f]
+; CHECK: sqdmlal.h s0, h0, v0[7] ; encoding: [0x00,0x38,0x70,0x5f]
+; CHECK: sqdmlal.s d0, s0, v0[3] ; encoding: [0x00,0x38,0xa0,0x5f]
+; CHECK: sqdmlsl.h s0, h0, v0[7] ; encoding: [0x00,0x78,0x70,0x5f]
+; CHECK: sqdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xc8,0x70,0x5f]
+; CHECK: sqdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x5f]
+; CHECK: sqdmull.h s0, h0, v0[7] ; encoding: [0x00,0xb8,0x70,0x5f]
+; CHECK: sqdmull.s d0, s0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x5f]
+; CHECK: sqrdmulh.h h0, h0, v0[7] ; encoding: [0x00,0xd8,0x70,0x5f]
+; CHECK: sqrdmulh.s s0, s0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x5f]
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD SMLAL
+;===-------------------------------------------------------------------------===
+ smlal.8h v1, v2, v3
+ smlal.4s v1, v2, v3
+ smlal.2d v1, v2, v3
+ smlal2.8h v1, v2, v3
+ smlal2.4s v1, v2, v3
+ smlal2.2d v1, v2, v3
+
+ smlal v13.8h, v8.8b, v0.8b
+ smlal v13.4s, v8.4h, v0.4h
+ smlal v13.2d, v8.2s, v0.2s
+ smlal2 v13.8h, v8.16b, v0.16b
+ smlal2 v13.4s, v8.8h, v0.8h
+ smlal2 v13.2d, v8.4s, v0.4s
+
+; CHECK: smlal.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x0e]
+; CHECK: smlal.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x0e]
+; CHECK: smlal.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x0e]
+; CHECK: smlal2.8h v1, v2, v3 ; encoding: [0x41,0x80,0x23,0x4e]
+; CHECK: smlal2.4s v1, v2, v3 ; encoding: [0x41,0x80,0x63,0x4e]
+; CHECK: smlal2.2d v1, v2, v3 ; encoding: [0x41,0x80,0xa3,0x4e]
+; CHECK: smlal.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x0e]
+; CHECK: smlal.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x0e]
+; CHECK: smlal.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x0e]
+; CHECK: smlal2.8h v13, v8, v0 ; encoding: [0x0d,0x81,0x20,0x4e]
+; CHECK: smlal2.4s v13, v8, v0 ; encoding: [0x0d,0x81,0x60,0x4e]
+; CHECK: smlal2.2d v13, v8, v0 ; encoding: [0x0d,0x81,0xa0,0x4e]
+
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD scalar x index
+;===-------------------------------------------------------------------------===
+
+ fmla.2s v0, v0, v0[0]
+ fmla.4s v0, v0, v0[1]
+ fmla.2d v0, v0, v0[1]
+ fmls.2s v0, v0, v0[0]
+ fmls.4s v0, v0, v0[1]
+ fmls.2d v0, v0, v0[1]
+ fmulx.2s v0, v0, v0[0]
+ fmulx.4s v0, v0, v0[1]
+ fmulx.2d v0, v0, v0[1]
+ fmul.2s v0, v0, v0[0]
+ fmul.4s v0, v0, v0[1]
+ fmul.2d v0, v0, v0[1]
+ mla.4h v0, v0, v0[0]
+ mla.8h v0, v0, v0[1]
+ mla.2s v0, v0, v0[2]
+ mla.4s v0, v0, v0[3]
+ mls.4h v0, v0, v0[0]
+ mls.8h v0, v0, v0[1]
+ mls.2s v0, v0, v0[2]
+ mls.4s v0, v0, v0[3]
+ mul.4h v0, v0, v0[0]
+ mul.8h v0, v0, v0[1]
+ mul.2s v0, v0, v0[2]
+ mul.4s v0, v0, v0[3]
+ smlal.4s v0, v0, v0[0]
+ smlal2.4s v0, v0, v0[1]
+ smlal.2d v0, v0, v0[2]
+ smlal2.2d v0, v0, v0[3]
+ smlsl.4s v0, v0, v0[0]
+ smlsl2.4s v0, v0, v0[1]
+ smlsl.2d v0, v0, v0[2]
+ smlsl2.2d v0, v0, v0[3]
+ smull.4s v0, v0, v0[0]
+ smull2.4s v0, v0, v0[1]
+ smull.2d v0, v0, v0[2]
+ smull2.2d v0, v0, v0[3]
+ sqdmlal.4s v0, v0, v0[0]
+ sqdmlal2.4s v0, v0, v0[1]
+ sqdmlal.2d v0, v0, v0[2]
+ sqdmlal2.2d v0, v0, v0[3]
+ sqdmlsl.4s v0, v0, v0[0]
+ sqdmlsl2.4s v0, v0, v0[1]
+ sqdmlsl.2d v0, v0, v0[2]
+ sqdmlsl2.2d v0, v0, v0[3]
+ sqdmulh.4h v0, v0, v0[0]
+ sqdmulh.8h v0, v0, v0[1]
+ sqdmulh.2s v0, v0, v0[2]
+ sqdmulh.4s v0, v0, v0[3]
+ sqdmull.4s v0, v0, v0[0]
+ sqdmull2.4s v0, v0, v0[1]
+ sqdmull.2d v0, v0, v0[2]
+ sqdmull2.2d v0, v0, v0[3]
+ sqrdmulh.4h v0, v0, v0[0]
+ sqrdmulh.8h v0, v0, v0[1]
+ sqrdmulh.2s v0, v0, v0[2]
+ sqrdmulh.4s v0, v0, v0[3]
+ umlal.4s v0, v0, v0[0]
+ umlal2.4s v0, v0, v0[1]
+ umlal.2d v0, v0, v0[2]
+ umlal2.2d v0, v0, v0[3]
+ umlsl.4s v0, v0, v0[0]
+ umlsl2.4s v0, v0, v0[1]
+ umlsl.2d v0, v0, v0[2]
+ umlsl2.2d v0, v0, v0[3]
+ umull.4s v0, v0, v0[0]
+ umull2.4s v0, v0, v0[1]
+ umull.2d v0, v0, v0[2]
+ umull2.2d v0, v0, v0[3]
+
+; CHECK: fmla.2s v0, v0, v0[0] ; encoding: [0x00,0x10,0x80,0x0f]
+; CHECK: fmla.4s v0, v0, v0[1] ; encoding: [0x00,0x10,0xa0,0x4f]
+; CHECK: fmla.2d v0, v0, v0[1] ; encoding: [0x00,0x18,0xc0,0x4f]
+; CHECK: fmls.2s v0, v0, v0[0] ; encoding: [0x00,0x50,0x80,0x0f]
+; CHECK: fmls.4s v0, v0, v0[1] ; encoding: [0x00,0x50,0xa0,0x4f]
+; CHECK: fmls.2d v0, v0, v0[1] ; encoding: [0x00,0x58,0xc0,0x4f]
+; CHECK: fmulx.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x2f]
+; CHECK: fmulx.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x6f]
+; CHECK: fmulx.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x6f]
+; CHECK: fmul.2s v0, v0, v0[0] ; encoding: [0x00,0x90,0x80,0x0f]
+; CHECK: fmul.4s v0, v0, v0[1] ; encoding: [0x00,0x90,0xa0,0x4f]
+; CHECK: fmul.2d v0, v0, v0[1] ; encoding: [0x00,0x98,0xc0,0x4f]
+; CHECK: mla.4h v0, v0, v0[0] ; encoding: [0x00,0x00,0x40,0x2f]
+; CHECK: mla.8h v0, v0, v0[1] ; encoding: [0x00,0x00,0x50,0x6f]
+; CHECK: mla.2s v0, v0, v0[2] ; encoding: [0x00,0x08,0x80,0x2f]
+; CHECK: mla.4s v0, v0, v0[3] ; encoding: [0x00,0x08,0xa0,0x6f]
+; CHECK: mls.4h v0, v0, v0[0] ; encoding: [0x00,0x40,0x40,0x2f]
+; CHECK: mls.8h v0, v0, v0[1] ; encoding: [0x00,0x40,0x50,0x6f]
+; CHECK: mls.2s v0, v0, v0[2] ; encoding: [0x00,0x48,0x80,0x2f]
+; CHECK: mls.4s v0, v0, v0[3] ; encoding: [0x00,0x48,0xa0,0x6f]
+; CHECK: mul.4h v0, v0, v0[0] ; encoding: [0x00,0x80,0x40,0x0f]
+; CHECK: mul.8h v0, v0, v0[1] ; encoding: [0x00,0x80,0x50,0x4f]
+; CHECK: mul.2s v0, v0, v0[2] ; encoding: [0x00,0x88,0x80,0x0f]
+; CHECK: mul.4s v0, v0, v0[3] ; encoding: [0x00,0x88,0xa0,0x4f]
+; CHECK: smlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x0f]
+; CHECK: smlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x4f]
+; CHECK: smlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x0f]
+; CHECK: smlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x4f]
+; CHECK: smlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x0f]
+; CHECK: smlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x4f]
+; CHECK: smlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x0f]
+; CHECK: smlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x4f]
+; CHECK: smull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x0f]
+; CHECK: smull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x4f]
+; CHECK: smull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x0f]
+; CHECK: smull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x4f]
+; CHECK: sqdmlal.4s v0, v0, v0[0] ; encoding: [0x00,0x30,0x40,0x0f]
+; CHECK: sqdmlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x30,0x50,0x4f]
+; CHECK: sqdmlal.2d v0, v0, v0[2] ; encoding: [0x00,0x38,0x80,0x0f]
+; CHECK: sqdmlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x38,0xa0,0x4f]
+; CHECK: sqdmlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x70,0x40,0x0f]
+; CHECK: sqdmlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x70,0x50,0x4f]
+; CHECK: sqdmlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x78,0x80,0x0f]
+; CHECK: sqdmlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x78,0xa0,0x4f]
+; CHECK: sqdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xc0,0x40,0x0f]
+; CHECK: sqdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xc0,0x50,0x4f]
+; CHECK: sqdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xc8,0x80,0x0f]
+; CHECK: sqdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xc8,0xa0,0x4f]
+; CHECK: sqdmull.4s v0, v0, v0[0] ; encoding: [0x00,0xb0,0x40,0x0f]
+; CHECK: sqdmull2.4s v0, v0, v0[1] ; encoding: [0x00,0xb0,0x50,0x4f]
+; CHECK: sqdmull.2d v0, v0, v0[2] ; encoding: [0x00,0xb8,0x80,0x0f]
+; CHECK: sqdmull2.2d v0, v0, v0[3] ; encoding: [0x00,0xb8,0xa0,0x4f]
+; CHECK: sqrdmulh.4h v0, v0, v0[0] ; encoding: [0x00,0xd0,0x40,0x0f]
+; CHECK: sqrdmulh.8h v0, v0, v0[1] ; encoding: [0x00,0xd0,0x50,0x4f]
+; CHECK: sqrdmulh.2s v0, v0, v0[2] ; encoding: [0x00,0xd8,0x80,0x0f]
+; CHECK: sqrdmulh.4s v0, v0, v0[3] ; encoding: [0x00,0xd8,0xa0,0x4f]
+; CHECK: umlal.4s v0, v0, v0[0] ; encoding: [0x00,0x20,0x40,0x2f]
+; CHECK: umlal2.4s v0, v0, v0[1] ; encoding: [0x00,0x20,0x50,0x6f]
+; CHECK: umlal.2d v0, v0, v0[2] ; encoding: [0x00,0x28,0x80,0x2f]
+; CHECK: umlal2.2d v0, v0, v0[3] ; encoding: [0x00,0x28,0xa0,0x6f]
+; CHECK: umlsl.4s v0, v0, v0[0] ; encoding: [0x00,0x60,0x40,0x2f]
+; CHECK: umlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x60,0x50,0x6f]
+; CHECK: umlsl.2d v0, v0, v0[2] ; encoding: [0x00,0x68,0x80,0x2f]
+; CHECK: umlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x68,0xa0,0x6f]
+; CHECK: umull.4s v0, v0, v0[0] ; encoding: [0x00,0xa0,0x40,0x2f]
+; CHECK: umull2.4s v0, v0, v0[1] ; encoding: [0x00,0xa0,0x50,0x6f]
+; CHECK: umull.2d v0, v0, v0[2] ; encoding: [0x00,0xa8,0x80,0x2f]
+; CHECK: umull2.2d v0, v0, v0[3] ; encoding: [0x00,0xa8,0xa0,0x6f]
+
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD scalar with shift
+;===-------------------------------------------------------------------------===
+
+ fcvtzs s0, s0, #1
+ fcvtzs d0, d0, #2
+ fcvtzu s0, s0, #1
+ fcvtzu d0, d0, #2
+ shl d0, d0, #1
+ sli d0, d0, #1
+ sqrshrn b0, h0, #1
+ sqrshrn h0, s0, #2
+ sqrshrn s0, d0, #3
+ sqrshrun b0, h0, #1
+ sqrshrun h0, s0, #2
+ sqrshrun s0, d0, #3
+ sqshlu b0, b0, #1
+ sqshlu h0, h0, #2
+ sqshlu s0, s0, #3
+ sqshlu d0, d0, #4
+ sqshl b0, b0, #1
+ sqshl h0, h0, #2
+ sqshl s0, s0, #3
+ sqshl d0, d0, #4
+ sqshrn b0, h0, #1
+ sqshrn h0, s0, #2
+ sqshrn s0, d0, #3
+ sqshrun b0, h0, #1
+ sqshrun h0, s0, #2
+ sqshrun s0, d0, #3
+ sri d0, d0, #1
+ srshr d0, d0, #1
+ srsra d0, d0, #1
+ sshr d0, d0, #1
+ ucvtf s0, s0, #1
+ ucvtf d0, d0, #2
+ scvtf s0, s0, #1
+ scvtf d0, d0, #2
+ uqrshrn b0, h0, #1
+ uqrshrn h0, s0, #2
+ uqrshrn s0, d0, #3
+ uqshl b0, b0, #1
+ uqshl h0, h0, #2
+ uqshl s0, s0, #3
+ uqshl d0, d0, #4
+ uqshrn b0, h0, #1
+ uqshrn h0, s0, #2
+ uqshrn s0, d0, #3
+ urshr d0, d0, #1
+ ursra d0, d0, #1
+ ushr d0, d0, #1
+ usra d0, d0, #1
+
+; CHECK: fcvtzs s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x5f]
+; CHECK: fcvtzs d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x5f]
+; CHECK: fcvtzu s0, s0, #1 ; encoding: [0x00,0xfc,0x3f,0x7f]
+; CHECK: fcvtzu d0, d0, #2 ; encoding: [0x00,0xfc,0x7e,0x7f]
+; CHECK: shl d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x5f]
+; CHECK: sli d0, d0, #1 ; encoding: [0x00,0x54,0x41,0x7f]
+; CHECK: sqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x5f]
+; CHECK: sqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x5f]
+; CHECK: sqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x5f]
+; CHECK: sqrshrun b0, h0, #1 ; encoding: [0x00,0x8c,0x0f,0x7f]
+; CHECK: sqrshrun h0, s0, #2 ; encoding: [0x00,0x8c,0x1e,0x7f]
+; CHECK: sqrshrun s0, d0, #3 ; encoding: [0x00,0x8c,0x3d,0x7f]
+; CHECK: sqshlu b0, b0, #1 ; encoding: [0x00,0x64,0x09,0x7f]
+; CHECK: sqshlu h0, h0, #2 ; encoding: [0x00,0x64,0x12,0x7f]
+; CHECK: sqshlu s0, s0, #3 ; encoding: [0x00,0x64,0x23,0x7f]
+; CHECK: sqshlu d0, d0, #4 ; encoding: [0x00,0x64,0x44,0x7f]
+; CHECK: sqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x5f]
+; CHECK: sqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x5f]
+; CHECK: sqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x5f]
+; CHECK: sqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x5f]
+; CHECK: sqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x5f]
+; CHECK: sqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x5f]
+; CHECK: sqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x5f]
+; CHECK: sqshrun b0, h0, #1 ; encoding: [0x00,0x84,0x0f,0x7f]
+; CHECK: sqshrun h0, s0, #2 ; encoding: [0x00,0x84,0x1e,0x7f]
+; CHECK: sqshrun s0, d0, #3 ; encoding: [0x00,0x84,0x3d,0x7f]
+; CHECK: sri d0, d0, #1 ; encoding: [0x00,0x44,0x7f,0x7f]
+; CHECK: srshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x5f]
+; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f]
+; CHECK: sshr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x5f]
+; CHECK: ucvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x7f]
+; CHECK: ucvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x7f]
+; check: scvtf s0, s0, #1 ; encoding: [0x00,0xe4,0x3f,0x5f]
+; check: scvtf d0, d0, #2 ; encoding: [0x00,0xe4,0x7e,0x5f]
+; CHECK: uqrshrn b0, h0, #1 ; encoding: [0x00,0x9c,0x0f,0x7f]
+; CHECK: uqrshrn h0, s0, #2 ; encoding: [0x00,0x9c,0x1e,0x7f]
+; CHECK: uqrshrn s0, d0, #3 ; encoding: [0x00,0x9c,0x3d,0x7f]
+; CHECK: uqshl b0, b0, #1 ; encoding: [0x00,0x74,0x09,0x7f]
+; CHECK: uqshl h0, h0, #2 ; encoding: [0x00,0x74,0x12,0x7f]
+; CHECK: uqshl s0, s0, #3 ; encoding: [0x00,0x74,0x23,0x7f]
+; CHECK: uqshl d0, d0, #4 ; encoding: [0x00,0x74,0x44,0x7f]
+; CHECK: uqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x7f]
+; CHECK: uqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x7f]
+; CHECK: uqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x7f]
+; CHECK: urshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x7f]
+; CHECK: ursra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x7f]
+; CHECK: ushr d0, d0, #1 ; encoding: [0x00,0x04,0x7f,0x7f]
+; CHECK: usra d0, d0, #1 ; encoding: [0x00,0x14,0x7f,0x7f]
+
+
+;===-------------------------------------------------------------------------===
+; AdvSIMD vector with shift
+;===-------------------------------------------------------------------------===
+
+ fcvtzs.2s v0, v0, #1
+ fcvtzs.4s v0, v0, #2
+ fcvtzs.2d v0, v0, #3
+ fcvtzu.2s v0, v0, #1
+ fcvtzu.4s v0, v0, #2
+ fcvtzu.2d v0, v0, #3
+ rshrn.8b v0, v0, #1
+ rshrn2.16b v0, v0, #2
+ rshrn.4h v0, v0, #3
+ rshrn2.8h v0, v0, #4
+ rshrn.2s v0, v0, #5
+ rshrn2.4s v0, v0, #6
+ scvtf.2s v0, v0, #1
+ scvtf.4s v0, v0, #2
+ scvtf.2d v0, v0, #3
+ shl.8b v0, v0, #1
+ shl.16b v0, v0, #2
+ shl.4h v0, v0, #3
+ shl.8h v0, v0, #4
+ shl.2s v0, v0, #5
+ shl.4s v0, v0, #6
+ shl.2d v0, v0, #7
+ shrn.8b v0, v0, #1
+ shrn2.16b v0, v0, #2
+ shrn.4h v0, v0, #3
+ shrn2.8h v0, v0, #4
+ shrn.2s v0, v0, #5
+ shrn2.4s v0, v0, #6
+ sli.8b v0, v0, #1
+ sli.16b v0, v0, #2
+ sli.4h v0, v0, #3
+ sli.8h v0, v0, #4
+ sli.2s v0, v0, #5
+ sli.4s v0, v0, #6
+ sli.2d v0, v0, #7
+ sqrshrn.8b v0, v0, #1
+ sqrshrn2.16b v0, v0, #2
+ sqrshrn.4h v0, v0, #3
+ sqrshrn2.8h v0, v0, #4
+ sqrshrn.2s v0, v0, #5
+ sqrshrn2.4s v0, v0, #6
+ sqrshrun.8b v0, v0, #1
+ sqrshrun2.16b v0, v0, #2
+ sqrshrun.4h v0, v0, #3
+ sqrshrun2.8h v0, v0, #4
+ sqrshrun.2s v0, v0, #5
+ sqrshrun2.4s v0, v0, #6
+ sqshlu.8b v0, v0, #1
+ sqshlu.16b v0, v0, #2
+ sqshlu.4h v0, v0, #3
+ sqshlu.8h v0, v0, #4
+ sqshlu.2s v0, v0, #5
+ sqshlu.4s v0, v0, #6
+ sqshlu.2d v0, v0, #7
+ sqshl.8b v0, v0, #1
+ sqshl.16b v0, v0, #2
+ sqshl.4h v0, v0, #3
+ sqshl.8h v0, v0, #4
+ sqshl.2s v0, v0, #5
+ sqshl.4s v0, v0, #6
+ sqshl.2d v0, v0, #7
+ sqshrn.8b v0, v0, #1
+ sqshrn2.16b v0, v0, #2
+ sqshrn.4h v0, v0, #3
+ sqshrn2.8h v0, v0, #4
+ sqshrn.2s v0, v0, #5
+ sqshrn2.4s v0, v0, #6
+ sqshrun.8b v0, v0, #1
+ sqshrun2.16b v0, v0, #2
+ sqshrun.4h v0, v0, #3
+ sqshrun2.8h v0, v0, #4
+ sqshrun.2s v0, v0, #5
+ sqshrun2.4s v0, v0, #6
+ sri.8b v0, v0, #1
+ sri.16b v0, v0, #2
+ sri.4h v0, v0, #3
+ sri.8h v0, v0, #4
+ sri.2s v0, v0, #5
+ sri.4s v0, v0, #6
+ sri.2d v0, v0, #7
+ srshr.8b v0, v0, #1
+ srshr.16b v0, v0, #2
+ srshr.4h v0, v0, #3
+ srshr.8h v0, v0, #4
+ srshr.2s v0, v0, #5
+ srshr.4s v0, v0, #6
+ srshr.2d v0, v0, #7
+ srsra.8b v0, v0, #1
+ srsra.16b v0, v0, #2
+ srsra.4h v0, v0, #3
+ srsra.8h v0, v0, #4
+ srsra.2s v0, v0, #5
+ srsra.4s v0, v0, #6
+ srsra.2d v0, v0, #7
+ sshll.8h v0, v0, #1
+ sshll2.8h v0, v0, #2
+ sshll.4s v0, v0, #3
+ sshll2.4s v0, v0, #4
+ sshll.2d v0, v0, #5
+ sshll2.2d v0, v0, #6
+ sshr.8b v0, v0, #1
+ sshr.16b v0, v0, #2
+ sshr.4h v0, v0, #3
+ sshr.8h v0, v0, #4
+ sshr.2s v0, v0, #5
+ sshr.4s v0, v0, #6
+ sshr.2d v0, v0, #7
+ sshr.8b v0, v0, #1
+ ssra.16b v0, v0, #2
+ ssra.4h v0, v0, #3
+ ssra.8h v0, v0, #4
+ ssra.2s v0, v0, #5
+ ssra.4s v0, v0, #6
+ ssra.2d v0, v0, #7
+ ssra d0, d0, #64
+ ucvtf.2s v0, v0, #1
+ ucvtf.4s v0, v0, #2
+ ucvtf.2d v0, v0, #3
+ uqrshrn.8b v0, v0, #1
+ uqrshrn2.16b v0, v0, #2
+ uqrshrn.4h v0, v0, #3
+ uqrshrn2.8h v0, v0, #4
+ uqrshrn.2s v0, v0, #5
+ uqrshrn2.4s v0, v0, #6
+ uqshl.8b v0, v0, #1
+ uqshl.16b v0, v0, #2
+ uqshl.4h v0, v0, #3
+ uqshl.8h v0, v0, #4
+ uqshl.2s v0, v0, #5
+ uqshl.4s v0, v0, #6
+ uqshl.2d v0, v0, #7
+ uqshrn.8b v0, v0, #1
+ uqshrn2.16b v0, v0, #2
+ uqshrn.4h v0, v0, #3
+ uqshrn2.8h v0, v0, #4
+ uqshrn.2s v0, v0, #5
+ uqshrn2.4s v0, v0, #6
+ urshr.8b v0, v0, #1
+ urshr.16b v0, v0, #2
+ urshr.4h v0, v0, #3
+ urshr.8h v0, v0, #4
+ urshr.2s v0, v0, #5
+ urshr.4s v0, v0, #6
+ urshr.2d v0, v0, #7
+ ursra.8b v0, v0, #1
+ ursra.16b v0, v0, #2
+ ursra.4h v0, v0, #3
+ ursra.8h v0, v0, #4
+ ursra.2s v0, v0, #5
+ ursra.4s v0, v0, #6
+ ursra.2d v0, v0, #7
+ ushll.8h v0, v0, #1
+ ushll2.8h v0, v0, #2
+ ushll.4s v0, v0, #3
+ ushll2.4s v0, v0, #4
+ ushll.2d v0, v0, #5
+ ushll2.2d v0, v0, #6
+ ushr.8b v0, v0, #1
+ ushr.16b v0, v0, #2
+ ushr.4h v0, v0, #3
+ ushr.8h v0, v0, #4
+ ushr.2s v0, v0, #5
+ ushr.4s v0, v0, #6
+ ushr.2d v0, v0, #7
+ usra.8b v0, v0, #1
+ usra.16b v0, v0, #2
+ usra.4h v0, v0, #3
+ usra.8h v0, v0, #4
+ usra.2s v0, v0, #5
+ usra.4s v0, v0, #6
+ usra.2d v0, v0, #7
+
+; CHECK: fcvtzs.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x0f]
+; CHECK: fcvtzs.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x4f]
+; CHECK: fcvtzs.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x4f]
+; CHECK: fcvtzu.2s v0, v0, #1 ; encoding: [0x00,0xfc,0x3f,0x2f]
+; CHECK: fcvtzu.4s v0, v0, #2 ; encoding: [0x00,0xfc,0x3e,0x6f]
+; CHECK: fcvtzu.2d v0, v0, #3 ; encoding: [0x00,0xfc,0x7d,0x6f]
+; CHECK: rshrn.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x0f]
+; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
+; CHECK: rshrn.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x0f]
+; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
+; CHECK: rshrn.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x0f]
+; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
+; CHECK: scvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x0f]
+; CHECK: scvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x4f]
+; CHECK: scvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x4f]
+; CHECK: shl.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x0f]
+; CHECK: shl.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x4f]
+; CHECK: shl.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x0f]
+; CHECK: shl.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x4f]
+; CHECK: shl.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x0f]
+; CHECK: shl.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x4f]
+; CHECK: shl.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x4f]
+; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f]
+; CHECK: shrn2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x4f]
+; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f]
+; CHECK: shrn2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x4f]
+; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f]
+; CHECK: shrn2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x4f]
+; CHECK: sli.8b v0, v0, #1 ; encoding: [0x00,0x54,0x09,0x2f]
+; CHECK: sli.16b v0, v0, #2 ; encoding: [0x00,0x54,0x0a,0x6f]
+; CHECK: sli.4h v0, v0, #3 ; encoding: [0x00,0x54,0x13,0x2f]
+; CHECK: sli.8h v0, v0, #4 ; encoding: [0x00,0x54,0x14,0x6f]
+; CHECK: sli.2s v0, v0, #5 ; encoding: [0x00,0x54,0x25,0x2f]
+; CHECK: sli.4s v0, v0, #6 ; encoding: [0x00,0x54,0x26,0x6f]
+; CHECK: sli.2d v0, v0, #7 ; encoding: [0x00,0x54,0x47,0x6f]
+; CHECK: sqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x0f]
+; CHECK: sqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x4f]
+; CHECK: sqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x0f]
+; CHECK: sqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x4f]
+; CHECK: sqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x0f]
+; CHECK: sqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x4f]
+; CHECK: sqrshrun.8b v0, v0, #1 ; encoding: [0x00,0x8c,0x0f,0x2f]
+; CHECK: sqrshrun2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x6f]
+; CHECK: sqrshrun.4h v0, v0, #3 ; encoding: [0x00,0x8c,0x1d,0x2f]
+; CHECK: sqrshrun2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x6f]
+; CHECK: sqrshrun.2s v0, v0, #5 ; encoding: [0x00,0x8c,0x3b,0x2f]
+; CHECK: sqrshrun2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x6f]
+; CHECK: sqshlu.8b v0, v0, #1 ; encoding: [0x00,0x64,0x09,0x2f]
+; CHECK: sqshlu.16b v0, v0, #2 ; encoding: [0x00,0x64,0x0a,0x6f]
+; CHECK: sqshlu.4h v0, v0, #3 ; encoding: [0x00,0x64,0x13,0x2f]
+; CHECK: sqshlu.8h v0, v0, #4 ; encoding: [0x00,0x64,0x14,0x6f]
+; CHECK: sqshlu.2s v0, v0, #5 ; encoding: [0x00,0x64,0x25,0x2f]
+; CHECK: sqshlu.4s v0, v0, #6 ; encoding: [0x00,0x64,0x26,0x6f]
+; CHECK: sqshlu.2d v0, v0, #7 ; encoding: [0x00,0x64,0x47,0x6f]
+; CHECK: sqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x0f]
+; CHECK: sqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x4f]
+; CHECK: sqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x0f]
+; CHECK: sqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x4f]
+; CHECK: sqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x0f]
+; CHECK: sqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x4f]
+; CHECK: sqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x4f]
+; CHECK: sqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x0f]
+; CHECK: sqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x4f]
+; CHECK: sqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x0f]
+; CHECK: sqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x4f]
+; CHECK: sqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x0f]
+; CHECK: sqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x4f]
+; CHECK: sqshrun.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x2f]
+; CHECK: sqshrun2.16b v0, v0, #2 ; encoding: [0x00,0x84,0x0e,0x6f]
+; CHECK: sqshrun.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x2f]
+; CHECK: sqshrun2.8h v0, v0, #4 ; encoding: [0x00,0x84,0x1c,0x6f]
+; CHECK: sqshrun.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x2f]
+; CHECK: sqshrun2.4s v0, v0, #6 ; encoding: [0x00,0x84,0x3a,0x6f]
+; CHECK: sri.8b v0, v0, #1 ; encoding: [0x00,0x44,0x0f,0x2f]
+; CHECK: sri.16b v0, v0, #2 ; encoding: [0x00,0x44,0x0e,0x6f]
+; CHECK: sri.4h v0, v0, #3 ; encoding: [0x00,0x44,0x1d,0x2f]
+; CHECK: sri.8h v0, v0, #4 ; encoding: [0x00,0x44,0x1c,0x6f]
+; CHECK: sri.2s v0, v0, #5 ; encoding: [0x00,0x44,0x3b,0x2f]
+; CHECK: sri.4s v0, v0, #6 ; encoding: [0x00,0x44,0x3a,0x6f]
+; CHECK: sri.2d v0, v0, #7 ; encoding: [0x00,0x44,0x79,0x6f]
+; CHECK: srshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x0f]
+; CHECK: srshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x4f]
+; CHECK: srshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x0f]
+; CHECK: srshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x4f]
+; CHECK: srshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x0f]
+; CHECK: srshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x4f]
+; CHECK: srshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x4f]
+; CHECK: srsra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x0f]
+; CHECK: srsra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x4f]
+; CHECK: srsra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x0f]
+; CHECK: srsra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x4f]
+; CHECK: srsra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x0f]
+; CHECK: srsra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x4f]
+; CHECK: srsra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x4f]
+; CHECK: sshll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x0f]
+; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f]
+; CHECK: sshll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x0f]
+; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f]
+; CHECK: sshll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x0f]
+; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f]
+; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f]
+; CHECK: sshr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x4f]
+; CHECK: sshr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x0f]
+; CHECK: sshr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x4f]
+; CHECK: sshr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x0f]
+; CHECK: sshr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x4f]
+; CHECK: sshr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x4f]
+; CHECK: sshr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x0f]
+; CHECK: ssra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x4f]
+; CHECK: ssra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x0f]
+; CHECK: ssra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x4f]
+; CHECK: ssra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x0f]
+; CHECK: ssra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x4f]
+; CHECK: ssra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x4f]
+; CHECK: ssra d0, d0, #64 ; encoding: [0x00,0x14,0x40,0x5f]
+; CHECK: ucvtf.2s v0, v0, #1 ; encoding: [0x00,0xe4,0x3f,0x2f]
+; CHECK: ucvtf.4s v0, v0, #2 ; encoding: [0x00,0xe4,0x3e,0x6f]
+; CHECK: ucvtf.2d v0, v0, #3 ; encoding: [0x00,0xe4,0x7d,0x6f]
+; CHECK: uqrshrn.8b v0, v0, #1 ; encoding: [0x00,0x9c,0x0f,0x2f]
+; CHECK: uqrshrn2.16b v0, v0, #2 ; encoding: [0x00,0x9c,0x0e,0x6f]
+; CHECK: uqrshrn.4h v0, v0, #3 ; encoding: [0x00,0x9c,0x1d,0x2f]
+; CHECK: uqrshrn2.8h v0, v0, #4 ; encoding: [0x00,0x9c,0x1c,0x6f]
+; CHECK: uqrshrn.2s v0, v0, #5 ; encoding: [0x00,0x9c,0x3b,0x2f]
+; CHECK: uqrshrn2.4s v0, v0, #6 ; encoding: [0x00,0x9c,0x3a,0x6f]
+; CHECK: uqshl.8b v0, v0, #1 ; encoding: [0x00,0x74,0x09,0x2f]
+; CHECK: uqshl.16b v0, v0, #2 ; encoding: [0x00,0x74,0x0a,0x6f]
+; CHECK: uqshl.4h v0, v0, #3 ; encoding: [0x00,0x74,0x13,0x2f]
+; CHECK: uqshl.8h v0, v0, #4 ; encoding: [0x00,0x74,0x14,0x6f]
+; CHECK: uqshl.2s v0, v0, #5 ; encoding: [0x00,0x74,0x25,0x2f]
+; CHECK: uqshl.4s v0, v0, #6 ; encoding: [0x00,0x74,0x26,0x6f]
+; CHECK: uqshl.2d v0, v0, #7 ; encoding: [0x00,0x74,0x47,0x6f]
+; CHECK: uqshrn.8b v0, v0, #1 ; encoding: [0x00,0x94,0x0f,0x2f]
+; CHECK: uqshrn2.16b v0, v0, #2 ; encoding: [0x00,0x94,0x0e,0x6f]
+; CHECK: uqshrn.4h v0, v0, #3 ; encoding: [0x00,0x94,0x1d,0x2f]
+; CHECK: uqshrn2.8h v0, v0, #4 ; encoding: [0x00,0x94,0x1c,0x6f]
+; CHECK: uqshrn.2s v0, v0, #5 ; encoding: [0x00,0x94,0x3b,0x2f]
+; CHECK: uqshrn2.4s v0, v0, #6 ; encoding: [0x00,0x94,0x3a,0x6f]
+; CHECK: urshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x2f]
+; CHECK: urshr.16b v0, v0, #2 ; encoding: [0x00,0x24,0x0e,0x6f]
+; CHECK: urshr.4h v0, v0, #3 ; encoding: [0x00,0x24,0x1d,0x2f]
+; CHECK: urshr.8h v0, v0, #4 ; encoding: [0x00,0x24,0x1c,0x6f]
+; CHECK: urshr.2s v0, v0, #5 ; encoding: [0x00,0x24,0x3b,0x2f]
+; CHECK: urshr.4s v0, v0, #6 ; encoding: [0x00,0x24,0x3a,0x6f]
+; CHECK: urshr.2d v0, v0, #7 ; encoding: [0x00,0x24,0x79,0x6f]
+; CHECK: ursra.8b v0, v0, #1 ; encoding: [0x00,0x34,0x0f,0x2f]
+; CHECK: ursra.16b v0, v0, #2 ; encoding: [0x00,0x34,0x0e,0x6f]
+; CHECK: ursra.4h v0, v0, #3 ; encoding: [0x00,0x34,0x1d,0x2f]
+; CHECK: ursra.8h v0, v0, #4 ; encoding: [0x00,0x34,0x1c,0x6f]
+; CHECK: ursra.2s v0, v0, #5 ; encoding: [0x00,0x34,0x3b,0x2f]
+; CHECK: ursra.4s v0, v0, #6 ; encoding: [0x00,0x34,0x3a,0x6f]
+; CHECK: ursra.2d v0, v0, #7 ; encoding: [0x00,0x34,0x79,0x6f]
+; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f]
+; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f]
+; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f]
+; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f]
+; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f]
+; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f]
+; CHECK: ushr.8b v0, v0, #1 ; encoding: [0x00,0x04,0x0f,0x2f]
+; CHECK: ushr.16b v0, v0, #2 ; encoding: [0x00,0x04,0x0e,0x6f]
+; CHECK: ushr.4h v0, v0, #3 ; encoding: [0x00,0x04,0x1d,0x2f]
+; CHECK: ushr.8h v0, v0, #4 ; encoding: [0x00,0x04,0x1c,0x6f]
+; CHECK: ushr.2s v0, v0, #5 ; encoding: [0x00,0x04,0x3b,0x2f]
+; CHECK: ushr.4s v0, v0, #6 ; encoding: [0x00,0x04,0x3a,0x6f]
+; CHECK: ushr.2d v0, v0, #7 ; encoding: [0x00,0x04,0x79,0x6f]
+; CHECK: usra.8b v0, v0, #1 ; encoding: [0x00,0x14,0x0f,0x2f]
+; CHECK: usra.16b v0, v0, #2 ; encoding: [0x00,0x14,0x0e,0x6f]
+; CHECK: usra.4h v0, v0, #3 ; encoding: [0x00,0x14,0x1d,0x2f]
+; CHECK: usra.8h v0, v0, #4 ; encoding: [0x00,0x14,0x1c,0x6f]
+; CHECK: usra.2s v0, v0, #5 ; encoding: [0x00,0x14,0x3b,0x2f]
+; CHECK: usra.4s v0, v0, #6 ; encoding: [0x00,0x14,0x3a,0x6f]
+; CHECK: usra.2d v0, v0, #7 ; encoding: [0x00,0x14,0x79,0x6f]
+
+
+; ARM Verbose syntax variants.
+
+ rshrn v9.8b, v11.8h, #1
+ rshrn2 v8.16b, v9.8h, #2
+ rshrn v7.4h, v8.4s, #3
+ rshrn2 v6.8h, v7.4s, #4
+ rshrn v5.2s, v6.2d, #5
+ rshrn2 v4.4s, v5.2d, #6
+
+ shrn v9.8b, v11.8h, #1
+ shrn2 v8.16b, v9.8h, #2
+ shrn v7.4h, v8.4s, #3
+ shrn2 v6.8h, v7.4s, #4
+ shrn v5.2s, v6.2d, #5
+ shrn2 v4.4s, v5.2d, #6
+
+ sqrshrn v9.8b, v11.8h, #1
+ sqrshrn2 v8.16b, v9.8h, #2
+ sqrshrn v7.4h, v8.4s, #3
+ sqrshrn2 v6.8h, v7.4s, #4
+ sqrshrn v5.2s, v6.2d, #5
+ sqrshrn2 v4.4s, v5.2d, #6
+
+ sqshrn v9.8b, v11.8h, #1
+ sqshrn2 v8.16b, v9.8h, #2
+ sqshrn v7.4h, v8.4s, #3
+ sqshrn2 v6.8h, v7.4s, #4
+ sqshrn v5.2s, v6.2d, #5
+ sqshrn2 v4.4s, v5.2d, #6
+
+ sqrshrun v9.8b, v11.8h, #1
+ sqrshrun2 v8.16b, v9.8h, #2
+ sqrshrun v7.4h, v8.4s, #3
+ sqrshrun2 v6.8h, v7.4s, #4
+ sqrshrun v5.2s, v6.2d, #5
+ sqrshrun2 v4.4s, v5.2d, #6
+
+ sqshrun v9.8b, v11.8h, #1
+ sqshrun2 v8.16b, v9.8h, #2
+ sqshrun v7.4h, v8.4s, #3
+ sqshrun2 v6.8h, v7.4s, #4
+ sqshrun v5.2s, v6.2d, #5
+ sqshrun2 v4.4s, v5.2d, #6
+
+ uqrshrn v9.8b, v11.8h, #1
+ uqrshrn2 v8.16b, v9.8h, #2
+ uqrshrn v7.4h, v8.4s, #3
+ uqrshrn2 v6.8h, v7.4s, #4
+ uqrshrn v5.2s, v6.2d, #5
+ uqrshrn2 v4.4s, v5.2d, #6
+
+ uqshrn v9.8b, v11.8h, #1
+ uqshrn2 v8.16b, v9.8h, #2
+ uqshrn v7.4h, v8.4s, #3
+ uqshrn2 v6.8h, v7.4s, #4
+ uqshrn v5.2s, v6.2d, #5
+ uqshrn2 v4.4s, v5.2d, #6
+
+ sshll2 v10.8h, v3.16b, #6
+ sshll2 v11.4s, v4.8h, #5
+ sshll2 v12.2d, v5.4s, #4
+ sshll v13.8h, v6.8b, #3
+ sshll v14.4s, v7.4h, #2
+ sshll v15.2d, v8.2s, #7
+
+ ushll2 v10.8h, v3.16b, #6
+ ushll2 v11.4s, v4.8h, #5
+ ushll2 v12.2d, v5.4s, #4
+ ushll v13.8h, v6.8b, #3
+ ushll v14.4s, v7.4h, #2
+ ushll v15.2d, v8.2s, #7
+
+
+; CHECK: rshrn.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x0f]
+; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
+; CHECK: rshrn.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x0f]
+; CHECK: rshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x4f]
+; CHECK: rshrn.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x0f]
+; CHECK: rshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x4f]
+; CHECK: shrn.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x0f]
+; CHECK: shrn2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x4f]
+; CHECK: shrn.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x0f]
+; CHECK: shrn2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x4f]
+; CHECK: shrn.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x0f]
+; CHECK: shrn2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x4f]
+; CHECK: sqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x0f]
+; CHECK: sqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x4f]
+; CHECK: sqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x0f]
+; CHECK: sqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x4f]
+; CHECK: sqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x0f]
+; CHECK: sqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x4f]
+; CHECK: sqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x0f]
+; CHECK: sqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x4f]
+; CHECK: sqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x0f]
+; CHECK: sqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x4f]
+; CHECK: sqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x0f]
+; CHECK: sqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x4f]
+; CHECK: sqrshrun.8b v9, v11, #1 ; encoding: [0x69,0x8d,0x0f,0x2f]
+; CHECK: sqrshrun2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x6f]
+; CHECK: sqrshrun.4h v7, v8, #3 ; encoding: [0x07,0x8d,0x1d,0x2f]
+; CHECK: sqrshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x8c,0x1c,0x6f]
+; CHECK: sqrshrun.2s v5, v6, #5 ; encoding: [0xc5,0x8c,0x3b,0x2f]
+; CHECK: sqrshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x8c,0x3a,0x6f]
+; CHECK: sqshrun.8b v9, v11, #1 ; encoding: [0x69,0x85,0x0f,0x2f]
+; CHECK: sqshrun2.16b v8, v9, #2 ; encoding: [0x28,0x85,0x0e,0x6f]
+; CHECK: sqshrun.4h v7, v8, #3 ; encoding: [0x07,0x85,0x1d,0x2f]
+; CHECK: sqshrun2.8h v6, v7, #4 ; encoding: [0xe6,0x84,0x1c,0x6f]
+; CHECK: sqshrun.2s v5, v6, #5 ; encoding: [0xc5,0x84,0x3b,0x2f]
+; CHECK: sqshrun2.4s v4, v5, #6 ; encoding: [0xa4,0x84,0x3a,0x6f]
+; CHECK: uqrshrn.8b v9, v11, #1 ; encoding: [0x69,0x9d,0x0f,0x2f]
+; CHECK: uqrshrn2.16b v8, v9, #2 ; encoding: [0x28,0x9d,0x0e,0x6f]
+; CHECK: uqrshrn.4h v7, v8, #3 ; encoding: [0x07,0x9d,0x1d,0x2f]
+; CHECK: uqrshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x9c,0x1c,0x6f]
+; CHECK: uqrshrn.2s v5, v6, #5 ; encoding: [0xc5,0x9c,0x3b,0x2f]
+; CHECK: uqrshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x9c,0x3a,0x6f]
+; CHECK: uqshrn.8b v9, v11, #1 ; encoding: [0x69,0x95,0x0f,0x2f]
+; CHECK: uqshrn2.16b v8, v9, #2 ; encoding: [0x28,0x95,0x0e,0x6f]
+; CHECK: uqshrn.4h v7, v8, #3 ; encoding: [0x07,0x95,0x1d,0x2f]
+; CHECK: uqshrn2.8h v6, v7, #4 ; encoding: [0xe6,0x94,0x1c,0x6f]
+; CHECK: uqshrn.2s v5, v6, #5 ; encoding: [0xc5,0x94,0x3b,0x2f]
+; CHECK: uqshrn2.4s v4, v5, #6 ; encoding: [0xa4,0x94,0x3a,0x6f]
+; CHECK: sshll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x4f]
+; CHECK: sshll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x4f]
+; CHECK: sshll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x4f]
+; CHECK: sshll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x0f]
+; CHECK: sshll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x0f]
+; CHECK: sshll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x0f]
+; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f]
+; CHECK: ushll2.4s v11, v4, #5 ; encoding: [0x8b,0xa4,0x15,0x6f]
+; CHECK: ushll2.2d v12, v5, #4 ; encoding: [0xac,0xa4,0x24,0x6f]
+; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f]
+; CHECK: ushll.4s v14, v7, #2 ; encoding: [0xee,0xa4,0x12,0x2f]
+; CHECK: ushll.2d v15, v8, #7 ; encoding: [0x0f,0xa5,0x27,0x2f]
+
+
+ pmull.8h v0, v0, v0
+ pmull2.8h v0, v0, v0
+ pmull.1q v2, v3, v4
+ pmull2.1q v2, v3, v4
+ pmull v2.1q, v3.1d, v4.1d
+ pmull2 v2.1q, v3.2d, v4.2d
+
+; CHECK: pmull.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x0e]
+; CHECK: pmull2.8h v0, v0, v0 ; encoding: [0x00,0xe0,0x20,0x4e]
+; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
+; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e]
+; CHECK: pmull.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x0e]
+; CHECK: pmull2.1q v2, v3, v4 ; encoding: [0x62,0xe0,0xe4,0x4e]
+
+
+ faddp.2d d1, v2
+ faddp.2s s3, v4
+; CHECK: faddp.2d d1, v2 ; encoding: [0x41,0xd8,0x70,0x7e]
+; CHECK: faddp.2s s3, v4 ; encoding: [0x83,0xd8,0x30,0x7e]
+
+ tbl.16b v2, {v4,v5,v6,v7}, v1
+ tbl.8b v0, {v4,v5,v6,v7}, v1
+ tbl.16b v2, {v5}, v1
+ tbl.8b v0, {v5}, v1
+ tbl.16b v2, {v5,v6,v7}, v1
+ tbl.8b v0, {v5,v6,v7}, v1
+ tbl.16b v2, {v6,v7}, v1
+ tbl.8b v0, {v6,v7}, v1
+; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e]
+; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e]
+; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e]
+; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e]
+; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e]
+; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e]
+; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e]
+; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e]
+
+ tbl v2.16b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.16b
+ tbl v0.8b, {v4.16b,v5.16b,v6.16b,v7.16b}, v1.8b
+ tbl v2.16b, {v5.16b}, v1.16b
+ tbl v0.8b, {v5.16b}, v1.8b
+ tbl v2.16b, {v5.16b,v6.16b,v7.16b}, v1.16b
+ tbl v0.8b, {v5.16b,v6.16b,v7.16b}, v1.8b
+ tbl v2.16b, {v6.16b,v7.16b}, v1.16b
+ tbl v0.8b, {v6.16b,v7.16b}, v1.8b
+; CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 ; encoding: [0x82,0x60,0x01,0x4e]
+; CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 ; encoding: [0x80,0x60,0x01,0x0e]
+; CHECK: tbl.16b v2, { v5 }, v1 ; encoding: [0xa2,0x00,0x01,0x4e]
+; CHECK: tbl.8b v0, { v5 }, v1 ; encoding: [0xa0,0x00,0x01,0x0e]
+; CHECK: tbl.16b v2, { v5, v6, v7 }, v1 ; encoding: [0xa2,0x40,0x01,0x4e]
+; CHECK: tbl.8b v0, { v5, v6, v7 }, v1 ; encoding: [0xa0,0x40,0x01,0x0e]
+; CHECK: tbl.16b v2, { v6, v7 }, v1 ; encoding: [0xc2,0x20,0x01,0x4e]
+; CHECK: tbl.8b v0, { v6, v7 }, v1 ; encoding: [0xc0,0x20,0x01,0x0e]
+
+ sqdmull s0, h0, h0
+ sqdmull d0, s0, s0
+; CHECK: sqdmull s0, h0, h0 ; encoding: [0x00,0xd0,0x60,0x5e]
+; CHECK: sqdmull d0, s0, s0 ; encoding: [0x00,0xd0,0xa0,0x5e]
+
+ frsqrte s0, s0
+ frsqrte d0, d0
+; CHECK: frsqrte s0, s0 ; encoding: [0x00,0xd8,0xa1,0x7e]
+; CHECK: frsqrte d0, d0 ; encoding: [0x00,0xd8,0xe1,0x7e]
+
+ mov.16b v0, v0
+ mov.2s v0, v0
+; CHECK: orr.16b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x4e]
+; CHECK: orr.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e]
+
+
+; uadalp/sadalp verbose mode aliases.
+ uadalp v14.4h, v25.8b
+ uadalp v15.8h, v24.16b
+ uadalp v16.2s, v23.4h
+ uadalp v17.4s, v22.8h
+ uadalp v18.1d, v21.2s
+ uadalp v19.2d, v20.4s
+
+ sadalp v1.4h, v11.8b
+ sadalp v2.8h, v12.16b
+ sadalp v3.2s, v13.4h
+ sadalp v4.4s, v14.8h
+ sadalp v5.1d, v15.2s
+ sadalp v6.2d, v16.4s
+
+; CHECK: uadalp.4h v14, v25 ; encoding: [0x2e,0x6b,0x20,0x2e]
+; CHECK: uadalp.8h v15, v24 ; encoding: [0x0f,0x6b,0x20,0x6e]
+; CHECK: uadalp.2s v16, v23 ; encoding: [0xf0,0x6a,0x60,0x2e]
+; CHECK: uadalp.4s v17, v22 ; encoding: [0xd1,0x6a,0x60,0x6e]
+; CHECK: uadalp.1d v18, v21 ; encoding: [0xb2,0x6a,0xa0,0x2e]
+; CHECK: uadalp.2d v19, v20 ; encoding: [0x93,0x6a,0xa0,0x6e]
+; CHECK: sadalp.4h v1, v11 ; encoding: [0x61,0x69,0x20,0x0e]
+; CHECK: sadalp.8h v2, v12 ; encoding: [0x82,0x69,0x20,0x4e]
+; CHECK: sadalp.2s v3, v13 ; encoding: [0xa3,0x69,0x60,0x0e]
+; CHECK: sadalp.4s v4, v14 ; encoding: [0xc4,0x69,0x60,0x4e]
+; CHECK: sadalp.1d v5, v15 ; encoding: [0xe5,0x69,0xa0,0x0e]
+; CHECK: sadalp.2d v6, v16 ; encoding: [0x06,0x6a,0xa0,0x4e]
+
+; MVN is an alias for 'not'.
+ mvn v1.8b, v4.8b
+ mvn v19.16b, v17.16b
+ mvn.8b v10, v6
+ mvn.16b v11, v7
+
+; CHECK: not.8b v1, v4 ; encoding: [0x81,0x58,0x20,0x2e]
+; CHECK: not.16b v19, v17 ; encoding: [0x33,0x5a,0x20,0x6e]
+; CHECK: not.8b v10, v6 ; encoding: [0xca,0x58,0x20,0x2e]
+; CHECK: not.16b v11, v7 ; encoding: [0xeb,0x58,0x20,0x6e]
+
+; sqdmull verbose mode aliases
+ sqdmull v10.4s, v12.4h, v12.4h
+ sqdmull2 v10.4s, v13.8h, v13.8h
+ sqdmull v10.2d, v13.2s, v13.2s
+ sqdmull2 v10.2d, v13.4s, v13.4s
+; CHECK: sqdmull.4s v10, v12, v12 ; encoding: [0x8a,0xd1,0x6c,0x0e]
+; CHECK: sqdmull2.4s v10, v13, v13 ; encoding: [0xaa,0xd1,0x6d,0x4e]
+; CHECK: sqdmull.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x0e]
+; CHECK: sqdmull2.2d v10, v13, v13 ; encoding: [0xaa,0xd1,0xad,0x4e]
+
+; xtn verbose mode aliases
+ xtn v14.8b, v14.8h
+ xtn2 v14.16b, v14.8h
+ xtn v14.4h, v14.4s
+ xtn2 v14.8h, v14.4s
+ xtn v14.2s, v14.2d
+ xtn2 v14.4s, v14.2d
+; CHECK: xtn.8b v14, v14 ; encoding: [0xce,0x29,0x21,0x0e]
+; CHECK: xtn2.16b v14, v14 ; encoding: [0xce,0x29,0x21,0x4e]
+; CHECK: xtn.4h v14, v14 ; encoding: [0xce,0x29,0x61,0x0e]
+; CHECK: xtn2.8h v14, v14 ; encoding: [0xce,0x29,0x61,0x4e]
+; CHECK: xtn.2s v14, v14 ; encoding: [0xce,0x29,0xa1,0x0e]
+; CHECK: xtn2.4s v14, v14 ; encoding: [0xce,0x29,0xa1,0x4e]
+
+; uaddl verbose mode aliases
+ uaddl v9.8h, v13.8b, v14.8b
+ uaddl2 v9.8h, v13.16b, v14.16b
+ uaddl v9.4s, v13.4h, v14.4h
+ uaddl2 v9.4s, v13.8h, v14.8h
+ uaddl v9.2d, v13.2s, v14.2s
+ uaddl2 v9.2d, v13.4s, v14.4s
+; CHECK: uaddl.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x2e]
+; CHECK: uaddl2.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x6e]
+; CHECK: uaddl.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x2e]
+; CHECK: uaddl2.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x6e]
+; CHECK: uaddl.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x2e]
+; CHECK: uaddl2.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x6e]
+
+; bit verbose mode aliases
+ bit v9.16b, v10.16b, v10.16b
+ bit v9.8b, v10.8b, v10.8b
+; CHECK: bit.16b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x6e]
+; CHECK: bit.8b v9, v10, v10 ; encoding: [0x49,0x1d,0xaa,0x2e]
+
+; pmull verbose mode aliases
+ pmull v8.8h, v8.8b, v8.8b
+ pmull2 v8.8h, v8.16b, v8.16b
+ pmull v8.1q, v8.1d, v8.1d
+ pmull2 v8.1q, v8.2d, v8.2d
+; CHECK: pmull.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x0e]
+; CHECK: pmull2.8h v8, v8, v8 ; encoding: [0x08,0xe1,0x28,0x4e]
+; CHECK: pmull.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x0e]
+; CHECK: pmull2.1q v8, v8, v8 ; encoding: [0x08,0xe1,0xe8,0x4e]
+
+; usubl verbose mode aliases
+ usubl v9.8h, v13.8b, v14.8b
+ usubl2 v9.8h, v13.16b, v14.16b
+ usubl v9.4s, v13.4h, v14.4h
+ usubl2 v9.4s, v13.8h, v14.8h
+ usubl v9.2d, v13.2s, v14.2s
+ usubl2 v9.2d, v13.4s, v14.4s
+; CHECK: usubl.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x2e]
+; CHECK: usubl2.8h v9, v13, v14 ; encoding: [0xa9,0x21,0x2e,0x6e]
+; CHECK: usubl.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x2e]
+; CHECK: usubl2.4s v9, v13, v14 ; encoding: [0xa9,0x21,0x6e,0x6e]
+; CHECK: usubl.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x2e]
+; CHECK: usubl2.2d v9, v13, v14 ; encoding: [0xa9,0x21,0xae,0x6e]
+
+; uabdl verbose mode aliases
+ uabdl v9.8h, v13.8b, v14.8b
+ uabdl2 v9.8h, v13.16b, v14.16b
+ uabdl v9.4s, v13.4h, v14.4h
+ uabdl2 v9.4s, v13.8h, v14.8h
+ uabdl v9.2d, v13.2s, v14.2s
+ uabdl2 v9.2d, v13.4s, v14.4s
+; CHECK: uabdl.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x2e]
+; CHECK: uabdl2.8h v9, v13, v14 ; encoding: [0xa9,0x71,0x2e,0x6e]
+; CHECK: uabdl.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x2e]
+; CHECK: uabdl2.4s v9, v13, v14 ; encoding: [0xa9,0x71,0x6e,0x6e]
+; CHECK: uabdl.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x2e]
+; CHECK: uabdl2.2d v9, v13, v14 ; encoding: [0xa9,0x71,0xae,0x6e]
+
+; umull verbose mode aliases
+ umull v9.8h, v13.8b, v14.8b
+ umull2 v9.8h, v13.16b, v14.16b
+ umull v9.4s, v13.4h, v14.4h
+ umull2 v9.4s, v13.8h, v14.8h
+ umull v9.2d, v13.2s, v14.2s
+ umull2 v9.2d, v13.4s, v14.4s
+; CHECK: umull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x2e]
+; CHECK: umull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x6e]
+; CHECK: umull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x2e]
+; CHECK: umull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x6e]
+; CHECK: umull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x2e]
+; CHECK: umull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x6e]
+
+; smull verbose mode aliases
+ smull v9.8h, v13.8b, v14.8b
+ smull2 v9.8h, v13.16b, v14.16b
+ smull v9.4s, v13.4h, v14.4h
+ smull2 v9.4s, v13.8h, v14.8h
+ smull v9.2d, v13.2s, v14.2s
+ smull2 v9.2d, v13.4s, v14.4s
+; CHECK: smull.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x0e]
+; CHECK: smull2.8h v9, v13, v14 ; encoding: [0xa9,0xc1,0x2e,0x4e]
+; CHECK: smull.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x0e]
+; CHECK: smull2.4s v9, v13, v14 ; encoding: [0xa9,0xc1,0x6e,0x4e]
+; CHECK: smull.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x0e]
+; CHECK: smull2.2d v9, v13, v14 ; encoding: [0xa9,0xc1,0xae,0x4e]
Added: llvm/trunk/test/MC/ARM64/aliases.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/aliases.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/aliases.s (added)
+++ llvm/trunk/test/MC/ARM64/aliases.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,733 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s
+
+foo:
+;-----------------------------------------------------------------------------
+; ADD #0 to/from SP/WSP is a MOV
+;-----------------------------------------------------------------------------
+ add x1, sp, #0
+; CHECK: mov x1, sp
+ add sp, x2, #0
+; CHECK: mov sp, x2
+ add w3, wsp, #0
+; CHECK: mov w3, wsp
+ add wsp, w4, #0
+; CHECK: mov wsp, w4
+ mov x5, sp
+; CHECK: mov x5, sp
+ mov sp, x6
+; CHECK: mov sp, x6
+ mov w7, wsp
+; CHECK: mov w7, wsp
+ mov wsp, w8
+; CHECK: mov wsp, w8
+
+;-----------------------------------------------------------------------------
+; ORR Rd, Rn, Rn is a MOV
+;-----------------------------------------------------------------------------
+ orr x2, xzr, x9
+; CHECK: mov x2, x9
+ orr w2, wzr, w9
+; CHECK: mov w2, w9
+ mov x3, x4
+; CHECK: mov x3, x4
+ mov w5, w6
+; CHECK: mov w5, w6
+
+;-----------------------------------------------------------------------------
+; TST Xn, #<imm>
+;-----------------------------------------------------------------------------
+ tst w1, #3
+ tst x1, #3
+ tst w1, w2
+ tst x1, x2
+ ands wzr, w1, w2, lsl #2
+ ands xzr, x1, x2, lsl #3
+ tst w3, w7, lsl #31
+ tst x2, x20, asr #0
+
+; CHECK: tst w1, #0x3 ; encoding: [0x3f,0x04,0x00,0x72]
+; CHECK: tst x1, #0x3 ; encoding: [0x3f,0x04,0x40,0xf2]
+; CHECK: tst w1, w2 ; encoding: [0x3f,0x00,0x02,0x6a]
+; CHECK: tst x1, x2 ; encoding: [0x3f,0x00,0x02,0xea]
+; CHECK: tst w1, w2, lsl #2 ; encoding: [0x3f,0x08,0x02,0x6a]
+; CHECK: tst x1, x2, lsl #3 ; encoding: [0x3f,0x0c,0x02,0xea]
+; CHECK: tst w3, w7, lsl #31 ; encoding: [0x7f,0x7c,0x07,0x6a]
+; CHECK: tst x2, x20, asr #0 ; encoding: [0x5f,0x00,0x94,0xea]
+
+;-----------------------------------------------------------------------------
+; ADDS to WZR/XZR is a CMN
+;-----------------------------------------------------------------------------
+ cmn w1, #3, lsl #0
+ cmn x2, #4194304
+ cmn w4, w5
+ cmn x6, x7
+ cmn w8, w9, asr #3
+ cmn x2, x3, lsr #4
+ cmn x2, w3, uxtb #1
+ cmn x4, x5, uxtx #1
+
+; CHECK: cmn w1, #3 ; encoding: [0x3f,0x0c,0x00,0x31]
+; CHECK: cmn x2, #4194304 ; encoding: [0x5f,0x00,0x50,0xb1]
+; CHECK: cmn w4, w5 ; encoding: [0x9f,0x00,0x05,0x2b]
+; CHECK: cmn x6, x7 ; encoding: [0xdf,0x00,0x07,0xab]
+; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b]
+; CHECK: cmn x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xab]
+; CHECK: cmn x2, w3, uxtb #1 ; encoding: [0x5f,0x04,0x23,0xab]
+; CHECK: cmn x4, x5, uxtx #1 ; encoding: [0x9f,0x64,0x25,0xab]
+
+
+;-----------------------------------------------------------------------------
+; SUBS to WZR/XZR is a CMP
+;-----------------------------------------------------------------------------
+ cmp w1, #1024, lsl #12
+ cmp x2, #1024
+ cmp w4, w5
+ cmp x6, x7
+ cmp w8, w9, asr #3
+ cmp x2, x3, lsr #4
+ cmp x2, w3, uxth #2
+ cmp x4, x5, uxtx
+ cmp wzr, w1
+ cmp x8, w8, uxtw
+ cmp w9, w8, uxtw
+ cmp wsp, w9, lsl #0
+
+; CHECK: cmp w1, #4194304 ; encoding: [0x3f,0x00,0x50,0x71]
+; CHECK: cmp x2, #1024 ; encoding: [0x5f,0x00,0x10,0xf1]
+; CHECK: cmp w4, w5 ; encoding: [0x9f,0x00,0x05,0x6b]
+; CHECK: cmp x6, x7 ; encoding: [0xdf,0x00,0x07,0xeb]
+; CHECK: cmp w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x6b]
+; CHECK: cmp x2, x3, lsr #4 ; encoding: [0x5f,0x10,0x43,0xeb]
+; CHECK: cmp x2, w3, uxth #2 ; encoding: [0x5f,0x28,0x23,0xeb]
+; CHECK: cmp x4, x5, uxtx ; encoding: [0x9f,0x60,0x25,0xeb]
+; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b]
+; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb]
+; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b]
+; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b]
+
+
+;-----------------------------------------------------------------------------
+; SUB/SUBS from WZR/XZR is a NEG
+;-----------------------------------------------------------------------------
+
+ neg w0, w1
+; CHECK: neg w0, w1
+ neg w0, w1, lsl #1
+; CHECK: sub w0, wzr, w1, lsl #1
+ neg x0, x1
+; CHECK: neg x0, x1
+ neg x0, x1, asr #1
+; CHECK: sub x0, xzr, x1, asr #1
+ negs w0, w1
+; CHECK: negs w0, w1
+ negs w0, w1, lsl #1
+; CHECK: subs w0, wzr, w1, lsl #1
+ negs x0, x1
+; CHECK: negs x0, x1
+ negs x0, x1, asr #1
+; CHECK: subs x0, xzr, x1, asr #1
+
+;-----------------------------------------------------------------------------
+; MOV aliases
+;-----------------------------------------------------------------------------
+
+ mov x0, #281470681743360
+ mov x0, #18446744073709486080
+
+; CHECK: movz x0, #65535, lsl #32
+; CHECK: movn x0, #65535
+
+ mov w0, #0xffffffff
+ mov w0, #0xffffff00
+
+; CHECK: movn w0, #0
+; CHECK: movn w0, #255
+
+;-----------------------------------------------------------------------------
+; MVN aliases
+;-----------------------------------------------------------------------------
+
+ mvn w4, w9
+ mvn x2, x3
+ orn w4, wzr, w9
+
+; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a]
+; CHECK: mvn x2, x3 ; encoding: [0xe2,0x03,0x23,0xaa]
+; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a]
+
+;-----------------------------------------------------------------------------
+; Bitfield aliases
+;-----------------------------------------------------------------------------
+
+ bfi w0, w0, #1, #4
+ bfi x0, x0, #1, #4
+ bfi w0, w0, #0, #2
+ bfi x0, x0, #0, #2
+ bfxil w0, w0, #2, #3
+ bfxil x0, x0, #2, #3
+ sbfiz w0, w0, #1, #4
+ sbfiz x0, x0, #1, #4
+ sbfx w0, w0, #2, #3
+ sbfx x0, x0, #2, #3
+ ubfiz w0, w0, #1, #4
+ ubfiz x0, x0, #1, #4
+ ubfx w0, w0, #2, #3
+ ubfx x0, x0, #2, #3
+
+; CHECK: bfm w0, w0, #31, #3
+; CHECK: bfm x0, x0, #63, #3
+; CHECK: bfm w0, w0, #0, #1
+; CHECK: bfm x0, x0, #0, #1
+; CHECK: bfm w0, w0, #2, #4
+; CHECK: bfm x0, x0, #2, #4
+; CHECK: sbfm w0, w0, #31, #3
+; CHECK: sbfm x0, x0, #63, #3
+; CHECK: sbfm w0, w0, #2, #4
+; CHECK: sbfm x0, x0, #2, #4
+; CHECK: ubfm w0, w0, #31, #3
+; CHECK: ubfm x0, x0, #63, #3
+; CHECK: ubfm w0, w0, #2, #4
+; CHECK: ubfm x0, x0, #2, #4
+
+;-----------------------------------------------------------------------------
+; Shift (immediate) aliases
+;-----------------------------------------------------------------------------
+
+; CHECK: asr w1, w3, #13
+; CHECK: asr x1, x3, #13
+; CHECK: lsl w0, w0, #1
+; CHECK: lsl x0, x0, #1
+; CHECK: lsr w0, w0, #4
+; CHECK: lsr x0, x0, #4
+
+ sbfm w1, w3, #13, #31
+ sbfm x1, x3, #13, #63
+ ubfm w0, w0, #31, #30
+ ubfm x0, x0, #63, #62
+ ubfm w0, w0, #4, #31
+ ubfm x0, x0, #4, #63
+; CHECK: extr w1, w3, w3, #5
+; CHECK: extr x1, x3, x3, #5
+ ror w1, w3, #5
+ ror x1, x3, #5
+; CHECK: lsl w1, wzr, #3
+ lsl w1, wzr, #3
+
+;-----------------------------------------------------------------------------
+; Sign/Zero extend aliases
+;-----------------------------------------------------------------------------
+
+ sxtb w1, w2
+ sxth w1, w2
+ uxtb w1, w2
+ uxth w1, w2
+
+; CHECK: sxtb w1, w2
+; CHECK: sxth w1, w2
+; CHECK: uxtb w1, w2
+; CHECK: uxth w1, w2
+
+ sxtb x1, x2
+ sxth x1, x2
+ sxtw x1, x2
+ uxtb x1, x2
+ uxth x1, x2
+ uxtw x1, x2
+
+; CHECK: sxtb x1, x2
+; CHECK: sxth x1, x2
+; CHECK: sxtw x1, x2
+; CHECK: uxtb x1, x2
+; CHECK: uxth x1, x2
+; CHECK: uxtw x1, x2
+
+;-----------------------------------------------------------------------------
+; Negate with carry
+;-----------------------------------------------------------------------------
+
+ ngc w1, w2
+ ngc x1, x2
+ ngcs w1, w2
+ ngcs x1, x2
+
+; CHECK: ngc w1, w2
+; CHECK: ngc x1, x2
+; CHECK: ngcs w1, w2
+; CHECK: ngcs x1, x2
+
+;-----------------------------------------------------------------------------
+; 6.6.1 Multiply aliases
+;-----------------------------------------------------------------------------
+
+ mneg w1, w2, w3
+ mneg x1, x2, x3
+ mul w1, w2, w3
+ mul x1, x2, x3
+ smnegl x1, w2, w3
+ umnegl x1, w2, w3
+ smull x1, w2, w3
+ umull x1, w2, w3
+
+; CHECK: mneg w1, w2, w3
+; CHECK: mneg x1, x2, x3
+; CHECK: mul w1, w2, w3
+; CHECK: mul x1, x2, x3
+; CHECK: smnegl x1, w2, w3
+; CHECK: umnegl x1, w2, w3
+; CHECK: smull x1, w2, w3
+; CHECK: umull x1, w2, w3
+
+;-----------------------------------------------------------------------------
+; Conditional select aliases
+;-----------------------------------------------------------------------------
+
+ cset w1, eq
+ cset x1, eq
+ csetm w1, ne
+ csetm x1, ne
+ cinc w1, w2, lt
+ cinc x1, x2, lt
+ cinv w1, w2, mi
+ cinv x1, x2, mi
+
+; CHECK: csinc w1, wzr, wzr, ne
+; CHECK: csinc x1, xzr, xzr, ne
+; CHECK: csinv w1, wzr, wzr, eq
+; CHECK: csinv x1, xzr, xzr, eq
+; CHECK: csinc w1, w2, w2, ge
+; CHECK: csinc x1, x2, x2, ge
+; CHECK: csinv w1, w2, w2, pl
+; CHECK: csinv x1, x2, x2, pl
+
+;-----------------------------------------------------------------------------
+; SYS aliases
+;-----------------------------------------------------------------------------
+
+ sys #0, c7, c1, #0
+; CHECK: ic ialluis
+ sys #0, c7, c5, #0
+; CHECK: ic iallu
+ sys #3, c7, c5, #1
+; CHECK: ic ivau
+
+ sys #3, c7, c4, #1
+; CHECK: dc zva
+ sys #0, c7, c6, #1
+; CHECK: dc ivac
+ sys #0, c7, c6, #2
+; CHECK: dc isw
+ sys #3, c7, c10, #1
+; CHECK: dc cvac
+ sys #0, c7, c10, #2
+; CHECK: dc csw
+ sys #3, c7, c11, #1
+; CHECK: dc cvau
+ sys #3, c7, c14, #1
+; CHECK: dc civac
+ sys #0, c7, c14, #2
+; CHECK: dc cisw
+
+ sys #0, c7, c8, #0
+; CHECK: at s1e1r
+ sys #4, c7, c8, #0
+; CHECK: at s1e2r
+ sys #6, c7, c8, #0
+; CHECK: at s1e3r
+ sys #0, c7, c8, #1
+; CHECK: at s1e1w
+ sys #4, c7, c8, #1
+; CHECK: at s1e2w
+ sys #6, c7, c8, #1
+; CHECK: at s1e3w
+ sys #0, c7, c8, #2
+; CHECK: at s1e0r
+ sys #0, c7, c8, #3
+; CHECK: at s1e0w
+ sys #4, c7, c8, #4
+; CHECK: at s12e1r
+ sys #4, c7, c8, #5
+; CHECK: at s12e1w
+ sys #4, c7, c8, #6
+; CHECK: at s12e0r
+ sys #4, c7, c8, #7
+; CHECK: at s12e0w
+
+ sys #0, c8, c3, #0
+; CHECK: tlbi vmalle1is
+ sys #4, c8, c3, #0
+; CHECK: tlbi alle2is
+ sys #6, c8, c3, #0
+; CHECK: tlbi alle3is
+ sys #0, c8, c3, #1
+; CHECK: tlbi vae1is
+ sys #4, c8, c3, #1
+; CHECK: tlbi vae2is
+ sys #6, c8, c3, #1
+; CHECK: tlbi vae3is
+ sys #0, c8, c3, #2
+; CHECK: tlbi aside1is
+ sys #0, c8, c3, #3
+; CHECK: tlbi vaae1is
+ sys #4, c8, c3, #4
+; CHECK: tlbi alle1is
+ sys #0, c8, c3, #5
+; CHECK: tlbi vale1is
+ sys #0, c8, c3, #7
+; CHECK: tlbi vaale1is
+ sys #0, c8, c7, #0
+; CHECK: tlbi vmalle1
+ sys #4, c8, c7, #0
+; CHECK: tlbi alle2
+ sys #4, c8, c3, #5
+; CHECK: tlbi vale2is
+ sys #6, c8, c3, #5
+; CHECK: tlbi vale3is
+ sys #6, c8, c7, #0
+; CHECK: tlbi alle3
+ sys #0, c8, c7, #1
+; CHECK: tlbi vae1
+ sys #4, c8, c7, #1
+; CHECK: tlbi vae2
+ sys #6, c8, c7, #1
+; CHECK: tlbi vae3
+ sys #0, c8, c7, #2
+; CHECK: tlbi aside1
+ sys #0, c8, c7, #3
+; CHECK: tlbi vaae1
+ sys #4, c8, c7, #4
+; CHECK: tlbi alle1
+ sys #0, c8, c7, #5
+; CHECK: tlbi vale1
+ sys #4, c8, c7, #5
+; CHECK: tlbi vale2
+ sys #6, c8, c7, #5
+; CHECK: tlbi vale3
+ sys #0, c8, c7, #7
+; CHECK: tlbi vaale1
+ sys #4, c8, c4, #1
+; CHECK: tlbi ipas2e1
+ sys #4, c8, c4, #5
+; CHECK: tlbi ipas2le1
+ sys #4, c8, c7, #6
+; CHECK: tlbi vmalls12e1
+ sys #4, c8, c3, #6
+; CHECK: tlbi vmalls12e1is
+
+ ic ialluis
+; CHECK: ic ialluis
+ ic iallu
+; CHECK: ic iallu
+ ic ivau
+; CHECK: ic ivau
+
+ dc zva
+; CHECK: dc zva
+ dc ivac
+; CHECK: dc ivac
+ dc isw
+; CHECK: dc isw
+ dc cvac
+; CHECK: dc cvac
+ dc csw
+; CHECK: dc csw
+ dc cvau
+; CHECK: dc cvau
+ dc civac
+; CHECK: dc civac
+ dc cisw
+; CHECK: dc cisw
+
+ at s1e1r
+; CHECK: at s1e1r
+ at s1e2r
+; CHECK: at s1e2r
+ at s1e3r
+; CHECK: at s1e3r
+ at s1e1w
+; CHECK: at s1e1w
+ at s1e2w
+; CHECK: at s1e2w
+ at s1e3w
+; CHECK: at s1e3w
+ at s1e0r
+; CHECK: at s1e0r
+ at s1e0w
+; CHECK: at s1e0w
+ at s12e1r
+; CHECK: at s12e1r
+ at s12e1w
+; CHECK: at s12e1w
+ at s12e0r
+; CHECK: at s12e0r
+ at s12e0w
+; CHECK: at s12e0w
+
+ tlbi vmalle1is
+; CHECK: tlbi vmalle1is
+ tlbi alle2is
+; CHECK: tlbi alle2is
+ tlbi alle3is
+; CHECK: tlbi alle3is
+ tlbi vae1is
+; CHECK: tlbi vae1is
+ tlbi vae2is
+; CHECK: tlbi vae2is
+ tlbi vae3is
+; CHECK: tlbi vae3is
+ tlbi aside1is
+; CHECK: tlbi aside1is
+ tlbi vaae1is
+; CHECK: tlbi vaae1is
+ tlbi alle1is
+; CHECK: tlbi alle1is
+ tlbi vale1is
+; CHECK: tlbi vale1is
+ tlbi vaale1is
+; CHECK: tlbi vaale1is
+ tlbi vmalle1
+; CHECK: tlbi vmalle1
+ tlbi alle2
+; CHECK: tlbi alle2
+ tlbi vale2is
+; CHECK: tlbi vale2is
+ tlbi vale3is
+; CHECK: tlbi vale3is
+ tlbi alle3
+; CHECK: tlbi alle3
+ tlbi vae1
+; CHECK: tlbi vae1
+ tlbi vae2
+; CHECK: tlbi vae2
+ tlbi vae3
+; CHECK: tlbi vae3
+ tlbi aside1
+; CHECK: tlbi aside1
+ tlbi vaae1
+; CHECK: tlbi vaae1
+ tlbi alle1
+; CHECK: tlbi alle1
+ tlbi vale1
+; CHECK: tlbi vale1
+ tlbi vale2
+; CHECK: tlbi vale2
+ tlbi vale3
+; CHECK: tlbi vale3
+ tlbi vaale1
+; CHECK: tlbi vaale1
+ tlbi ipas2e1, x10
+; CHECK: tlbi ipas2e1, x10
+ tlbi ipas2le1, x1
+; CHECK: tlbi ipas2le1, x1
+ tlbi vmalls12e1
+; CHECK: tlbi vmalls12e1
+ tlbi vmalls12e1is
+; CHECK: tlbi vmalls12e1is
+
+;-----------------------------------------------------------------------------
+; 5.8.5 Vector Arithmetic aliases
+;-----------------------------------------------------------------------------
+
+ cmls.8b v0, v2, v1
+ cmls.16b v0, v2, v1
+ cmls.4h v0, v2, v1
+ cmls.8h v0, v2, v1
+ cmls.2s v0, v2, v1
+ cmls.4s v0, v2, v1
+ cmls.2d v0, v2, v1
+; CHECK: cmhs.8b v0, v1, v2
+; CHECK: cmhs.16b v0, v1, v2
+; CHECK: cmhs.4h v0, v1, v2
+; CHECK: cmhs.8h v0, v1, v2
+; CHECK: cmhs.2s v0, v1, v2
+; CHECK: cmhs.4s v0, v1, v2
+; CHECK: cmhs.2d v0, v1, v2
+
+ cmlo.8b v0, v2, v1
+ cmlo.16b v0, v2, v1
+ cmlo.4h v0, v2, v1
+ cmlo.8h v0, v2, v1
+ cmlo.2s v0, v2, v1
+ cmlo.4s v0, v2, v1
+ cmlo.2d v0, v2, v1
+; CHECK: cmhi.8b v0, v1, v2
+; CHECK: cmhi.16b v0, v1, v2
+; CHECK: cmhi.4h v0, v1, v2
+; CHECK: cmhi.8h v0, v1, v2
+; CHECK: cmhi.2s v0, v1, v2
+; CHECK: cmhi.4s v0, v1, v2
+; CHECK: cmhi.2d v0, v1, v2
+
+ cmle.8b v0, v2, v1
+ cmle.16b v0, v2, v1
+ cmle.4h v0, v2, v1
+ cmle.8h v0, v2, v1
+ cmle.2s v0, v2, v1
+ cmle.4s v0, v2, v1
+ cmle.2d v0, v2, v1
+; CHECK: cmge.8b v0, v1, v2
+; CHECK: cmge.16b v0, v1, v2
+; CHECK: cmge.4h v0, v1, v2
+; CHECK: cmge.8h v0, v1, v2
+; CHECK: cmge.2s v0, v1, v2
+; CHECK: cmge.4s v0, v1, v2
+; CHECK: cmge.2d v0, v1, v2
+
+ cmlt.8b v0, v2, v1
+ cmlt.16b v0, v2, v1
+ cmlt.4h v0, v2, v1
+ cmlt.8h v0, v2, v1
+ cmlt.2s v0, v2, v1
+ cmlt.4s v0, v2, v1
+ cmlt.2d v0, v2, v1
+; CHECK: cmgt.8b v0, v1, v2
+; CHECK: cmgt.16b v0, v1, v2
+; CHECK: cmgt.4h v0, v1, v2
+; CHECK: cmgt.8h v0, v1, v2
+; CHECK: cmgt.2s v0, v1, v2
+; CHECK: cmgt.4s v0, v1, v2
+; CHECK: cmgt.2d v0, v1, v2
+
+ fcmle.2s v0, v2, v1
+ fcmle.4s v0, v2, v1
+ fcmle.2d v0, v2, v1
+; CHECK: fcmge.2s v0, v1, v2
+; CHECK: fcmge.4s v0, v1, v2
+; CHECK: fcmge.2d v0, v1, v2
+
+ fcmlt.2s v0, v2, v1
+ fcmlt.4s v0, v2, v1
+ fcmlt.2d v0, v2, v1
+; CHECK: fcmgt.2s v0, v1, v2
+; CHECK: fcmgt.4s v0, v1, v2
+; CHECK: fcmgt.2d v0, v1, v2
+
+ facle.2s v0, v2, v1
+ facle.4s v0, v2, v1
+ facle.2d v0, v2, v1
+; CHECK: facge.2s v0, v1, v2
+; CHECK: facge.4s v0, v1, v2
+; CHECK: facge.2d v0, v1, v2
+
+ faclt.2s v0, v2, v1
+ faclt.4s v0, v2, v1
+ faclt.2d v0, v2, v1
+; CHECK: facgt.2s v0, v1, v2
+; CHECK: facgt.4s v0, v1, v2
+; CHECK: facgt.2d v0, v1, v2
+
+;-----------------------------------------------------------------------------
+; 5.8.6 Scalar Arithmetic aliases
+;-----------------------------------------------------------------------------
+
+ cmls d0, d2, d1
+; CHECK: cmhs d0, d1, d2
+
+ cmle d0, d2, d1
+; CHECK: cmge d0, d1, d2
+
+ cmlo d0, d2, d1
+; CHECK: cmhi d0, d1, d2
+
+ cmlt d0, d2, d1
+; CHECK: cmgt d0, d1, d2
+
+ fcmle s0, s2, s1
+ fcmle d0, d2, d1
+; CHECK: fcmge s0, s1, s2
+; CHECK: fcmge d0, d1, d2
+
+ fcmlt s0, s2, s1
+ fcmlt d0, d2, d1
+; CHECK: fcmgt s0, s1, s2
+; CHECK: fcmgt d0, d1, d2
+
+ facle s0, s2, s1
+ facle d0, d2, d1
+; CHECK: facge s0, s1, s2
+; CHECK: facge d0, d1, d2
+
+ faclt s0, s2, s1
+ faclt d0, d2, d1
+; CHECK: facgt s0, s1, s2
+; CHECK: facgt d0, d1, d2
+
+;-----------------------------------------------------------------------------
+; 5.8.14 Vector Shift (immediate)
+;-----------------------------------------------------------------------------
+ sxtl v1.8h, v2.8b
+; CHECK: sshll.8h v1, v2, #0
+ sxtl.8h v1, v2
+; CHECK: sshll.8h v1, v2, #0
+
+ sxtl v1.4s, v2.4h
+; CHECK: sshll.4s v1, v2, #0
+ sxtl.4s v1, v2
+; CHECK: sshll.4s v1, v2, #0
+
+ sxtl v1.2d, v2.2s
+; CHECK: sshll.2d v1, v2, #0
+ sxtl.2d v1, v2
+; CHECK: sshll.2d v1, v2, #0
+
+ sxtl2 v1.8h, v2.16b
+; CHECK: sshll2.8h v1, v2, #0
+ sxtl2.8h v1, v2
+; CHECK: sshll2.8h v1, v2, #0
+
+ sxtl2 v1.4s, v2.8h
+; CHECK: sshll2.4s v1, v2, #0
+ sxtl2.4s v1, v2
+; CHECK: sshll2.4s v1, v2, #0
+
+ sxtl2 v1.2d, v2.4s
+; CHECK: sshll2.2d v1, v2, #0
+ sxtl2.2d v1, v2
+; CHECK: sshll2.2d v1, v2, #0
+
+ uxtl v1.8h, v2.8b
+; CHECK: ushll.8h v1, v2, #0
+ uxtl.8h v1, v2
+; CHECK: ushll.8h v1, v2, #0
+
+ uxtl v1.4s, v2.4h
+; CHECK: ushll.4s v1, v2, #0
+ uxtl.4s v1, v2
+; CHECK: ushll.4s v1, v2, #0
+
+ uxtl v1.2d, v2.2s
+; CHECK: ushll.2d v1, v2, #0
+ uxtl.2d v1, v2
+; CHECK: ushll.2d v1, v2, #0
+
+ uxtl2 v1.8h, v2.16b
+; CHECK: ushll2.8h v1, v2, #0
+ uxtl2.8h v1, v2
+; CHECK: ushll2.8h v1, v2, #0
+
+ uxtl2 v1.4s, v2.8h
+; CHECK: ushll2.4s v1, v2, #0
+ uxtl2.4s v1, v2
+; CHECK: ushll2.4s v1, v2, #0
+
+ uxtl2 v1.2d, v2.4s
+; CHECK: ushll2.2d v1, v2, #0
+ uxtl2.2d v1, v2
+; CHECK: ushll2.2d v1, v2, #0
+
+
+;-----------------------------------------------------------------------------
+; MOVI verbose syntax with shift operand omitted.
+;-----------------------------------------------------------------------------
+ movi v4.16b, #0x00
+ movi v4.16B, #0x01
+ movi v4.8b, #0x02
+ movi v4.8B, #0x03
+ movi v1.2d, #0x000000000000ff
+ movi v2.2D, #0x000000000000ff
+
+; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f]
+; CHECK: movi.16b v4, #1 ; encoding: [0x24,0xe4,0x00,0x4f]
+; CHECK: movi.8b v4, #2 ; encoding: [0x44,0xe4,0x00,0x0f]
+; CHECK: movi.8b v4, #3 ; encoding: [0x64,0xe4,0x00,0x0f]
+; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f]
+; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f]
Added: llvm/trunk/test/MC/ARM64/arithmetic-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/arithmetic-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/arithmetic-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/arithmetic-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,631 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+;==---------------------------------------------------------------------------==
+; Add/Subtract with carry/borrow
+;==---------------------------------------------------------------------------==
+
+ adc w1, w2, w3
+ adc x1, x2, x3
+ adcs w5, w4, w3
+ adcs x5, x4, x3
+
+; CHECK: adc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x1a]
+; CHECK: adc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x9a]
+; CHECK: adcs w5, w4, w3 ; encoding: [0x85,0x00,0x03,0x3a]
+; CHECK: adcs x5, x4, x3 ; encoding: [0x85,0x00,0x03,0xba]
+
+ sbc w1, w2, w3
+ sbc x1, x2, x3
+ sbcs w1, w2, w3
+ sbcs x1, x2, x3
+
+; CHECK: sbc w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x5a]
+; CHECK: sbc x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xda]
+; CHECK: sbcs w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x7a]
+; CHECK: sbcs x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xfa]
+
+;==---------------------------------------------------------------------------==
+; Add/Subtract with (optionally shifted) immediate
+;==---------------------------------------------------------------------------==
+
+ add w3, w4, #1024
+ add w3, w4, #1024, lsl #0
+ add x3, x4, #1024
+ add x3, x4, #1024, lsl #0
+
+; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11]
+; CHECK: add w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x11]
+; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91]
+; CHECK: add x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0x91]
+
+ add w3, w4, #1024, lsl #12
+ add w3, w4, #4194304
+ add w3, w4, #0, lsl #12
+ add x3, x4, #1024, lsl #12
+ add x3, x4, #4194304
+ add x3, x4, #0, lsl #12
+ add sp, sp, #32
+
+; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11]
+; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11]
+; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11]
+; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91]
+; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91]
+; CHECK: add x3, x4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x91]
+; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91]
+
+ adds w3, w4, #1024
+ adds w3, w4, #1024, lsl #0
+ adds w3, w4, #1024, lsl #12
+ adds x3, x4, #1024
+ adds x3, x4, #1024, lsl #0
+ adds x3, x4, #1024, lsl #12
+
+; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31]
+; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31]
+; CHECK: adds w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x31]
+; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1]
+; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1]
+; CHECK: adds x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xb1]
+
+ sub w3, w4, #1024
+ sub w3, w4, #1024, lsl #0
+ sub w3, w4, #1024, lsl #12
+ sub x3, x4, #1024
+ sub x3, x4, #1024, lsl #0
+ sub x3, x4, #1024, lsl #12
+ sub sp, sp, #32
+
+; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51]
+; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51]
+; CHECK: sub w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x51]
+; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1]
+; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1]
+; CHECK: sub x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xd1]
+; CHECK: sub sp, sp, #32 ; encoding: [0xff,0x83,0x00,0xd1]
+
+ subs w3, w4, #1024
+ subs w3, w4, #1024, lsl #0
+ subs w3, w4, #1024, lsl #12
+ subs x3, x4, #1024
+ subs x3, x4, #1024, lsl #0
+ subs x3, x4, #1024, lsl #12
+
+; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71]
+; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71]
+; CHECK: subs w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x71]
+; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1]
+; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1]
+; CHECK: subs x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xf1]
+
+;==---------------------------------------------------------------------------==
+; Add/Subtract register with (optional) shift
+;==---------------------------------------------------------------------------==
+
+ add w12, w13, w14
+ add x12, x13, x14
+ add w12, w13, w14, lsl #12
+ add x12, x13, x14, lsl #12
+ add w12, w13, w14, lsr #42
+ add x12, x13, x14, lsr #42
+ add w12, w13, w14, asr #39
+ add x12, x13, x14, asr #39
+
+; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b]
+; CHECK: add x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0x8b]
+; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b]
+; CHECK: add x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x8b]
+; CHECK: add w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x0b]
+; CHECK: add x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x8b]
+; CHECK: add w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x0b]
+; CHECK: add x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x8b]
+
+ sub w12, w13, w14
+ sub x12, x13, x14
+ sub w12, w13, w14, lsl #12
+ sub x12, x13, x14, lsl #12
+ sub w12, w13, w14, lsr #42
+ sub x12, x13, x14, lsr #42
+ sub w12, w13, w14, asr #39
+ sub x12, x13, x14, asr #39
+
+; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b]
+; CHECK: sub x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xcb]
+; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b]
+; CHECK: sub x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xcb]
+; CHECK: sub w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x4b]
+; CHECK: sub x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xcb]
+; CHECK: sub w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x4b]
+; CHECK: sub x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xcb]
+
+ adds w12, w13, w14
+ adds x12, x13, x14
+ adds w12, w13, w14, lsl #12
+ adds x12, x13, x14, lsl #12
+ adds w12, w13, w14, lsr #42
+ adds x12, x13, x14, lsr #42
+ adds w12, w13, w14, asr #39
+ adds x12, x13, x14, asr #39
+
+; CHECK: adds w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x2b]
+; CHECK: adds x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xab]
+; CHECK: adds w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x2b]
+; CHECK: adds x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xab]
+; CHECK: adds w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x2b]
+; CHECK: adds x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xab]
+; CHECK: adds w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x2b]
+; CHECK: adds x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xab]
+
+ subs w12, w13, w14
+ subs x12, x13, x14
+ subs w12, w13, w14, lsl #12
+ subs x12, x13, x14, lsl #12
+ subs w12, w13, w14, lsr #42
+ subs x12, x13, x14, lsr #42
+ subs w12, w13, w14, asr #39
+ subs x12, x13, x14, asr #39
+
+; CHECK: subs w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x6b]
+; CHECK: subs x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xeb]
+; CHECK: subs w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x6b]
+; CHECK: subs x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xeb]
+; CHECK: subs w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x6b]
+; CHECK: subs x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xeb]
+; CHECK: subs w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x6b]
+; CHECK: subs x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xeb]
+
+; Check use of upper case register names rdar://14354073
+ add X2, X2, X2
+; CHECK: add x2, x2, x2 ; encoding: [0x42,0x00,0x02,0x8b]
+
+;==---------------------------------------------------------------------------==
+; Add/Subtract with (optional) extend
+;==---------------------------------------------------------------------------==
+
+ add w1, w2, w3, uxtb
+ add w1, w2, w3, uxth
+ add w1, w2, w3, uxtw
+ add w1, w2, w3, uxtx
+ add w1, w2, w3, sxtb
+ add w1, w2, w3, sxth
+ add w1, w2, w3, sxtw
+ add w1, w2, w3, sxtx
+
+; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
+; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
+; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b]
+; CHECK: add w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x0b]
+; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
+; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
+; CHECK: add w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x0b]
+; CHECK: add w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x0b]
+
+ add x1, x2, w3, uxtb
+ add x1, x2, w3, uxth
+ add x1, x2, w3, uxtw
+ add x1, x2, w3, sxtb
+ add x1, x2, w3, sxth
+ add x1, x2, w3, sxtw
+
+; CHECK: add x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x8b]
+; CHECK: add x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0x8b]
+; CHECK: add x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x8b]
+; CHECK: add x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x8b]
+; CHECK: add x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x8b]
+; CHECK: add x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x8b]
+
+ add w1, wsp, w3
+ add w1, wsp, w3, uxtw #0
+ add w2, wsp, w3, lsl #1
+ add sp, x2, x3
+ add sp, x2, x3, uxtx #0
+
+; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
+; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b]
+; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x67,0x23,0x0b]
+; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
+; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b]
+
+ sub w1, w2, w3, uxtb
+ sub w1, w2, w3, uxth
+ sub w1, w2, w3, uxtw
+ sub w1, w2, w3, uxtx
+ sub w1, w2, w3, sxtb
+ sub w1, w2, w3, sxth
+ sub w1, w2, w3, sxtw
+ sub w1, w2, w3, sxtx
+
+; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
+; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
+; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b]
+; CHECK: sub w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x4b]
+; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
+; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
+; CHECK: sub w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x4b]
+; CHECK: sub w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x4b]
+
+ sub x1, x2, w3, uxtb
+ sub x1, x2, w3, uxth
+ sub x1, x2, w3, uxtw
+ sub x1, x2, w3, sxtb
+ sub x1, x2, w3, sxth
+ sub x1, x2, w3, sxtw
+
+; CHECK: sub x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xcb]
+; CHECK: sub x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xcb]
+; CHECK: sub x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xcb]
+; CHECK: sub x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xcb]
+; CHECK: sub x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xcb]
+; CHECK: sub x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xcb]
+
+ sub w1, wsp, w3
+ sub w1, wsp, w3, uxtw #0
+ sub sp, x2, x3
+ sub sp, x2, x3, uxtx #0
+ sub sp, x3, x7, lsl #4
+
+; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b]
+; CHECK: sub w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x4b]
+; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb]
+; CHECK: sub sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0xcb]
+; CHECK: sp, x3, x7, lsl #4 ; encoding: [0x7f,0x70,0x27,0xcb]
+
+ adds w1, w2, w3, uxtb
+ adds w1, w2, w3, uxth
+ adds w1, w2, w3, uxtw
+ adds w1, w2, w3, uxtx
+ adds w1, w2, w3, sxtb
+ adds w1, w2, w3, sxth
+ adds w1, w2, w3, sxtw
+ adds w1, w2, w3, sxtx
+
+; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
+; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
+; CHECK: adds w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x2b]
+; CHECK: adds w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x2b]
+; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
+; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b]
+; CHECK: adds w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x2b]
+; CHECK: adds w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x2b]
+
+ adds x1, x2, w3, uxtb
+ adds x1, x2, w3, uxth
+ adds x1, x2, w3, uxtw
+ adds x1, x2, w3, uxtx
+ adds x1, x2, w3, sxtb
+ adds x1, x2, w3, sxth
+ adds x1, x2, w3, sxtw
+ adds x1, x2, w3, sxtx
+
+; CHECK: adds x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xab]
+; CHECK: adds x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xab]
+; CHECK: adds x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xab]
+; CHECK: adds x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xab]
+; CHECK: adds x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xab]
+; CHECK: adds x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xab]
+; CHECK: adds x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xab]
+; CHECK: adds x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xab]
+
+ adds w1, wsp, w3
+ adds w1, wsp, w3, uxtw #0
+ adds wzr, wsp, w3, lsl #4
+
+; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
+; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
+; CHECK: adds wzr, wsp, w3, lsl #4 ; encoding: [0xff,0x73,0x23,0x2b]
+
+ subs w1, w2, w3, uxtb
+ subs w1, w2, w3, uxth
+ subs w1, w2, w3, uxtw
+ subs w1, w2, w3, uxtx
+ subs w1, w2, w3, sxtb
+ subs w1, w2, w3, sxth
+ subs w1, w2, w3, sxtw
+ subs w1, w2, w3, sxtx
+
+; CHECK: subs w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x6b]
+; CHECK: subs w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x6b]
+; CHECK: subs w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x6b]
+; CHECK: subs w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x6b]
+; CHECK: subs w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x6b]
+; CHECK: subs w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x6b]
+; CHECK: subs w1, w2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0x6b]
+; CHECK: subs w1, w2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0x6b]
+
+ subs x1, x2, w3, uxtb
+ subs x1, x2, w3, uxth
+ subs x1, x2, w3, uxtw
+ subs x1, x2, w3, uxtx
+ subs x1, x2, w3, sxtb
+ subs x1, x2, w3, sxth
+ subs x1, x2, w3, sxtw
+ subs x1, x2, w3, sxtx
+
+; CHECK: subs x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xeb]
+; CHECK: subs x1, x2, w3, uxth ; encoding: [0x41,0x20,0x23,0xeb]
+; CHECK: subs x1, x2, w3, uxtw ; encoding: [0x41,0x40,0x23,0xeb]
+; CHECK: subs x1, x2, w3, uxtx ; encoding: [0x41,0x60,0x23,0xeb]
+; CHECK: subs x1, x2, w3, sxtb ; encoding: [0x41,0x80,0x23,0xeb]
+; CHECK: subs x1, x2, w3, sxth ; encoding: [0x41,0xa0,0x23,0xeb]
+; CHECK: subs x1, x2, w3, sxtw ; encoding: [0x41,0xc0,0x23,0xeb]
+; CHECK: subs x1, x2, w3, sxtx ; encoding: [0x41,0xe0,0x23,0xeb]
+
+ subs w1, wsp, w3
+ subs w1, wsp, w3, uxtw #0
+
+; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b]
+; CHECK: subs w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x6b]
+
+ cmp wsp, w9, lsl #0
+ subs x3, sp, x9, lsl #2
+ cmp wsp, w8, uxtw
+ subs wzr, wsp, w8, uxtw
+ cmp sp, w8, uxtw
+ subs xzr, sp, w8, uxtw
+
+; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b]
+; CHECK: subs x3, sp, x9, lsl #2 ; encoding: [0xe3,0x6b,0x29,0xeb]
+; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
+; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b]
+; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb]
+; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb]
+
+ sub wsp, w9, w8, uxtw
+ sub w1, wsp, w8, uxtw
+ sub wsp, wsp, w8, uxtw
+ sub sp, x9, w8, uxtw
+ sub x1, sp, w8, uxtw
+ sub sp, sp, w8, uxtw
+ subs w1, wsp, w8, uxtw
+ subs x1, sp, w8, uxtw
+
+; CHECK: sub wsp, w9, w8 ; encoding: [0x3f,0x41,0x28,0x4b]
+; CHECK: sub w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x4b]
+; CHECK: sub wsp, wsp, w8 ; encoding: [0xff,0x43,0x28,0x4b]
+; CHECK: sub sp, x9, w8 ; encoding: [0x3f,0x41,0x28,0xcb]
+; CHECK: sub x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xcb]
+; CHECK: sub sp, sp, w8 ; encoding: [0xff,0x43,0x28,0xcb]
+; CHECK: subs w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x6b]
+; CHECK: subs x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xeb]
+
+;==---------------------------------------------------------------------------==
+; Signed/Unsigned divide
+;==---------------------------------------------------------------------------==
+
+ sdiv w1, w2, w3
+ sdiv x1, x2, x3
+ udiv w1, w2, w3
+ udiv x1, x2, x3
+
+; CHECK: sdiv w1, w2, w3 ; encoding: [0x41,0x0c,0xc3,0x1a]
+; CHECK: sdiv x1, x2, x3 ; encoding: [0x41,0x0c,0xc3,0x9a]
+; CHECK: udiv w1, w2, w3 ; encoding: [0x41,0x08,0xc3,0x1a]
+; CHECK: udiv x1, x2, x3 ; encoding: [0x41,0x08,0xc3,0x9a]
+
+;==---------------------------------------------------------------------------==
+; Variable shifts
+;==---------------------------------------------------------------------------==
+
+ asrv w1, w2, w3
+ asrv x1, x2, x3
+ asr w1, w2, w3
+ asr x1, x2, x3
+ lslv w1, w2, w3
+ lslv x1, x2, x3
+ lsl w1, w2, w3
+ lsl x1, x2, x3
+ lsrv w1, w2, w3
+ lsrv x1, x2, x3
+ lsr w1, w2, w3
+ lsr x1, x2, x3
+ rorv w1, w2, w3
+ rorv x1, x2, x3
+ ror w1, w2, w3
+ ror x1, x2, x3
+
+; CHECK: encoding: [0x41,0x28,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x28,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x28,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x28,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x20,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x20,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x20,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x20,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x24,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x24,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x24,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x24,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x2c,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x2c,0xc3,0x9a]
+; CHECK: encoding: [0x41,0x2c,0xc3,0x1a]
+; CHECK: encoding: [0x41,0x2c,0xc3,0x9a]
+
+;==---------------------------------------------------------------------------==
+; One operand instructions
+;==---------------------------------------------------------------------------==
+
+ cls w1, w2
+ cls x1, x2
+ clz w1, w2
+ clz x1, x2
+ rbit w1, w2
+ rbit x1, x2
+ rev w1, w2
+ rev x1, x2
+ rev16 w1, w2
+ rev16 x1, x2
+ rev32 x1, x2
+
+; CHECK: encoding: [0x41,0x14,0xc0,0x5a]
+; CHECK: encoding: [0x41,0x14,0xc0,0xda]
+; CHECK: encoding: [0x41,0x10,0xc0,0x5a]
+; CHECK: encoding: [0x41,0x10,0xc0,0xda]
+; CHECK: encoding: [0x41,0x00,0xc0,0x5a]
+; CHECK: encoding: [0x41,0x00,0xc0,0xda]
+; CHECK: encoding: [0x41,0x08,0xc0,0x5a]
+; CHECK: encoding: [0x41,0x0c,0xc0,0xda]
+; CHECK: encoding: [0x41,0x04,0xc0,0x5a]
+; CHECK: encoding: [0x41,0x04,0xc0,0xda]
+; CHECK: encoding: [0x41,0x08,0xc0,0xda]
+
+;==---------------------------------------------------------------------------==
+; 6.6.1 Multiply-add instructions
+;==---------------------------------------------------------------------------==
+
+ madd w1, w2, w3, w4
+ madd x1, x2, x3, x4
+ msub w1, w2, w3, w4
+ msub x1, x2, x3, x4
+ smaddl x1, w2, w3, x4
+ smsubl x1, w2, w3, x4
+ umaddl x1, w2, w3, x4
+ umsubl x1, w2, w3, x4
+
+; CHECK: madd w1, w2, w3, w4 ; encoding: [0x41,0x10,0x03,0x1b]
+; CHECK: madd x1, x2, x3, x4 ; encoding: [0x41,0x10,0x03,0x9b]
+; CHECK: msub w1, w2, w3, w4 ; encoding: [0x41,0x90,0x03,0x1b]
+; CHECK: msub x1, x2, x3, x4 ; encoding: [0x41,0x90,0x03,0x9b]
+; CHECK: smaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0x23,0x9b]
+; CHECK: smsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0x23,0x9b]
+; CHECK: umaddl x1, w2, w3, x4 ; encoding: [0x41,0x10,0xa3,0x9b]
+; CHECK: umsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0xa3,0x9b]
+
+;==---------------------------------------------------------------------------==
+; Multiply-high instructions
+;==---------------------------------------------------------------------------==
+
+ smulh x1, x2, x3
+ umulh x1, x2, x3
+
+; CHECK: smulh x1, x2, x3 ; encoding: [0x41,0x7c,0x43,0x9b]
+; CHECK: umulh x1, x2, x3 ; encoding: [0x41,0x7c,0xc3,0x9b]
+
+;==---------------------------------------------------------------------------==
+; Move immediate instructions
+;==---------------------------------------------------------------------------==
+
+ movz w0, #1
+ movz x0, #1
+ movz w0, #1, lsl #16
+ movz x0, #1, lsl #16
+
+; CHECK: movz w0, #1 ; encoding: [0x20,0x00,0x80,0x52]
+; CHECK: movz x0, #1 ; encoding: [0x20,0x00,0x80,0xd2]
+; CHECK: movz w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52]
+; CHECK: movz x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2]
+
+ movn w0, #2
+ movn x0, #2
+ movn w0, #2, lsl #16
+ movn x0, #2, lsl #16
+
+; CHECK: movn w0, #2 ; encoding: [0x40,0x00,0x80,0x12]
+; CHECK: movn x0, #2 ; encoding: [0x40,0x00,0x80,0x92]
+; CHECK: movn w0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12]
+; CHECK: movn x0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92]
+
+ movk w0, #1
+ movk x0, #1
+ movk w0, #1, lsl #16
+ movk x0, #1, lsl #16
+
+; CHECK: movk w0, #1 ; encoding: [0x20,0x00,0x80,0x72]
+; CHECK: movk x0, #1 ; encoding: [0x20,0x00,0x80,0xf2]
+; CHECK: movk w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72]
+; CHECK: movk x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2]
+
+;==---------------------------------------------------------------------------==
+; Conditionally set flags instructions
+;==---------------------------------------------------------------------------==
+
+ ccmn w1, #2, #3, eq
+ ccmn x1, #2, #3, eq
+ ccmp w1, #2, #3, eq
+ ccmp x1, #2, #3, eq
+
+; CHECK: encoding: [0x23,0x08,0x42,0x3a]
+; CHECK: encoding: [0x23,0x08,0x42,0xba]
+; CHECK: encoding: [0x23,0x08,0x42,0x7a]
+; CHECK: encoding: [0x23,0x08,0x42,0xfa]
+
+ ccmn w1, w2, #3, eq
+ ccmn x1, x2, #3, eq
+ ccmp w1, w2, #3, eq
+ ccmp x1, x2, #3, eq
+
+; CHECK: encoding: [0x23,0x00,0x42,0x3a]
+; CHECK: encoding: [0x23,0x00,0x42,0xba]
+; CHECK: encoding: [0x23,0x00,0x42,0x7a]
+; CHECK: encoding: [0x23,0x00,0x42,0xfa]
+
+;==---------------------------------------------------------------------------==
+; Conditional select instructions
+;==---------------------------------------------------------------------------==
+
+ csel w1, w2, w3, eq
+ csel x1, x2, x3, eq
+ csinc w1, w2, w3, eq
+ csinc x1, x2, x3, eq
+ csinv w1, w2, w3, eq
+ csinv x1, x2, x3, eq
+ csneg w1, w2, w3, eq
+ csneg x1, x2, x3, eq
+
+; CHECK: encoding: [0x41,0x00,0x83,0x1a]
+; CHECK: encoding: [0x41,0x00,0x83,0x9a]
+; CHECK: encoding: [0x41,0x04,0x83,0x1a]
+; CHECK: encoding: [0x41,0x04,0x83,0x9a]
+; CHECK: encoding: [0x41,0x00,0x83,0x5a]
+; CHECK: encoding: [0x41,0x00,0x83,0xda]
+; CHECK: encoding: [0x41,0x04,0x83,0x5a]
+; CHECK: encoding: [0x41,0x04,0x83,0xda]
+
+; Make sure we handle upper case, too. In particular, condition codes.
+ CSEL W16, W7, W27, EQ
+ CSEL W15, W6, W26, NE
+ CSEL W14, W5, W25, CS
+ CSEL W13, W4, W24, HS
+ csel w12, w3, w23, CC
+ csel w11, w2, w22, LO
+ csel w10, w1, w21, MI
+ csel x9, x9, x1, PL
+ csel x8, x8, x2, VS
+ CSEL X7, X7, X3, VC
+ CSEL X6, X7, X4, HI
+ CSEL X5, X6, X5, LS
+ CSEL X4, X5, X6, GE
+ csel x3, x4, x7, LT
+ csel x2, x3, x8, GT
+ csel x1, x2, x9, LE
+ csel x10, x1, x20, AL
+
+; CHECK: csel w16, w7, w27, eq ; encoding: [0xf0,0x00,0x9b,0x1a]
+; CHECK: csel w15, w6, w26, ne ; encoding: [0xcf,0x10,0x9a,0x1a]
+; CHECK: csel w14, w5, w25, cs ; encoding: [0xae,0x20,0x99,0x1a]
+; CHECK: csel w13, w4, w24, cs ; encoding: [0x8d,0x20,0x98,0x1a]
+; CHECK: csel w12, w3, w23, cc ; encoding: [0x6c,0x30,0x97,0x1a]
+; CHECK: csel w11, w2, w22, cc ; encoding: [0x4b,0x30,0x96,0x1a]
+; CHECK: csel w10, w1, w21, mi ; encoding: [0x2a,0x40,0x95,0x1a]
+; CHECK: csel x9, x9, x1, pl ; encoding: [0x29,0x51,0x81,0x9a]
+; CHECK: csel x8, x8, x2, vs ; encoding: [0x08,0x61,0x82,0x9a]
+; CHECK: csel x7, x7, x3, vc ; encoding: [0xe7,0x70,0x83,0x9a]
+; CHECK: csel x6, x7, x4, hi ; encoding: [0xe6,0x80,0x84,0x9a]
+; CHECK: csel x5, x6, x5, ls ; encoding: [0xc5,0x90,0x85,0x9a]
+; CHECK: csel x4, x5, x6, ge ; encoding: [0xa4,0xa0,0x86,0x9a]
+; CHECK: csel x3, x4, x7, lt ; encoding: [0x83,0xb0,0x87,0x9a]
+; CHECK: csel x2, x3, x8, gt ; encoding: [0x62,0xc0,0x88,0x9a]
+; CHECK: csel x1, x2, x9, le ; encoding: [0x41,0xd0,0x89,0x9a]
+; CHECK: csel x10, x1, x20, al ; encoding: [0x2a,0xe0,0x94,0x9a]
+
+
+;==---------------------------------------------------------------------------==
+; Scalar saturating arithmetic
+;==---------------------------------------------------------------------------==
+ uqxtn b4, h2
+ uqxtn h2, s3
+ uqxtn s9, d2
+
+; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e]
+; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e]
+; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e]
Added: llvm/trunk/test/MC/ARM64/arm64-fixup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/arm64-fixup.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/arm64-fixup.s (added)
+++ llvm/trunk/test/MC/ARM64/arm64-fixup.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,10 @@
+; RUN: llvm-mc < %s -triple arm64-apple-darwin --show-encoding | FileCheck %s
+
+foo:
+ adr x3, Lbar
+; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A']
+; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_arm64_pcrel_adr_imm21
+Lbar:
+ adrp x3, _printf at page
+; CHECK: adrp x3, _printf at PAGE ; encoding: [0x03'A',A,A,0x90'A']
+; CHECK: fixup A - offset: 0, value: _printf at PAGE, kind: fixup_arm64_pcrel_adrp_imm21
Added: llvm/trunk/test/MC/ARM64/basic-a64-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/basic-a64-instructions.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/basic-a64-instructions.s (added)
+++ llvm/trunk/test/MC/ARM64/basic-a64-instructions.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s
+
+ crc32b w5, w7, w20
+ crc32h w28, wzr, w30
+ crc32w w0, w1, w2
+ crc32x w7, w9, x20
+ crc32cb w9, w5, w4
+ crc32ch w13, w17, w25
+ crc32cw wzr, w3, w5
+ crc32cx w18, w16, xzr
+// CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
+// CHECK: crc32h w28, wzr, w30 // encoding: [0xfc,0x47,0xde,0x1a]
+// CHECK: crc32w w0, w1, w2 // encoding: [0x20,0x48,0xc2,0x1a]
+// CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
+// CHECK: crc32cb w9, w5, w4 // encoding: [0xa9,0x50,0xc4,0x1a]
+// CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
+// CHECK: crc32cw wzr, w3, w5 // encoding: [0x7f,0x58,0xc5,0x1a]
+// CHECK: crc32cx w18, w16, xzr // encoding: [0x12,0x5e,0xdf,0x9a]
Added: llvm/trunk/test/MC/ARM64/bitfield-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/bitfield-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/bitfield-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/bitfield-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,30 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+;==---------------------------------------------------------------------------==
+; 5.4.4 Bitfield Operations
+;==---------------------------------------------------------------------------==
+
+ bfm w1, w2, #1, #15
+ bfm x1, x2, #1, #15
+ sbfm w1, w2, #1, #15
+ sbfm x1, x2, #1, #15
+ ubfm w1, w2, #1, #15
+ ubfm x1, x2, #1, #15
+
+; CHECK: bfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33]
+; CHECK: bfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3]
+; CHECK: sbfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x13]
+; CHECK: sbfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93]
+; CHECK: ubfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53]
+; CHECK: ubfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3]
+
+;==---------------------------------------------------------------------------==
+; 5.4.5 Extract (immediate)
+;==---------------------------------------------------------------------------==
+
+ extr w1, w2, w3, #15
+ extr x2, x3, x4, #1
+
+; CHECK: extr w1, w2, w3, #15 ; encoding: [0x41,0x3c,0x83,0x13]
+; CHECK: extr x2, x3, x4, #1 ; encoding: [0x62,0x04,0xc4,0x93]
Added: llvm/trunk/test/MC/ARM64/branch-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/branch-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/branch-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/branch-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,159 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+
+;-----------------------------------------------------------------------------
+; Unconditional branch (register) instructions.
+;-----------------------------------------------------------------------------
+
+ ret
+; CHECK: encoding: [0xc0,0x03,0x5f,0xd6]
+ ret x1
+; CHECK: encoding: [0x20,0x00,0x5f,0xd6]
+ drps
+; CHECK: encoding: [0xe0,0x03,0xbf,0xd6]
+ eret
+; CHECK: encoding: [0xe0,0x03,0x9f,0xd6]
+ br x5
+; CHECK: encoding: [0xa0,0x00,0x1f,0xd6]
+ blr x9
+; CHECK: encoding: [0x20,0x01,0x3f,0xd6]
+ bl L1
+; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_call26
+
+;-----------------------------------------------------------------------------
+; Contitional branch instructions.
+;-----------------------------------------------------------------------------
+
+ b L1
+; CHECK: b L1 ; encoding: [A,A,A,0b000101AA]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch26
+ b.eq L1
+; CHECK: b.eq L1 ; encoding: [0bAAA00000,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.ne L1
+; CHECK: b.ne L1 ; encoding: [0bAAA00001,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.cs L1
+; CHECK: b.cs L1 ; encoding: [0bAAA00010,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.cc L1
+; CHECK: b.cc L1 ; encoding: [0bAAA00011,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.mi L1
+; CHECK: b.mi L1 ; encoding: [0bAAA00100,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.pl L1
+; CHECK: b.pl L1 ; encoding: [0bAAA00101,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.vs L1
+; CHECK: b.vs L1 ; encoding: [0bAAA00110,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.vc L1
+; CHECK: b.vc L1 ; encoding: [0bAAA00111,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.hi L1
+; CHECK: b.hi L1 ; encoding: [0bAAA01000,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.ls L1
+; CHECK: b.ls L1 ; encoding: [0bAAA01001,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.ge L1
+; CHECK: b.ge L1 ; encoding: [0bAAA01010,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.lt L1
+; CHECK: b.lt L1 ; encoding: [0bAAA01011,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.gt L1
+; CHECK: b.gt L1 ; encoding: [0bAAA01100,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.le L1
+; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+ b.al L1
+; CHECK: b L1 ; encoding: [0bAAA01110,A,A,0x54]
+; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19
+L1:
+ b #28
+; CHECK: b #28
+ b.lt #28
+; CHECK: b.lt #28
+ b.cc #1048572
+; CHECK: b.cc #1048572 ; encoding: [0xe3,0xff,0x7f,0x54]
+ b #134217724
+; CHECK: b #134217724 ; encoding: [0xff,0xff,0xff,0x15]
+ b #-134217728
+; CHECK: b #-134217728 ; encoding: [0x00,0x00,0x00,0x16]
+
+;-----------------------------------------------------------------------------
+; Compare-and-branch instructions.
+;-----------------------------------------------------------------------------
+
+ cbz w1, foo
+; CHECK: encoding: [0bAAA00001,A,A,0x34]
+ cbz x1, foo
+; CHECK: encoding: [0bAAA00001,A,A,0xb4]
+ cbnz w2, foo
+; CHECK: encoding: [0bAAA00010,A,A,0x35]
+ cbnz x2, foo
+; CHECK: encoding: [0bAAA00010,A,A,0xb5]
+ cbz w1, #28
+; CHECK: cbz w1, #28
+ cbz w20, #1048572
+; CHECK: cbz w20, #1048572 ; encoding: [0xf4,0xff,0x7f,0x34]
+ cbnz x2, #-1048576
+; CHECK: cbnz x2, #-1048576 ; encoding: [0x02,0x00,0x80,0xb5]
+
+
+;-----------------------------------------------------------------------------
+; Bit-test-and-branch instructions.
+;-----------------------------------------------------------------------------
+
+ tbz x1, #3, foo
+; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36]
+ tbnz x1, #63, foo
+; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0xb7]
+
+ tbz w1, #3, foo
+; CHECK: encoding: [0bAAA00001,A,0b00011AAA,0x36]
+ tbnz w1, #31, foo
+; CHECK: encoding: [0bAAA00001,A,0b11111AAA,0x37]
+
+ tbz w1, #3, #28
+; CHECK: tbz w1, #3, #28
+ tbz w3, #5, #32764
+; CHECK: tbz w3, #5, #32764 ; encoding: [0xe3,0xff,0x2b,0x36]
+ tbnz x3, #8, #-32768
+; CHECK: tbnz w3, #8, #-32768 ; encoding: [0x03,0x00,0x44,0x37]
+
+;-----------------------------------------------------------------------------
+; Exception generation instructions.
+;-----------------------------------------------------------------------------
+
+ brk #1
+; CHECK: encoding: [0x20,0x00,0x20,0xd4]
+ dcps1 #2
+; CHECK: encoding: [0x41,0x00,0xa0,0xd4]
+ dcps2 #3
+; CHECK: encoding: [0x62,0x00,0xa0,0xd4]
+ dcps3 #4
+; CHECK: encoding: [0x83,0x00,0xa0,0xd4]
+ hlt #5
+; CHECK: encoding: [0xa0,0x00,0x40,0xd4]
+ hvc #6
+; CHECK: encoding: [0xc2,0x00,0x00,0xd4]
+ smc #7
+; CHECK: encoding: [0xe3,0x00,0x00,0xd4]
+ svc #8
+; CHECK: encoding: [0x01,0x01,0x00,0xd4]
+
+; The immediate defaults to zero for DCPSn
+ dcps1
+ dcps2
+ dcps3
+
+; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4]
+; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4]
+; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4]
+
Added: llvm/trunk/test/MC/ARM64/crypto.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/crypto.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/crypto.s (added)
+++ llvm/trunk/test/MC/ARM64/crypto.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,66 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding -output-asm-variant=1 < %s | FileCheck %s
+
+foo:
+ aese.16b v0, v1
+ aesd.16b v0, v1
+ aesmc.16b v0, v1
+ aesimc.16b v0, v1
+
+ sha1c.4s q0, s1, v2
+ sha1p.4s q0, s1, v2
+ sha1m.4s q0, s1, v2
+ sha1su0.4s v0, v1, v2
+ sha256h.4s q0, q1, v2
+ sha256h2.4s q0, q1, v2
+ sha256su1.4s v0, v1, v2
+ sha1h s0, s1
+ sha1su1.4s v0, v1
+ sha256su0.4s v0, v1
+
+; CHECK: aese.16b v0, v1 ; encoding: [0x20,0x48,0x28,0x4e]
+; CHECK: aesd.16b v0, v1 ; encoding: [0x20,0x58,0x28,0x4e]
+; CHECK: aesmc.16b v0, v1 ; encoding: [0x20,0x68,0x28,0x4e]
+; CHECK: aesimc.16b v0, v1 ; encoding: [0x20,0x78,0x28,0x4e]
+
+; CHECK: sha1c.4s q0, s1, v2 ; encoding: [0x20,0x00,0x02,0x5e]
+; CHECK: sha1p.4s q0, s1, v2 ; encoding: [0x20,0x10,0x02,0x5e]
+; CHECK: sha1m.4s q0, s1, v2 ; encoding: [0x20,0x20,0x02,0x5e]
+; CHECK: sha1su0.4s v0, v1, v2 ; encoding: [0x20,0x30,0x02,0x5e]
+; CHECK: sha256h.4s q0, q1, v2 ; encoding: [0x20,0x40,0x02,0x5e]
+; CHECK: sha256h2.4s q0, q1, v2 ; encoding: [0x20,0x50,0x02,0x5e]
+; CHECK: sha256su1.4s v0, v1, v2 ; encoding: [0x20,0x60,0x02,0x5e]
+; CHECK: sha1h s0, s1 ; encoding: [0x20,0x08,0x28,0x5e]
+; CHECK: sha1su1.4s v0, v1 ; encoding: [0x20,0x18,0x28,0x5e]
+; CHECK: sha256su0.4s v0, v1 ; encoding: [0x20,0x28,0x28,0x5e]
+
+ aese v2.16b, v3.16b
+ aesd v5.16b, v7.16b
+ aesmc v11.16b, v13.16b
+ aesimc v17.16b, v19.16b
+
+; CHECK: aese.16b v2, v3 ; encoding: [0x62,0x48,0x28,0x4e]
+; CHECK: aesd.16b v5, v7 ; encoding: [0xe5,0x58,0x28,0x4e]
+; CHECK: aesmc.16b v11, v13 ; encoding: [0xab,0x69,0x28,0x4e]
+; CHECK: aesimc.16b v17, v19 ; encoding: [0x71,0x7a,0x28,0x4e]
+
+ sha1c q23, s29, v3.4s
+ sha1p q14, s15, v9.4s
+ sha1m q2, s6, v5.4s
+ sha1su0 v3.4s, v5.4s, v9.4s
+ sha256h q2, q7, v18.4s
+ sha256h2 q28, q18, v28.4s
+ sha256su1 v4.4s, v5.4s, v9.4s
+ sha1h s30, s0
+ sha1su1 v10.4s, v21.4s
+ sha256su0 v2.4s, v31.4s
+
+; CHECK: sha1c.4s q23, s29, v3 ; encoding: [0xb7,0x03,0x03,0x5e]
+; CHECK: sha1p.4s q14, s15, v9 ; encoding: [0xee,0x11,0x09,0x5e]
+; CHECK: sha1m.4s q2, s6, v5 ; encoding: [0xc2,0x20,0x05,0x5e]
+; CHECK: sha1su0.4s v3, v5, v9 ; encoding: [0xa3,0x30,0x09,0x5e]
+; CHECK: sha256h.4s q2, q7, v18 ; encoding: [0xe2,0x40,0x12,0x5e]
+; CHECK: sha256h2.4s q28, q18, v28 ; encoding: [0x5c,0x52,0x1c,0x5e]
+; CHECK: sha256su1.4s v4, v5, v9 ; encoding: [0xa4,0x60,0x09,0x5e]
+; CHECK: sha1h s30, s0 ; encoding: [0x1e,0x08,0x28,0x5e]
+; CHECK: sha1su1.4s v10, v21 ; encoding: [0xaa,0x1a,0x28,0x5e]
+; CHECK: sha256su0.4s v2, v31 ; encoding: [0xe2,0x2b,0x28,0x5e]
Added: llvm/trunk/test/MC/ARM64/diags.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/diags.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/diags.s (added)
+++ llvm/trunk/test/MC/ARM64/diags.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,242 @@
+; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+foo:
+
+; The first should encode as an expression. The second should error expecting
+; a register.
+ ldr x3, (foo + 4)
+ ldr x3, [foo + 4]
+; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58]
+; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_arm64_pcrel_imm19
+; CHECK-ERRORS: error: register expected
+
+; The last argument should be flagged as an error. rdar://9576009
+ ld4.8b {v0, v1, v2, v3}, [x0], #33
+; CHECK-ERRORS: error: invalid operand for instruction
+; CHECK-ERRORS: ld4.8b {v0, v1, v2, v3}, [x0], #33
+
+
+ ldr x0, [x0, #804]
+ ldr w0, [x0, #802]
+ ldr x0, [x0, #804]!
+ ldr w0, [w0, #301]!
+ ldr x0, [x0], #804
+ ldr w0, [w0], #301
+
+ ldp w3, w4, [x5, #11]!
+ ldp x3, x4, [x5, #12]!
+ ldp q3, q4, [x5, #12]!
+ ldp w3, w4, [x5], #11
+ ldp x3, x4, [x5], #12
+ ldp q3, q4, [x5], #12
+
+ ldur x0, [x1, #-257]
+
+; CHECK-ERRORS: error: index must be a multiple of 8 in range [0,32760].
+; CHECK-ERRORS: ldr x0, [x0, #804]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 4 in range [0,16380].
+; CHECK-ERRORS: ldr w0, [x0, #802]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be an integer in range [-256,255].
+; CHECK-ERRORS: ldr x0, [x0, #804]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be an integer in range [-256,255].
+; CHECK-ERRORS: ldr w0, [w0, #301]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be an integer in range [-256,255].
+; CHECK-ERRORS: ldr x0, [x0], #804
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be an integer in range [-256,255].
+; CHECK-ERRORS: ldr w0, [w0], #301
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256,252].
+; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504].
+; CHECK-ERRORS: ldp x3, x4, [x5, #12]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024,1008].
+; CHECK-ERRORS: ldp q3, q4, [x5, #12]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256,252].
+; CHECK-ERRORS: ldp w3, w4, [x5], #11
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504].
+; CHECK-ERRORS: ldp x3, x4, [x5], #12
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504].
+; CHECK-ERRORS: ldp q3, q4, [x5], #12
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: index must be an integer in range [-256,255].
+; CHECK-ERRORS: ldur x0, [x1, #-257]
+; CHECK-ERRORS: ^
+
+
+
+; Shift immediates range checking.
+ sqrshrn b4, h9, #10
+ rshrn v9.8b, v11.8h, #17
+ sqrshrn v7.4h, v8.4s, #39
+ uqshrn2 v4.4s, v5.2d, #67
+
+; CHECK-ERRORS: error: immediate must be an integer in range [1,8].
+; CHECK-ERRORS: sqrshrn b4, h9, #10
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1,8].
+; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1,16].
+; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: immediate must be an integer in range [1,32].
+; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67
+; CHECK-ERRORS: ^
+
+
+ st1.s4 {v14, v15}, [x2], #32
+; CHECK-ERRORS: error: invalid type suffix for instruction
+; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
+; CHECK-ERRORS: ^
+
+
+
+; Load pair instructions where Rt==Rt2 and writeback load/store instructions
+; where Rt==Rn or Rt2==Rn are unpredicatable.
+ ldp x1, x2, [x2], #16
+ ldp x2, x2, [x2], #16
+ ldp w1, w2, [x2], #16
+ ldp w2, w2, [x2], #16
+ ldp x1, x1, [x2]
+
+ ldr x2, [x2], #8
+ ldr x2, [x2, #8]!
+ ldr w2, [x2], #8
+ ldr w2, [x2, #8]!
+
+ str x2, [x2], #8
+ str x2, [x2, #8]!
+ str w2, [x2], #8
+ str w2, [x2, #8]!
+
+; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
+; CHECK-ERRORS: ldp x1, x2, [x2], #16
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
+; CHECK-ERRORS: ldp x2, x2, [x2], #16
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
+; CHECK-ERRORS: ldp w1, w2, [x2], #16
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
+; CHECK-ERRORS: ldp w2, w2, [x2], #16
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
+; CHECK-ERRORS: ldp x1, x1, [x2]
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
+; CHECK-ERRORS: ldr x2, [x2], #8
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
+; CHECK-ERRORS: ldr x2, [x2, #8]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
+; CHECK-ERRORS: ldr w2, [x2], #8
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
+; CHECK-ERRORS: ldr w2, [x2, #8]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
+; CHECK-ERRORS: str x2, [x2], #8
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
+; CHECK-ERRORS: str x2, [x2, #8]!
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
+; CHECK-ERRORS: str w2, [x2], #8
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
+; CHECK-ERRORS: str w2, [x2, #8]!
+; CHECK-ERRORS: ^
+
+; The validity checking for shifted-immediate operands. rdar://13174476
+; Where the immediate is out of range.
+ add w1, w2, w3, lsr #75
+
+; CHECK-ERRORS: error: immediate value too large for shifter operand
+; CHECK-ERRORS: add w1, w2, w3, lsr #75
+; CHECK-ERRORS: ^
+
+; logical instructions on 32-bit regs with shift > 31 is not legal
+orr w0, w0, w0, lsl #32
+; CHECK-ERRORS: error: shift value out of range
+; CHECK-ERRORS: orr w0, w0, w0, lsl #32
+; CHECK-ERRORS: ^
+eor w0, w0, w0, lsl #32
+; CHECK-ERRORS: error: shift value out of range
+; CHECK-ERRORS: eor w0, w0, w0, lsl #32
+; CHECK-ERRORS: ^
+and w0, w0, w0, lsl #32
+; CHECK-ERRORS: error: shift value out of range
+; CHECK-ERRORS: and w0, w0, w0, lsl #32
+; CHECK-ERRORS: ^
+ands w0, w0, w0, lsl #32
+; CHECK-ERRORS: error: shift value out of range
+; CHECK-ERRORS: ands w0, w0, w0, lsl #32
+; CHECK-ERRORS: ^
+
+; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
+add w3, w5, sym at PAGEOFF
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: add w3, w5, sym at PAGEOFF
+; CHECK-ERRORS: ^
+
+adds w3, w5, sym at PAGEOFF
+adds x9, x12, sym at PAGEOFF
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: adds w3, w5, sym at PAGEOFF
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: adds x9, x12, sym at PAGEOFF
+; CHECK-ERRORS: ^
+
+sub x3, x5, sym at PAGEOFF
+sub w20, w30, sym at PAGEOFF
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: sub x3, x5, sym at PAGEOFF
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: sub w20, w30, sym at PAGEOFF
+; CHECK-ERRORS: ^
+
+subs w9, w10, sym at PAGEOFF
+subs x20, x30, sym at PAGEOFF
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: subs w9, w10, sym at PAGEOFF
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid immediate expression
+; CHECK-ERRORS: subs x20, x30, sym at PAGEOFF
+; CHECK-ERRORS: ^
+
+tbl v0.8b, { v1 }, v0.8b
+tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
+tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
+tbx v2.8b, { v0 }, v6.8b
+; CHECK-ERRORS: error: invalid operand for instruction
+; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid operand for instruction
+; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid operand for instruction
+; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
+; CHECK-ERRORS: ^
+; CHECK-ERRORS: error: invalid operand for instruction
+; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
+; CHECK-ERRORS: ^
+
+b.c #0x4
+; CHECK-ERRORS: error: invalid condition code
+; CHECK-ERRORS: b.c #0x4
+; CHECK-ERRORS: ^
Added: llvm/trunk/test/MC/ARM64/directive_loh.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/directive_loh.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/directive_loh.s (added)
+++ llvm/trunk/test/MC/ARM64/directive_loh.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,93 @@
+# RUN: not llvm-mc -triple arm64-apple-darwin < %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+.globl _fct1
+_fct1:
+ L1:
+ L2:
+ L3:
+ L4:
+ ret lr;
+
+# Known LOHs with:
+# - Regular syntax.
+# - Alternative syntax.
+
+# CHECK: .loh AdrpAdrp L1, L2
+# CHECK: .loh AdrpAdrp L1, L2
+.loh AdrpAdrp L1, L2
+.loh 1 L1, L2
+
+# CHECK: .loh AdrpLdr L1, L2
+# CHECK: .loh AdrpLdr L1, L2
+.loh AdrpLdr L1, L2
+.loh 2 L1, L2
+
+# CHECK: .loh AdrpAddLdr L1, L2, L3
+# CHECK: .loh AdrpAddLdr L1, L2, L3
+.loh AdrpAddLdr L1, L2, L3
+.loh 3 L1, L2, L3
+
+# CHECK: .loh AdrpLdrGotLdr L1, L2, L3
+# CHECK: .loh AdrpLdrGotLdr L1, L2, L3
+.loh AdrpLdrGotLdr L1, L2, L3
+.loh 4 L1, L2, L3
+
+# CHECK: .loh AdrpAddStr L1, L2, L3
+# CHECK: .loh AdrpAddStr L1, L2, L3
+.loh AdrpAddStr L1, L2, L3
+.loh 5 L1, L2, L3
+
+# CHECK: .loh AdrpLdrGotStr L1, L2, L3
+# CHECK: .loh AdrpLdrGotStr L1, L2, L3
+.loh AdrpLdrGotStr L1, L2, L3
+.loh 6 L1, L2, L3
+
+# CHECK: .loh AdrpAdd L1, L2
+# CHECK: .loh AdrpAdd L1, L2
+.loh AdrpAdd L1, L2
+.loh 7 L1, L2
+
+# CHECK: .loh AdrpLdrGot L1, L2
+# CHECK: .loh AdrpLdrGot L1, L2
+.loh AdrpLdrGot L1, L2
+.loh 8 L1, L2
+
+# End Known LOHs.
+
+### Errors Check ####
+
+# Unknown textual identifier.
+# CHECK-ERRORS: error: invalid identifier in directive
+# CHECK-ERRORS-NEXT: .loh Unknown
+# CHECK-ERRORS-NEXT: ^
+.loh Unknown
+# Unknown numeric identifier.
+# CHECK-ERRORS: error: invalid numeric identifier in directive
+# CHECK-ERRORS-NEXT: .loh 153, L1
+# CHECK-ERRORS-NEXT: ^
+.loh 153, L1
+
+# Too much arguments.
+# CHECK-ERRORS: error: unexpected token in '.loh' directive
+# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1, L2, L3
+# CHECK-ERRORS-NEXT: ^
+.loh AdrpAdrp L1, L2, L3
+
+# Too much arguments with alternative syntax.
+# CHECK-ERRORS: error: unexpected token in '.loh' directive
+# CHECK-ERRORS-NEXT: .loh 1 L1, L2, L3
+# CHECK-ERRORS-NEXT: ^
+.loh 1 L1, L2, L3
+
+# Too few argumets.
+# CHECK-ERRORS: error: unexpected token in '.loh' directive
+# CHECK-ERRORS-NEXT: .loh AdrpAdrp L1
+# CHECK-ERRORS-NEXT: ^
+.loh AdrpAdrp L1
+
+# Too few argumets with alternative syntax.
+# CHECK-ERRORS: error: unexpected token in '.loh' directive
+# CHECK-ERRORS-NEXT: .loh 1 L1
+# CHECK-ERRORS-NEXT: ^
+.loh 1 L1
Added: llvm/trunk/test/MC/ARM64/elf-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/elf-relocs.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/elf-relocs.s (added)
+++ llvm/trunk/test/MC/ARM64/elf-relocs.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,249 @@
+// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
+// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
+
+ add x0, x2, #:lo12:sym
+// CHECK: add x0, x2, :lo12:sym
+// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
+
+ add x5, x7, #:dtprel_lo12:sym
+// CHECK: add x5, x7, :dtprel_lo12:sym
+// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
+
+ add x9, x12, #:dtprel_lo12_nc:sym
+// CHECK: add x9, x12, :dtprel_lo12_nc:sym
+// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
+
+ add x20, x30, #:tprel_lo12:sym
+// CHECK: add x20, lr, :tprel_lo12:sym
+// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
+
+ add x9, x12, #:tprel_lo12_nc:sym
+// CHECK: add x9, x12, :tprel_lo12_nc:sym
+// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
+
+ add x5, x0, #:tlsdesc_lo12:sym
+// CHECK: add x5, x0, :tlsdesc_lo12:sym
+// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
+
+ add x0, x2, #:lo12:sym+8
+// CHECK: add x0, x2, :lo12:sym
+// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
+
+ add x5, x7, #:dtprel_lo12:sym+1
+// CHECK: add x5, x7, :dtprel_lo12:sym+1
+// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
+
+ add x9, x12, #:dtprel_lo12_nc:sym+2
+// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
+// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
+
+ add x20, x30, #:tprel_lo12:sym+12
+// CHECK: add x20, lr, :tprel_lo12:sym+12
+// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
+
+ add x9, x12, #:tprel_lo12_nc:sym+54
+// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
+// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
+
+ add x5, x0, #:tlsdesc_lo12:sym+70
+// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
+// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
+
+ .hword sym + 4 - .
+// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
+ .word sym - . + 8
+// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
+ .xword sym-.
+// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
+
+ .hword sym
+// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
+ .word sym+1
+// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
+ .xword sym+16
+// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
+
+ adrp x0, sym
+// CHECK: adrp x0, sym
+// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
+
+ adrp x15, :got:sym
+// CHECK: adrp x15, :got:sym
+// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
+
+ adrp x29, :gottprel:sym
+// CHECK: adrp fp, :gottprel:sym
+// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
+
+ adrp x2, :tlsdesc:sym
+// CHECK: adrp x2, :tlsdesc:sym
+// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE sym
+
+ // LLVM is not competent enough to do this relocation because the
+ // page boundary could occur anywhere after linking. A relocation
+ // is needed.
+ adrp x3, trickQuestion
+ .global trickQuestion
+trickQuestion:
+// CHECK: adrp x3, trickQuestion
+// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
+
+ ldrb w2, [x3, #:lo12:sym]
+ ldrsb w5, [x7, #:lo12:sym]
+ ldrsb x11, [x13, #:lo12:sym]
+ ldr b17, [x19, #:lo12:sym]
+// CHECK: ldrb w2, [x3, :lo12:sym]
+// CHECK: ldrsb w5, [x7, :lo12:sym]
+// CHECK: ldrsb x11, [x13, :lo12:sym]
+// CHECK: ldr b17, [x19, :lo12:sym]
+// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
+
+ ldrb w23, [x29, #:dtprel_lo12_nc:sym]
+ ldrsb w23, [x19, #:dtprel_lo12:sym]
+ ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
+ ldr b11, [x7, #:dtprel_lo12:sym]
+// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
+// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
+// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
+
+ ldrb w1, [x2, #:tprel_lo12:sym]
+ ldrsb w3, [x4, #:tprel_lo12_nc:sym]
+ ldrsb x5, [x6, #:tprel_lo12:sym]
+ ldr b7, [x8, #:tprel_lo12_nc:sym]
+// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
+// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
+
+ ldrh w2, [x3, #:lo12:sym]
+ ldrsh w5, [x7, #:lo12:sym]
+ ldrsh x11, [x13, #:lo12:sym]
+ ldr h17, [x19, #:lo12:sym]
+// CHECK: ldrh w2, [x3, :lo12:sym]
+// CHECK: ldrsh w5, [x7, :lo12:sym]
+// CHECK: ldrsh x11, [x13, :lo12:sym]
+// CHECK: ldr h17, [x19, :lo12:sym]
+// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
+
+ ldrh w23, [x29, #:dtprel_lo12_nc:sym]
+ ldrsh w23, [x19, #:dtprel_lo12:sym]
+ ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
+ ldr h11, [x7, #:dtprel_lo12:sym]
+// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
+// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
+// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
+
+ ldrh w1, [x2, #:tprel_lo12:sym]
+ ldrsh w3, [x4, #:tprel_lo12_nc:sym]
+ ldrsh x5, [x6, #:tprel_lo12:sym]
+ ldr h7, [x8, #:tprel_lo12_nc:sym]
+// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
+// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
+
+ ldr w1, [x2, #:lo12:sym]
+ ldrsw x3, [x4, #:lo12:sym]
+ ldr s4, [x5, #:lo12:sym]
+// CHECK: ldr w1, [x2, :lo12:sym]
+// CHECK: ldrsw x3, [x4, :lo12:sym]
+// CHECK: ldr s4, [x5, :lo12:sym]
+// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
+
+ ldr w1, [x2, #:dtprel_lo12:sym]
+ ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
+ ldr s4, [x5, #:dtprel_lo12_nc:sym]
+// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
+// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
+// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
+
+
+ ldr w1, [x2, #:tprel_lo12:sym]
+ ldrsw x3, [x4, #:tprel_lo12_nc:sym]
+ ldr s4, [x5, #:tprel_lo12_nc:sym]
+// CHECK: ldr w1, [x2, :tprel_lo12:sym]
+// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
+// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
+
+ ldr x28, [x27, #:lo12:sym]
+ ldr d26, [x25, #:lo12:sym]
+// CHECK: ldr x28, [x27, :lo12:sym]
+// CHECK: ldr d26, [x25, :lo12:sym]
+// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
+
+ ldr x24, [x23, #:got_lo12:sym]
+ ldr d22, [x21, #:got_lo12:sym]
+// CHECK: ldr x24, [x23, :got_lo12:sym]
+// CHECK: ldr d22, [x21, :got_lo12:sym]
+// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
+
+ ldr x24, [x23, #:dtprel_lo12_nc:sym]
+ ldr d22, [x21, #:dtprel_lo12:sym]
+// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
+// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
+
+ ldr x24, [x23, #:tprel_lo12:sym]
+ ldr d22, [x21, #:tprel_lo12_nc:sym]
+// CHECK: ldr x24, [x23, :tprel_lo12:sym]
+// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
+// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
+
+ ldr x24, [x23, #:gottprel_lo12:sym]
+ ldr d22, [x21, #:gottprel_lo12:sym]
+// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
+// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
+// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
+
+ ldr x24, [x23, #:tlsdesc_lo12:sym]
+ ldr d22, [x21, #:tlsdesc_lo12:sym]
+// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
+// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
+// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
+// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
+
+ ldr q20, [x19, #:lo12:sym]
+// CHECK: ldr q20, [x19, :lo12:sym]
+// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
+
+// Since relocated instructions print without a '#', that syntax should
+// certainly be accepted when assembling.
+ add x3, x5, :lo12:imm
+// CHECK: add x3, x5, :lo12:imm
Added: llvm/trunk/test/MC/ARM64/fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/fp-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/fp-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/fp-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,507 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+;-----------------------------------------------------------------------------
+; Floating-point arithmetic
+;-----------------------------------------------------------------------------
+
+ fabs s1, s2
+ fabs d1, d2
+
+; CHECK: fabs s1, s2 ; encoding: [0x41,0xc0,0x20,0x1e]
+; CHECK: fabs d1, d2 ; encoding: [0x41,0xc0,0x60,0x1e]
+
+ fadd s1, s2, s3
+ fadd d1, d2, d3
+
+; CHECK: fadd s1, s2, s3 ; encoding: [0x41,0x28,0x23,0x1e]
+; CHECK: fadd d1, d2, d3 ; encoding: [0x41,0x28,0x63,0x1e]
+
+ fdiv s1, s2, s3
+ fdiv d1, d2, d3
+
+; CHECK: fdiv s1, s2, s3 ; encoding: [0x41,0x18,0x23,0x1e]
+; CHECK: fdiv d1, d2, d3 ; encoding: [0x41,0x18,0x63,0x1e]
+
+ fmadd s1, s2, s3, s4
+ fmadd d1, d2, d3, d4
+
+; CHECK: fmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x03,0x1f]
+; CHECK: fmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x43,0x1f]
+
+ fmax s1, s2, s3
+ fmax d1, d2, d3
+ fmaxnm s1, s2, s3
+ fmaxnm d1, d2, d3
+
+; CHECK: fmax s1, s2, s3 ; encoding: [0x41,0x48,0x23,0x1e]
+; CHECK: fmax d1, d2, d3 ; encoding: [0x41,0x48,0x63,0x1e]
+; CHECK: fmaxnm s1, s2, s3 ; encoding: [0x41,0x68,0x23,0x1e]
+; CHECK: fmaxnm d1, d2, d3 ; encoding: [0x41,0x68,0x63,0x1e]
+
+ fmin s1, s2, s3
+ fmin d1, d2, d3
+ fminnm s1, s2, s3
+ fminnm d1, d2, d3
+
+; CHECK: fmin s1, s2, s3 ; encoding: [0x41,0x58,0x23,0x1e]
+; CHECK: fmin d1, d2, d3 ; encoding: [0x41,0x58,0x63,0x1e]
+; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e]
+; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e]
+
+ fmsub s1, s2, s3, s4
+ fmsub d1, d2, d3, d4
+
+; CHECK: fmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x03,0x1f]
+; CHECK: fmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x43,0x1f]
+
+ fmul s1, s2, s3
+ fmul d1, d2, d3
+
+; CHECK: fmul s1, s2, s3 ; encoding: [0x41,0x08,0x23,0x1e]
+; CHECK: fmul d1, d2, d3 ; encoding: [0x41,0x08,0x63,0x1e]
+
+ fneg s1, s2
+ fneg d1, d2
+
+; CHECK: fneg s1, s2 ; encoding: [0x41,0x40,0x21,0x1e]
+; CHECK: fneg d1, d2 ; encoding: [0x41,0x40,0x61,0x1e]
+
+ fnmadd s1, s2, s3, s4
+ fnmadd d1, d2, d3, d4
+
+; CHECK: fnmadd s1, s2, s3, s4 ; encoding: [0x41,0x10,0x23,0x1f]
+; CHECK: fnmadd d1, d2, d3, d4 ; encoding: [0x41,0x10,0x63,0x1f]
+
+ fnmsub s1, s2, s3, s4
+ fnmsub d1, d2, d3, d4
+
+; CHECK: fnmsub s1, s2, s3, s4 ; encoding: [0x41,0x90,0x23,0x1f]
+; CHECK: fnmsub d1, d2, d3, d4 ; encoding: [0x41,0x90,0x63,0x1f]
+
+ fnmul s1, s2, s3
+ fnmul d1, d2, d3
+
+; CHECK: fnmul s1, s2, s3 ; encoding: [0x41,0x88,0x23,0x1e]
+; CHECK: fnmul d1, d2, d3 ; encoding: [0x41,0x88,0x63,0x1e]
+
+ fsqrt s1, s2
+ fsqrt d1, d2
+
+; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e]
+; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e]
+
+ fsub s1, s2, s3
+ fsub d1, d2, d3
+
+; CHECK: fsub s1, s2, s3 ; encoding: [0x41,0x38,0x23,0x1e]
+; CHECK: fsub d1, d2, d3 ; encoding: [0x41,0x38,0x63,0x1e]
+
+;-----------------------------------------------------------------------------
+; Floating-point comparison
+;-----------------------------------------------------------------------------
+
+ fccmp s1, s2, #0, eq
+ fccmp d1, d2, #0, eq
+ fccmpe s1, s2, #0, eq
+ fccmpe d1, d2, #0, eq
+
+; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e]
+; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e]
+; CHECK: fccmpe s1, s2, #0, eq ; encoding: [0x30,0x04,0x22,0x1e]
+; CHECK: fccmpe d1, d2, #0, eq ; encoding: [0x30,0x04,0x62,0x1e]
+
+ fcmp s1, s2
+ fcmp d1, d2
+ fcmp s1, #0.0
+ fcmp d1, #0.0
+ fcmpe s1, s2
+ fcmpe d1, d2
+ fcmpe s1, #0.0
+ fcmpe d1, #0.0
+
+; CHECK: fcmp s1, s2 ; encoding: [0x20,0x20,0x22,0x1e]
+; CHECK: fcmp d1, d2 ; encoding: [0x20,0x20,0x62,0x1e]
+; CHECK: fcmp s1, #0.0 ; encoding: [0x28,0x20,0x20,0x1e]
+; CHECK: fcmp d1, #0.0 ; encoding: [0x28,0x20,0x60,0x1e]
+; CHECK: fcmpe s1, s2 ; encoding: [0x30,0x20,0x22,0x1e]
+; CHECK: fcmpe d1, d2 ; encoding: [0x30,0x20,0x62,0x1e]
+; CHECK: fcmpe s1, #0.0 ; encoding: [0x38,0x20,0x20,0x1e]
+; CHECK: fcmpe d1, #0.0 ; encoding: [0x38,0x20,0x60,0x1e]
+
+;-----------------------------------------------------------------------------
+; Floating-point conditional select
+;-----------------------------------------------------------------------------
+
+ fcsel s1, s2, s3, eq
+ fcsel d1, d2, d3, eq
+
+; CHECK: fcsel s1, s2, s3, eq ; encoding: [0x41,0x0c,0x23,0x1e]
+; CHECK: fcsel d1, d2, d3, eq ; encoding: [0x41,0x0c,0x63,0x1e]
+
+;-----------------------------------------------------------------------------
+; Floating-point convert
+;-----------------------------------------------------------------------------
+
+ fcvt h1, d2
+ fcvt s1, d2
+ fcvt d1, h2
+ fcvt s1, h2
+ fcvt d1, s2
+ fcvt h1, s2
+
+; CHECK: fcvt h1, d2 ; encoding: [0x41,0xc0,0x63,0x1e]
+; CHECK: fcvt s1, d2 ; encoding: [0x41,0x40,0x62,0x1e]
+; CHECK: fcvt d1, h2 ; encoding: [0x41,0xc0,0xe2,0x1e]
+; CHECK: fcvt s1, h2 ; encoding: [0x41,0x40,0xe2,0x1e]
+; CHECK: fcvt d1, s2 ; encoding: [0x41,0xc0,0x22,0x1e]
+; CHECK: fcvt h1, s2 ; encoding: [0x41,0xc0,0x23,0x1e]
+
+ fcvtas w1, d2
+ fcvtas w1, d2, #1
+ fcvtas x1, d2
+ fcvtas x1, d2, #1
+ fcvtas w1, s2
+ fcvtas w1, s2, #1
+ fcvtas x1, s2
+ fcvtas x1, s2, #1
+
+; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
+; CHECK: fcvtas w1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x1e]
+; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
+; CHECK: fcvtas x1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x9e]
+; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
+; CHECK: fcvtas w1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x1e]
+; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
+; CHECK: fcvtas x1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x9e]
+
+ fcvtau w1, s2
+ fcvtau w1, s2, #1
+ fcvtau w1, d2
+ fcvtau w1, d2, #1
+ fcvtau x1, s2
+ fcvtau x1, s2, #1
+ fcvtau x1, d2
+ fcvtau x1, d2, #1
+
+; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
+; CHECK: fcvtau w1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x1e]
+; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
+; CHECK: fcvtau w1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x1e]
+; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e]
+; CHECK: fcvtau x1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x9e]
+; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e]
+; CHECK: fcvtau x1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x9e]
+
+ fcvtms w1, s2
+ fcvtms w1, s2, #1
+ fcvtms w1, d2
+ fcvtms w1, d2, #1
+ fcvtms x1, s2
+ fcvtms x1, s2, #1
+ fcvtms x1, d2
+ fcvtms x1, d2, #1
+
+; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e]
+; CHECK: fcvtms w1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x1e]
+; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e]
+; CHECK: fcvtms w1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x1e]
+; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e]
+; CHECK: fcvtms x1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x9e]
+; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e]
+; CHECK: fcvtms x1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x9e]
+
+ fcvtmu w1, s2
+ fcvtmu w1, s2, #1
+ fcvtmu w1, d2
+ fcvtmu w1, d2, #1
+ fcvtmu x1, s2
+ fcvtmu x1, s2, #1
+ fcvtmu x1, d2
+ fcvtmu x1, d2, #1
+
+; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e]
+; CHECK: fcvtmu w1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x1e]
+; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e]
+; CHECK: fcvtmu w1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x1e]
+; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e]
+; CHECK: fcvtmu x1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x9e]
+; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e]
+; CHECK: fcvtmu x1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x9e]
+
+ fcvtns w1, s2
+ fcvtns w1, s2, #1
+ fcvtns w1, d2
+ fcvtns w1, d2, #1
+ fcvtns x1, s2
+ fcvtns x1, s2, #1
+ fcvtns x1, d2
+ fcvtns x1, d2, #1
+
+; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e]
+; CHECK: fcvtns w1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x1e]
+; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e]
+; CHECK: fcvtns w1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x1e]
+; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e]
+; CHECK: fcvtns x1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x9e]
+; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e]
+; CHECK: fcvtns x1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x9e]
+
+ fcvtnu w1, s2
+ fcvtnu w1, s2, #1
+ fcvtnu w1, d2
+ fcvtnu w1, d2, #1
+ fcvtnu x1, s2
+ fcvtnu x1, s2, #1
+ fcvtnu x1, d2
+ fcvtnu x1, d2, #1
+
+; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
+; CHECK: fcvtnu w1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x1e]
+; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
+; CHECK: fcvtnu w1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x1e]
+; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e]
+; CHECK: fcvtnu x1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x9e]
+; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e]
+; CHECK: fcvtnu x1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x9e]
+
+ fcvtps w1, s2
+ fcvtps w1, s2, #1
+ fcvtps w1, d2
+ fcvtps w1, d2, #1
+ fcvtps x1, s2
+ fcvtps x1, s2, #1
+ fcvtps x1, d2
+ fcvtps x1, d2, #1
+
+; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e]
+; CHECK: fcvtps w1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x1e]
+; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e]
+; CHECK: fcvtps w1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x1e]
+; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e]
+; CHECK: fcvtps x1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x9e]
+; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e]
+; CHECK: fcvtps x1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x9e]
+
+ fcvtpu w1, s2
+ fcvtpu w1, s2, #1
+ fcvtpu w1, d2
+ fcvtpu w1, d2, #1
+ fcvtpu x1, s2
+ fcvtpu x1, s2, #1
+ fcvtpu x1, d2
+ fcvtpu x1, d2, #1
+
+; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e]
+; CHECK: fcvtpu w1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x1e]
+; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e]
+; CHECK: fcvtpu w1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x1e]
+; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e]
+; CHECK: fcvtpu x1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x9e]
+; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e]
+; CHECK: fcvtpu x1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x9e]
+
+ fcvtzs w1, s2
+ fcvtzs w1, s2, #1
+ fcvtzs w1, d2
+ fcvtzs w1, d2, #1
+ fcvtzs x1, s2
+ fcvtzs x1, s2, #1
+ fcvtzs x1, d2
+ fcvtzs x1, d2, #1
+
+; CHECK: fcvtzs w1, s2 ; encoding: [0x41,0x00,0x38,0x1e]
+; CHECK: fcvtzs w1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x1e]
+; CHECK: fcvtzs w1, d2 ; encoding: [0x41,0x00,0x78,0x1e]
+; CHECK: fcvtzs w1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x1e]
+; CHECK: fcvtzs x1, s2 ; encoding: [0x41,0x00,0x38,0x9e]
+; CHECK: fcvtzs x1, s2, #1 ; encoding: [0x41,0xfc,0x18,0x9e]
+; CHECK: fcvtzs x1, d2 ; encoding: [0x41,0x00,0x78,0x9e]
+; CHECK: fcvtzs x1, d2, #1 ; encoding: [0x41,0xfc,0x58,0x9e]
+
+ fcvtzu w1, s2
+ fcvtzu w1, s2, #1
+ fcvtzu w1, d2
+ fcvtzu w1, d2, #1
+ fcvtzu x1, s2
+ fcvtzu x1, s2, #1
+ fcvtzu x1, d2
+ fcvtzu x1, d2, #1
+
+; CHECK: fcvtzu w1, s2 ; encoding: [0x41,0x00,0x39,0x1e]
+; CHECK: fcvtzu w1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x1e]
+; CHECK: fcvtzu w1, d2 ; encoding: [0x41,0x00,0x79,0x1e]
+; CHECK: fcvtzu w1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x1e]
+; CHECK: fcvtzu x1, s2 ; encoding: [0x41,0x00,0x39,0x9e]
+; CHECK: fcvtzu x1, s2, #1 ; encoding: [0x41,0xfc,0x19,0x9e]
+; CHECK: fcvtzu x1, d2 ; encoding: [0x41,0x00,0x79,0x9e]
+; CHECK: fcvtzu x1, d2, #1 ; encoding: [0x41,0xfc,0x59,0x9e]
+
+ scvtf s1, w2
+ scvtf s1, w2, #1
+ scvtf d1, w2
+ scvtf d1, w2, #1
+ scvtf s1, x2
+ scvtf s1, x2, #1
+ scvtf d1, x2
+ scvtf d1, x2, #1
+
+; CHECK: scvtf s1, w2 ; encoding: [0x41,0x00,0x22,0x1e]
+; CHECK: scvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x02,0x1e]
+; CHECK: scvtf d1, w2 ; encoding: [0x41,0x00,0x62,0x1e]
+; CHECK: scvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x42,0x1e]
+; CHECK: scvtf s1, x2 ; encoding: [0x41,0x00,0x22,0x9e]
+; CHECK: scvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x02,0x9e]
+; CHECK: scvtf d1, x2 ; encoding: [0x41,0x00,0x62,0x9e]
+; CHECK: scvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x42,0x9e]
+
+ ucvtf s1, w2
+ ucvtf s1, w2, #1
+ ucvtf d1, w2
+ ucvtf d1, w2, #1
+ ucvtf s1, x2
+ ucvtf s1, x2, #1
+ ucvtf d1, x2
+ ucvtf d1, x2, #1
+
+; CHECK: ucvtf s1, w2 ; encoding: [0x41,0x00,0x23,0x1e]
+; CHECK: ucvtf s1, w2, #1 ; encoding: [0x41,0xfc,0x03,0x1e]
+; CHECK: ucvtf d1, w2 ; encoding: [0x41,0x00,0x63,0x1e]
+; CHECK: ucvtf d1, w2, #1 ; encoding: [0x41,0xfc,0x43,0x1e]
+; CHECK: ucvtf s1, x2 ; encoding: [0x41,0x00,0x23,0x9e]
+; CHECK: ucvtf s1, x2, #1 ; encoding: [0x41,0xfc,0x03,0x9e]
+; CHECK: ucvtf d1, x2 ; encoding: [0x41,0x00,0x63,0x9e]
+; CHECK: ucvtf d1, x2, #1 ; encoding: [0x41,0xfc,0x43,0x9e]
+
+;-----------------------------------------------------------------------------
+; Floating-point move
+;-----------------------------------------------------------------------------
+
+ fmov s1, w2
+ fmov w1, s2
+ fmov d1, x2
+ fmov x1, d2
+
+; CHECK: fmov s1, w2 ; encoding: [0x41,0x00,0x27,0x1e]
+; CHECK: fmov w1, s2 ; encoding: [0x41,0x00,0x26,0x1e]
+; CHECK: fmov d1, x2 ; encoding: [0x41,0x00,0x67,0x9e]
+; CHECK: fmov x1, d2 ; encoding: [0x41,0x00,0x66,0x9e]
+
+ fmov s1, #0.125
+ fmov s1, #0x40
+ fmov d1, #0.125
+ fmov d1, #0x40
+ fmov d1, #-4.843750e-01
+ fmov d1, #4.843750e-01
+ fmov d3, #3
+ fmov s2, #0.0
+ fmov d2, #0.0
+
+; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e]
+; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e]
+; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e]
+; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e]
+; CHECK: fmov d1, #-4.843750e-01 ; encoding: [0x01,0xf0,0x7b,0x1e]
+; CHECK: fmov d1, #4.843750e-01 ; encoding: [0x01,0xf0,0x6b,0x1e]
+; CHECK: fmov d3, #3.000000e+00 ; encoding: [0x03,0x10,0x61,0x1e]
+; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e]
+; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e]
+
+ fmov s1, s2
+ fmov d1, d2
+
+; CHECK: fmov s1, s2 ; encoding: [0x41,0x40,0x20,0x1e]
+; CHECK: fmov d1, d2 ; encoding: [0x41,0x40,0x60,0x1e]
+
+
+ fmov x2, v5.d[1]
+ fmov.d x9, v7[1]
+ fmov v1.d[1], x1
+ fmov.d v8[1], x6
+
+; CHECK: fmov.d x2, v5[1] ; encoding: [0xa2,0x00,0xae,0x9e]
+; CHECK: fmov.d x9, v7[1] ; encoding: [0xe9,0x00,0xae,0x9e]
+; CHECK: fmov.d v1[1], x1 ; encoding: [0x21,0x00,0xaf,0x9e]
+; CHECK: fmov.d v8[1], x6 ; encoding: [0xc8,0x00,0xaf,0x9e]
+
+
+;-----------------------------------------------------------------------------
+; Floating-point round to integral
+;-----------------------------------------------------------------------------
+
+ frinta s1, s2
+ frinta d1, d2
+
+; CHECK: frinta s1, s2 ; encoding: [0x41,0x40,0x26,0x1e]
+; CHECK: frinta d1, d2 ; encoding: [0x41,0x40,0x66,0x1e]
+
+ frinti s1, s2
+ frinti d1, d2
+
+; CHECK: frinti s1, s2 ; encoding: [0x41,0xc0,0x27,0x1e]
+; CHECK: frinti d1, d2 ; encoding: [0x41,0xc0,0x67,0x1e]
+
+ frintm s1, s2
+ frintm d1, d2
+
+; CHECK: frintm s1, s2 ; encoding: [0x41,0x40,0x25,0x1e]
+; CHECK: frintm d1, d2 ; encoding: [0x41,0x40,0x65,0x1e]
+
+ frintn s1, s2
+ frintn d1, d2
+
+; CHECK: frintn s1, s2 ; encoding: [0x41,0x40,0x24,0x1e]
+; CHECK: frintn d1, d2 ; encoding: [0x41,0x40,0x64,0x1e]
+
+ frintp s1, s2
+ frintp d1, d2
+
+; CHECK: frintp s1, s2 ; encoding: [0x41,0xc0,0x24,0x1e]
+; CHECK: frintp d1, d2 ; encoding: [0x41,0xc0,0x64,0x1e]
+
+ frintx s1, s2
+ frintx d1, d2
+
+; CHECK: frintx s1, s2 ; encoding: [0x41,0x40,0x27,0x1e]
+; CHECK: frintx d1, d2 ; encoding: [0x41,0x40,0x67,0x1e]
+
+ frintz s1, s2
+ frintz d1, d2
+
+; CHECK: frintz s1, s2 ; encoding: [0x41,0xc0,0x25,0x1e]
+; CHECK: frintz d1, d2 ; encoding: [0x41,0xc0,0x65,0x1e]
+
+ cmhs d0, d0, d0
+ cmtst d0, d0, d0
+
+; CHECK: cmhs d0, d0, d0 ; encoding: [0x00,0x3c,0xe0,0x7e]
+; CHECK: cmtst d0, d0, d0 ; encoding: [0x00,0x8c,0xe0,0x5e]
+
+
+
+;-----------------------------------------------------------------------------
+; Floating-point extract and narrow
+;-----------------------------------------------------------------------------
+ sqxtn b4, h2
+ sqxtn h2, s3
+ sqxtn s9, d2
+
+; CHECK: sqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x5e]
+; CHECK: sqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x5e]
+; CHECK: sqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x5e]
+
+ sqxtun b4, h2
+ sqxtun h2, s3
+ sqxtun s9, d2
+
+; CHECK: sqxtun b4, h2 ; encoding: [0x44,0x28,0x21,0x7e]
+; CHECK: sqxtun h2, s3 ; encoding: [0x62,0x28,0x61,0x7e]
+; CHECK: sqxtun s9, d2 ; encoding: [0x49,0x28,0xa1,0x7e]
+
+ uqxtn b4, h2
+ uqxtn h2, s3
+ uqxtn s9, d2
+
+; CHECK: uqxtn b4, h2 ; encoding: [0x44,0x48,0x21,0x7e]
+; CHECK: uqxtn h2, s3 ; encoding: [0x62,0x48,0x61,0x7e]
+; CHECK: uqxtn s9, d2 ; encoding: [0x49,0x48,0xa1,0x7e]
Added: llvm/trunk/test/MC/ARM64/large-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/large-relocs.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/large-relocs.s (added)
+++ llvm/trunk/test/MC/ARM64/large-relocs.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -o - %s | FileCheck %s
+// RUN: llvm-mc -triple=arm64-linux-gnu -show-encoding -filetype=obj -o - %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-OBJ %s
+
+ movz x2, #:abs_g0:sym
+ movk w3, #:abs_g0_nc:sym
+// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw
+// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw
+
+// CHECK-OBJ: 0 R_AARCH64_MOVW_UABS_G0 sym
+// CHECK-OBJ: 4 R_AARCH64_MOVW_UABS_G0_NC sym
+
+ movz x4, #:abs_g1:sym
+ movk w5, #:abs_g1_nc:sym
+// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw
+// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw
+
+// CHECK-OBJ: 8 R_AARCH64_MOVW_UABS_G1 sym
+// CHECK-OBJ: c R_AARCH64_MOVW_UABS_G1_NC sym
+
+ movz x6, #:abs_g2:sym
+ movk x7, #:abs_g2_nc:sym
+// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw
+// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw
+
+// CHECK-OBJ: 10 R_AARCH64_MOVW_UABS_G2 sym
+// CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym
+
+ movz x8, #:abs_g3:sym
+// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw
+
+// CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym
Added: llvm/trunk/test/MC/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/MC/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,6 @@
+config.suffixes = ['.ll', '.c', '.cpp', '.s']
+
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
+
Added: llvm/trunk/test/MC/ARM64/logical-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/logical-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/logical-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/logical-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,224 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+;==---------------------------------------------------------------------------==
+; 5.4.2 Logical (immediate)
+;==---------------------------------------------------------------------------==
+
+ and w0, w0, #1
+ and x0, x0, #1
+ and w1, w2, #15
+ and x1, x2, #15
+ and sp, x5, #~15
+ ands w0, w0, #1
+ ands x0, x0, #1
+ ands w1, w2, #15
+ ands x1, x2, #15
+
+; CHECK: and w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x12]
+; CHECK: and x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0x92]
+; CHECK: and w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x12]
+; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
+; CHECK: and sp, x5, #0xfffffffffffffff0 ; encoding: [0xbf,0xec,0x7c,0x92]
+; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72]
+; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2]
+; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72]
+; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
+
+ eor w1, w2, #0x4000
+ eor x1, x2, #0x8000
+
+; CHECK: eor w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x52]
+; CHECK: eor x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xd2]
+
+ orr w1, w2, #0x4000
+ orr x1, x2, #0x8000
+
+; CHECK: orr w1, w2, #0x4000 ; encoding: [0x41,0x00,0x12,0x32]
+; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
+
+ orr w8, wzr, #0x1
+ orr x8, xzr, #0x1
+
+; CHECK: orr w8, wzr, #0x1 ; encoding: [0xe8,0x03,0x00,0x32]
+; CHECK: orr x8, xzr, #0x1 ; encoding: [0xe8,0x03,0x40,0xb2]
+
+;==---------------------------------------------------------------------------==
+; 5.5.3 Logical (shifted register)
+;==---------------------------------------------------------------------------==
+
+ and w1, w2, w3
+ and x1, x2, x3
+ and w1, w2, w3, lsl #2
+ and x1, x2, x3, lsl #2
+ and w1, w2, w3, lsr #2
+ and x1, x2, x3, lsr #2
+ and w1, w2, w3, asr #2
+ and x1, x2, x3, asr #2
+ and w1, w2, w3, ror #2
+ and x1, x2, x3, ror #2
+
+; CHECK: and w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x0a]
+; CHECK: and x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x8a]
+; CHECK: and w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x0a]
+; CHECK: and x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0x8a]
+; CHECK: and w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x0a]
+; CHECK: and x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0x8a]
+; CHECK: and w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x0a]
+; CHECK: and x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0x8a]
+; CHECK: and w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x0a]
+; CHECK: and x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0x8a]
+
+ ands w1, w2, w3
+ ands x1, x2, x3
+ ands w1, w2, w3, lsl #2
+ ands x1, x2, x3, lsl #2
+ ands w1, w2, w3, lsr #2
+ ands x1, x2, x3, lsr #2
+ ands w1, w2, w3, asr #2
+ ands x1, x2, x3, asr #2
+ ands w1, w2, w3, ror #2
+ ands x1, x2, x3, ror #2
+
+; CHECK: ands w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x6a]
+; CHECK: ands x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xea]
+; CHECK: ands w1, w2, w3, lsl #2 ; encoding: [0x41,0x08,0x03,0x6a]
+; CHECK: ands x1, x2, x3, lsl #2 ; encoding: [0x41,0x08,0x03,0xea]
+; CHECK: ands w1, w2, w3, lsr #2 ; encoding: [0x41,0x08,0x43,0x6a]
+; CHECK: ands x1, x2, x3, lsr #2 ; encoding: [0x41,0x08,0x43,0xea]
+; CHECK: ands w1, w2, w3, asr #2 ; encoding: [0x41,0x08,0x83,0x6a]
+; CHECK: ands x1, x2, x3, asr #2 ; encoding: [0x41,0x08,0x83,0xea]
+; CHECK: ands w1, w2, w3, ror #2 ; encoding: [0x41,0x08,0xc3,0x6a]
+; CHECK: ands x1, x2, x3, ror #2 ; encoding: [0x41,0x08,0xc3,0xea]
+
+ bic w1, w2, w3
+ bic x1, x2, x3
+ bic w1, w2, w3, lsl #3
+ bic x1, x2, x3, lsl #3
+ bic w1, w2, w3, lsr #3
+ bic x1, x2, x3, lsr #3
+ bic w1, w2, w3, asr #3
+ bic x1, x2, x3, asr #3
+ bic w1, w2, w3, ror #3
+ bic x1, x2, x3, ror #3
+
+; CHECK: bic w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x0a]
+; CHECK: bic x1, x2, x3 ; encoding: [0x41,0x00,0x23,0x8a]
+; CHECK: bic w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x0a]
+; CHECK: bic x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x8a]
+; CHECK: bic w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x0a]
+; CHECK: bic x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x8a]
+; CHECK: bic w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x0a]
+; CHECK: bic x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x8a]
+; CHECK: bic w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x0a]
+; CHECK: bic x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x8a]
+
+ bics w1, w2, w3
+ bics x1, x2, x3
+ bics w1, w2, w3, lsl #3
+ bics x1, x2, x3, lsl #3
+ bics w1, w2, w3, lsr #3
+ bics x1, x2, x3, lsr #3
+ bics w1, w2, w3, asr #3
+ bics x1, x2, x3, asr #3
+ bics w1, w2, w3, ror #3
+ bics x1, x2, x3, ror #3
+
+; CHECK: bics w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x6a]
+; CHECK: bics x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xea]
+; CHECK: bics w1, w2, w3, lsl #3 ; encoding: [0x41,0x0c,0x23,0x6a]
+; CHECK: bics x1, x2, x3, lsl #3 ; encoding: [0x41,0x0c,0x23,0xea]
+; CHECK: bics w1, w2, w3, lsr #3 ; encoding: [0x41,0x0c,0x63,0x6a]
+; CHECK: bics x1, x2, x3, lsr #3 ; encoding: [0x41,0x0c,0x63,0xea]
+; CHECK: bics w1, w2, w3, asr #3 ; encoding: [0x41,0x0c,0xa3,0x6a]
+; CHECK: bics x1, x2, x3, asr #3 ; encoding: [0x41,0x0c,0xa3,0xea]
+; CHECK: bics w1, w2, w3, ror #3 ; encoding: [0x41,0x0c,0xe3,0x6a]
+; CHECK: bics x1, x2, x3, ror #3 ; encoding: [0x41,0x0c,0xe3,0xea]
+
+ eon w1, w2, w3
+ eon x1, x2, x3
+ eon w1, w2, w3, lsl #4
+ eon x1, x2, x3, lsl #4
+ eon w1, w2, w3, lsr #4
+ eon x1, x2, x3, lsr #4
+ eon w1, w2, w3, asr #4
+ eon x1, x2, x3, asr #4
+ eon w1, w2, w3, ror #4
+ eon x1, x2, x3, ror #4
+
+; CHECK: eon w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x4a]
+; CHECK: eon x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xca]
+; CHECK: eon w1, w2, w3, lsl #4 ; encoding: [0x41,0x10,0x23,0x4a]
+; CHECK: eon x1, x2, x3, lsl #4 ; encoding: [0x41,0x10,0x23,0xca]
+; CHECK: eon w1, w2, w3, lsr #4 ; encoding: [0x41,0x10,0x63,0x4a]
+; CHECK: eon x1, x2, x3, lsr #4 ; encoding: [0x41,0x10,0x63,0xca]
+; CHECK: eon w1, w2, w3, asr #4 ; encoding: [0x41,0x10,0xa3,0x4a]
+; CHECK: eon x1, x2, x3, asr #4 ; encoding: [0x41,0x10,0xa3,0xca]
+; CHECK: eon w1, w2, w3, ror #4 ; encoding: [0x41,0x10,0xe3,0x4a]
+; CHECK: eon x1, x2, x3, ror #4 ; encoding: [0x41,0x10,0xe3,0xca]
+
+ eor w1, w2, w3
+ eor x1, x2, x3
+ eor w1, w2, w3, lsl #5
+ eor x1, x2, x3, lsl #5
+ eor w1, w2, w3, lsr #5
+ eor x1, x2, x3, lsr #5
+ eor w1, w2, w3, asr #5
+ eor x1, x2, x3, asr #5
+ eor w1, w2, w3, ror #5
+ eor x1, x2, x3, ror #5
+
+; CHECK: eor w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x4a]
+; CHECK: eor x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xca]
+; CHECK: eor w1, w2, w3, lsl #5 ; encoding: [0x41,0x14,0x03,0x4a]
+; CHECK: eor x1, x2, x3, lsl #5 ; encoding: [0x41,0x14,0x03,0xca]
+; CHECK: eor w1, w2, w3, lsr #5 ; encoding: [0x41,0x14,0x43,0x4a]
+; CHECK: eor x1, x2, x3, lsr #5 ; encoding: [0x41,0x14,0x43,0xca]
+; CHECK: eor w1, w2, w3, asr #5 ; encoding: [0x41,0x14,0x83,0x4a]
+; CHECK: eor x1, x2, x3, asr #5 ; encoding: [0x41,0x14,0x83,0xca]
+; CHECK: eor w1, w2, w3, ror #5 ; encoding: [0x41,0x14,0xc3,0x4a]
+; CHECK: eor x1, x2, x3, ror #5 ; encoding: [0x41,0x14,0xc3,0xca]
+
+ orr w1, w2, w3
+ orr x1, x2, x3
+ orr w1, w2, w3, lsl #6
+ orr x1, x2, x3, lsl #6
+ orr w1, w2, w3, lsr #6
+ orr x1, x2, x3, lsr #6
+ orr w1, w2, w3, asr #6
+ orr x1, x2, x3, asr #6
+ orr w1, w2, w3, ror #6
+ orr x1, x2, x3, ror #6
+
+; CHECK: orr w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x2a]
+; CHECK: orr x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xaa]
+; CHECK: orr w1, w2, w3, lsl #6 ; encoding: [0x41,0x18,0x03,0x2a]
+; CHECK: orr x1, x2, x3, lsl #6 ; encoding: [0x41,0x18,0x03,0xaa]
+; CHECK: orr w1, w2, w3, lsr #6 ; encoding: [0x41,0x18,0x43,0x2a]
+; CHECK: orr x1, x2, x3, lsr #6 ; encoding: [0x41,0x18,0x43,0xaa]
+; CHECK: orr w1, w2, w3, asr #6 ; encoding: [0x41,0x18,0x83,0x2a]
+; CHECK: orr x1, x2, x3, asr #6 ; encoding: [0x41,0x18,0x83,0xaa]
+; CHECK: orr w1, w2, w3, ror #6 ; encoding: [0x41,0x18,0xc3,0x2a]
+; CHECK: orr x1, x2, x3, ror #6 ; encoding: [0x41,0x18,0xc3,0xaa]
+
+ orn w1, w2, w3
+ orn x1, x2, x3
+ orn w1, w2, w3, lsl #7
+ orn x1, x2, x3, lsl #7
+ orn w1, w2, w3, lsr #7
+ orn x1, x2, x3, lsr #7
+ orn w1, w2, w3, asr #7
+ orn x1, x2, x3, asr #7
+ orn w1, w2, w3, ror #7
+ orn x1, x2, x3, ror #7
+
+; CHECK: orn w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x2a]
+; CHECK: orn x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xaa]
+; CHECK: orn w1, w2, w3, lsl #7 ; encoding: [0x41,0x1c,0x23,0x2a]
+; CHECK: orn x1, x2, x3, lsl #7 ; encoding: [0x41,0x1c,0x23,0xaa]
+; CHECK: orn w1, w2, w3, lsr #7 ; encoding: [0x41,0x1c,0x63,0x2a]
+; CHECK: orn x1, x2, x3, lsr #7 ; encoding: [0x41,0x1c,0x63,0xaa]
+; CHECK: orn w1, w2, w3, asr #7 ; encoding: [0x41,0x1c,0xa3,0x2a]
+; CHECK: orn x1, x2, x3, asr #7 ; encoding: [0x41,0x1c,0xa3,0xaa]
+; CHECK: orn w1, w2, w3, ror #7 ; encoding: [0x41,0x1c,0xe3,0x2a]
+; CHECK: orn x1, x2, x3, ror #7 ; encoding: [0x41,0x1c,0xe3,0xaa]
Added: llvm/trunk/test/MC/ARM64/mapping-across-sections.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/mapping-across-sections.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/mapping-across-sections.s (added)
+++ llvm/trunk/test/MC/ARM64/mapping-across-sections.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,28 @@
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+
+ .text
+ add w0, w0, w0
+
+// .wibble should *not* inherit .text's mapping symbol. It's a completely different section.
+ .section .wibble
+ add w0, w0, w0
+
+// A setion should be able to start with a $d
+ .section .starts_data
+ .word 42
+
+// Changing back to .text should not emit a redundant $x
+ .text
+ add w0, w0, w0
+
+// With all those constraints, we want:
+// + .text to have $x at 0 and no others
+// + .wibble to have $x at 0
+// + .starts_data to have $d at 0
+
+
+// CHECK: 00000000 .starts_data 00000000 $d
+// CHECK-NEXT: 00000000 .text 00000000 $x
+// CHECK-NEXT: 00000000 .wibble 00000000 $x
+// CHECK-NOT: ${{[adtx]}}
+
Added: llvm/trunk/test/MC/ARM64/mapping-within-section.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/mapping-within-section.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/mapping-within-section.s (added)
+++ llvm/trunk/test/MC/ARM64/mapping-within-section.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,23 @@
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s | llvm-objdump -t - | FileCheck %s
+
+ .text
+// $x at 0x0000
+ add w0, w0, w0
+// $d at 0x0004
+ .ascii "012"
+ .byte 1
+ .hword 2
+ .word 4
+ .xword 8
+ .single 4.0
+ .double 8.0
+ .space 10
+ .zero 3
+ .fill 10, 2, 42
+ .org 100, 12
+// $x at 0x0018
+ add x0, x0, x0
+
+// CHECK: 00000004 .text 00000000 $d
+// CHECK-NEXT: 00000000 .text 00000000 $x
+// CHECK-NEXT: 00000064 .text 00000000 $x
Added: llvm/trunk/test/MC/ARM64/memory.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/memory.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/memory.s (added)
+++ llvm/trunk/test/MC/ARM64/memory.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,634 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+foo:
+;-----------------------------------------------------------------------------
+; Indexed loads
+;-----------------------------------------------------------------------------
+
+ ldr w5, [x4, #20]
+ ldr x4, [x3]
+ ldr x2, [sp, #32]
+ ldr b5, [sp, #1]
+ ldr h6, [sp, #2]
+ ldr s7, [sp, #4]
+ ldr d8, [sp, #8]
+ ldr q9, [sp, #16]
+ ldrb w4, [x3]
+ ldrb w5, [x4, #20]
+ ldrb w2, [x3, _foo at pageoff]
+ ldrb w3, [x2, "+[Test method].var"@PAGEOFF]
+ ldrsb w9, [x3]
+ ldrsb x2, [sp, #128]
+ ldrh w2, [sp, #32]
+ ldrsh w3, [sp, #32]
+ ldrsh x5, [x9, #24]
+ ldrsw x9, [sp, #512]
+
+ prfm #5, [sp, #32]
+ prfm #31, [sp, #32]
+ prfm pldl1keep, [x2]
+ prfm pldl1strm, [x2]
+ prfm pldl2keep, [x2]
+ prfm pldl2strm, [x2]
+ prfm pldl3keep, [x2]
+ prfm pldl3strm, [x2]
+ prfm pstl1keep, [x2]
+ prfm pstl1strm, [x2]
+ prfm pstl2keep, [x2]
+ prfm pstl2strm, [x2]
+ prfm pstl3keep, [x2]
+ prfm pstl3strm, [x2]
+ prfm pstl3strm, [x4, x5, lsl #3]
+
+; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
+; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
+; CHECK: ldr x2, [sp, #32] ; encoding: [0xe2,0x13,0x40,0xf9]
+; CHECK: ldr b5, [sp, #1] ; encoding: [0xe5,0x07,0x40,0x3d]
+; CHECK: ldr h6, [sp, #2] ; encoding: [0xe6,0x07,0x40,0x7d]
+; CHECK: ldr s7, [sp, #4] ; encoding: [0xe7,0x07,0x40,0xbd]
+; CHECK: ldr d8, [sp, #8] ; encoding: [0xe8,0x07,0x40,0xfd]
+; CHECK: ldr q9, [sp, #16] ; encoding: [0xe9,0x07,0xc0,0x3d]
+; CHECK: ldrb w4, [x3] ; encoding: [0x64,0x00,0x40,0x39]
+; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
+; CHECK: ldrb w2, [x3, _foo at PAGEOFF] ; encoding: [0x62,0bAAAAAA00,0b01AAAAAA,0x39]
+; CHECK: ldrb w3, [x2, "+[Test method].var"@PAGEOFF] ; encoding: [0x43,0bAAAAAA00,0b01AAAAAA,0x39]
+; CHECK: ldrsb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x39]
+; CHECK: ldrsb x2, [sp, #128] ; encoding: [0xe2,0x03,0x82,0x39]
+; CHECK: ldrh w2, [sp, #32] ; encoding: [0xe2,0x43,0x40,0x79]
+; CHECK: ldrsh w3, [sp, #32] ; encoding: [0xe3,0x43,0xc0,0x79]
+; CHECK: ldrsh x5, [x9, #24] ; encoding: [0x25,0x31,0x80,0x79]
+; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9]
+; CHECK: prfm pldl3strm, [sp, #32] ; encoding: [0xe5,0x13,0x80,0xf9]
+; CHECK: prfm #31, [sp, #32] ; encoding: [0xff,0x13,0x80,0xf9]
+; CHECK: prfm pldl1keep, [x2] ; encoding: [0x40,0x00,0x80,0xf9]
+; CHECK: prfm pldl1strm, [x2] ; encoding: [0x41,0x00,0x80,0xf9]
+; CHECK: prfm pldl2keep, [x2] ; encoding: [0x42,0x00,0x80,0xf9]
+; CHECK: prfm pldl2strm, [x2] ; encoding: [0x43,0x00,0x80,0xf9]
+; CHECK: prfm pldl3keep, [x2] ; encoding: [0x44,0x00,0x80,0xf9]
+; CHECK: prfm pldl3strm, [x2] ; encoding: [0x45,0x00,0x80,0xf9]
+; CHECK: prfm pstl1keep, [x2] ; encoding: [0x50,0x00,0x80,0xf9]
+; CHECK: prfm pstl1strm, [x2] ; encoding: [0x51,0x00,0x80,0xf9]
+; CHECK: prfm pstl2keep, [x2] ; encoding: [0x52,0x00,0x80,0xf9]
+; CHECK: prfm pstl2strm, [x2] ; encoding: [0x53,0x00,0x80,0xf9]
+; CHECK: prfm pstl3keep, [x2] ; encoding: [0x54,0x00,0x80,0xf9]
+; CHECK: prfm pstl3strm, [x2] ; encoding: [0x55,0x00,0x80,0xf9]
+; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
+
+;-----------------------------------------------------------------------------
+; Indexed stores
+;-----------------------------------------------------------------------------
+
+ str x4, [x3]
+ str x2, [sp, #32]
+ str w5, [x4, #20]
+ str b5, [sp, #1]
+ str h6, [sp, #2]
+ str s7, [sp, #4]
+ str d8, [sp, #8]
+ str q9, [sp, #16]
+ strb w4, [x3]
+ strb w5, [x4, #20]
+ strh w2, [sp, #32]
+
+; CHECK: str x4, [x3] ; encoding: [0x64,0x00,0x00,0xf9]
+; CHECK: str x2, [sp, #32] ; encoding: [0xe2,0x13,0x00,0xf9]
+; CHECK: str w5, [x4, #20] ; encoding: [0x85,0x14,0x00,0xb9]
+; CHECK: str b5, [sp, #1] ; encoding: [0xe5,0x07,0x00,0x3d]
+; CHECK: str h6, [sp, #2] ; encoding: [0xe6,0x07,0x00,0x7d]
+; CHECK: str s7, [sp, #4] ; encoding: [0xe7,0x07,0x00,0xbd]
+; CHECK: str d8, [sp, #8] ; encoding: [0xe8,0x07,0x00,0xfd]
+; CHECK: str q9, [sp, #16] ; encoding: [0xe9,0x07,0x80,0x3d]
+; CHECK: strb w4, [x3] ; encoding: [0x64,0x00,0x00,0x39]
+; CHECK: strb w5, [x4, #20] ; encoding: [0x85,0x50,0x00,0x39]
+; CHECK: strh w2, [sp, #32] ; encoding: [0xe2,0x43,0x00,0x79]
+
+;-----------------------------------------------------------------------------
+; Unscaled immediate loads and stores
+;-----------------------------------------------------------------------------
+
+ ldur w2, [x3]
+ ldur w2, [sp, #24]
+ ldur x2, [x3]
+ ldur x2, [sp, #24]
+ ldur b5, [sp, #1]
+ ldur h6, [sp, #2]
+ ldur s7, [sp, #4]
+ ldur d8, [sp, #8]
+ ldur q9, [sp, #16]
+ ldursb w9, [x3]
+ ldursb x2, [sp, #128]
+ ldursh w3, [sp, #32]
+ ldursh x5, [x9, #24]
+ ldursw x9, [sp, #-128]
+
+; CHECK: ldur w2, [x3] ; encoding: [0x62,0x00,0x40,0xb8]
+; CHECK: ldur w2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xb8]
+; CHECK: ldur x2, [x3] ; encoding: [0x62,0x00,0x40,0xf8]
+; CHECK: ldur x2, [sp, #24] ; encoding: [0xe2,0x83,0x41,0xf8]
+; CHECK: ldur b5, [sp, #1] ; encoding: [0xe5,0x13,0x40,0x3c]
+; CHECK: ldur h6, [sp, #2] ; encoding: [0xe6,0x23,0x40,0x7c]
+; CHECK: ldur s7, [sp, #4] ; encoding: [0xe7,0x43,0x40,0xbc]
+; CHECK: ldur d8, [sp, #8] ; encoding: [0xe8,0x83,0x40,0xfc]
+; CHECK: ldur q9, [sp, #16] ; encoding: [0xe9,0x03,0xc1,0x3c]
+; CHECK: ldursb w9, [x3] ; encoding: [0x69,0x00,0xc0,0x38]
+; CHECK: ldursb x2, [sp, #128] ; encoding: [0xe2,0x03,0x88,0x38]
+; CHECK: ldursh w3, [sp, #32] ; encoding: [0xe3,0x03,0xc2,0x78]
+; CHECK: ldursh x5, [x9, #24] ; encoding: [0x25,0x81,0x81,0x78]
+; CHECK: ldursw x9, [sp, #-128] ; encoding: [0xe9,0x03,0x98,0xb8]
+
+ stur w4, [x3]
+ stur w2, [sp, #32]
+ stur x4, [x3]
+ stur x2, [sp, #32]
+ stur w5, [x4, #20]
+ stur b5, [sp, #1]
+ stur h6, [sp, #2]
+ stur s7, [sp, #4]
+ stur d8, [sp, #8]
+ stur q9, [sp, #16]
+ sturb w4, [x3]
+ sturb w5, [x4, #20]
+ sturh w2, [sp, #32]
+ prfum #5, [sp, #32]
+
+; CHECK: stur w4, [x3] ; encoding: [0x64,0x00,0x00,0xb8]
+; CHECK: stur w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xb8]
+; CHECK: stur x4, [x3] ; encoding: [0x64,0x00,0x00,0xf8]
+; CHECK: stur x2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0xf8]
+; CHECK: stur w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0xb8]
+; CHECK: stur b5, [sp, #1] ; encoding: [0xe5,0x13,0x00,0x3c]
+; CHECK: stur h6, [sp, #2] ; encoding: [0xe6,0x23,0x00,0x7c]
+; CHECK: stur s7, [sp, #4] ; encoding: [0xe7,0x43,0x00,0xbc]
+; CHECK: stur d8, [sp, #8] ; encoding: [0xe8,0x83,0x00,0xfc]
+; CHECK: stur q9, [sp, #16] ; encoding: [0xe9,0x03,0x81,0x3c]
+; CHECK: sturb w4, [x3] ; encoding: [0x64,0x00,0x00,0x38]
+; CHECK: sturb w5, [x4, #20] ; encoding: [0x85,0x40,0x01,0x38]
+; CHECK: sturh w2, [sp, #32] ; encoding: [0xe2,0x03,0x02,0x78]
+; CHECK: prfum pldl3strm, [sp, #32] ; encoding: [0xe5,0x03,0x82,0xf8]
+
+;-----------------------------------------------------------------------------
+; Unprivileged loads and stores
+;-----------------------------------------------------------------------------
+
+ ldtr w3, [x4, #16]
+ ldtr x3, [x4, #16]
+ ldtrb w3, [x4, #16]
+ ldtrsb w9, [x3]
+ ldtrsb x2, [sp, #128]
+ ldtrh w3, [x4, #16]
+ ldtrsh w3, [sp, #32]
+ ldtrsh x5, [x9, #24]
+ ldtrsw x9, [sp, #-128]
+
+; CHECK: ldtr w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xb8]
+; CHECK: ldtr x3, [x4, #16] ; encoding: [0x83,0x08,0x41,0xf8]
+; CHECK: ldtrb w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x38]
+; CHECK: ldtrsb w9, [x3] ; encoding: [0x69,0x08,0xc0,0x38]
+; CHECK: ldtrsb x2, [sp, #128] ; encoding: [0xe2,0x0b,0x88,0x38]
+; CHECK: ldtrh w3, [x4, #16] ; encoding: [0x83,0x08,0x41,0x78]
+; CHECK: ldtrsh w3, [sp, #32] ; encoding: [0xe3,0x0b,0xc2,0x78]
+; CHECK: ldtrsh x5, [x9, #24] ; encoding: [0x25,0x89,0x81,0x78]
+; CHECK: ldtrsw x9, [sp, #-128] ; encoding: [0xe9,0x0b,0x98,0xb8]
+
+ sttr w5, [x4, #20]
+ sttr x4, [x3]
+ sttr x2, [sp, #32]
+ sttrb w4, [x3]
+ sttrb w5, [x4, #20]
+ sttrh w2, [sp, #32]
+
+; CHECK: sttr w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0xb8]
+; CHECK: sttr x4, [x3] ; encoding: [0x64,0x08,0x00,0xf8]
+; CHECK: sttr x2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0xf8]
+; CHECK: sttrb w4, [x3] ; encoding: [0x64,0x08,0x00,0x38]
+; CHECK: sttrb w5, [x4, #20] ; encoding: [0x85,0x48,0x01,0x38]
+; CHECK: sttrh w2, [sp, #32] ; encoding: [0xe2,0x0b,0x02,0x78]
+
+;-----------------------------------------------------------------------------
+; Pre-indexed loads and stores
+;-----------------------------------------------------------------------------
+
+ ldr fp, [x7, #8]!
+ ldr lr, [x7, #8]!
+ ldr b5, [x0, #1]!
+ ldr h6, [x0, #2]!
+ ldr s7, [x0, #4]!
+ ldr d8, [x0, #8]!
+ ldr q9, [x0, #16]!
+
+ str lr, [x7, #-8]!
+ str fp, [x7, #-8]!
+ str b5, [x0, #-1]!
+ str h6, [x0, #-2]!
+ str s7, [x0, #-4]!
+ str d8, [x0, #-8]!
+ str q9, [x0, #-16]!
+
+; CHECK: ldr fp, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
+; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
+; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
+; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
+; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc]
+; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc]
+; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
+
+; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
+; CHECK: str fp, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
+; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
+; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
+; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
+; CHECK: str d8, [x0, #-8]! ; encoding: [0x08,0x8c,0x1f,0xfc]
+; CHECK: str q9, [x0, #-16]! ; encoding: [0x09,0x0c,0x9f,0x3c]
+
+;-----------------------------------------------------------------------------
+; post-indexed loads and stores
+;-----------------------------------------------------------------------------
+ str lr, [x7], #-8
+ str fp, [x7], #-8
+ str b5, [x0], #-1
+ str h6, [x0], #-2
+ str s7, [x0], #-4
+ str d8, [x0], #-8
+ str q9, [x0], #-16
+
+ ldr fp, [x7], #8
+ ldr lr, [x7], #8
+ ldr b5, [x0], #1
+ ldr h6, [x0], #2
+ ldr s7, [x0], #4
+ ldr d8, [x0], #8
+ ldr q9, [x0], #16
+
+; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
+; CHECK: str fp, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
+; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
+; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
+; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
+; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
+; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
+
+; CHECK: ldr fp, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
+; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
+; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
+; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
+; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc]
+; CHECK: ldr d8, [x0], #8 ; encoding: [0x08,0x84,0x40,0xfc]
+; CHECK: ldr q9, [x0], #16 ; encoding: [0x09,0x04,0xc1,0x3c]
+
+;-----------------------------------------------------------------------------
+; Load/Store pair (indexed, offset)
+;-----------------------------------------------------------------------------
+
+ ldp w3, w2, [x15, #16]
+ ldp x4, x9, [sp, #-16]
+ ldpsw x2, x3, [x14, #16]
+ ldpsw x2, x3, [sp, #-16]
+ ldp s10, s1, [x2, #64]
+ ldp d10, d1, [x2]
+ ldp q2, q3, [x0, #32]
+
+; CHECK: ldp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x29]
+; CHECK: ldp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa9]
+; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69]
+; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69]
+; CHECK: ldp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2d]
+; CHECK: ldp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6d]
+; CHECK: ldp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x41,0xad]
+
+ stp w3, w2, [x15, #16]
+ stp x4, x9, [sp, #-16]
+ stp s10, s1, [x2, #64]
+ stp d10, d1, [x2]
+ stp q2, q3, [x0, #32]
+
+; CHECK: stp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x29]
+; CHECK: stp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa9]
+; CHECK: stp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2d]
+; CHECK: stp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6d]
+; CHECK: stp q2, q3, [x0, #32] ; encoding: [0x02,0x0c,0x01,0xad]
+
+;-----------------------------------------------------------------------------
+; Load/Store pair (pre-indexed)
+;-----------------------------------------------------------------------------
+
+ ldp w3, w2, [x15, #16]!
+ ldp x4, x9, [sp, #-16]!
+ ldpsw x2, x3, [x14, #16]!
+ ldpsw x2, x3, [sp, #-16]!
+ ldp s10, s1, [x2, #64]!
+ ldp d10, d1, [x2, #16]!
+
+; CHECK: ldp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0xc2,0x29]
+; CHECK: ldp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xff,0xa9]
+; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69]
+; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69]
+; CHECK: ldp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0xc8,0x2d]
+; CHECK: ldp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0xc1,0x6d]
+
+ stp w3, w2, [x15, #16]!
+ stp x4, x9, [sp, #-16]!
+ stp s10, s1, [x2, #64]!
+ stp d10, d1, [x2, #16]!
+
+; CHECK: stp w3, w2, [x15, #16]! ; encoding: [0xe3,0x09,0x82,0x29]
+; CHECK: stp x4, x9, [sp, #-16]! ; encoding: [0xe4,0x27,0xbf,0xa9]
+; CHECK: stp s10, s1, [x2, #64]! ; encoding: [0x4a,0x04,0x88,0x2d]
+; CHECK: stp d10, d1, [x2, #16]! ; encoding: [0x4a,0x04,0x81,0x6d]
+
+;-----------------------------------------------------------------------------
+; Load/Store pair (post-indexed)
+;-----------------------------------------------------------------------------
+
+ ldp w3, w2, [x15], #16
+ ldp x4, x9, [sp], #-16
+ ldpsw x2, x3, [x14], #16
+ ldpsw x2, x3, [sp], #-16
+ ldp s10, s1, [x2], #64
+ ldp d10, d1, [x2], #16
+
+; CHECK: ldp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0xc2,0x28]
+; CHECK: ldp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xff,0xa8]
+; CHECK: ldpsw x2, x3, [x14], #16 ; encoding: [0xc2,0x0d,0xc2,0x68]
+; CHECK: ldpsw x2, x3, [sp], #-16 ; encoding: [0xe2,0x0f,0xfe,0x68]
+; CHECK: ldp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0xc8,0x2c]
+; CHECK: ldp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0xc1,0x6c]
+
+ stp w3, w2, [x15], #16
+ stp x4, x9, [sp], #-16
+ stp s10, s1, [x2], #64
+ stp d10, d1, [x2], #16
+
+; CHECK: stp w3, w2, [x15], #16 ; encoding: [0xe3,0x09,0x82,0x28]
+; CHECK: stp x4, x9, [sp], #-16 ; encoding: [0xe4,0x27,0xbf,0xa8]
+; CHECK: stp s10, s1, [x2], #64 ; encoding: [0x4a,0x04,0x88,0x2c]
+; CHECK: stp d10, d1, [x2], #16 ; encoding: [0x4a,0x04,0x81,0x6c]
+
+;-----------------------------------------------------------------------------
+; Load/Store pair (no-allocate)
+;-----------------------------------------------------------------------------
+
+ ldnp w3, w2, [x15, #16]
+ ldnp x4, x9, [sp, #-16]
+ ldnp s10, s1, [x2, #64]
+ ldnp d10, d1, [x2]
+
+; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28]
+; CHECK: ldnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x7f,0xa8]
+; CHECK: ldnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x48,0x2c]
+; CHECK: ldnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x40,0x6c]
+
+ stnp w3, w2, [x15, #16]
+ stnp x4, x9, [sp, #-16]
+ stnp s10, s1, [x2, #64]
+ stnp d10, d1, [x2]
+
+; CHECK: stnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x02,0x28]
+; CHECK: stnp x4, x9, [sp, #-16] ; encoding: [0xe4,0x27,0x3f,0xa8]
+; CHECK: stnp s10, s1, [x2, #64] ; encoding: [0x4a,0x04,0x08,0x2c]
+; CHECK: stnp d10, d1, [x2] ; encoding: [0x4a,0x04,0x00,0x6c]
+
+;-----------------------------------------------------------------------------
+; Load/Store register offset
+;-----------------------------------------------------------------------------
+
+ ldr w0, [x0, x0]
+ ldr w0, [x0, x0, lsl #2]
+ ldr x0, [x0, x0]
+ ldr x0, [x0, x0, lsl #3]
+ ldr x0, [x0, x0, sxtx]
+
+; CHECK: ldr w0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xb8]
+; CHECK: ldr w0, [x0, x0, lsl #2] ; encoding: [0x00,0x78,0x60,0xb8]
+; CHECK: ldr x0, [x0, x0] ; encoding: [0x00,0x68,0x60,0xf8]
+; CHECK: ldr x0, [x0, x0, lsl #3] ; encoding: [0x00,0x78,0x60,0xf8]
+; CHECK: ldr x0, [x0, x0, sxtx] ; encoding: [0x00,0xe8,0x60,0xf8]
+
+ ldr b1, [x1, x2]
+ ldr b1, [x1, x2, lsl #0]
+ ldr h1, [x1, x2]
+ ldr h1, [x1, x2, lsl #1]
+ ldr s1, [x1, x2]
+ ldr s1, [x1, x2, lsl #2]
+ ldr d1, [x1, x2]
+ ldr d1, [x1, x2, lsl #3]
+ ldr q1, [x1, x2]
+ ldr q1, [x1, x2, lsl #4]
+
+; CHECK: ldr b1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x3c]
+; CHECK: ldr b1, [x1, x2, lsl #0] ; encoding: [0x21,0x78,0x62,0x3c]
+; CHECK: ldr h1, [x1, x2] ; encoding: [0x21,0x68,0x62,0x7c]
+; CHECK: ldr h1, [x1, x2, lsl #1] ; encoding: [0x21,0x78,0x62,0x7c]
+; CHECK: ldr s1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xbc]
+; CHECK: ldr s1, [x1, x2, lsl #2] ; encoding: [0x21,0x78,0x62,0xbc]
+; CHECK: ldr d1, [x1, x2] ; encoding: [0x21,0x68,0x62,0xfc]
+; CHECK: ldr d1, [x1, x2, lsl #3] ; encoding: [0x21,0x78,0x62,0xfc]
+; CHECK: ldr q1, [x1, x2] ; encoding: [0x21,0x68,0xe2,0x3c]
+; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c]
+
+ str d1, [sp, x3]
+ str d1, [sp, x3, uxtw #3]
+ str q1, [sp, x3]
+ str q1, [sp, x3, uxtw #4]
+
+; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc]
+; CHECK: str d1, [sp, x3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc]
+; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c]
+; CHECK: str q1, [sp, x3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c]
+
+;-----------------------------------------------------------------------------
+; Load literal
+;-----------------------------------------------------------------------------
+
+ ldr w5, foo
+ ldr x4, foo
+ ldrsw x9, foo
+ prfm #5, foo
+
+; CHECK: ldr w5, foo ; encoding: [0bAAA00101,A,A,0x18]
+; CHECK: ldr x4, foo ; encoding: [0bAAA00100,A,A,0x58]
+; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98]
+; CHECK: prfm pldl3strm, foo ; encoding: [0bAAA00101,A,A,0xd8]
+
+;-----------------------------------------------------------------------------
+; Load/Store exclusive
+;-----------------------------------------------------------------------------
+
+ ldxr w6, [x1]
+ ldxr x6, [x1]
+ ldxrb w6, [x1]
+ ldxrh w6, [x1]
+ ldxp w7, w3, [x9]
+ ldxp x7, x3, [x9]
+
+; CHECK: ldxrb w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x08]
+; CHECK: ldxrh w6, [x1] ; encoding: [0x26,0x7c,0x5f,0x48]
+; CHECK: ldxp w7, w3, [x9] ; encoding: [0x27,0x0d,0x7f,0x88]
+; CHECK: ldxp x7, x3, [x9] ; encoding: [0x27,0x0d,0x7f,0xc8]
+
+ stxr w1, x4, [x3]
+ stxr w1, w4, [x3]
+ stxrb w1, w4, [x3]
+ stxrh w1, w4, [x3]
+ stxp w1, x2, x6, [x1]
+ stxp w1, w2, w6, [x1]
+
+; CHECK: stxr w1, x4, [x3] ; encoding: [0x64,0x7c,0x01,0xc8]
+; CHECK: stxr w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x88]
+; CHECK: stxrb w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x08]
+; CHECK: stxrh w1, w4, [x3] ; encoding: [0x64,0x7c,0x01,0x48]
+; CHECK: stxp w1, x2, x6, [x1] ; encoding: [0x22,0x18,0x21,0xc8]
+; CHECK: stxp w1, w2, w6, [x1] ; encoding: [0x22,0x18,0x21,0x88]
+
+;-----------------------------------------------------------------------------
+; Load-acquire/Store-release non-exclusive
+;-----------------------------------------------------------------------------
+
+ ldar w4, [sp]
+ ldar x4, [sp, #0]
+ ldarb w4, [sp]
+ ldarh w4, [sp]
+
+; CHECK: ldar w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x88]
+; CHECK: ldar x4, [sp] ; encoding: [0xe4,0xff,0xdf,0xc8]
+; CHECK: ldarb w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x08]
+; CHECK: ldarh w4, [sp] ; encoding: [0xe4,0xff,0xdf,0x48]
+
+ stlr w3, [x6]
+ stlr x3, [x6]
+ stlrb w3, [x6]
+ stlrh w3, [x6]
+
+; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88]
+; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8]
+; CHECK: stlrb w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x08]
+; CHECK: stlrh w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x48]
+
+;-----------------------------------------------------------------------------
+; Load-acquire/Store-release exclusive
+;-----------------------------------------------------------------------------
+
+ ldaxr w2, [x4]
+ ldaxr x2, [x4]
+ ldaxrb w2, [x4, #0]
+ ldaxrh w2, [x4]
+ ldaxp w2, w6, [x1]
+ ldaxp x2, x6, [x1]
+
+; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
+; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
+; CHECK: ldaxrb w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x08]
+; CHECK: ldaxrh w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x48]
+; CHECK: ldaxp w2, w6, [x1] ; encoding: [0x22,0x98,0x7f,0x88]
+; CHECK: ldaxp x2, x6, [x1] ; encoding: [0x22,0x98,0x7f,0xc8]
+
+ stlxr w8, x7, [x1]
+ stlxr w8, w7, [x1]
+ stlxrb w8, w7, [x1]
+ stlxrh w8, w7, [x1]
+ stlxp w1, x2, x6, [x1]
+ stlxp w1, w2, w6, [x1]
+
+; CHECK: stlxr w8, x7, [x1] ; encoding: [0x27,0xfc,0x08,0xc8]
+; CHECK: stlxr w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x88]
+; CHECK: stlxrb w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x08]
+; CHECK: stlxrh w8, w7, [x1] ; encoding: [0x27,0xfc,0x08,0x48]
+; CHECK: stlxp w1, x2, x6, [x1] ; encoding: [0x22,0x98,0x21,0xc8]
+; CHECK: stlxp w1, w2, w6, [x1] ; encoding: [0x22,0x98,0x21,0x88]
+
+
+;-----------------------------------------------------------------------------
+; LDUR/STUR aliases for negative and unaligned LDR/STR instructions.
+;
+; According to the ARM ISA documentation:
+; "A programmer-friendly assembler should also generate these instructions
+; in response to the standard LDR/STR mnemonics when the immediate offset is
+; unambiguous, i.e. negative or unaligned."
+;-----------------------------------------------------------------------------
+
+ ldr x11, [fp, #-8]
+ ldr x11, [fp, #7]
+ ldr w0, [x0, #2]
+ ldr w0, [x0, #-256]
+ ldr b2, [x1, #-2]
+ ldr h3, [x2, #3]
+ ldr h3, [x3, #-4]
+ ldr s3, [x4, #3]
+ ldr s3, [x5, #-4]
+ ldr d4, [x6, #4]
+ ldr d4, [x7, #-8]
+ ldr q5, [x8, #8]
+ ldr q5, [x9, #-16]
+
+; CHECK: ldur x11, [fp, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
+; CHECK: ldur x11, [fp, #7] ; encoding: [0xab,0x73,0x40,0xf8]
+; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
+; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
+; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
+; CHECK: ldur h3, [x2, #3] ; encoding: [0x43,0x30,0x40,0x7c]
+; CHECK: ldur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x5f,0x7c]
+; CHECK: ldur s3, [x4, #3] ; encoding: [0x83,0x30,0x40,0xbc]
+; CHECK: ldur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x5f,0xbc]
+; CHECK: ldur d4, [x6, #4] ; encoding: [0xc4,0x40,0x40,0xfc]
+; CHECK: ldur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x5f,0xfc]
+; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
+; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
+
+ str x11, [fp, #-8]
+ str x11, [fp, #7]
+ str w0, [x0, #2]
+ str w0, [x0, #-256]
+ str b2, [x1, #-2]
+ str h3, [x2, #3]
+ str h3, [x3, #-4]
+ str s3, [x4, #3]
+ str s3, [x5, #-4]
+ str d4, [x6, #4]
+ str d4, [x7, #-8]
+ str q5, [x8, #8]
+ str q5, [x9, #-16]
+
+; CHECK: stur x11, [fp, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
+; CHECK: stur x11, [fp, #7] ; encoding: [0xab,0x73,0x00,0xf8]
+; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
+; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
+; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
+; CHECK: stur h3, [x2, #3] ; encoding: [0x43,0x30,0x00,0x7c]
+; CHECK: stur h3, [x3, #-4] ; encoding: [0x63,0xc0,0x1f,0x7c]
+; CHECK: stur s3, [x4, #3] ; encoding: [0x83,0x30,0x00,0xbc]
+; CHECK: stur s3, [x5, #-4] ; encoding: [0xa3,0xc0,0x1f,0xbc]
+; CHECK: stur d4, [x6, #4] ; encoding: [0xc4,0x40,0x00,0xfc]
+; CHECK: stur d4, [x7, #-8] ; encoding: [0xe4,0x80,0x1f,0xfc]
+; CHECK: stur q5, [x8, #8] ; encoding: [0x05,0x81,0x80,0x3c]
+; CHECK: stur q5, [x9, #-16] ; encoding: [0x25,0x01,0x9f,0x3c]
+
+ ldrb w3, [x1, #-1]
+ ldrh w4, [x2, #1]
+ ldrh w5, [x3, #-1]
+ ldrsb w6, [x4, #-1]
+ ldrsb x7, [x5, #-1]
+ ldrsh w8, [x6, #1]
+ ldrsh w9, [x7, #-1]
+ ldrsh x1, [x8, #1]
+ ldrsh x2, [x9, #-1]
+ ldrsw x3, [x10, #10]
+ ldrsw x4, [x11, #-1]
+
+; CHECK: ldurb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x5f,0x38]
+; CHECK: ldurh w4, [x2, #1] ; encoding: [0x44,0x10,0x40,0x78]
+; CHECK: ldurh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x5f,0x78]
+; CHECK: ldursb w6, [x4, #-1] ; encoding: [0x86,0xf0,0xdf,0x38]
+; CHECK: ldursb x7, [x5, #-1] ; encoding: [0xa7,0xf0,0x9f,0x38]
+; CHECK: ldursh w8, [x6, #1] ; encoding: [0xc8,0x10,0xc0,0x78]
+; CHECK: ldursh w9, [x7, #-1] ; encoding: [0xe9,0xf0,0xdf,0x78]
+; CHECK: ldursh x1, [x8, #1] ; encoding: [0x01,0x11,0x80,0x78]
+; CHECK: ldursh x2, [x9, #-1] ; encoding: [0x22,0xf1,0x9f,0x78]
+; CHECK: ldursw x3, [x10, #10] ; encoding: [0x43,0xa1,0x80,0xb8]
+; CHECK: ldursw x4, [x11, #-1] ; encoding: [0x64,0xf1,0x9f,0xb8]
+
+ strb w3, [x1, #-1]
+ strh w4, [x2, #1]
+ strh w5, [x3, #-1]
+
+; CHECK: sturb w3, [x1, #-1] ; encoding: [0x23,0xf0,0x1f,0x38]
+; CHECK: sturh w4, [x2, #1] ; encoding: [0x44,0x10,0x00,0x78]
+; CHECK: sturh w5, [x3, #-1] ; encoding: [0x65,0xf0,0x1f,0x78]
Added: llvm/trunk/test/MC/ARM64/separator.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/separator.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/separator.s (added)
+++ llvm/trunk/test/MC/ARM64/separator.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,20 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
+
+; ARM64 uses a multi-character statment separator, "%%". Check that we lex
+; it properly and recognize the multiple assembly statements on the line.
+
+; To make sure the output assembly correctly handled the instructions,
+; tell it to show encodings. That will result in the two 'mov' instructions
+; being on separate lines in the output. We look for the "; encoding" string
+; to verify that. For this test, we don't care what the encoding is, just that
+; there is one for each 'mov' instruction.
+
+
+_foo:
+; CHECK: foo
+; CHECK: mov x0, x1 ; encoding
+; CHECK: mov x1, x0 ; encoding
+ mov x0, x1 %% mov x1, x0
+ ret lr
+
+
Added: llvm/trunk/test/MC/ARM64/simd-ldst.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/simd-ldst.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/simd-ldst.s (added)
+++ llvm/trunk/test/MC/ARM64/simd-ldst.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,2404 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s
+
+_ld1st1_multiple:
+ ld1.8b {v0}, [x1]
+ ld1.8b {v0, v1}, [x1]
+ ld1.8b {v0, v1, v2}, [x1]
+ ld1.8b {v0, v1, v2, v3}, [x1]
+
+ ld1.8b {v3}, [x1]
+ ld1.8b {v3, v4}, [x2]
+ ld1.8b {v4, v5, v6}, [x3]
+ ld1.8b {v7, v8, v9, v10}, [x4]
+
+ ld1.16b {v0}, [x1]
+ ld1.16b {v0, v1}, [x1]
+ ld1.16b {v0, v1, v2}, [x1]
+ ld1.16b {v0, v1, v2, v3}, [x1]
+
+ ld1.4h {v0}, [x1]
+ ld1.4h {v0, v1}, [x1]
+ ld1.4h {v0, v1, v2}, [x1]
+ ld1.4h {v0, v1, v2, v3}, [x1]
+
+ ld1.8h {v0}, [x1]
+ ld1.8h {v0, v1}, [x1]
+ ld1.8h {v0, v1, v2}, [x1]
+ ld1.8h {v0, v1, v2, v3}, [x1]
+
+ ld1.2s {v0}, [x1]
+ ld1.2s {v0, v1}, [x1]
+ ld1.2s {v0, v1, v2}, [x1]
+ ld1.2s {v0, v1, v2, v3}, [x1]
+
+ ld1.4s {v0}, [x1]
+ ld1.4s {v0, v1}, [x1]
+ ld1.4s {v0, v1, v2}, [x1]
+ ld1.4s {v0, v1, v2, v3}, [x1]
+
+ ld1.1d {v0}, [x1]
+ ld1.1d {v0, v1}, [x1]
+ ld1.1d {v0, v1, v2}, [x1]
+ ld1.1d {v0, v1, v2, v3}, [x1]
+
+ ld1.2d {v0}, [x1]
+ ld1.2d {v0, v1}, [x1]
+ ld1.2d {v0, v1, v2}, [x1]
+ ld1.2d {v0, v1, v2, v3}, [x1]
+
+ st1.8b {v0}, [x1]
+ st1.8b {v0, v1}, [x1]
+ st1.8b {v0, v1, v2}, [x1]
+ st1.8b {v0, v1, v2, v3}, [x1]
+
+ st1.16b {v0}, [x1]
+ st1.16b {v0, v1}, [x1]
+ st1.16b {v0, v1, v2}, [x1]
+ st1.16b {v0, v1, v2, v3}, [x1]
+
+ st1.4h {v0}, [x1]
+ st1.4h {v0, v1}, [x1]
+ st1.4h {v0, v1, v2}, [x1]
+ st1.4h {v0, v1, v2, v3}, [x1]
+
+ st1.8h {v0}, [x1]
+ st1.8h {v0, v1}, [x1]
+ st1.8h {v0, v1, v2}, [x1]
+ st1.8h {v0, v1, v2, v3}, [x1]
+
+ st1.2s {v0}, [x1]
+ st1.2s {v0, v1}, [x1]
+ st1.2s {v0, v1, v2}, [x1]
+ st1.2s {v0, v1, v2, v3}, [x1]
+
+ st1.4s {v0}, [x1]
+ st1.4s {v0, v1}, [x1]
+ st1.4s {v0, v1, v2}, [x1]
+ st1.4s {v0, v1, v2, v3}, [x1]
+
+ st1.1d {v0}, [x1]
+ st1.1d {v0, v1}, [x1]
+ st1.1d {v0, v1, v2}, [x1]
+ st1.1d {v0, v1, v2, v3}, [x1]
+
+ st1.2d {v0}, [x1]
+ st1.2d {v0, v1}, [x1]
+ st1.2d {v0, v1, v2}, [x1]
+ st1.2d {v0, v1, v2, v3}, [x1]
+
+ st1.2d {v5}, [x1]
+ st1.2d {v7, v8}, [x10]
+ st1.2d {v11, v12, v13}, [x1]
+ st1.2d {v28, v29, v30, v31}, [x13]
+
+; CHECK: _ld1st1_multiple:
+; CHECK: ld1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x0c]
+; CHECK: ld1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x0c]
+; CHECK: ld1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x0c]
+; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x0c]
+
+; CHECK: ld1.8b { v3 }, [x1] ; encoding: [0x23,0x70,0x40,0x0c]
+; CHECK: ld1.8b { v3, v4 }, [x2] ; encoding: [0x43,0xa0,0x40,0x0c]
+; CHECK: ld1.8b { v4, v5, v6 }, [x3] ; encoding: [0x64,0x60,0x40,0x0c]
+; CHECK: ld1.8b { v7, v8, v9, v10 }, [x4] ; encoding: [0x87,0x20,0x40,0x0c]
+
+; CHECK: ld1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x40,0x4c]
+; CHECK: ld1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x40,0x4c]
+; CHECK: ld1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x40,0x4c]
+; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x40,0x4c]
+
+; CHECK: ld1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x0c]
+; CHECK: ld1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x0c]
+; CHECK: ld1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x0c]
+; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x0c]
+
+; CHECK: ld1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x40,0x4c]
+; CHECK: ld1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x40,0x4c]
+; CHECK: ld1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x40,0x4c]
+; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x40,0x4c]
+
+; CHECK: ld1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x0c]
+; CHECK: ld1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x0c]
+; CHECK: ld1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x0c]
+; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x0c]
+
+; CHECK: ld1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x40,0x4c]
+; CHECK: ld1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x40,0x4c]
+; CHECK: ld1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x40,0x4c]
+; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x40,0x4c]
+
+; CHECK: ld1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x0c]
+; CHECK: ld1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x0c]
+; CHECK: ld1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x0c]
+; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x0c]
+
+; CHECK: ld1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x40,0x4c]
+; CHECK: ld1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x40,0x4c]
+; CHECK: ld1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x40,0x4c]
+; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x40,0x4c]
+
+
+; CHECK: st1.8b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x0c]
+; CHECK: st1.8b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x0c]
+; CHECK: st1.8b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x0c]
+; CHECK: st1.8b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x0c]
+
+; CHECK: st1.16b { v0 }, [x1] ; encoding: [0x20,0x70,0x00,0x4c]
+; CHECK: st1.16b { v0, v1 }, [x1] ; encoding: [0x20,0xa0,0x00,0x4c]
+; CHECK: st1.16b { v0, v1, v2 }, [x1] ; encoding: [0x20,0x60,0x00,0x4c]
+; CHECK: st1.16b { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x20,0x00,0x4c]
+
+; CHECK: st1.4h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x0c]
+; CHECK: st1.4h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x0c]
+; CHECK: st1.4h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x0c]
+; CHECK: st1.4h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x0c]
+
+; CHECK: st1.8h { v0 }, [x1] ; encoding: [0x20,0x74,0x00,0x4c]
+; CHECK: st1.8h { v0, v1 }, [x1] ; encoding: [0x20,0xa4,0x00,0x4c]
+; CHECK: st1.8h { v0, v1, v2 }, [x1] ; encoding: [0x20,0x64,0x00,0x4c]
+; CHECK: st1.8h { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x24,0x00,0x4c]
+
+; CHECK: st1.2s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x0c]
+; CHECK: st1.2s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x0c]
+; CHECK: st1.2s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x0c]
+; CHECK: st1.2s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x0c]
+
+; CHECK: st1.4s { v0 }, [x1] ; encoding: [0x20,0x78,0x00,0x4c]
+; CHECK: st1.4s { v0, v1 }, [x1] ; encoding: [0x20,0xa8,0x00,0x4c]
+; CHECK: st1.4s { v0, v1, v2 }, [x1] ; encoding: [0x20,0x68,0x00,0x4c]
+; CHECK: st1.4s { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x28,0x00,0x4c]
+
+; CHECK: st1.1d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x0c]
+; CHECK: st1.1d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x0c]
+; CHECK: st1.1d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x0c]
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x0c]
+
+; CHECK: st1.2d { v0 }, [x1] ; encoding: [0x20,0x7c,0x00,0x4c]
+; CHECK: st1.2d { v0, v1 }, [x1] ; encoding: [0x20,0xac,0x00,0x4c]
+; CHECK: st1.2d { v0, v1, v2 }, [x1] ; encoding: [0x20,0x6c,0x00,0x4c]
+; CHECK: st1.2d { v0, v1, v2, v3 }, [x1] ; encoding: [0x20,0x2c,0x00,0x4c]
+
+; CHECK: st1.2d { v5 }, [x1] ; encoding: [0x25,0x7c,0x00,0x4c]
+; CHECK: st1.2d { v7, v8 }, [x10] ; encoding: [0x47,0xad,0x00,0x4c]
+; CHECK: st1.2d { v11, v12, v13 }, [x1] ; encoding: [0x2b,0x6c,0x00,0x4c]
+; CHECK: st1.2d { v28, v29, v30, v31 }, [x13] ; encoding: [0xbc,0x2d,0x00,0x4c]
+
+_ld2st2_multiple:
+ ld2.8b {v4, v5}, [x19]
+ ld2.16b {v4, v5}, [x19]
+ ld2.4h {v4, v5}, [x19]
+ ld2.8h {v4, v5}, [x19]
+ ld2.2s {v4, v5}, [x19]
+ ld2.4s {v4, v5}, [x19]
+ ld2.2d {v4, v5}, [x19]
+
+ st2.8b {v4, v5}, [x19]
+ st2.16b {v4, v5}, [x19]
+ st2.4h {v4, v5}, [x19]
+ st2.8h {v4, v5}, [x19]
+ st2.2s {v4, v5}, [x19]
+ st2.4s {v4, v5}, [x19]
+ st2.2d {v4, v5}, [x19]
+
+
+; CHECK: _ld2st2_multiple
+; CHECK: ld2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x0c]
+; CHECK: ld2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x4c]
+; CHECK: ld2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x0c]
+; CHECK: ld2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x40,0x4c]
+; CHECK: ld2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x0c]
+; CHECK: ld2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x40,0x4c]
+; CHECK: ld2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x40,0x4c]
+
+; CHECK: st2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x0c]
+; CHECK: st2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x00,0x4c]
+; CHECK: st2.4h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x0c]
+; CHECK: st2.8h { v4, v5 }, [x19] ; encoding: [0x64,0x86,0x00,0x4c]
+; CHECK: st2.2s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x0c]
+; CHECK: st2.4s { v4, v5 }, [x19] ; encoding: [0x64,0x8a,0x00,0x4c]
+; CHECK: st2.2d { v4, v5 }, [x19] ; encoding: [0x64,0x8e,0x00,0x4c]
+
+
+ld3st3_multiple:
+ ld3.8b {v4, v5, v6}, [x19]
+ ld3.16b {v4, v5, v6}, [x19]
+ ld3.4h {v4, v5, v6}, [x19]
+ ld3.8h {v4, v5, v6}, [x19]
+ ld3.2s {v4, v5, v6}, [x19]
+ ld3.4s {v4, v5, v6}, [x19]
+ ld3.2d {v4, v5, v6}, [x19]
+
+ ld3.8b {v9, v10, v11}, [x9]
+ ld3.16b {v14, v15, v16}, [x19]
+ ld3.4h {v24, v25, v26}, [x29]
+ ld3.8h {v30, v31, v0}, [x9]
+ ld3.2s {v2, v3, v4}, [x19]
+ ld3.4s {v4, v5, v6}, [x29]
+ ld3.2d {v7, v8, v9}, [x9]
+
+ st3.8b {v4, v5, v6}, [x19]
+ st3.16b {v4, v5, v6}, [x19]
+ st3.4h {v4, v5, v6}, [x19]
+ st3.8h {v4, v5, v6}, [x19]
+ st3.2s {v4, v5, v6}, [x19]
+ st3.4s {v4, v5, v6}, [x19]
+ st3.2d {v4, v5, v6}, [x19]
+
+ st3.8b {v10, v11, v12}, [x9]
+ st3.16b {v14, v15, v16}, [x19]
+ st3.4h {v24, v25, v26}, [x29]
+ st3.8h {v30, v31, v0}, [x9]
+ st3.2s {v2, v3, v4}, [x19]
+ st3.4s {v7, v8, v9}, [x29]
+ st3.2d {v4, v5, v6}, [x9]
+
+; CHECK: ld3st3_multiple:
+; CHECK: ld3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x0c]
+; CHECK: ld3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x40,0x4c]
+; CHECK: ld3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x0c]
+; CHECK: ld3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x40,0x4c]
+; CHECK: ld3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x0c]
+; CHECK: ld3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x40,0x4c]
+; CHECK: ld3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x40,0x4c]
+
+; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
+; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c]
+; CHECK: ld3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x40,0x0c]
+; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c]
+; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
+; CHECK: ld3.4s { v4, v5, v6 }, [fp] ; encoding: [0xa4,0x4b,0x40,0x4c]
+; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
+
+; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c]
+; CHECK: st3.16b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x4c]
+; CHECK: st3.4h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x0c]
+; CHECK: st3.8h { v4, v5, v6 }, [x19] ; encoding: [0x64,0x46,0x00,0x4c]
+; CHECK: st3.2s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x0c]
+; CHECK: st3.4s { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4a,0x00,0x4c]
+; CHECK: st3.2d { v4, v5, v6 }, [x19] ; encoding: [0x64,0x4e,0x00,0x4c]
+
+; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c]
+; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c]
+; CHECK: st3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x00,0x0c]
+; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c]
+; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
+; CHECK: st3.4s { v7, v8, v9 }, [fp] ; encoding: [0xa7,0x4b,0x00,0x4c]
+; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c]
+
+ld4st4_multiple:
+ ld4.8b {v4, v5, v6, v7}, [x19]
+ ld4.16b {v4, v5, v6, v7}, [x19]
+ ld4.4h {v4, v5, v6, v7}, [x19]
+ ld4.8h {v4, v5, v6, v7}, [x19]
+ ld4.2s {v4, v5, v6, v7}, [x19]
+ ld4.4s {v4, v5, v6, v7}, [x19]
+ ld4.2d {v4, v5, v6, v7}, [x19]
+
+ st4.8b {v4, v5, v6, v7}, [x19]
+ st4.16b {v4, v5, v6, v7}, [x19]
+ st4.4h {v4, v5, v6, v7}, [x19]
+ st4.8h {v4, v5, v6, v7}, [x19]
+ st4.2s {v4, v5, v6, v7}, [x19]
+ st4.4s {v4, v5, v6, v7}, [x19]
+ st4.2d {v4, v5, v6, v7}, [x19]
+
+; CHECK: ld4st4_multiple:
+; CHECK: ld4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x0c]
+; CHECK: ld4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x40,0x4c]
+; CHECK: ld4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x0c]
+; CHECK: ld4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x40,0x4c]
+; CHECK: ld4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x0c]
+; CHECK: ld4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x40,0x4c]
+; CHECK: ld4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x40,0x4c]
+
+; CHECK: st4.8b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x0c]
+; CHECK: st4.16b { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x02,0x00,0x4c]
+; CHECK: st4.4h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x0c]
+; CHECK: st4.8h { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x06,0x00,0x4c]
+; CHECK: st4.2s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x0c]
+; CHECK: st4.4s { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0a,0x00,0x4c]
+; CHECK: st4.2d { v4, v5, v6, v7 }, [x19] ; encoding: [0x64,0x0e,0x00,0x4c]
+
+;-----------------------------------------------------------------------------
+; Post-increment versions.
+;-----------------------------------------------------------------------------
+
+_ld1st1_multiple_post:
+ ld1.8b {v0}, [x1], x15
+ ld1.8b {v0, v1}, [x1], x15
+ ld1.8b {v0, v1, v2}, [x1], x15
+ ld1.8b {v0, v1, v2, v3}, [x1], x15
+
+ ld1.16b {v0}, [x1], x15
+ ld1.16b {v0, v1}, [x1], x15
+ ld1.16b {v0, v1, v2}, [x1], x15
+ ld1.16b {v0, v1, v2, v3}, [x1], x15
+
+ ld1.4h {v0}, [x1], x15
+ ld1.4h {v0, v1}, [x1], x15
+ ld1.4h {v0, v1, v2}, [x1], x15
+ ld1.4h {v0, v1, v2, v3}, [x1], x15
+
+ ld1.8h {v0}, [x1], x15
+ ld1.8h {v0, v1}, [x1], x15
+ ld1.8h {v0, v1, v2}, [x1], x15
+ ld1.8h {v0, v1, v2, v3}, [x1], x15
+
+ ld1.2s {v0}, [x1], x15
+ ld1.2s {v0, v1}, [x1], x15
+ ld1.2s {v0, v1, v2}, [x1], x15
+ ld1.2s {v0, v1, v2, v3}, [x1], x15
+
+ ld1.4s {v0}, [x1], x15
+ ld1.4s {v0, v1}, [x1], x15
+ ld1.4s {v0, v1, v2}, [x1], x15
+ ld1.4s {v0, v1, v2, v3}, [x1], x15
+
+ ld1.1d {v0}, [x1], x15
+ ld1.1d {v0, v1}, [x1], x15
+ ld1.1d {v0, v1, v2}, [x1], x15
+ ld1.1d {v0, v1, v2, v3}, [x1], x15
+
+ ld1.2d {v0}, [x1], x15
+ ld1.2d {v0, v1}, [x1], x15
+ ld1.2d {v0, v1, v2}, [x1], x15
+ ld1.2d {v0, v1, v2, v3}, [x1], x15
+
+ st1.8b {v0}, [x1], x15
+ st1.8b {v0, v1}, [x1], x15
+ st1.8b {v0, v1, v2}, [x1], x15
+ st1.8b {v0, v1, v2, v3}, [x1], x15
+
+ st1.16b {v0}, [x1], x15
+ st1.16b {v0, v1}, [x1], x15
+ st1.16b {v0, v1, v2}, [x1], x15
+ st1.16b {v0, v1, v2, v3}, [x1], x15
+
+ st1.4h {v0}, [x1], x15
+ st1.4h {v0, v1}, [x1], x15
+ st1.4h {v0, v1, v2}, [x1], x15
+ st1.4h {v0, v1, v2, v3}, [x1], x15
+
+ st1.8h {v0}, [x1], x15
+ st1.8h {v0, v1}, [x1], x15
+ st1.8h {v0, v1, v2}, [x1], x15
+ st1.8h {v0, v1, v2, v3}, [x1], x15
+
+ st1.2s {v0}, [x1], x15
+ st1.2s {v0, v1}, [x1], x15
+ st1.2s {v0, v1, v2}, [x1], x15
+ st1.2s {v0, v1, v2, v3}, [x1], x15
+
+ st1.4s {v0}, [x1], x15
+ st1.4s {v0, v1}, [x1], x15
+ st1.4s {v0, v1, v2}, [x1], x15
+ st1.4s {v0, v1, v2, v3}, [x1], x15
+
+ st1.1d {v0}, [x1], x15
+ st1.1d {v0, v1}, [x1], x15
+ st1.1d {v0, v1, v2}, [x1], x15
+ st1.1d {v0, v1, v2, v3}, [x1], x15
+
+ st1.2d {v0}, [x1], x15
+ st1.2d {v0, v1}, [x1], x15
+ st1.2d {v0, v1, v2}, [x1], x15
+ st1.2d {v0, v1, v2, v3}, [x1], x15
+
+ ld1.8b {v0}, [x1], #8
+ ld1.8b {v0, v1}, [x1], #16
+ ld1.8b {v0, v1, v2}, [x1], #24
+ ld1.8b {v0, v1, v2, v3}, [x1], #32
+
+ ld1.16b {v0}, [x1], #16
+ ld1.16b {v0, v1}, [x1], #32
+ ld1.16b {v0, v1, v2}, [x1], #48
+ ld1.16b {v0, v1, v2, v3}, [x1], #64
+
+ ld1.4h {v0}, [x1], #8
+ ld1.4h {v0, v1}, [x1], #16
+ ld1.4h {v0, v1, v2}, [x1], #24
+ ld1.4h {v0, v1, v2, v3}, [x1], #32
+
+ ld1.8h {v0}, [x1], #16
+ ld1.8h {v0, v1}, [x1], #32
+ ld1.8h {v0, v1, v2}, [x1], #48
+ ld1.8h {v0, v1, v2, v3}, [x1], #64
+
+ ld1.2s {v0}, [x1], #8
+ ld1.2s {v0, v1}, [x1], #16
+ ld1.2s {v0, v1, v2}, [x1], #24
+ ld1.2s {v0, v1, v2, v3}, [x1], #32
+
+ ld1.4s {v0}, [x1], #16
+ ld1.4s {v0, v1}, [x1], #32
+ ld1.4s {v0, v1, v2}, [x1], #48
+ ld1.4s {v0, v1, v2, v3}, [x1], #64
+
+ ld1.1d {v0}, [x1], #8
+ ld1.1d {v0, v1}, [x1], #16
+ ld1.1d {v0, v1, v2}, [x1], #24
+ ld1.1d {v0, v1, v2, v3}, [x1], #32
+
+ ld1.2d {v0}, [x1], #16
+ ld1.2d {v0, v1}, [x1], #32
+ ld1.2d {v0, v1, v2}, [x1], #48
+ ld1.2d {v0, v1, v2, v3}, [x1], #64
+
+ st1.8b {v0}, [x1], #8
+ st1.8b {v0, v1}, [x1], #16
+ st1.8b {v0, v1, v2}, [x1], #24
+ st1.8b {v0, v1, v2, v3}, [x1], #32
+
+ st1.16b {v0}, [x1], #16
+ st1.16b {v0, v1}, [x1], #32
+ st1.16b {v0, v1, v2}, [x1], #48
+ st1.16b {v0, v1, v2, v3}, [x1], #64
+
+ st1.4h {v0}, [x1], #8
+ st1.4h {v0, v1}, [x1], #16
+ st1.4h {v0, v1, v2}, [x1], #24
+ st1.4h {v0, v1, v2, v3}, [x1], #32
+
+ st1.8h {v0}, [x1], #16
+ st1.8h {v0, v1}, [x1], #32
+ st1.8h {v0, v1, v2}, [x1], #48
+ st1.8h {v0, v1, v2, v3}, [x1], #64
+
+ st1.2s {v0}, [x1], #8
+ st1.2s {v0, v1}, [x1], #16
+ st1.2s {v0, v1, v2}, [x1], #24
+ st1.2s {v0, v1, v2, v3}, [x1], #32
+
+ st1.4s {v0}, [x1], #16
+ st1.4s {v0, v1}, [x1], #32
+ st1.4s {v0, v1, v2}, [x1], #48
+ st1.4s {v0, v1, v2, v3}, [x1], #64
+
+ st1.1d {v0}, [x1], #8
+ st1.1d {v0, v1}, [x1], #16
+ st1.1d {v0, v1, v2}, [x1], #24
+ st1.1d {v0, v1, v2, v3}, [x1], #32
+
+ st1.2d {v0}, [x1], #16
+ st1.2d {v0, v1}, [x1], #32
+ st1.2d {v0, v1, v2}, [x1], #48
+ st1.2d {v0, v1, v2, v3}, [x1], #64
+
+; CHECK: ld1st1_multiple_post:
+; CHECK: ld1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x0c]
+; CHECK: ld1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x0c]
+; CHECK: ld1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x0c]
+; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x0c]
+
+; CHECK: ld1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0xcf,0x4c]
+; CHECK: ld1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0xcf,0x4c]
+; CHECK: ld1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0xcf,0x4c]
+; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0xcf,0x4c]
+
+; CHECK: ld1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x0c]
+; CHECK: ld1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x0c]
+; CHECK: ld1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x0c]
+; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x0c]
+
+; CHECK: ld1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0xcf,0x4c]
+; CHECK: ld1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0xcf,0x4c]
+; CHECK: ld1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0xcf,0x4c]
+; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0xcf,0x4c]
+
+; CHECK: ld1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x0c]
+; CHECK: ld1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x0c]
+; CHECK: ld1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x0c]
+; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x0c]
+
+; CHECK: ld1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0xcf,0x4c]
+; CHECK: ld1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0xcf,0x4c]
+; CHECK: ld1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0xcf,0x4c]
+; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0xcf,0x4c]
+
+; CHECK: ld1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x0c]
+; CHECK: ld1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x0c]
+; CHECK: ld1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x0c]
+; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x0c]
+
+; CHECK: ld1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0xcf,0x4c]
+; CHECK: ld1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0xcf,0x4c]
+; CHECK: ld1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0xcf,0x4c]
+; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0xcf,0x4c]
+
+; CHECK: st1.8b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x0c]
+; CHECK: st1.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x0c]
+; CHECK: st1.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x0c]
+; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x0c]
+
+; CHECK: st1.16b { v0 }, [x1], x15 ; encoding: [0x20,0x70,0x8f,0x4c]
+; CHECK: st1.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa0,0x8f,0x4c]
+; CHECK: st1.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x60,0x8f,0x4c]
+; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x20,0x8f,0x4c]
+
+; CHECK: st1.4h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x0c]
+; CHECK: st1.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x0c]
+; CHECK: st1.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x0c]
+; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x0c]
+
+; CHECK: st1.8h { v0 }, [x1], x15 ; encoding: [0x20,0x74,0x8f,0x4c]
+; CHECK: st1.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa4,0x8f,0x4c]
+; CHECK: st1.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x64,0x8f,0x4c]
+; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x24,0x8f,0x4c]
+
+; CHECK: st1.2s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x0c]
+; CHECK: st1.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x0c]
+; CHECK: st1.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x0c]
+; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x0c]
+
+; CHECK: st1.4s { v0 }, [x1], x15 ; encoding: [0x20,0x78,0x8f,0x4c]
+; CHECK: st1.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0xa8,0x8f,0x4c]
+; CHECK: st1.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x68,0x8f,0x4c]
+; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x28,0x8f,0x4c]
+
+; CHECK: st1.1d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x0c]
+; CHECK: st1.1d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x0c]
+; CHECK: st1.1d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x0c]
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x0c]
+
+; CHECK: st1.2d { v0 }, [x1], x15 ; encoding: [0x20,0x7c,0x8f,0x4c]
+; CHECK: st1.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0xac,0x8f,0x4c]
+; CHECK: st1.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x6c,0x8f,0x4c]
+; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x2c,0x8f,0x4c]
+
+; CHECK: ld1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0xdf,0x0c]
+; CHECK: ld1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0xdf,0x0c]
+; CHECK: ld1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0xdf,0x0c]
+; CHECK: ld1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0xdf,0x0c]
+
+; CHECK: ld1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0xdf,0x4c]
+; CHECK: ld1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0xdf,0x4c]
+; CHECK: ld1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0xdf,0x4c]
+; CHECK: ld1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0xdf,0x4c]
+
+; CHECK: ld1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0xdf,0x0c]
+; CHECK: ld1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0xdf,0x0c]
+; CHECK: ld1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0xdf,0x0c]
+; CHECK: ld1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0xdf,0x0c]
+
+; CHECK: ld1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0xdf,0x4c]
+; CHECK: ld1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0xdf,0x4c]
+; CHECK: ld1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0xdf,0x4c]
+; CHECK: ld1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0xdf,0x4c]
+
+; CHECK: ld1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0xdf,0x0c]
+; CHECK: ld1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0xdf,0x0c]
+; CHECK: ld1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0xdf,0x0c]
+; CHECK: ld1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0xdf,0x0c]
+
+; CHECK: ld1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0xdf,0x4c]
+; CHECK: ld1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0xdf,0x4c]
+; CHECK: ld1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0xdf,0x4c]
+; CHECK: ld1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0xdf,0x4c]
+
+; CHECK: ld1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0xdf,0x0c]
+; CHECK: ld1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0xdf,0x0c]
+; CHECK: ld1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0xdf,0x0c]
+; CHECK: ld1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0xdf,0x0c]
+
+; CHECK: ld1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0xdf,0x4c]
+; CHECK: ld1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0xdf,0x4c]
+; CHECK: ld1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0xdf,0x4c]
+; CHECK: ld1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0xdf,0x4c]
+
+; CHECK: st1.8b { v0 }, [x1], #8 ; encoding: [0x20,0x70,0x9f,0x0c]
+; CHECK: st1.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa0,0x9f,0x0c]
+; CHECK: st1.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x60,0x9f,0x0c]
+; CHECK: st1.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x20,0x9f,0x0c]
+
+; CHECK: st1.16b { v0 }, [x1], #16 ; encoding: [0x20,0x70,0x9f,0x4c]
+; CHECK: st1.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa0,0x9f,0x4c]
+; CHECK: st1.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x60,0x9f,0x4c]
+; CHECK: st1.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x20,0x9f,0x4c]
+
+; CHECK: st1.4h { v0 }, [x1], #8 ; encoding: [0x20,0x74,0x9f,0x0c]
+; CHECK: st1.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa4,0x9f,0x0c]
+; CHECK: st1.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x64,0x9f,0x0c]
+; CHECK: st1.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x24,0x9f,0x0c]
+
+; CHECK: st1.8h { v0 }, [x1], #16 ; encoding: [0x20,0x74,0x9f,0x4c]
+; CHECK: st1.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa4,0x9f,0x4c]
+; CHECK: st1.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x64,0x9f,0x4c]
+; CHECK: st1.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x24,0x9f,0x4c]
+
+; CHECK: st1.2s { v0 }, [x1], #8 ; encoding: [0x20,0x78,0x9f,0x0c]
+; CHECK: st1.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0xa8,0x9f,0x0c]
+; CHECK: st1.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x68,0x9f,0x0c]
+; CHECK: st1.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x28,0x9f,0x0c]
+
+; CHECK: st1.4s { v0 }, [x1], #16 ; encoding: [0x20,0x78,0x9f,0x4c]
+; CHECK: st1.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0xa8,0x9f,0x4c]
+; CHECK: st1.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x68,0x9f,0x4c]
+; CHECK: st1.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x28,0x9f,0x4c]
+
+; CHECK: st1.1d { v0 }, [x1], #8 ; encoding: [0x20,0x7c,0x9f,0x0c]
+; CHECK: st1.1d { v0, v1 }, [x1], #16 ; encoding: [0x20,0xac,0x9f,0x0c]
+; CHECK: st1.1d { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x6c,0x9f,0x0c]
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x2c,0x9f,0x0c]
+
+; CHECK: st1.2d { v0 }, [x1], #16 ; encoding: [0x20,0x7c,0x9f,0x4c]
+; CHECK: st1.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0xac,0x9f,0x4c]
+; CHECK: st1.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x6c,0x9f,0x4c]
+; CHECK: st1.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x2c,0x9f,0x4c]
+
+
+_ld2st2_multiple_post:
+ ld2.8b {v0, v1}, [x1], x15
+ ld2.16b {v0, v1}, [x1], x15
+ ld2.4h {v0, v1}, [x1], x15
+ ld2.8h {v0, v1}, [x1], x15
+ ld2.2s {v0, v1}, [x1], x15
+ ld2.4s {v0, v1}, [x1], x15
+ ld2.2d {v0, v1}, [x1], x15
+
+ st2.8b {v0, v1}, [x1], x15
+ st2.16b {v0, v1}, [x1], x15
+ st2.4h {v0, v1}, [x1], x15
+ st2.8h {v0, v1}, [x1], x15
+ st2.2s {v0, v1}, [x1], x15
+ st2.4s {v0, v1}, [x1], x15
+ st2.2d {v0, v1}, [x1], x15
+
+ ld2.8b {v0, v1}, [x1], #16
+ ld2.16b {v0, v1}, [x1], #32
+ ld2.4h {v0, v1}, [x1], #16
+ ld2.8h {v0, v1}, [x1], #32
+ ld2.2s {v0, v1}, [x1], #16
+ ld2.4s {v0, v1}, [x1], #32
+ ld2.2d {v0, v1}, [x1], #32
+
+ st2.8b {v0, v1}, [x1], #16
+ st2.16b {v0, v1}, [x1], #32
+ st2.4h {v0, v1}, [x1], #16
+ st2.8h {v0, v1}, [x1], #32
+ st2.2s {v0, v1}, [x1], #16
+ st2.4s {v0, v1}, [x1], #32
+ st2.2d {v0, v1}, [x1], #32
+
+
+; CHECK: ld2st2_multiple_post:
+; CHECK: ld2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x0c]
+; CHECK: ld2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0xcf,0x4c]
+; CHECK: ld2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x0c]
+; CHECK: ld2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0xcf,0x4c]
+; CHECK: ld2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x0c]
+; CHECK: ld2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0xcf,0x4c]
+; CHECK: ld2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0xcf,0x4c]
+
+; CHECK: st2.8b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x0c]
+; CHECK: st2.16b { v0, v1 }, [x1], x15 ; encoding: [0x20,0x80,0x8f,0x4c]
+; CHECK: st2.4h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x0c]
+; CHECK: st2.8h { v0, v1 }, [x1], x15 ; encoding: [0x20,0x84,0x8f,0x4c]
+; CHECK: st2.2s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x0c]
+; CHECK: st2.4s { v0, v1 }, [x1], x15 ; encoding: [0x20,0x88,0x8f,0x4c]
+; CHECK: st2.2d { v0, v1 }, [x1], x15 ; encoding: [0x20,0x8c,0x8f,0x4c]
+
+; CHECK: ld2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0xdf,0x0c]
+; CHECK: ld2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0xdf,0x4c]
+; CHECK: ld2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0xdf,0x0c]
+; CHECK: ld2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0xdf,0x4c]
+; CHECK: ld2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0xdf,0x0c]
+; CHECK: ld2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0xdf,0x4c]
+; CHECK: ld2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0xdf,0x4c]
+
+; CHECK: st2.8b { v0, v1 }, [x1], #16 ; encoding: [0x20,0x80,0x9f,0x0c]
+; CHECK: st2.16b { v0, v1 }, [x1], #32 ; encoding: [0x20,0x80,0x9f,0x4c]
+; CHECK: st2.4h { v0, v1 }, [x1], #16 ; encoding: [0x20,0x84,0x9f,0x0c]
+; CHECK: st2.8h { v0, v1 }, [x1], #32 ; encoding: [0x20,0x84,0x9f,0x4c]
+; CHECK: st2.2s { v0, v1 }, [x1], #16 ; encoding: [0x20,0x88,0x9f,0x0c]
+; CHECK: st2.4s { v0, v1 }, [x1], #32 ; encoding: [0x20,0x88,0x9f,0x4c]
+; CHECK: st2.2d { v0, v1 }, [x1], #32 ; encoding: [0x20,0x8c,0x9f,0x4c]
+
+
+_ld3st3_multiple_post:
+ ld3.8b {v0, v1, v2}, [x1], x15
+ ld3.16b {v0, v1, v2}, [x1], x15
+ ld3.4h {v0, v1, v2}, [x1], x15
+ ld3.8h {v0, v1, v2}, [x1], x15
+ ld3.2s {v0, v1, v2}, [x1], x15
+ ld3.4s {v0, v1, v2}, [x1], x15
+ ld3.2d {v0, v1, v2}, [x1], x15
+
+ st3.8b {v0, v1, v2}, [x1], x15
+ st3.16b {v0, v1, v2}, [x1], x15
+ st3.4h {v0, v1, v2}, [x1], x15
+ st3.8h {v0, v1, v2}, [x1], x15
+ st3.2s {v0, v1, v2}, [x1], x15
+ st3.4s {v0, v1, v2}, [x1], x15
+ st3.2d {v0, v1, v2}, [x1], x15
+
+ ld3.8b {v0, v1, v2}, [x1], #24
+ ld3.16b {v0, v1, v2}, [x1], #48
+ ld3.4h {v0, v1, v2}, [x1], #24
+ ld3.8h {v0, v1, v2}, [x1], #48
+ ld3.2s {v0, v1, v2}, [x1], #24
+ ld3.4s {v0, v1, v2}, [x1], #48
+ ld3.2d {v0, v1, v2}, [x1], #48
+
+ st3.8b {v0, v1, v2}, [x1], #24
+ st3.16b {v0, v1, v2}, [x1], #48
+ st3.4h {v0, v1, v2}, [x1], #24
+ st3.8h {v0, v1, v2}, [x1], #48
+ st3.2s {v0, v1, v2}, [x1], #24
+ st3.4s {v0, v1, v2}, [x1], #48
+ st3.2d {v0, v1, v2}, [x1], #48
+
+; CHECK: ld3st3_multiple_post:
+; CHECK: ld3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x0c]
+; CHECK: ld3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0xcf,0x4c]
+; CHECK: ld3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x0c]
+; CHECK: ld3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0xcf,0x4c]
+; CHECK: ld3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x0c]
+; CHECK: ld3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0xcf,0x4c]
+; CHECK: ld3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0xcf,0x4c]
+
+; CHECK: st3.8b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x0c]
+; CHECK: st3.16b { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x40,0x8f,0x4c]
+; CHECK: st3.4h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x0c]
+; CHECK: st3.8h { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x44,0x8f,0x4c]
+; CHECK: st3.2s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x0c]
+; CHECK: st3.4s { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x48,0x8f,0x4c]
+; CHECK: st3.2d { v0, v1, v2 }, [x1], x15 ; encoding: [0x20,0x4c,0x8f,0x4c]
+
+; CHECK: ld3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0xdf,0x0c]
+; CHECK: ld3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0xdf,0x4c]
+; CHECK: ld3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0xdf,0x0c]
+; CHECK: ld3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0xdf,0x4c]
+; CHECK: ld3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0xdf,0x0c]
+; CHECK: ld3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0xdf,0x4c]
+; CHECK: ld3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0xdf,0x4c]
+
+; CHECK: st3.8b { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x40,0x9f,0x0c]
+; CHECK: st3.16b { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x40,0x9f,0x4c]
+; CHECK: st3.4h { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x44,0x9f,0x0c]
+; CHECK: st3.8h { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x44,0x9f,0x4c]
+; CHECK: st3.2s { v0, v1, v2 }, [x1], #24 ; encoding: [0x20,0x48,0x9f,0x0c]
+; CHECK: st3.4s { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x48,0x9f,0x4c]
+; CHECK: st3.2d { v0, v1, v2 }, [x1], #48 ; encoding: [0x20,0x4c,0x9f,0x4c]
+
+_ld4st4_multiple_post:
+ ld4.8b {v0, v1, v2, v3}, [x1], x15
+ ld4.16b {v0, v1, v2, v3}, [x1], x15
+ ld4.4h {v0, v1, v2, v3}, [x1], x15
+ ld4.8h {v0, v1, v2, v3}, [x1], x15
+ ld4.2s {v0, v1, v2, v3}, [x1], x15
+ ld4.4s {v0, v1, v2, v3}, [x1], x15
+ ld4.2d {v0, v1, v2, v3}, [x1], x15
+
+ st4.8b {v0, v1, v2, v3}, [x1], x15
+ st4.16b {v0, v1, v2, v3}, [x1], x15
+ st4.4h {v0, v1, v2, v3}, [x1], x15
+ st4.8h {v0, v1, v2, v3}, [x1], x15
+ st4.2s {v0, v1, v2, v3}, [x1], x15
+ st4.4s {v0, v1, v2, v3}, [x1], x15
+ st4.2d {v0, v1, v2, v3}, [x1], x15
+
+ ld4.8b {v0, v1, v2, v3}, [x1], #32
+ ld4.16b {v0, v1, v2, v3}, [x1], #64
+ ld4.4h {v0, v1, v2, v3}, [x1], #32
+ ld4.8h {v0, v1, v2, v3}, [x1], #64
+ ld4.2s {v0, v1, v2, v3}, [x1], #32
+ ld4.4s {v0, v1, v2, v3}, [x1], #64
+ ld4.2d {v0, v1, v2, v3}, [x1], #64
+
+ st4.8b {v0, v1, v2, v3}, [x1], #32
+ st4.16b {v0, v1, v2, v3}, [x1], #64
+ st4.4h {v0, v1, v2, v3}, [x1], #32
+ st4.8h {v0, v1, v2, v3}, [x1], #64
+ st4.2s {v0, v1, v2, v3}, [x1], #32
+ st4.4s {v0, v1, v2, v3}, [x1], #64
+ st4.2d {v0, v1, v2, v3}, [x1], #64
+
+
+; CHECK: ld4st4_multiple_post:
+; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x0c]
+; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0xcf,0x4c]
+; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x0c]
+; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0xcf,0x4c]
+; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x0c]
+; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0xcf,0x4c]
+; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0xcf,0x4c]
+
+; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x0c]
+; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x00,0x8f,0x4c]
+; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x0c]
+; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x04,0x8f,0x4c]
+; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x0c]
+; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x08,0x8f,0x4c]
+; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], x15 ; encoding: [0x20,0x0c,0x8f,0x4c]
+
+; CHECK: ld4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0xdf,0x0c]
+; CHECK: ld4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0xdf,0x4c]
+; CHECK: ld4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0xdf,0x0c]
+; CHECK: ld4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0xdf,0x4c]
+; CHECK: ld4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0xdf,0x0c]
+; CHECK: ld4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0xdf,0x4c]
+; CHECK: ld4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0xdf,0x4c]
+
+; CHECK: st4.8b { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x00,0x9f,0x0c]
+; CHECK: st4.16b { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x00,0x9f,0x4c]
+; CHECK: st4.4h { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x04,0x9f,0x0c]
+; CHECK: st4.8h { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x04,0x9f,0x4c]
+; CHECK: st4.2s { v0, v1, v2, v3 }, [x1], #32 ; encoding: [0x20,0x08,0x9f,0x0c]
+; CHECK: st4.4s { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x08,0x9f,0x4c]
+; CHECK: st4.2d { v0, v1, v2, v3 }, [x1], #64 ; encoding: [0x20,0x0c,0x9f,0x4c]
+
+ld1r:
+ ld1r.8b {v4}, [x2]
+ ld1r.8b {v4}, [x2], x3
+ ld1r.16b {v4}, [x2]
+ ld1r.16b {v4}, [x2], x3
+ ld1r.4h {v4}, [x2]
+ ld1r.4h {v4}, [x2], x3
+ ld1r.8h {v4}, [x2]
+ ld1r.8h {v4}, [x2], x3
+ ld1r.2s {v4}, [x2]
+ ld1r.2s {v4}, [x2], x3
+ ld1r.4s {v4}, [x2]
+ ld1r.4s {v4}, [x2], x3
+ ld1r.1d {v4}, [x2]
+ ld1r.1d {v4}, [x2], x3
+ ld1r.2d {v4}, [x2]
+ ld1r.2d {v4}, [x2], x3
+
+ ld1r.8b {v4}, [x2], #1
+ ld1r.16b {v4}, [x2], #1
+ ld1r.4h {v4}, [x2], #2
+ ld1r.8h {v4}, [x2], #2
+ ld1r.2s {v4}, [x2], #4
+ ld1r.4s {v4}, [x2], #4
+ ld1r.1d {v4}, [x2], #8
+ ld1r.2d {v4}, [x2], #8
+
+; CHECK: ld1r:
+; CHECK: ld1r.8b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x0d]
+; CHECK: ld1r.8b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x0d]
+; CHECK: ld1r.16b { v4 }, [x2] ; encoding: [0x44,0xc0,0x40,0x4d]
+; CHECK: ld1r.16b { v4 }, [x2], x3 ; encoding: [0x44,0xc0,0xc3,0x4d]
+; CHECK: ld1r.4h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x0d]
+; CHECK: ld1r.4h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x0d]
+; CHECK: ld1r.8h { v4 }, [x2] ; encoding: [0x44,0xc4,0x40,0x4d]
+; CHECK: ld1r.8h { v4 }, [x2], x3 ; encoding: [0x44,0xc4,0xc3,0x4d]
+; CHECK: ld1r.2s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x0d]
+; CHECK: ld1r.2s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x0d]
+; CHECK: ld1r.4s { v4 }, [x2] ; encoding: [0x44,0xc8,0x40,0x4d]
+; CHECK: ld1r.4s { v4 }, [x2], x3 ; encoding: [0x44,0xc8,0xc3,0x4d]
+; CHECK: ld1r.1d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x0d]
+; CHECK: ld1r.1d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x0d]
+; CHECK: ld1r.2d { v4 }, [x2] ; encoding: [0x44,0xcc,0x40,0x4d]
+; CHECK: ld1r.2d { v4 }, [x2], x3 ; encoding: [0x44,0xcc,0xc3,0x4d]
+
+; CHECK: ld1r.8b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x0d]
+; CHECK: ld1r.16b { v4 }, [x2], #1 ; encoding: [0x44,0xc0,0xdf,0x4d]
+; CHECK: ld1r.4h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x0d]
+; CHECK: ld1r.8h { v4 }, [x2], #2 ; encoding: [0x44,0xc4,0xdf,0x4d]
+; CHECK: ld1r.2s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x0d]
+; CHECK: ld1r.4s { v4 }, [x2], #4 ; encoding: [0x44,0xc8,0xdf,0x4d]
+; CHECK: ld1r.1d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x0d]
+; CHECK: ld1r.2d { v4 }, [x2], #8 ; encoding: [0x44,0xcc,0xdf,0x4d]
+
+ld2r:
+ ld2r.8b {v4, v5}, [x2]
+ ld2r.8b {v4, v5}, [x2], x3
+ ld2r.16b {v4, v5}, [x2]
+ ld2r.16b {v4, v5}, [x2], x3
+ ld2r.4h {v4, v5}, [x2]
+ ld2r.4h {v4, v5}, [x2], x3
+ ld2r.8h {v4, v5}, [x2]
+ ld2r.8h {v4, v5}, [x2], x3
+ ld2r.2s {v4, v5}, [x2]
+ ld2r.2s {v4, v5}, [x2], x3
+ ld2r.4s {v4, v5}, [x2]
+ ld2r.4s {v4, v5}, [x2], x3
+ ld2r.1d {v4, v5}, [x2]
+ ld2r.1d {v4, v5}, [x2], x3
+ ld2r.2d {v4, v5}, [x2]
+ ld2r.2d {v4, v5}, [x2], x3
+
+ ld2r.8b {v4, v5}, [x2], #2
+ ld2r.16b {v4, v5}, [x2], #2
+ ld2r.4h {v4, v5}, [x2], #4
+ ld2r.8h {v4, v5}, [x2], #4
+ ld2r.2s {v4, v5}, [x2], #8
+ ld2r.4s {v4, v5}, [x2], #8
+ ld2r.1d {v4, v5}, [x2], #16
+ ld2r.2d {v4, v5}, [x2], #16
+
+; CHECK: ld2r:
+; CHECK: ld2r.8b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x0d]
+; CHECK: ld2r.8b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x0d]
+; CHECK: ld2r.16b { v4, v5 }, [x2] ; encoding: [0x44,0xc0,0x60,0x4d]
+; CHECK: ld2r.16b { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc0,0xe3,0x4d]
+; CHECK: ld2r.4h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x0d]
+; CHECK: ld2r.4h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x0d]
+; CHECK: ld2r.8h { v4, v5 }, [x2] ; encoding: [0x44,0xc4,0x60,0x4d]
+; CHECK: ld2r.8h { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc4,0xe3,0x4d]
+; CHECK: ld2r.2s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x0d]
+; CHECK: ld2r.2s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x0d]
+; CHECK: ld2r.4s { v4, v5 }, [x2] ; encoding: [0x44,0xc8,0x60,0x4d]
+; CHECK: ld2r.4s { v4, v5 }, [x2], x3 ; encoding: [0x44,0xc8,0xe3,0x4d]
+; CHECK: ld2r.1d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x0d]
+; CHECK: ld2r.1d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x0d]
+; CHECK: ld2r.2d { v4, v5 }, [x2] ; encoding: [0x44,0xcc,0x60,0x4d]
+; CHECK: ld2r.2d { v4, v5 }, [x2], x3 ; encoding: [0x44,0xcc,0xe3,0x4d]
+
+; CHECK: ld2r.8b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x0d]
+; CHECK: ld2r.16b { v4, v5 }, [x2], #2 ; encoding: [0x44,0xc0,0xff,0x4d]
+; CHECK: ld2r.4h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x0d]
+; CHECK: ld2r.8h { v4, v5 }, [x2], #4 ; encoding: [0x44,0xc4,0xff,0x4d]
+; CHECK: ld2r.2s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x0d]
+; CHECK: ld2r.4s { v4, v5 }, [x2], #8 ; encoding: [0x44,0xc8,0xff,0x4d]
+; CHECK: ld2r.1d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x0d]
+; CHECK: ld2r.2d { v4, v5 }, [x2], #16 ; encoding: [0x44,0xcc,0xff,0x4d]
+
+ld3r:
+ ld3r.8b {v4, v5, v6}, [x2]
+ ld3r.8b {v4, v5, v6}, [x2], x3
+ ld3r.16b {v4, v5, v6}, [x2]
+ ld3r.16b {v4, v5, v6}, [x2], x3
+ ld3r.4h {v4, v5, v6}, [x2]
+ ld3r.4h {v4, v5, v6}, [x2], x3
+ ld3r.8h {v4, v5, v6}, [x2]
+ ld3r.8h {v4, v5, v6}, [x2], x3
+ ld3r.2s {v4, v5, v6}, [x2]
+ ld3r.2s {v4, v5, v6}, [x2], x3
+ ld3r.4s {v4, v5, v6}, [x2]
+ ld3r.4s {v4, v5, v6}, [x2], x3
+ ld3r.1d {v4, v5, v6}, [x2]
+ ld3r.1d {v4, v5, v6}, [x2], x3
+ ld3r.2d {v4, v5, v6}, [x2]
+ ld3r.2d {v4, v5, v6}, [x2], x3
+
+ ld3r.8b {v4, v5, v6}, [x2], #3
+ ld3r.16b {v4, v5, v6}, [x2], #3
+ ld3r.4h {v4, v5, v6}, [x2], #6
+ ld3r.8h {v4, v5, v6}, [x2], #6
+ ld3r.2s {v4, v5, v6}, [x2], #12
+ ld3r.4s {v4, v5, v6}, [x2], #12
+ ld3r.1d {v4, v5, v6}, [x2], #24
+ ld3r.2d {v4, v5, v6}, [x2], #24
+
+; CHECK: ld3r:
+; CHECK: ld3r.8b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x0d]
+; CHECK: ld3r.8b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x0d]
+; CHECK: ld3r.16b { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe0,0x40,0x4d]
+; CHECK: ld3r.16b { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe0,0xc3,0x4d]
+; CHECK: ld3r.4h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x0d]
+; CHECK: ld3r.4h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x0d]
+; CHECK: ld3r.8h { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe4,0x40,0x4d]
+; CHECK: ld3r.8h { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe4,0xc3,0x4d]
+; CHECK: ld3r.2s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x0d]
+; CHECK: ld3r.2s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x0d]
+; CHECK: ld3r.4s { v4, v5, v6 }, [x2] ; encoding: [0x44,0xe8,0x40,0x4d]
+; CHECK: ld3r.4s { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xe8,0xc3,0x4d]
+; CHECK: ld3r.1d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x0d]
+; CHECK: ld3r.1d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x0d]
+; CHECK: ld3r.2d { v4, v5, v6 }, [x2] ; encoding: [0x44,0xec,0x40,0x4d]
+; CHECK: ld3r.2d { v4, v5, v6 }, [x2], x3 ; encoding: [0x44,0xec,0xc3,0x4d]
+
+; CHECK: ld3r.8b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x0d]
+; CHECK: ld3r.16b { v4, v5, v6 }, [x2], #3 ; encoding: [0x44,0xe0,0xdf,0x4d]
+; CHECK: ld3r.4h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x0d]
+; CHECK: ld3r.8h { v4, v5, v6 }, [x2], #6 ; encoding: [0x44,0xe4,0xdf,0x4d]
+; CHECK: ld3r.2s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x0d]
+; CHECK: ld3r.4s { v4, v5, v6 }, [x2], #12 ; encoding: [0x44,0xe8,0xdf,0x4d]
+; CHECK: ld3r.1d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x0d]
+; CHECK: ld3r.2d { v4, v5, v6 }, [x2], #24 ; encoding: [0x44,0xec,0xdf,0x4d]
+
+ld4r:
+ ld4r.8b {v4, v5, v6, v7}, [x2]
+ ld4r.8b {v4, v5, v6, v7}, [x2], x3
+ ld4r.16b {v4, v5, v6, v7}, [x2]
+ ld4r.16b {v4, v5, v6, v7}, [x2], x3
+ ld4r.4h {v4, v5, v6, v7}, [x2]
+ ld4r.4h {v4, v5, v6, v7}, [x2], x3
+ ld4r.8h {v4, v5, v6, v7}, [x2]
+ ld4r.8h {v4, v5, v6, v7}, [x2], x3
+ ld4r.2s {v4, v5, v6, v7}, [x2]
+ ld4r.2s {v4, v5, v6, v7}, [x2], x3
+ ld4r.4s {v4, v5, v6, v7}, [x2]
+ ld4r.4s {v4, v5, v6, v7}, [x2], x3
+ ld4r.1d {v4, v5, v6, v7}, [x2]
+ ld4r.1d {v4, v5, v6, v7}, [x2], x3
+ ld4r.2d {v4, v5, v6, v7}, [x2]
+ ld4r.2d {v4, v5, v6, v7}, [x2], x3
+
+ ld4r.8b {v4, v5, v6, v7}, [x2], #4
+ ld4r.16b {v5, v6, v7, v8}, [x2], #4
+ ld4r.4h {v6, v7, v8, v9}, [x2], #8
+ ld4r.8h {v1, v2, v3, v4}, [x2], #8
+ ld4r.2s {v2, v3, v4, v5}, [x2], #16
+ ld4r.4s {v3, v4, v5, v6}, [x2], #16
+ ld4r.1d {v0, v1, v2, v3}, [x2], #32
+ ld4r.2d {v4, v5, v6, v7}, [x2], #32
+
+; CHECK: ld4r:
+; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x0d]
+; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x0d]
+; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe0,0x60,0x4d]
+; CHECK: ld4r.16b { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe0,0xe3,0x4d]
+; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x0d]
+; CHECK: ld4r.4h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x0d]
+; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe4,0x60,0x4d]
+; CHECK: ld4r.8h { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe4,0xe3,0x4d]
+; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x0d]
+; CHECK: ld4r.2s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x0d]
+; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xe8,0x60,0x4d]
+; CHECK: ld4r.4s { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xe8,0xe3,0x4d]
+; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x0d]
+; CHECK: ld4r.1d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x0d]
+; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2] ; encoding: [0x44,0xec,0x60,0x4d]
+; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], x3 ; encoding: [0x44,0xec,0xe3,0x4d]
+
+; CHECK: ld4r.8b { v4, v5, v6, v7 }, [x2], #4 ; encoding: [0x44,0xe0,0xff,0x0d]
+; CHECK: ld4r.16b { v5, v6, v7, v8 }, [x2], #4 ; encoding: [0x45,0xe0,0xff,0x4d]
+; CHECK: ld4r.4h { v6, v7, v8, v9 }, [x2], #8 ; encoding: [0x46,0xe4,0xff,0x0d]
+; CHECK: ld4r.8h { v1, v2, v3, v4 }, [x2], #8 ; encoding: [0x41,0xe4,0xff,0x4d]
+; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d]
+; CHECK: ld4r.4s { v3, v4, v5, v6 }, [x2], #16 ; encoding: [0x43,0xe8,0xff,0x4d]
+; CHECK: ld4r.1d { v0, v1, v2, v3 }, [x2], #32 ; encoding: [0x40,0xec,0xff,0x0d]
+; CHECK: ld4r.2d { v4, v5, v6, v7 }, [x2], #32 ; encoding: [0x44,0xec,0xff,0x4d]
+
+
+_ld1:
+ ld1.b {v4}[13], [x3]
+ ld1.h {v4}[2], [x3]
+ ld1.s {v4}[2], [x3]
+ ld1.d {v4}[1], [x3]
+ ld1.b {v4}[13], [x3], x5
+ ld1.h {v4}[2], [x3], x5
+ ld1.s {v4}[2], [x3], x5
+ ld1.d {v4}[1], [x3], x5
+ ld1.b {v4}[13], [x3], #1
+ ld1.h {v4}[2], [x3], #2
+ ld1.s {v4}[2], [x3], #4
+ ld1.d {v4}[1], [x3], #8
+
+; CHECK: _ld1:
+; CHECK: ld1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x40,0x4d]
+; CHECK: ld1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x40,0x0d]
+; CHECK: ld1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x40,0x4d]
+; CHECK: ld1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x40,0x4d]
+; CHECK: ld1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0xc5,0x4d]
+; CHECK: ld1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0xc5,0x0d]
+; CHECK: ld1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0xc5,0x4d]
+; CHECK: ld1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0xc5,0x4d]
+; CHECK: ld1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0xdf,0x4d]
+; CHECK: ld1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0xdf,0x0d]
+; CHECK: ld1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0xdf,0x4d]
+; CHECK: ld1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0xdf,0x4d]
+
+_ld2:
+ ld2.b {v4, v5}[13], [x3]
+ ld2.h {v4, v5}[2], [x3]
+ ld2.s {v4, v5}[2], [x3]
+ ld2.d {v4, v5}[1], [x3]
+ ld2.b {v4, v5}[13], [x3], x5
+ ld2.h {v4, v5}[2], [x3], x5
+ ld2.s {v4, v5}[2], [x3], x5
+ ld2.d {v4, v5}[1], [x3], x5
+ ld2.b {v4, v5}[13], [x3], #2
+ ld2.h {v4, v5}[2], [x3], #4
+ ld2.s {v4, v5}[2], [x3], #8
+ ld2.d {v4, v5}[1], [x3], #16
+
+
+; CHECK: _ld2:
+; CHECK: ld2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x60,0x4d]
+; CHECK: ld2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x60,0x0d]
+; CHECK: ld2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x60,0x4d]
+; CHECK: ld2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x60,0x4d]
+; CHECK: ld2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xe5,0x4d]
+; CHECK: ld2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xe5,0x0d]
+; CHECK: ld2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xe5,0x4d]
+; CHECK: ld2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xe5,0x4d]
+; CHECK: ld2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xff,0x4d]
+; CHECK: ld2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xff,0x0d]
+; CHECK: ld2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xff,0x4d]
+; CHECK: ld2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xff,0x4d]
+
+
+_ld3:
+ ld3.b {v4, v5, v6}[13], [x3]
+ ld3.h {v4, v5, v6}[2], [x3]
+ ld3.s {v4, v5, v6}[2], [x3]
+ ld3.d {v4, v5, v6}[1], [x3]
+ ld3.b {v4, v5, v6}[13], [x3], x5
+ ld3.h {v4, v5, v6}[2], [x3], x5
+ ld3.s {v4, v5, v6}[2], [x3], x5
+ ld3.d {v4, v5, v6}[1], [x3], x5
+ ld3.b {v4, v5, v6}[13], [x3], #3
+ ld3.h {v4, v5, v6}[2], [x3], #6
+ ld3.s {v4, v5, v6}[2], [x3], #12
+ ld3.d {v4, v5, v6}[1], [x3], #24
+
+
+; CHECK: _ld3:
+; CHECK: ld3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x40,0x4d]
+; CHECK: ld3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x40,0x0d]
+; CHECK: ld3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x40,0x4d]
+; CHECK: ld3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x40,0x4d]
+; CHECK: ld3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0xc5,0x4d]
+; CHECK: ld3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0xc5,0x0d]
+; CHECK: ld3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xc5,0x4d]
+; CHECK: ld3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xc5,0x4d]
+; CHECK: ld3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0xdf,0x4d]
+; CHECK: ld3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0xdf,0x0d]
+; CHECK: ld3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0xdf,0x4d]
+; CHECK: ld3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0xdf,0x4d]
+
+
+_ld4:
+ ld4.b {v4, v5, v6, v7}[13], [x3]
+ ld4.h {v4, v5, v6, v7}[2], [x3]
+ ld4.s {v4, v5, v6, v7}[2], [x3]
+ ld4.d {v4, v5, v6, v7}[1], [x3]
+ ld4.b {v4, v5, v6, v7}[13], [x3], x5
+ ld4.h {v4, v5, v6, v7}[2], [x3], x5
+ ld4.s {v4, v5, v6, v7}[2], [x3], x5
+ ld4.d {v4, v5, v6, v7}[1], [x3], x5
+ ld4.b {v4, v5, v6, v7}[13], [x3], #4
+ ld4.h {v4, v5, v6, v7}[2], [x3], #8
+ ld4.s {v4, v5, v6, v7}[2], [x3], #16
+ ld4.d {v4, v5, v6, v7}[1], [x3], #32
+
+; CHECK: _ld4:
+; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x60,0x4d]
+; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x60,0x0d]
+; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x60,0x4d]
+; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x60,0x4d]
+; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xe5,0x4d]
+; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xe5,0x0d]
+; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xe5,0x4d]
+; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xe5,0x4d]
+; CHECK: ld4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xff,0x4d]
+; CHECK: ld4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xff,0x0d]
+; CHECK: ld4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xff,0x4d]
+; CHECK: ld4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xff,0x4d]
+
+_st1:
+ st1.b {v4}[13], [x3]
+ st1.h {v4}[2], [x3]
+ st1.s {v4}[2], [x3]
+ st1.d {v4}[1], [x3]
+ st1.b {v4}[13], [x3], x5
+ st1.h {v4}[2], [x3], x5
+ st1.s {v4}[2], [x3], x5
+ st1.d {v4}[1], [x3], x5
+ st1.b {v4}[13], [x3], #1
+ st1.h {v4}[2], [x3], #2
+ st1.s {v4}[2], [x3], #4
+ st1.d {v4}[1], [x3], #8
+
+; CHECK: _st1:
+; CHECK: st1.b { v4 }[13], [x3] ; encoding: [0x64,0x14,0x00,0x4d]
+; CHECK: st1.h { v4 }[2], [x3] ; encoding: [0x64,0x50,0x00,0x0d]
+; CHECK: st1.s { v4 }[2], [x3] ; encoding: [0x64,0x80,0x00,0x4d]
+; CHECK: st1.d { v4 }[1], [x3] ; encoding: [0x64,0x84,0x00,0x4d]
+; CHECK: st1.b { v4 }[13], [x3], x5 ; encoding: [0x64,0x14,0x85,0x4d]
+; CHECK: st1.h { v4 }[2], [x3], x5 ; encoding: [0x64,0x50,0x85,0x0d]
+; CHECK: st1.s { v4 }[2], [x3], x5 ; encoding: [0x64,0x80,0x85,0x4d]
+; CHECK: st1.d { v4 }[1], [x3], x5 ; encoding: [0x64,0x84,0x85,0x4d]
+; CHECK: st1.b { v4 }[13], [x3], #1 ; encoding: [0x64,0x14,0x9f,0x4d]
+; CHECK: st1.h { v4 }[2], [x3], #2 ; encoding: [0x64,0x50,0x9f,0x0d]
+; CHECK: st1.s { v4 }[2], [x3], #4 ; encoding: [0x64,0x80,0x9f,0x4d]
+; CHECK: st1.d { v4 }[1], [x3], #8 ; encoding: [0x64,0x84,0x9f,0x4d]
+
+_st2:
+ st2.b {v4, v5}[13], [x3]
+ st2.h {v4, v5}[2], [x3]
+ st2.s {v4, v5}[2], [x3]
+ st2.d {v4, v5}[1], [x3]
+ st2.b {v4, v5}[13], [x3], x5
+ st2.h {v4, v5}[2], [x3], x5
+ st2.s {v4, v5}[2], [x3], x5
+ st2.d {v4, v5}[1], [x3], x5
+ st2.b {v4, v5}[13], [x3], #2
+ st2.h {v4, v5}[2], [x3], #4
+ st2.s {v4, v5}[2], [x3], #8
+ st2.d {v4, v5}[1], [x3], #16
+
+; CHECK: _st2:
+; CHECK: st2.b { v4, v5 }[13], [x3] ; encoding: [0x64,0x14,0x20,0x4d]
+; CHECK: st2.h { v4, v5 }[2], [x3] ; encoding: [0x64,0x50,0x20,0x0d]
+; CHECK: st2.s { v4, v5 }[2], [x3] ; encoding: [0x64,0x80,0x20,0x4d]
+; CHECK: st2.d { v4, v5 }[1], [x3] ; encoding: [0x64,0x84,0x20,0x4d]
+; CHECK: st2.b { v4, v5 }[13], [x3], x5 ; encoding: [0x64,0x14,0xa5,0x4d]
+; CHECK: st2.h { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x50,0xa5,0x0d]
+; CHECK: st2.s { v4, v5 }[2], [x3], x5 ; encoding: [0x64,0x80,0xa5,0x4d]
+; CHECK: st2.d { v4, v5 }[1], [x3], x5 ; encoding: [0x64,0x84,0xa5,0x4d]
+; CHECK: st2.b { v4, v5 }[13], [x3], #2 ; encoding: [0x64,0x14,0xbf,0x4d]
+; CHECK: st2.h { v4, v5 }[2], [x3], #4 ; encoding: [0x64,0x50,0xbf,0x0d]
+; CHECK: st2.s { v4, v5 }[2], [x3], #8 ; encoding: [0x64,0x80,0xbf,0x4d]
+; CHECK: st2.d { v4, v5 }[1], [x3], #16 ; encoding: [0x64,0x84,0xbf,0x4d]
+
+
+_st3:
+ st3.b {v4, v5, v6}[13], [x3]
+ st3.h {v4, v5, v6}[2], [x3]
+ st3.s {v4, v5, v6}[2], [x3]
+ st3.d {v4, v5, v6}[1], [x3]
+ st3.b {v4, v5, v6}[13], [x3], x5
+ st3.h {v4, v5, v6}[2], [x3], x5
+ st3.s {v4, v5, v6}[2], [x3], x5
+ st3.d {v4, v5, v6}[1], [x3], x5
+ st3.b {v4, v5, v6}[13], [x3], #3
+ st3.h {v4, v5, v6}[2], [x3], #6
+ st3.s {v4, v5, v6}[2], [x3], #12
+ st3.d {v4, v5, v6}[1], [x3], #24
+
+; CHECK: _st3:
+; CHECK: st3.b { v4, v5, v6 }[13], [x3] ; encoding: [0x64,0x34,0x00,0x4d]
+; CHECK: st3.h { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0x70,0x00,0x0d]
+; CHECK: st3.s { v4, v5, v6 }[2], [x3] ; encoding: [0x64,0xa0,0x00,0x4d]
+; CHECK: st3.d { v4, v5, v6 }[1], [x3] ; encoding: [0x64,0xa4,0x00,0x4d]
+; CHECK: st3.b { v4, v5, v6 }[13], [x3], x5 ; encoding: [0x64,0x34,0x85,0x4d]
+; CHECK: st3.h { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0x70,0x85,0x0d]
+; CHECK: st3.s { v4, v5, v6 }[2], [x3], x5 ; encoding: [0x64,0xa0,0x85,0x4d]
+; CHECK: st3.d { v4, v5, v6 }[1], [x3], x5 ; encoding: [0x64,0xa4,0x85,0x4d]
+; CHECK: st3.b { v4, v5, v6 }[13], [x3], #3 ; encoding: [0x64,0x34,0x9f,0x4d]
+; CHECK: st3.h { v4, v5, v6 }[2], [x3], #6 ; encoding: [0x64,0x70,0x9f,0x0d]
+; CHECK: st3.s { v4, v5, v6 }[2], [x3], #12 ; encoding: [0x64,0xa0,0x9f,0x4d]
+; CHECK: st3.d { v4, v5, v6 }[1], [x3], #24 ; encoding: [0x64,0xa4,0x9f,0x4d]
+
+_st4:
+ st4.b {v4, v5, v6, v7}[13], [x3]
+ st4.h {v4, v5, v6, v7}[2], [x3]
+ st4.s {v4, v5, v6, v7}[2], [x3]
+ st4.d {v4, v5, v6, v7}[1], [x3]
+ st4.b {v4, v5, v6, v7}[13], [x3], x5
+ st4.h {v4, v5, v6, v7}[2], [x3], x5
+ st4.s {v4, v5, v6, v7}[2], [x3], x5
+ st4.d {v4, v5, v6, v7}[1], [x3], x5
+ st4.b {v4, v5, v6, v7}[13], [x3], #4
+ st4.h {v4, v5, v6, v7}[2], [x3], #8
+ st4.s {v4, v5, v6, v7}[2], [x3], #16
+ st4.d {v4, v5, v6, v7}[1], [x3], #32
+
+; CHECK: _st4:
+; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3] ; encoding: [0x64,0x34,0x20,0x4d]
+; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0x70,0x20,0x0d]
+; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3] ; encoding: [0x64,0xa0,0x20,0x4d]
+; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3] ; encoding: [0x64,0xa4,0x20,0x4d]
+; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], x5 ; encoding: [0x64,0x34,0xa5,0x4d]
+; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0x70,0xa5,0x0d]
+; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], x5 ; encoding: [0x64,0xa0,0xa5,0x4d]
+; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], x5 ; encoding: [0x64,0xa4,0xa5,0x4d]
+; CHECK: st4.b { v4, v5, v6, v7 }[13], [x3], #4 ; encoding: [0x64,0x34,0xbf,0x4d]
+; CHECK: st4.h { v4, v5, v6, v7 }[2], [x3], #8 ; encoding: [0x64,0x70,0xbf,0x0d]
+; CHECK: st4.s { v4, v5, v6, v7 }[2], [x3], #16 ; encoding: [0x64,0xa0,0xbf,0x4d]
+; CHECK: st4.d { v4, v5, v6, v7 }[1], [x3], #32 ; encoding: [0x64,0xa4,0xbf,0x4d]
+
+
+;---------
+; ARM verbose syntax equivalents to the above.
+;---------
+verbose_syntax:
+
+ ld1 { v1.8b }, [x1]
+ ld1 { v2.8b, v3.8b }, [x1]
+ ld1 { v3.8b, v4.8b, v5.8b }, [x1]
+ ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1]
+
+ ld1 { v1.16b }, [x1]
+ ld1 { v2.16b, v3.16b }, [x1]
+ ld1 { v3.16b, v4.16b, v5.16b }, [x1]
+ ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1]
+
+ ld1 { v1.4h }, [x1]
+ ld1 { v2.4h, v3.4h }, [x1]
+ ld1 { v3.4h, v4.4h, v5.4h }, [x1]
+ ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1]
+
+ ld1 { v1.8h }, [x1]
+ ld1 { v2.8h, v3.8h }, [x1]
+ ld1 { v3.8h, v4.8h, v5.8h }, [x1]
+ ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1]
+
+ ld1 { v1.2s }, [x1]
+ ld1 { v2.2s, v3.2s }, [x1]
+ ld1 { v3.2s, v4.2s, v5.2s }, [x1]
+ ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1]
+
+ ld1 { v1.4s }, [x1]
+ ld1 { v2.4s, v3.4s }, [x1]
+ ld1 { v3.4s, v4.4s, v5.4s }, [x1]
+ ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1]
+
+ ld1 { v1.1d }, [x1]
+ ld1 { v2.1d, v3.1d }, [x1]
+ ld1 { v3.1d, v4.1d, v5.1d }, [x1]
+ ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1]
+
+ ld1 { v1.2d }, [x1]
+ ld1 { v2.2d, v3.2d }, [x1]
+ ld1 { v3.2d, v4.2d, v5.2d }, [x1]
+ ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1]
+
+ st1 { v1.8b }, [x1]
+ st1 { v2.8b, v3.8b }, [x1]
+ st1 { v3.8b, v4.8b, v5.8b }, [x1]
+ st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1]
+
+ st1 { v1.16b }, [x1]
+ st1 { v2.16b, v3.16b }, [x1]
+ st1 { v3.16b, v4.16b, v5.16b }, [x1]
+ st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1]
+
+ st1 { v1.4h }, [x1]
+ st1 { v2.4h, v3.4h }, [x1]
+ st1 { v3.4h, v4.4h, v5.4h }, [x1]
+ st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1]
+
+ st1 { v1.8h }, [x1]
+ st1 { v2.8h, v3.8h }, [x1]
+ st1 { v3.8h, v4.8h, v5.8h }, [x1]
+ st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1]
+
+ st1 { v1.2s }, [x1]
+ st1 { v2.2s, v3.2s }, [x1]
+ st1 { v3.2s, v4.2s, v5.2s }, [x1]
+ st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1]
+
+ st1 { v1.4s }, [x1]
+ st1 { v2.4s, v3.4s }, [x1]
+ st1 { v3.4s, v4.4s, v5.4s }, [x1]
+ st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1]
+
+ st1 { v1.1d }, [x1]
+ st1 { v2.1d, v3.1d }, [x1]
+ st1 { v3.1d, v4.1d, v5.1d }, [x1]
+ st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1]
+
+ st1 { v1.2d }, [x1]
+ st1 { v2.2d, v3.2d }, [x1]
+ st1 { v3.2d, v4.2d, v5.2d }, [x1]
+ st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1]
+
+ ld2 { v3.8b, v4.8b }, [x19]
+ ld2 { v3.16b, v4.16b }, [x19]
+ ld2 { v3.4h, v4.4h }, [x19]
+ ld2 { v3.8h, v4.8h }, [x19]
+ ld2 { v3.2s, v4.2s }, [x19]
+ ld2 { v3.4s, v4.4s }, [x19]
+ ld2 { v3.2d, v4.2d }, [x19]
+
+ st2 { v3.8b, v4.8b }, [x19]
+ st2 { v3.16b, v4.16b }, [x19]
+ st2 { v3.4h, v4.4h }, [x19]
+ st2 { v3.8h, v4.8h }, [x19]
+ st2 { v3.2s, v4.2s }, [x19]
+ st2 { v3.4s, v4.4s }, [x19]
+ st2 { v3.2d, v4.2d }, [x19]
+
+ ld3 { v2.8b, v3.8b, v4.8b }, [x19]
+ ld3 { v2.16b, v3.16b, v4.16b }, [x19]
+ ld3 { v2.4h, v3.4h, v4.4h }, [x19]
+ ld3 { v2.8h, v3.8h, v4.8h }, [x19]
+ ld3 { v2.2s, v3.2s, v4.2s }, [x19]
+ ld3 { v2.4s, v3.4s, v4.4s }, [x19]
+ ld3 { v2.2d, v3.2d, v4.2d }, [x19]
+
+ st3 { v2.8b, v3.8b, v4.8b }, [x19]
+ st3 { v2.16b, v3.16b, v4.16b }, [x19]
+ st3 { v2.4h, v3.4h, v4.4h }, [x19]
+ st3 { v2.8h, v3.8h, v4.8h }, [x19]
+ st3 { v2.2s, v3.2s, v4.2s }, [x19]
+ st3 { v2.4s, v3.4s, v4.4s }, [x19]
+ st3 { v2.2d, v3.2d, v4.2d }, [x19]
+
+ ld4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
+ ld4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
+ ld4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
+ ld4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
+ ld4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
+ ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
+ ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
+
+ st4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
+ st4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
+ st4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
+ st4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
+ st4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
+ st4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
+ st4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
+
+ ld1 { v1.8b }, [x1], x15
+ ld1 { v2.8b, v3.8b }, [x1], x15
+ ld1 { v3.8b, v4.8b, v5.8b }, [x1], x15
+ ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
+
+ ld1 { v1.16b }, [x1], x15
+ ld1 { v2.16b, v3.16b }, [x1], x15
+ ld1 { v3.16b, v4.16b, v5.16b }, [x1], x15
+ ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
+
+ ld1 { v1.4h }, [x1], x15
+ ld1 { v2.4h, v3.4h }, [x1], x15
+ ld1 { v3.4h, v4.4h, v5.4h }, [x1], x15
+ ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
+
+ ld1 { v1.8h }, [x1], x15
+ ld1 { v2.8h, v3.8h }, [x1], x15
+ ld1 { v3.8h, v4.8h, v5.8h }, [x1], x15
+ ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
+
+ ld1 { v1.2s }, [x1], x15
+ ld1 { v2.2s, v3.2s }, [x1], x15
+ ld1 { v3.2s, v4.2s, v5.2s }, [x1], x15
+ ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
+
+ ld1 { v1.4s }, [x1], x15
+ ld1 { v2.4s, v3.4s }, [x1], x15
+ ld1 { v3.4s, v4.4s, v5.4s }, [x1], x15
+ ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
+
+ ld1 { v1.1d }, [x1], x15
+ ld1 { v2.1d, v3.1d }, [x1], x15
+ ld1 { v3.1d, v4.1d, v5.1d }, [x1], x15
+ ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15
+
+ ld1 { v1.2d }, [x1], x15
+ ld1 { v2.2d, v3.2d }, [x1], x15
+ ld1 { v3.2d, v4.2d, v5.2d }, [x1], x15
+ ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
+
+ st1 { v1.8b }, [x1], x15
+ st1 { v2.8b, v3.8b }, [x1], x15
+ st1 { v3.8b, v4.8b, v5.8b }, [x1], x15
+ st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
+
+ st1 { v1.16b }, [x1], x15
+ st1 { v2.16b, v3.16b }, [x1], x15
+ st1 { v3.16b, v4.16b, v5.16b }, [x1], x15
+ st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
+
+ st1 { v1.4h }, [x1], x15
+ st1 { v2.4h, v3.4h }, [x1], x15
+ st1 { v3.4h, v4.4h, v5.4h }, [x1], x15
+ st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
+
+ st1 { v1.8h }, [x1], x15
+ st1 { v2.8h, v3.8h }, [x1], x15
+ st1 { v3.8h, v4.8h, v5.8h }, [x1], x15
+ st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
+
+ st1 { v1.2s }, [x1], x15
+ st1 { v2.2s, v3.2s }, [x1], x15
+ st1 { v3.2s, v4.2s, v5.2s }, [x1], x15
+ st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
+
+ st1 { v1.4s }, [x1], x15
+ st1 { v2.4s, v3.4s }, [x1], x15
+ st1 { v3.4s, v4.4s, v5.4s }, [x1], x15
+ st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
+
+ st1 { v1.1d }, [x1], x15
+ st1 { v2.1d, v3.1d }, [x1], x15
+ st1 { v3.1d, v4.1d, v5.1d }, [x1], x15
+ st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], x15
+
+ st1 { v1.2d }, [x1], x15
+ st1 { v2.2d, v3.2d }, [x1], x15
+ st1 { v3.2d, v4.2d, v5.2d }, [x1], x15
+ st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
+
+ ld1 { v1.8b }, [x1], #8
+ ld1 { v2.8b, v3.8b }, [x1], #16
+ ld1 { v3.8b, v4.8b, v5.8b }, [x1], #24
+ ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
+
+ ld1 { v1.16b }, [x1], #16
+ ld1 { v2.16b, v3.16b }, [x1], #32
+ ld1 { v3.16b, v4.16b, v5.16b }, [x1], #48
+ ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
+
+ ld1 { v1.4h }, [x1], #8
+ ld1 { v2.4h, v3.4h }, [x1], #16
+ ld1 { v3.4h, v4.4h, v5.4h }, [x1], #24
+ ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
+
+ ld1 { v1.8h }, [x1], #16
+ ld1 { v2.8h, v3.8h }, [x1], #32
+ ld1 { v3.8h, v4.8h, v5.8h }, [x1], #48
+ ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
+
+ ld1 { v1.2s }, [x1], #8
+ ld1 { v2.2s, v3.2s }, [x1], #16
+ ld1 { v3.2s, v4.2s, v5.2s }, [x1], #24
+ ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
+
+ ld1 { v1.4s }, [x1], #16
+ ld1 { v2.4s, v3.4s }, [x1], #32
+ ld1 { v3.4s, v4.4s, v5.4s }, [x1], #48
+ ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
+
+ ld1 { v1.1d }, [x1], #8
+ ld1 { v2.1d, v3.1d }, [x1], #16
+ ld1 { v3.1d, v4.1d, v5.1d }, [x1], #24
+ ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32
+
+ ld1 { v1.2d }, [x1], #16
+ ld1 { v2.2d, v3.2d }, [x1], #32
+ ld1 { v3.2d, v4.2d, v5.2d }, [x1], #48
+ ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
+
+ st1 { v1.8b }, [x1], #8
+ st1 { v2.8b, v3.8b }, [x1], #16
+ st1 { v3.8b, v4.8b, v5.8b }, [x1], #24
+ st1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
+
+ st1 { v1.16b }, [x1], #16
+ st1 { v2.16b, v3.16b }, [x1], #32
+ st1 { v3.16b, v4.16b, v5.16b }, [x1], #48
+ st1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
+
+ st1 { v1.4h }, [x1], #8
+ st1 { v2.4h, v3.4h }, [x1], #16
+ st1 { v3.4h, v4.4h, v5.4h }, [x1], #24
+ st1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
+
+ st1 { v1.8h }, [x1], #16
+ st1 { v2.8h, v3.8h }, [x1], #32
+ st1 { v3.8h, v4.8h, v5.8h }, [x1], #48
+ st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
+
+ st1 { v1.2s }, [x1], #8
+ st1 { v2.2s, v3.2s }, [x1], #16
+ st1 { v3.2s, v4.2s, v5.2s }, [x1], #24
+ st1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
+
+ st1 { v1.4s }, [x1], #16
+ st1 { v2.4s, v3.4s }, [x1], #32
+ st1 { v3.4s, v4.4s, v5.4s }, [x1], #48
+ st1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
+
+ st1 { v1.1d }, [x1], #8
+ st1 { v2.1d, v3.1d }, [x1], #16
+ st1 { v3.1d, v4.1d, v5.1d }, [x1], #24
+ st1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x1], #32
+
+ st1 { v1.2d }, [x1], #16
+ st1 { v2.2d, v3.2d }, [x1], #32
+ st1 { v3.2d, v4.2d, v5.2d }, [x1], #48
+ st1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
+
+ ld2 { v2.8b, v3.8b }, [x1], x15
+ ld2 { v2.16b, v3.16b }, [x1], x15
+ ld2 { v2.4h, v3.4h }, [x1], x15
+ ld2 { v2.8h, v3.8h }, [x1], x15
+ ld2 { v2.2s, v3.2s }, [x1], x15
+ ld2 { v2.4s, v3.4s }, [x1], x15
+ ld2 { v2.2d, v3.2d }, [x1], x15
+
+ st2 { v2.8b, v3.8b }, [x1], x15
+ st2 { v2.16b, v3.16b }, [x1], x15
+ st2 { v2.4h, v3.4h }, [x1], x15
+ st2 { v2.8h, v3.8h }, [x1], x15
+ st2 { v2.2s, v3.2s }, [x1], x15
+ st2 { v2.4s, v3.4s }, [x1], x15
+ st2 { v2.2d, v3.2d }, [x1], x15
+
+ ld2 { v2.8b, v3.8b }, [x1], #16
+ ld2 { v2.16b, v3.16b }, [x1], #32
+ ld2 { v2.4h, v3.4h }, [x1], #16
+ ld2 { v2.8h, v3.8h }, [x1], #32
+ ld2 { v2.2s, v3.2s }, [x1], #16
+ ld2 { v2.4s, v3.4s }, [x1], #32
+ ld2 { v2.2d, v3.2d }, [x1], #32
+
+ st2 { v2.8b, v3.8b }, [x1], #16
+ st2 { v2.16b, v3.16b }, [x1], #32
+ st2 { v2.4h, v3.4h }, [x1], #16
+ st2 { v2.8h, v3.8h }, [x1], #32
+ st2 { v2.2s, v3.2s }, [x1], #16
+ st2 { v2.4s, v3.4s }, [x1], #32
+ st2 { v2.2d, v3.2d }, [x1], #32
+
+ ld3 { v3.8b, v4.8b, v5.8b }, [x1], x15
+ ld3 { v3.16b, v4.16b, v5.16b }, [x1], x15
+ ld3 { v3.4h, v4.4h, v5.4h }, [x1], x15
+ ld3 { v3.8h, v4.8h, v5.8h }, [x1], x15
+ ld3 { v3.2s, v4.2s, v5.2s }, [x1], x15
+ ld3 { v3.4s, v4.4s, v5.4s }, [x1], x15
+ ld3 { v3.2d, v4.2d, v5.2d }, [x1], x15
+
+ st3 { v3.8b, v4.8b, v5.8b }, [x1], x15
+ st3 { v3.16b, v4.16b, v5.16b }, [x1], x15
+ st3 { v3.4h, v4.4h, v5.4h }, [x1], x15
+ st3 { v3.8h, v4.8h, v5.8h }, [x1], x15
+ st3 { v3.2s, v4.2s, v5.2s }, [x1], x15
+ st3 { v3.4s, v4.4s, v5.4s }, [x1], x15
+ st3 { v3.2d, v4.2d, v5.2d }, [x1], x15
+ ld3 { v3.8b, v4.8b, v5.8b }, [x1], #24
+
+ ld3 { v3.16b, v4.16b, v5.16b }, [x1], #48
+ ld3 { v3.4h, v4.4h, v5.4h }, [x1], #24
+ ld3 { v3.8h, v4.8h, v5.8h }, [x1], #48
+ ld3 { v3.2s, v4.2s, v5.2s }, [x1], #24
+ ld3 { v3.4s, v4.4s, v5.4s }, [x1], #48
+ ld3 { v3.2d, v4.2d, v5.2d }, [x1], #48
+
+ st3 { v3.8b, v4.8b, v5.8b }, [x1], #24
+ st3 { v3.16b, v4.16b, v5.16b }, [x1], #48
+ st3 { v3.4h, v4.4h, v5.4h }, [x1], #24
+ st3 { v3.8h, v4.8h, v5.8h }, [x1], #48
+ st3 { v3.2s, v4.2s, v5.2s }, [x1], #24
+ st3 { v3.4s, v4.4s, v5.4s }, [x1], #48
+ st3 { v3.2d, v4.2d, v5.2d }, [x1], #48
+
+ ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
+ ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
+ ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
+ ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
+ ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
+ ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
+ ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
+
+ st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], x15
+ st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], x15
+ st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], x15
+ st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], x15
+ st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], x15
+ st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], x15
+ st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], x15
+
+ ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
+ ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
+ ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
+ ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
+ ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
+ ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
+ ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
+
+ st4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x1], #32
+ st4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x1], #64
+ st4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x1], #32
+ st4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x1], #64
+ st4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x1], #32
+ st4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x1], #64
+ st4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x1], #64
+
+
+ ld1r { v12.8b }, [x2]
+ ld1r { v12.8b }, [x2], x3
+ ld1r { v12.16b }, [x2]
+ ld1r { v12.16b }, [x2], x3
+ ld1r { v12.4h }, [x2]
+ ld1r { v12.4h }, [x2], x3
+ ld1r { v12.8h }, [x2]
+ ld1r { v12.8h }, [x2], x3
+ ld1r { v12.2s }, [x2]
+ ld1r { v12.2s }, [x2], x3
+ ld1r { v12.4s }, [x2]
+ ld1r { v12.4s }, [x2], x3
+ ld1r { v12.1d }, [x2]
+ ld1r { v12.1d }, [x2], x3
+ ld1r { v12.2d }, [x2]
+ ld1r { v12.2d }, [x2], x3
+
+ ld1r { v12.8b }, [x2], #1
+ ld1r { v12.16b }, [x2], #1
+ ld1r { v12.4h }, [x2], #2
+ ld1r { v12.8h }, [x2], #2
+ ld1r { v12.2s }, [x2], #4
+ ld1r { v12.4s }, [x2], #4
+ ld1r { v12.1d }, [x2], #8
+ ld1r { v12.2d }, [x2], #8
+ ld2r { v3.8b, v4.8b }, [x2]
+ ld2r { v3.8b, v4.8b }, [x2], x3
+ ld2r { v3.16b, v4.16b }, [x2]
+ ld2r { v3.16b, v4.16b }, [x2], x3
+ ld2r { v3.4h, v4.4h }, [x2]
+ ld2r { v3.4h, v4.4h }, [x2], x3
+ ld2r { v3.8h, v4.8h }, [x2]
+ ld2r { v3.8h, v4.8h }, [x2], x3
+ ld2r { v3.2s, v4.2s }, [x2]
+ ld2r { v3.2s, v4.2s }, [x2], x3
+ ld2r { v3.4s, v4.4s }, [x2]
+ ld2r { v3.4s, v4.4s }, [x2], x3
+ ld2r { v3.1d, v4.1d }, [x2]
+ ld2r { v3.1d, v4.1d }, [x2], x3
+ ld2r { v3.2d, v4.2d }, [x2]
+ ld2r { v3.2d, v4.2d }, [x2], x3
+
+ ld2r { v3.8b, v4.8b }, [x2], #2
+ ld2r { v3.16b, v4.16b }, [x2], #2
+ ld2r { v3.4h, v4.4h }, [x2], #4
+ ld2r { v3.8h, v4.8h }, [x2], #4
+ ld2r { v3.2s, v4.2s }, [x2], #8
+ ld2r { v3.4s, v4.4s }, [x2], #8
+ ld2r { v3.1d, v4.1d }, [x2], #16
+ ld2r { v3.2d, v4.2d }, [x2], #16
+
+ ld3r { v2.8b, v3.8b, v4.8b }, [x2]
+ ld3r { v2.8b, v3.8b, v4.8b }, [x2], x3
+ ld3r { v2.16b, v3.16b, v4.16b }, [x2]
+ ld3r { v2.16b, v3.16b, v4.16b }, [x2], x3
+ ld3r { v2.4h, v3.4h, v4.4h }, [x2]
+ ld3r { v2.4h, v3.4h, v4.4h }, [x2], x3
+ ld3r { v2.8h, v3.8h, v4.8h }, [x2]
+ ld3r { v2.8h, v3.8h, v4.8h }, [x2], x3
+ ld3r { v2.2s, v3.2s, v4.2s }, [x2]
+ ld3r { v2.2s, v3.2s, v4.2s }, [x2], x3
+ ld3r { v2.4s, v3.4s, v4.4s }, [x2]
+ ld3r { v2.4s, v3.4s, v4.4s }, [x2], x3
+ ld3r { v2.1d, v3.1d, v4.1d }, [x2]
+ ld3r { v2.1d, v3.1d, v4.1d }, [x2], x3
+ ld3r { v2.2d, v3.2d, v4.2d }, [x2]
+ ld3r { v2.2d, v3.2d, v4.2d }, [x2], x3
+
+ ld3r { v2.8b, v3.8b, v4.8b }, [x2], #3
+ ld3r { v2.16b, v3.16b, v4.16b }, [x2], #3
+ ld3r { v2.4h, v3.4h, v4.4h }, [x2], #6
+ ld3r { v2.8h, v3.8h, v4.8h }, [x2], #6
+ ld3r { v2.2s, v3.2s, v4.2s }, [x2], #12
+ ld3r { v2.4s, v3.4s, v4.4s }, [x2], #12
+ ld3r { v2.1d, v3.1d, v4.1d }, [x2], #24
+ ld3r { v2.2d, v3.2d, v4.2d }, [x2], #24
+
+ ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2]
+ ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], x3
+ ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2]
+ ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], x3
+ ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2]
+ ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], x3
+ ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2]
+ ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], x3
+ ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2]
+ ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], x3
+ ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2]
+ ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], x3
+ ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2]
+ ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], x3
+ ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2]
+ ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], x3
+
+ ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], #4
+ ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], #4
+ ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], #8
+ ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], #8
+ ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], #16
+ ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], #16
+ ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], #32
+ ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], #32
+
+ ld1 { v6.b }[13], [x3]
+ ld1 { v6.h }[2], [x3]
+ ld1 { v6.s }[2], [x3]
+ ld1 { v6.d }[1], [x3]
+ ld1 { v6.b }[13], [x3], x5
+ ld1 { v6.h }[2], [x3], x5
+ ld1 { v6.s }[2], [x3], x5
+ ld1 { v6.d }[1], [x3], x5
+ ld1 { v6.b }[13], [x3], #1
+ ld1 { v6.h }[2], [x3], #2
+ ld1 { v6.s }[2], [x3], #4
+ ld1 { v6.d }[1], [x3], #8
+
+ ld2 { v5.b, v6.b }[13], [x3]
+ ld2 { v5.h, v6.h }[2], [x3]
+ ld2 { v5.s, v6.s }[2], [x3]
+ ld2 { v5.d, v6.d }[1], [x3]
+ ld2 { v5.b, v6.b }[13], [x3], x5
+ ld2 { v5.h, v6.h }[2], [x3], x5
+ ld2 { v5.s, v6.s }[2], [x3], x5
+ ld2 { v5.d, v6.d }[1], [x3], x5
+ ld2 { v5.b, v6.b }[13], [x3], #2
+ ld2 { v5.h, v6.h }[2], [x3], #4
+ ld2 { v5.s, v6.s }[2], [x3], #8
+ ld2 { v5.d, v6.d }[1], [x3], #16
+
+ ld3 { v7.b, v8.b, v9.b }[13], [x3]
+ ld3 { v7.h, v8.h, v9.h }[2], [x3]
+ ld3 { v7.s, v8.s, v9.s }[2], [x3]
+ ld3 { v7.d, v8.d, v9.d }[1], [x3]
+ ld3 { v7.b, v8.b, v9.b }[13], [x3], x5
+ ld3 { v7.h, v8.h, v9.h }[2], [x3], x5
+ ld3 { v7.s, v8.s, v9.s }[2], [x3], x5
+ ld3 { v7.d, v8.d, v9.d }[1], [x3], x5
+ ld3 { v7.b, v8.b, v9.b }[13], [x3], #3
+ ld3 { v7.h, v8.h, v9.h }[2], [x3], #6
+ ld3 { v7.s, v8.s, v9.s }[2], [x3], #12
+ ld3 { v7.d, v8.d, v9.d }[1], [x3], #24
+
+ ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
+ ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
+ ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
+ ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
+ ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
+ ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
+ ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
+ ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
+ ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
+ ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
+ ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
+ ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
+
+ st1 { v6.b }[13], [x3]
+ st1 { v6.h }[2], [x3]
+ st1 { v6.s }[2], [x3]
+ st1 { v6.d }[1], [x3]
+ st1 { v6.b }[13], [x3], x5
+ st1 { v6.h }[2], [x3], x5
+ st1 { v6.s }[2], [x3], x5
+ st1 { v6.d }[1], [x3], x5
+ st1 { v6.b }[13], [x3], #1
+ st1 { v6.h }[2], [x3], #2
+ st1 { v6.s }[2], [x3], #4
+ st1 { v6.d }[1], [x3], #8
+
+
+ st2 { v5.b, v6.b }[13], [x3]
+ st2 { v5.h, v6.h }[2], [x3]
+ st2 { v5.s, v6.s }[2], [x3]
+ st2 { v5.d, v6.d }[1], [x3]
+ st2 { v5.b, v6.b }[13], [x3], x5
+ st2 { v5.h, v6.h }[2], [x3], x5
+ st2 { v5.s, v6.s }[2], [x3], x5
+ st2 { v5.d, v6.d }[1], [x3], x5
+ st2 { v5.b, v6.b }[13], [x3], #2
+ st2 { v5.h, v6.h }[2], [x3], #4
+ st2 { v5.s, v6.s }[2], [x3], #8
+ st2 { v5.d, v6.d }[1], [x3], #16
+
+ st3 { v7.b, v8.b, v9.b }[13], [x3]
+ st3 { v7.h, v8.h, v9.h }[2], [x3]
+ st3 { v7.s, v8.s, v9.s }[2], [x3]
+ st3 { v7.d, v8.d, v9.d }[1], [x3]
+ st3 { v7.b, v8.b, v9.b }[13], [x3], x5
+ st3 { v7.h, v8.h, v9.h }[2], [x3], x5
+ st3 { v7.s, v8.s, v9.s }[2], [x3], x5
+ st3 { v7.d, v8.d, v9.d }[1], [x3], x5
+ st3 { v7.b, v8.b, v9.b }[13], [x3], #3
+ st3 { v7.h, v8.h, v9.h }[2], [x3], #6
+ st3 { v7.s, v8.s, v9.s }[2], [x3], #12
+ st3 { v7.d, v8.d, v9.d }[1], [x3], #24
+
+ st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
+ st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
+ st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
+ st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
+ st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
+ st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
+ st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
+ st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
+ st4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
+ st4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
+ st4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
+ st4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
+
+; CHECK: ld1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x0c]
+; CHECK: ld1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x0c]
+; CHECK: ld1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x0c]
+; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x0c]
+; CHECK: ld1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x40,0x4c]
+; CHECK: ld1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x40,0x4c]
+; CHECK: ld1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x40,0x4c]
+; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x40,0x4c]
+; CHECK: ld1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x0c]
+; CHECK: ld1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x0c]
+; CHECK: ld1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x0c]
+; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x0c]
+; CHECK: ld1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x40,0x4c]
+; CHECK: ld1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x40,0x4c]
+; CHECK: ld1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x40,0x4c]
+; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x40,0x4c]
+; CHECK: ld1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x0c]
+; CHECK: ld1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x0c]
+; CHECK: ld1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x0c]
+; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x0c]
+; CHECK: ld1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x40,0x4c]
+; CHECK: ld1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x40,0x4c]
+; CHECK: ld1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x40,0x4c]
+; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x40,0x4c]
+; CHECK: ld1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x0c]
+; CHECK: ld1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x0c]
+; CHECK: ld1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x0c]
+; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x0c]
+; CHECK: ld1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x40,0x4c]
+; CHECK: ld1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x40,0x4c]
+; CHECK: ld1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x40,0x4c]
+; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x40,0x4c]
+; CHECK: st1.8b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x0c]
+; CHECK: st1.8b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x0c]
+; CHECK: st1.8b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x0c]
+; CHECK: st1.8b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x0c]
+; CHECK: st1.16b { v1 }, [x1] ; encoding: [0x21,0x70,0x00,0x4c]
+; CHECK: st1.16b { v2, v3 }, [x1] ; encoding: [0x22,0xa0,0x00,0x4c]
+; CHECK: st1.16b { v3, v4, v5 }, [x1] ; encoding: [0x23,0x60,0x00,0x4c]
+; CHECK: st1.16b { v4, v5, v6, v7 }, [x1] ; encoding: [0x24,0x20,0x00,0x4c]
+; CHECK: st1.4h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x0c]
+; CHECK: st1.4h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x0c]
+; CHECK: st1.4h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x0c]
+; CHECK: st1.4h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x0c]
+; CHECK: st1.8h { v1 }, [x1] ; encoding: [0x21,0x74,0x00,0x4c]
+; CHECK: st1.8h { v2, v3 }, [x1] ; encoding: [0x22,0xa4,0x00,0x4c]
+; CHECK: st1.8h { v3, v4, v5 }, [x1] ; encoding: [0x23,0x64,0x00,0x4c]
+; CHECK: st1.8h { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x24,0x00,0x4c]
+; CHECK: st1.2s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x0c]
+; CHECK: st1.2s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x0c]
+; CHECK: st1.2s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x0c]
+; CHECK: st1.2s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x0c]
+; CHECK: st1.4s { v1 }, [x1] ; encoding: [0x21,0x78,0x00,0x4c]
+; CHECK: st1.4s { v2, v3 }, [x1] ; encoding: [0x22,0xa8,0x00,0x4c]
+; CHECK: st1.4s { v3, v4, v5 }, [x1] ; encoding: [0x23,0x68,0x00,0x4c]
+; CHECK: st1.4s { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x28,0x00,0x4c]
+; CHECK: st1.1d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x0c]
+; CHECK: st1.1d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x0c]
+; CHECK: st1.1d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x0c]
+; CHECK: st1.1d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x0c]
+; CHECK: st1.2d { v1 }, [x1] ; encoding: [0x21,0x7c,0x00,0x4c]
+; CHECK: st1.2d { v2, v3 }, [x1] ; encoding: [0x22,0xac,0x00,0x4c]
+; CHECK: st1.2d { v3, v4, v5 }, [x1] ; encoding: [0x23,0x6c,0x00,0x4c]
+; CHECK: st1.2d { v7, v8, v9, v10 }, [x1] ; encoding: [0x27,0x2c,0x00,0x4c]
+; CHECK: ld2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x0c]
+; CHECK: ld2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x40,0x4c]
+; CHECK: ld2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x0c]
+; CHECK: ld2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x40,0x4c]
+; CHECK: ld2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x0c]
+; CHECK: ld2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x40,0x4c]
+; CHECK: ld2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x40,0x4c]
+; CHECK: st2.8b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x0c]
+; CHECK: st2.16b { v3, v4 }, [x19] ; encoding: [0x63,0x82,0x00,0x4c]
+; CHECK: st2.4h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x0c]
+; CHECK: st2.8h { v3, v4 }, [x19] ; encoding: [0x63,0x86,0x00,0x4c]
+; CHECK: st2.2s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x0c]
+; CHECK: st2.4s { v3, v4 }, [x19] ; encoding: [0x63,0x8a,0x00,0x4c]
+; CHECK: st2.2d { v3, v4 }, [x19] ; encoding: [0x63,0x8e,0x00,0x4c]
+; CHECK: ld3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x0c]
+; CHECK: ld3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x40,0x4c]
+; CHECK: ld3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x0c]
+; CHECK: ld3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x40,0x4c]
+; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
+; CHECK: ld3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x4c]
+; CHECK: ld3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x40,0x4c]
+; CHECK: st3.8b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x0c]
+; CHECK: st3.16b { v2, v3, v4 }, [x19] ; encoding: [0x62,0x42,0x00,0x4c]
+; CHECK: st3.4h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x0c]
+; CHECK: st3.8h { v2, v3, v4 }, [x19] ; encoding: [0x62,0x46,0x00,0x4c]
+; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
+; CHECK: st3.4s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x4c]
+; CHECK: st3.2d { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4e,0x00,0x4c]
+; CHECK: ld4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x0c]
+; CHECK: ld4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x40,0x4c]
+; CHECK: ld4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x0c]
+; CHECK: ld4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x40,0x4c]
+; CHECK: ld4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x0c]
+; CHECK: ld4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x40,0x4c]
+; CHECK: ld4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x40,0x4c]
+; CHECK: st4.8b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x0c]
+; CHECK: st4.16b { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x02,0x00,0x4c]
+; CHECK: st4.4h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x0c]
+; CHECK: st4.8h { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x06,0x00,0x4c]
+; CHECK: st4.2s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x0c]
+; CHECK: st4.4s { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0a,0x00,0x4c]
+; CHECK: st4.2d { v2, v3, v4, v5 }, [x19] ; encoding: [0x62,0x0e,0x00,0x4c]
+; CHECK: ld1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x0c]
+; CHECK: ld1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x0c]
+; CHECK: ld1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x0c]
+; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x0c]
+; CHECK: ld1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0xcf,0x4c]
+; CHECK: ld1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0xcf,0x4c]
+; CHECK: ld1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0xcf,0x4c]
+; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0xcf,0x4c]
+; CHECK: ld1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x0c]
+; CHECK: ld1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x0c]
+; CHECK: ld1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x0c]
+; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x0c]
+; CHECK: ld1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0xcf,0x4c]
+; CHECK: ld1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0xcf,0x4c]
+; CHECK: ld1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0xcf,0x4c]
+; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0xcf,0x4c]
+; CHECK: ld1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x0c]
+; CHECK: ld1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x0c]
+; CHECK: ld1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x0c]
+; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x0c]
+; CHECK: ld1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0xcf,0x4c]
+; CHECK: ld1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0xcf,0x4c]
+; CHECK: ld1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0xcf,0x4c]
+; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0xcf,0x4c]
+; CHECK: ld1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x0c]
+; CHECK: ld1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x0c]
+; CHECK: ld1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x0c]
+; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x0c]
+; CHECK: ld1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0xcf,0x4c]
+; CHECK: ld1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0xcf,0x4c]
+; CHECK: ld1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0xcf,0x4c]
+; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0xcf,0x4c]
+; CHECK: st1.8b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x0c]
+; CHECK: st1.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x0c]
+; CHECK: st1.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x0c]
+; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x0c]
+; CHECK: st1.16b { v1 }, [x1], x15 ; encoding: [0x21,0x70,0x8f,0x4c]
+; CHECK: st1.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa0,0x8f,0x4c]
+; CHECK: st1.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x60,0x8f,0x4c]
+; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x20,0x8f,0x4c]
+; CHECK: st1.4h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x0c]
+; CHECK: st1.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x0c]
+; CHECK: st1.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x0c]
+; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x0c]
+; CHECK: st1.8h { v1 }, [x1], x15 ; encoding: [0x21,0x74,0x8f,0x4c]
+; CHECK: st1.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa4,0x8f,0x4c]
+; CHECK: st1.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x64,0x8f,0x4c]
+; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x24,0x8f,0x4c]
+; CHECK: st1.2s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x0c]
+; CHECK: st1.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x0c]
+; CHECK: st1.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x0c]
+; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x0c]
+; CHECK: st1.4s { v1 }, [x1], x15 ; encoding: [0x21,0x78,0x8f,0x4c]
+; CHECK: st1.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0xa8,0x8f,0x4c]
+; CHECK: st1.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x68,0x8f,0x4c]
+; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x28,0x8f,0x4c]
+; CHECK: st1.1d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x0c]
+; CHECK: st1.1d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x0c]
+; CHECK: st1.1d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x0c]
+; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x0c]
+; CHECK: st1.2d { v1 }, [x1], x15 ; encoding: [0x21,0x7c,0x8f,0x4c]
+; CHECK: st1.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0xac,0x8f,0x4c]
+; CHECK: st1.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x6c,0x8f,0x4c]
+; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x2c,0x8f,0x4c]
+; CHECK: ld1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0xdf,0x0c]
+; CHECK: ld1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0xdf,0x0c]
+; CHECK: ld1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0xdf,0x0c]
+; CHECK: ld1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0xdf,0x0c]
+; CHECK: ld1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0xdf,0x4c]
+; CHECK: ld1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0xdf,0x4c]
+; CHECK: ld1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0xdf,0x4c]
+; CHECK: ld1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0xdf,0x4c]
+; CHECK: ld1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0xdf,0x0c]
+; CHECK: ld1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0xdf,0x0c]
+; CHECK: ld1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0xdf,0x0c]
+; CHECK: ld1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0xdf,0x0c]
+; CHECK: ld1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0xdf,0x4c]
+; CHECK: ld1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0xdf,0x4c]
+; CHECK: ld1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0xdf,0x4c]
+; CHECK: ld1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0xdf,0x4c]
+; CHECK: ld1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0xdf,0x0c]
+; CHECK: ld1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0xdf,0x0c]
+; CHECK: ld1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0xdf,0x0c]
+; CHECK: ld1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0xdf,0x0c]
+; CHECK: ld1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0xdf,0x4c]
+; CHECK: ld1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0xdf,0x4c]
+; CHECK: ld1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0xdf,0x4c]
+; CHECK: ld1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0xdf,0x4c]
+; CHECK: ld1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0xdf,0x0c]
+; CHECK: ld1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0xdf,0x0c]
+; CHECK: ld1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0xdf,0x0c]
+; CHECK: ld1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0xdf,0x0c]
+; CHECK: ld1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0xdf,0x4c]
+; CHECK: ld1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0xdf,0x4c]
+; CHECK: ld1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0xdf,0x4c]
+; CHECK: ld1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0xdf,0x4c]
+; CHECK: st1.8b { v1 }, [x1], #8 ; encoding: [0x21,0x70,0x9f,0x0c]
+; CHECK: st1.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa0,0x9f,0x0c]
+; CHECK: st1.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x60,0x9f,0x0c]
+; CHECK: st1.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x20,0x9f,0x0c]
+; CHECK: st1.16b { v1 }, [x1], #16 ; encoding: [0x21,0x70,0x9f,0x4c]
+; CHECK: st1.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa0,0x9f,0x4c]
+; CHECK: st1.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x60,0x9f,0x4c]
+; CHECK: st1.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x20,0x9f,0x4c]
+; CHECK: st1.4h { v1 }, [x1], #8 ; encoding: [0x21,0x74,0x9f,0x0c]
+; CHECK: st1.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa4,0x9f,0x0c]
+; CHECK: st1.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x64,0x9f,0x0c]
+; CHECK: st1.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x24,0x9f,0x0c]
+; CHECK: st1.8h { v1 }, [x1], #16 ; encoding: [0x21,0x74,0x9f,0x4c]
+; CHECK: st1.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa4,0x9f,0x4c]
+; CHECK: st1.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x64,0x9f,0x4c]
+; CHECK: st1.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x24,0x9f,0x4c]
+; CHECK: st1.2s { v1 }, [x1], #8 ; encoding: [0x21,0x78,0x9f,0x0c]
+; CHECK: st1.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0xa8,0x9f,0x0c]
+; CHECK: st1.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x68,0x9f,0x0c]
+; CHECK: st1.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x28,0x9f,0x0c]
+; CHECK: st1.4s { v1 }, [x1], #16 ; encoding: [0x21,0x78,0x9f,0x4c]
+; CHECK: st1.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0xa8,0x9f,0x4c]
+; CHECK: st1.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x68,0x9f,0x4c]
+; CHECK: st1.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x28,0x9f,0x4c]
+; CHECK: st1.1d { v1 }, [x1], #8 ; encoding: [0x21,0x7c,0x9f,0x0c]
+; CHECK: st1.1d { v2, v3 }, [x1], #16 ; encoding: [0x22,0xac,0x9f,0x0c]
+; CHECK: st1.1d { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x6c,0x9f,0x0c]
+; CHECK: st1.1d { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x2c,0x9f,0x0c]
+; CHECK: st1.2d { v1 }, [x1], #16 ; encoding: [0x21,0x7c,0x9f,0x4c]
+; CHECK: st1.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0xac,0x9f,0x4c]
+; CHECK: st1.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x6c,0x9f,0x4c]
+; CHECK: st1.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x2c,0x9f,0x4c]
+; CHECK: ld2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x0c]
+; CHECK: ld2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0xcf,0x4c]
+; CHECK: ld2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x0c]
+; CHECK: ld2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0xcf,0x4c]
+; CHECK: ld2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x0c]
+; CHECK: ld2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0xcf,0x4c]
+; CHECK: ld2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0xcf,0x4c]
+; CHECK: st2.8b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x0c]
+; CHECK: st2.16b { v2, v3 }, [x1], x15 ; encoding: [0x22,0x80,0x8f,0x4c]
+; CHECK: st2.4h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x0c]
+; CHECK: st2.8h { v2, v3 }, [x1], x15 ; encoding: [0x22,0x84,0x8f,0x4c]
+; CHECK: st2.2s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x0c]
+; CHECK: st2.4s { v2, v3 }, [x1], x15 ; encoding: [0x22,0x88,0x8f,0x4c]
+; CHECK: st2.2d { v2, v3 }, [x1], x15 ; encoding: [0x22,0x8c,0x8f,0x4c]
+; CHECK: ld2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0xdf,0x0c]
+; CHECK: ld2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0xdf,0x4c]
+; CHECK: ld2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0xdf,0x0c]
+; CHECK: ld2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0xdf,0x4c]
+; CHECK: ld2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0xdf,0x0c]
+; CHECK: ld2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0xdf,0x4c]
+; CHECK: ld2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0xdf,0x4c]
+; CHECK: st2.8b { v2, v3 }, [x1], #16 ; encoding: [0x22,0x80,0x9f,0x0c]
+; CHECK: st2.16b { v2, v3 }, [x1], #32 ; encoding: [0x22,0x80,0x9f,0x4c]
+; CHECK: st2.4h { v2, v3 }, [x1], #16 ; encoding: [0x22,0x84,0x9f,0x0c]
+; CHECK: st2.8h { v2, v3 }, [x1], #32 ; encoding: [0x22,0x84,0x9f,0x4c]
+; CHECK: st2.2s { v2, v3 }, [x1], #16 ; encoding: [0x22,0x88,0x9f,0x0c]
+; CHECK: st2.4s { v2, v3 }, [x1], #32 ; encoding: [0x22,0x88,0x9f,0x4c]
+; CHECK: st2.2d { v2, v3 }, [x1], #32 ; encoding: [0x22,0x8c,0x9f,0x4c]
+; CHECK: ld3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x0c]
+; CHECK: ld3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0xcf,0x4c]
+; CHECK: ld3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x0c]
+; CHECK: ld3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0xcf,0x4c]
+; CHECK: ld3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x0c]
+; CHECK: ld3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0xcf,0x4c]
+; CHECK: ld3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0xcf,0x4c]
+; CHECK: st3.8b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x0c]
+; CHECK: st3.16b { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x40,0x8f,0x4c]
+; CHECK: st3.4h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x0c]
+; CHECK: st3.8h { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x44,0x8f,0x4c]
+; CHECK: st3.2s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x0c]
+; CHECK: st3.4s { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x48,0x8f,0x4c]
+; CHECK: st3.2d { v3, v4, v5 }, [x1], x15 ; encoding: [0x23,0x4c,0x8f,0x4c]
+; CHECK: ld3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0xdf,0x0c]
+; CHECK: ld3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0xdf,0x4c]
+; CHECK: ld3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0xdf,0x0c]
+; CHECK: ld3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0xdf,0x4c]
+; CHECK: ld3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0xdf,0x0c]
+; CHECK: ld3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0xdf,0x4c]
+; CHECK: ld3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0xdf,0x4c]
+; CHECK: st3.8b { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x40,0x9f,0x0c]
+; CHECK: st3.16b { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x40,0x9f,0x4c]
+; CHECK: st3.4h { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x44,0x9f,0x0c]
+; CHECK: st3.8h { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x44,0x9f,0x4c]
+; CHECK: st3.2s { v3, v4, v5 }, [x1], #24 ; encoding: [0x23,0x48,0x9f,0x0c]
+; CHECK: st3.4s { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x48,0x9f,0x4c]
+; CHECK: st3.2d { v3, v4, v5 }, [x1], #48 ; encoding: [0x23,0x4c,0x9f,0x4c]
+; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x0c]
+; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0xcf,0x4c]
+; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x0c]
+; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0xcf,0x4c]
+; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x0c]
+; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0xcf,0x4c]
+; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0xcf,0x4c]
+; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x0c]
+; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], x15 ; encoding: [0x24,0x00,0x8f,0x4c]
+; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x0c]
+; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x04,0x8f,0x4c]
+; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x0c]
+; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x08,0x8f,0x4c]
+; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], x15 ; encoding: [0x27,0x0c,0x8f,0x4c]
+; CHECK: ld4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0xdf,0x0c]
+; CHECK: ld4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0xdf,0x4c]
+; CHECK: ld4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0xdf,0x0c]
+; CHECK: ld4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0xdf,0x4c]
+; CHECK: ld4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0xdf,0x0c]
+; CHECK: ld4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0xdf,0x4c]
+; CHECK: ld4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0xdf,0x4c]
+; CHECK: st4.8b { v4, v5, v6, v7 }, [x1], #32 ; encoding: [0x24,0x00,0x9f,0x0c]
+; CHECK: st4.16b { v4, v5, v6, v7 }, [x1], #64 ; encoding: [0x24,0x00,0x9f,0x4c]
+; CHECK: st4.4h { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x04,0x9f,0x0c]
+; CHECK: st4.8h { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x04,0x9f,0x4c]
+; CHECK: st4.2s { v7, v8, v9, v10 }, [x1], #32 ; encoding: [0x27,0x08,0x9f,0x0c]
+; CHECK: st4.4s { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x08,0x9f,0x4c]
+; CHECK: st4.2d { v7, v8, v9, v10 }, [x1], #64 ; encoding: [0x27,0x0c,0x9f,0x4c]
+; CHECK: ld1r.8b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x0d]
+; CHECK: ld1r.8b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x0d]
+; CHECK: ld1r.16b { v12 }, [x2] ; encoding: [0x4c,0xc0,0x40,0x4d]
+; CHECK: ld1r.16b { v12 }, [x2], x3 ; encoding: [0x4c,0xc0,0xc3,0x4d]
+; CHECK: ld1r.4h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x0d]
+; CHECK: ld1r.4h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x0d]
+; CHECK: ld1r.8h { v12 }, [x2] ; encoding: [0x4c,0xc4,0x40,0x4d]
+; CHECK: ld1r.8h { v12 }, [x2], x3 ; encoding: [0x4c,0xc4,0xc3,0x4d]
+; CHECK: ld1r.2s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x0d]
+; CHECK: ld1r.2s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x0d]
+; CHECK: ld1r.4s { v12 }, [x2] ; encoding: [0x4c,0xc8,0x40,0x4d]
+; CHECK: ld1r.4s { v12 }, [x2], x3 ; encoding: [0x4c,0xc8,0xc3,0x4d]
+; CHECK: ld1r.1d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x0d]
+; CHECK: ld1r.1d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x0d]
+; CHECK: ld1r.2d { v12 }, [x2] ; encoding: [0x4c,0xcc,0x40,0x4d]
+; CHECK: ld1r.2d { v12 }, [x2], x3 ; encoding: [0x4c,0xcc,0xc3,0x4d]
+; CHECK: ld1r.8b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x0d]
+; CHECK: ld1r.16b { v12 }, [x2], #1 ; encoding: [0x4c,0xc0,0xdf,0x4d]
+; CHECK: ld1r.4h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x0d]
+; CHECK: ld1r.8h { v12 }, [x2], #2 ; encoding: [0x4c,0xc4,0xdf,0x4d]
+; CHECK: ld1r.2s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x0d]
+; CHECK: ld1r.4s { v12 }, [x2], #4 ; encoding: [0x4c,0xc8,0xdf,0x4d]
+; CHECK: ld1r.1d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x0d]
+; CHECK: ld1r.2d { v12 }, [x2], #8 ; encoding: [0x4c,0xcc,0xdf,0x4d]
+; CHECK: ld2r.8b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x0d]
+; CHECK: ld2r.8b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x0d]
+; CHECK: ld2r.16b { v3, v4 }, [x2] ; encoding: [0x43,0xc0,0x60,0x4d]
+; CHECK: ld2r.16b { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc0,0xe3,0x4d]
+; CHECK: ld2r.4h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x0d]
+; CHECK: ld2r.4h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x0d]
+; CHECK: ld2r.8h { v3, v4 }, [x2] ; encoding: [0x43,0xc4,0x60,0x4d]
+; CHECK: ld2r.8h { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc4,0xe3,0x4d]
+; CHECK: ld2r.2s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x0d]
+; CHECK: ld2r.2s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x0d]
+; CHECK: ld2r.4s { v3, v4 }, [x2] ; encoding: [0x43,0xc8,0x60,0x4d]
+; CHECK: ld2r.4s { v3, v4 }, [x2], x3 ; encoding: [0x43,0xc8,0xe3,0x4d]
+; CHECK: ld2r.1d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x0d]
+; CHECK: ld2r.1d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x0d]
+; CHECK: ld2r.2d { v3, v4 }, [x2] ; encoding: [0x43,0xcc,0x60,0x4d]
+; CHECK: ld2r.2d { v3, v4 }, [x2], x3 ; encoding: [0x43,0xcc,0xe3,0x4d]
+; CHECK: ld2r.8b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x0d]
+; CHECK: ld2r.16b { v3, v4 }, [x2], #2 ; encoding: [0x43,0xc0,0xff,0x4d]
+; CHECK: ld2r.4h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x0d]
+; CHECK: ld2r.8h { v3, v4 }, [x2], #4 ; encoding: [0x43,0xc4,0xff,0x4d]
+; CHECK: ld2r.2s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x0d]
+; CHECK: ld2r.4s { v3, v4 }, [x2], #8 ; encoding: [0x43,0xc8,0xff,0x4d]
+; CHECK: ld2r.1d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x0d]
+; CHECK: ld2r.2d { v3, v4 }, [x2], #16 ; encoding: [0x43,0xcc,0xff,0x4d]
+; CHECK: ld3r.8b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x0d]
+; CHECK: ld3r.8b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x0d]
+; CHECK: ld3r.16b { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe0,0x40,0x4d]
+; CHECK: ld3r.16b { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe0,0xc3,0x4d]
+; CHECK: ld3r.4h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x0d]
+; CHECK: ld3r.4h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x0d]
+; CHECK: ld3r.8h { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe4,0x40,0x4d]
+; CHECK: ld3r.8h { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe4,0xc3,0x4d]
+; CHECK: ld3r.2s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x0d]
+; CHECK: ld3r.2s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x0d]
+; CHECK: ld3r.4s { v2, v3, v4 }, [x2] ; encoding: [0x42,0xe8,0x40,0x4d]
+; CHECK: ld3r.4s { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xe8,0xc3,0x4d]
+; CHECK: ld3r.1d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x0d]
+; CHECK: ld3r.1d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x0d]
+; CHECK: ld3r.2d { v2, v3, v4 }, [x2] ; encoding: [0x42,0xec,0x40,0x4d]
+; CHECK: ld3r.2d { v2, v3, v4 }, [x2], x3 ; encoding: [0x42,0xec,0xc3,0x4d]
+; CHECK: ld3r.8b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x0d]
+; CHECK: ld3r.16b { v2, v3, v4 }, [x2], #3 ; encoding: [0x42,0xe0,0xdf,0x4d]
+; CHECK: ld3r.4h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x0d]
+; CHECK: ld3r.8h { v2, v3, v4 }, [x2], #6 ; encoding: [0x42,0xe4,0xdf,0x4d]
+; CHECK: ld3r.2s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x0d]
+; CHECK: ld3r.4s { v2, v3, v4 }, [x2], #12 ; encoding: [0x42,0xe8,0xdf,0x4d]
+; CHECK: ld3r.1d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x0d]
+; CHECK: ld3r.2d { v2, v3, v4 }, [x2], #24 ; encoding: [0x42,0xec,0xdf,0x4d]
+; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x0d]
+; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x0d]
+; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe0,0x60,0x4d]
+; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe0,0xe3,0x4d]
+; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x0d]
+; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x0d]
+; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe4,0x60,0x4d]
+; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe4,0xe3,0x4d]
+; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x0d]
+; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x0d]
+; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xe8,0x60,0x4d]
+; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xe8,0xe3,0x4d]
+; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x0d]
+; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x0d]
+; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2] ; encoding: [0x42,0xec,0x60,0x4d]
+; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], x3 ; encoding: [0x42,0xec,0xe3,0x4d]
+; CHECK: ld4r.8b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x0d]
+; CHECK: ld4r.16b { v2, v3, v4, v5 }, [x2], #4 ; encoding: [0x42,0xe0,0xff,0x4d]
+; CHECK: ld4r.4h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x0d]
+; CHECK: ld4r.8h { v2, v3, v4, v5 }, [x2], #8 ; encoding: [0x42,0xe4,0xff,0x4d]
+; CHECK: ld4r.2s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x0d]
+; CHECK: ld4r.4s { v2, v3, v4, v5 }, [x2], #16 ; encoding: [0x42,0xe8,0xff,0x4d]
+; CHECK: ld4r.1d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x0d]
+; CHECK: ld4r.2d { v2, v3, v4, v5 }, [x2], #32 ; encoding: [0x42,0xec,0xff,0x4d]
+; CHECK: ld1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x40,0x4d]
+; CHECK: ld1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x40,0x0d]
+; CHECK: ld1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x40,0x4d]
+; CHECK: ld1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x40,0x4d]
+; CHECK: ld1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0xc5,0x4d]
+; CHECK: ld1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0xc5,0x0d]
+; CHECK: ld1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0xc5,0x4d]
+; CHECK: ld1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0xc5,0x4d]
+; CHECK: ld1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0xdf,0x4d]
+; CHECK: ld1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0xdf,0x0d]
+; CHECK: ld1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0xdf,0x4d]
+; CHECK: ld1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0xdf,0x4d]
+; CHECK: ld2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x60,0x4d]
+; CHECK: ld2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x60,0x0d]
+; CHECK: ld2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x60,0x4d]
+; CHECK: ld2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x60,0x4d]
+; CHECK: ld2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xe5,0x4d]
+; CHECK: ld2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xe5,0x0d]
+; CHECK: ld2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xe5,0x4d]
+; CHECK: ld2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xe5,0x4d]
+; CHECK: ld2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xff,0x4d]
+; CHECK: ld2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xff,0x0d]
+; CHECK: ld2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xff,0x4d]
+; CHECK: ld2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xff,0x4d]
+; CHECK: ld3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x40,0x4d]
+; CHECK: ld3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x40,0x0d]
+; CHECK: ld3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x40,0x4d]
+; CHECK: ld3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x40,0x4d]
+; CHECK: ld3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0xc5,0x4d]
+; CHECK: ld3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0xc5,0x0d]
+; CHECK: ld3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xc5,0x4d]
+; CHECK: ld3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xc5,0x4d]
+; CHECK: ld3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0xdf,0x4d]
+; CHECK: ld3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0xdf,0x0d]
+; CHECK: ld3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0xdf,0x4d]
+; CHECK: ld3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0xdf,0x4d]
+; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x60,0x4d]
+; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x60,0x0d]
+; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x60,0x4d]
+; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x60,0x4d]
+; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xe5,0x4d]
+; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xe5,0x0d]
+; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xe5,0x4d]
+; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xe5,0x4d]
+; CHECK: ld4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xff,0x4d]
+; CHECK: ld4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xff,0x0d]
+; CHECK: ld4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xff,0x4d]
+; CHECK: ld4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xff,0x4d]
+; CHECK: st1.b { v6 }[13], [x3] ; encoding: [0x66,0x14,0x00,0x4d]
+; CHECK: st1.h { v6 }[2], [x3] ; encoding: [0x66,0x50,0x00,0x0d]
+; CHECK: st1.s { v6 }[2], [x3] ; encoding: [0x66,0x80,0x00,0x4d]
+; CHECK: st1.d { v6 }[1], [x3] ; encoding: [0x66,0x84,0x00,0x4d]
+; CHECK: st1.b { v6 }[13], [x3], x5 ; encoding: [0x66,0x14,0x85,0x4d]
+; CHECK: st1.h { v6 }[2], [x3], x5 ; encoding: [0x66,0x50,0x85,0x0d]
+; CHECK: st1.s { v6 }[2], [x3], x5 ; encoding: [0x66,0x80,0x85,0x4d]
+; CHECK: st1.d { v6 }[1], [x3], x5 ; encoding: [0x66,0x84,0x85,0x4d]
+; CHECK: st1.b { v6 }[13], [x3], #1 ; encoding: [0x66,0x14,0x9f,0x4d]
+; CHECK: st1.h { v6 }[2], [x3], #2 ; encoding: [0x66,0x50,0x9f,0x0d]
+; CHECK: st1.s { v6 }[2], [x3], #4 ; encoding: [0x66,0x80,0x9f,0x4d]
+; CHECK: st1.d { v6 }[1], [x3], #8 ; encoding: [0x66,0x84,0x9f,0x4d]
+; CHECK: st2.b { v5, v6 }[13], [x3] ; encoding: [0x65,0x14,0x20,0x4d]
+; CHECK: st2.h { v5, v6 }[2], [x3] ; encoding: [0x65,0x50,0x20,0x0d]
+; CHECK: st2.s { v5, v6 }[2], [x3] ; encoding: [0x65,0x80,0x20,0x4d]
+; CHECK: st2.d { v5, v6 }[1], [x3] ; encoding: [0x65,0x84,0x20,0x4d]
+; CHECK: st2.b { v5, v6 }[13], [x3], x5 ; encoding: [0x65,0x14,0xa5,0x4d]
+; CHECK: st2.h { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x50,0xa5,0x0d]
+; CHECK: st2.s { v5, v6 }[2], [x3], x5 ; encoding: [0x65,0x80,0xa5,0x4d]
+; CHECK: st2.d { v5, v6 }[1], [x3], x5 ; encoding: [0x65,0x84,0xa5,0x4d]
+; CHECK: st2.b { v5, v6 }[13], [x3], #2 ; encoding: [0x65,0x14,0xbf,0x4d]
+; CHECK: st2.h { v5, v6 }[2], [x3], #4 ; encoding: [0x65,0x50,0xbf,0x0d]
+; CHECK: st2.s { v5, v6 }[2], [x3], #8 ; encoding: [0x65,0x80,0xbf,0x4d]
+; CHECK: st2.d { v5, v6 }[1], [x3], #16 ; encoding: [0x65,0x84,0xbf,0x4d]
+; CHECK: st3.b { v7, v8, v9 }[13], [x3] ; encoding: [0x67,0x34,0x00,0x4d]
+; CHECK: st3.h { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0x70,0x00,0x0d]
+; CHECK: st3.s { v7, v8, v9 }[2], [x3] ; encoding: [0x67,0xa0,0x00,0x4d]
+; CHECK: st3.d { v7, v8, v9 }[1], [x3] ; encoding: [0x67,0xa4,0x00,0x4d]
+; CHECK: st3.b { v7, v8, v9 }[13], [x3], x5 ; encoding: [0x67,0x34,0x85,0x4d]
+; CHECK: st3.h { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0x70,0x85,0x0d]
+; CHECK: st3.s { v7, v8, v9 }[2], [x3], x5 ; encoding: [0x67,0xa0,0x85,0x4d]
+; CHECK: st3.d { v7, v8, v9 }[1], [x3], x5 ; encoding: [0x67,0xa4,0x85,0x4d]
+; CHECK: st3.b { v7, v8, v9 }[13], [x3], #3 ; encoding: [0x67,0x34,0x9f,0x4d]
+; CHECK: st3.h { v7, v8, v9 }[2], [x3], #6 ; encoding: [0x67,0x70,0x9f,0x0d]
+; CHECK: st3.s { v7, v8, v9 }[2], [x3], #12 ; encoding: [0x67,0xa0,0x9f,0x4d]
+; CHECK: st3.d { v7, v8, v9 }[1], [x3], #24 ; encoding: [0x67,0xa4,0x9f,0x4d]
+; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3] ; encoding: [0x67,0x34,0x20,0x4d]
+; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0x70,0x20,0x0d]
+; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3] ; encoding: [0x67,0xa0,0x20,0x4d]
+; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3] ; encoding: [0x67,0xa4,0x20,0x4d]
+; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], x5 ; encoding: [0x67,0x34,0xa5,0x4d]
+; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0x70,0xa5,0x0d]
+; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], x5 ; encoding: [0x67,0xa0,0xa5,0x4d]
+; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], x5 ; encoding: [0x67,0xa4,0xa5,0x4d]
+; CHECK: st4.b { v7, v8, v9, v10 }[13], [x3], #4 ; encoding: [0x67,0x34,0xbf,0x4d]
+; CHECK: st4.h { v7, v8, v9, v10 }[2], [x3], #8 ; encoding: [0x67,0x70,0xbf,0x0d]
+; CHECK: st4.s { v7, v8, v9, v10 }[2], [x3], #16 ; encoding: [0x67,0xa0,0xbf,0x4d]
+; CHECK: st4.d { v7, v8, v9, v10 }[1], [x3], #32 ; encoding: [0x67,0xa4,0xbf,0x4d]
Added: llvm/trunk/test/MC/ARM64/small-data-fixups.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/small-data-fixups.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/small-data-fixups.s (added)
+++ llvm/trunk/test/MC/ARM64/small-data-fixups.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,24 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o - %s | macho-dump | FileCheck %s
+
+foo:
+ .long 0
+bar:
+ .long 1
+
+baz:
+ .byte foo - bar
+ .short foo - bar
+
+; CHECK: # Relocation 0
+; CHECK: (('word-0', 0x9),
+; CHECK: ('word-1', 0x1a000002)),
+; CHECK: # Relocation 1
+; CHECK: (('word-0', 0x9),
+; CHECK: ('word-1', 0xa000001)),
+; CHECK: # Relocation 2
+; CHECK: (('word-0', 0x8),
+; CHECK: ('word-1', 0x18000002)),
+; CHECK: # Relocation 3
+; CHECK: (('word-0', 0x8),
+; CHECK: ('word-1', 0x8000001)),
+
Added: llvm/trunk/test/MC/ARM64/system-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/system-encoding.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/system-encoding.s (added)
+++ llvm/trunk/test/MC/ARM64/system-encoding.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,679 @@
+; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+
+foo:
+
+;-----------------------------------------------------------------------------
+; Simple encodings (instuctions w/ no operands)
+;-----------------------------------------------------------------------------
+
+ nop
+ sev
+ sevl
+ wfe
+ wfi
+ yield
+
+; CHECK: nop ; encoding: [0x1f,0x20,0x03,0xd5]
+; CHECK: sev ; encoding: [0x9f,0x20,0x03,0xd5]
+; CHECK: sevl ; encoding: [0xbf,0x20,0x03,0xd5]
+; CHECK: wfe ; encoding: [0x5f,0x20,0x03,0xd5]
+; CHECK: wfi ; encoding: [0x7f,0x20,0x03,0xd5]
+; CHECK: yield ; encoding: [0x3f,0x20,0x03,0xd5]
+
+;-----------------------------------------------------------------------------
+; Single-immediate operand instructions
+;-----------------------------------------------------------------------------
+
+ clrex #10
+; CHECK: clrex #10 ; encoding: [0x5f,0x3a,0x03,0xd5]
+ isb #15
+ isb sy
+; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5]
+; CHECK: isb ; encoding: [0xdf,0x3f,0x03,0xd5]
+ dmb #3
+ dmb osh
+; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
+; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5]
+ dsb #7
+ dsb nsh
+; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5]
+; CHECK: dsb nsh ; encoding: [0x9f,0x37,0x03,0xd5]
+
+;-----------------------------------------------------------------------------
+; Generic system instructions
+;-----------------------------------------------------------------------------
+ sys #2, c0, c5, #7
+; CHECK: encoding: [0xff,0x05,0x0a,0xd5]
+ sys #7, C6, c10, #7, x7
+; CHECK: encoding: [0xe7,0x6a,0x0f,0xd5]
+ sysl x20, #6, c3, C15, #7
+; CHECK: encoding: [0xf4,0x3f,0x2e,0xd5]
+
+; Check for error on invalid 'C' operand value.
+ sys #2, c16, c5, #7
+; CHECK-ERRORS: invalid operand for instruction
+
+;-----------------------------------------------------------------------------
+; MSR/MRS instructions
+;-----------------------------------------------------------------------------
+ msr ACTLR_EL1, x3
+ msr ACTLR_EL2, x3
+ msr ACTLR_EL3, x3
+ msr ADFSR_EL1, x3
+ msr ADFSR_EL2, x3
+ msr ADFSR_EL3, x3
+ msr AIDR_EL1, x3
+ msr AIFSR_EL1, x3
+ msr AIFSR_EL2, x3
+ msr AIFSR_EL3, x3
+ msr AMAIR_EL1, x3
+ msr AMAIR_EL2, x3
+ msr AMAIR_EL3, x3
+ msr CCSIDR_EL1, x3
+ msr CLIDR_EL1, x3
+ msr CNTFRQ_EL0, x3
+ msr CNTHCTL_EL2, x3
+ msr CNTHP_CTL_EL2, x3
+ msr CNTHP_CVAL_EL2, x3
+ msr CNTHP_TVAL_EL2, x3
+ msr CNTKCTL_EL1, x3
+ msr CNTPCT_EL0, x3
+ msr CNTP_CTL_EL0, x3
+ msr CNTP_CVAL_EL0, x3
+ msr CNTP_TVAL_EL0, x3
+ msr CNTVCT_EL0, x3
+ msr CNTVOFF_EL2, x3
+ msr CNTV_CTL_EL0, x3
+ msr CNTV_CVAL_EL0, x3
+ msr CNTV_TVAL_EL0, x3
+ msr CONTEXTIDR_EL1, x3
+ msr CPACR_EL1, x3
+ msr CPTR_EL2, x3
+ msr CPTR_EL3, x3
+ msr CSSELR_EL1, x3
+ msr CTR_EL0, x3
+ msr CURRENT_EL, x3
+ msr DACR32_EL2, x3
+ msr DCZID_EL0, x3
+ msr ECOIDR_EL1, x3
+ msr ESR_EL1, x3
+ msr ESR_EL2, x3
+ msr ESR_EL3, x3
+ msr FAR_EL1, x3
+ msr FAR_EL2, x3
+ msr FAR_EL3, x3
+ msr FPEXC32_EL2, x3
+ msr HACR_EL2, x3
+ msr HCR_EL2, x3
+ msr HPFAR_EL2, x3
+ msr HSTR_EL2, x3
+ msr ID_AA64DFR0_EL1, x3
+ msr ID_AA64DFR1_EL1, x3
+ msr ID_AA64ISAR0_EL1, x3
+ msr ID_AA64ISAR1_EL1, x3
+ msr ID_AA64MMFR0_EL1, x3
+ msr ID_AA64MMFR1_EL1, x3
+ msr ID_AA64PFR0_EL1, x3
+ msr ID_AA64PFR1_EL1, x3
+ msr IFSR32_EL2, x3
+ msr ISR_EL1, x3
+ msr MAIR_EL1, x3
+ msr MAIR_EL2, x3
+ msr MAIR_EL3, x3
+ msr MDCR_EL2, x3
+ msr MDCR_EL3, x3
+ msr MIDR_EL1, x3
+ msr MPIDR_EL1, x3
+ msr MVFR0_EL1, x3
+ msr MVFR1_EL1, x3
+ msr PAR_EL1, x3
+ msr RVBAR_EL1, x3
+ msr RVBAR_EL2, x3
+ msr RVBAR_EL3, x3
+ msr SCR_EL3, x3
+ msr SCTLR_EL1, x3
+ msr SCTLR_EL2, x3
+ msr SCTLR_EL3, x3
+ msr SDER32_EL3, x3
+ msr TCR_EL1, x3
+ msr TCR_EL2, x3
+ msr TCR_EL3, x3
+ msr TEECR32_EL1, x3
+ msr TEEHBR32_EL1, x3
+ msr TPIDRRO_EL0, x3
+ msr TPIDR_EL0, x3
+ msr TPIDR_EL1, x3
+ msr TPIDR_EL2, x3
+ msr TPIDR_EL3, x3
+ msr TTBR0_EL1, x3
+ msr TTBR0_EL2, x3
+ msr TTBR0_EL3, x3
+ msr TTBR1_EL1, x3
+ msr VBAR_EL1, x3
+ msr VBAR_EL2, x3
+ msr VBAR_EL3, x3
+ msr VMPIDR_EL2, x3
+ msr VPIDR_EL2, x3
+ msr VTCR_EL2, x3
+ msr VTTBR_EL2, x3
+ msr SPSel, x3
+ msr S2_2_C4_C6_4, x1
+; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5]
+; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5]
+; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5]
+; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5]
+; CHECK: msr ADFSR_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5]
+; CHECK: msr ADFSR_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5]
+; CHECK: msr AIDR_EL1, x3 ; encoding: [0xe3,0x00,0x19,0xd5]
+; CHECK: msr AFSR1_EL1, x3 ; encoding: [0x23,0x51,0x18,0xd5]
+; CHECK: msr AIFSR_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5]
+; CHECK: msr AIFSR_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5]
+; CHECK: msr AMAIR_EL1, x3 ; encoding: [0x03,0xa3,0x18,0xd5]
+; CHECK: msr AMAIR_EL2, x3 ; encoding: [0x03,0xa3,0x1c,0xd5]
+; CHECK: msr AMAIR_EL3, x3 ; encoding: [0x03,0xa3,0x1e,0xd5]
+; CHECK: msr CCSIDR_EL1, x3 ; encoding: [0x03,0x00,0x19,0xd5]
+; CHECK: msr CLIDR_EL1, x3 ; encoding: [0x23,0x00,0x19,0xd5]
+; CHECK: msr CNTFRQ_EL0, x3 ; encoding: [0x03,0xe0,0x1b,0xd5]
+; CHECK: msr CNTHCTL_EL2, x3 ; encoding: [0x03,0xe1,0x1c,0xd5]
+; CHECK: msr CNTHP_CTL_EL2, x3 ; encoding: [0x23,0xe2,0x1c,0xd5]
+; CHECK: msr CNTHP_CVAL_EL2, x3 ; encoding: [0x43,0xe2,0x1c,0xd5]
+; CHECK: msr CNTHP_TVAL_EL2, x3 ; encoding: [0x03,0xe2,0x1c,0xd5]
+; CHECK: msr CNTKCTL_EL1, x3 ; encoding: [0x03,0xe1,0x18,0xd5]
+; CHECK: msr CNTPCT_EL0, x3 ; encoding: [0x23,0xe0,0x1b,0xd5]
+; CHECK: msr CNTP_CTL_EL0, x3 ; encoding: [0x23,0xe2,0x1b,0xd5]
+; CHECK: msr CNTP_CVAL_EL0, x3 ; encoding: [0x43,0xe2,0x1b,0xd5]
+; CHECK: msr CNTP_TVAL_EL0, x3 ; encoding: [0x03,0xe2,0x1b,0xd5]
+; CHECK: msr CNTVCT_EL0, x3 ; encoding: [0x43,0xe0,0x1b,0xd5]
+; CHECK: msr CNTVOFF_EL2, x3 ; encoding: [0x63,0xe0,0x1c,0xd5]
+; CHECK: msr CNTV_CTL_EL0, x3 ; encoding: [0x23,0xe3,0x1b,0xd5]
+; CHECK: msr CNTV_CVAL_EL0, x3 ; encoding: [0x43,0xe3,0x1b,0xd5]
+; CHECK: msr CNTV_TVAL_EL0, x3 ; encoding: [0x03,0xe3,0x1b,0xd5]
+; CHECK: msr CONTEXTIDR_EL1, x3 ; encoding: [0x23,0xd0,0x18,0xd5]
+; CHECK: msr CPACR_EL1, x3 ; encoding: [0x43,0x10,0x18,0xd5]
+; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5]
+; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5]
+; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5]
+; CHECK: msr CTR_EL0, x3 ; encoding: [0x23,0x00,0x1b,0xd5]
+; CHECK: msr CurrentEL, x3 ; encoding: [0x43,0x42,0x18,0xd5]
+; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5]
+; CHECK: msr DCZID_EL0, x3 ; encoding: [0xe3,0x00,0x1b,0xd5]
+; CHECK: msr REVIDR_EL1, x3 ; encoding: [0xc3,0x00,0x18,0xd5]
+; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5]
+; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5]
+; CHECK: msr ESR_EL3, x3 ; encoding: [0x03,0x52,0x1e,0xd5]
+; CHECK: msr FAR_EL1, x3 ; encoding: [0x03,0x60,0x18,0xd5]
+; CHECK: msr FAR_EL2, x3 ; encoding: [0x03,0x60,0x1c,0xd5]
+; CHECK: msr FAR_EL3, x3 ; encoding: [0x03,0x60,0x1e,0xd5]
+; CHECK: msr FPEXC32_EL2, x3 ; encoding: [0x03,0x53,0x1c,0xd5]
+; CHECK: msr HACR_EL2, x3 ; encoding: [0xe3,0x11,0x1c,0xd5]
+; CHECK: msr HCR_EL2, x3 ; encoding: [0x03,0x11,0x1c,0xd5]
+; CHECK: msr HPFAR_EL2, x3 ; encoding: [0x83,0x60,0x1c,0xd5]
+; CHECK: msr HSTR_EL2, x3 ; encoding: [0x63,0x11,0x1c,0xd5]
+; CHECK: msr ID_AA64DFR0_EL1, x3 ; encoding: [0x03,0x05,0x18,0xd5]
+; CHECK: msr ID_AA64DFR1_EL1, x3 ; encoding: [0x23,0x05,0x18,0xd5]
+; CHECK: msr ID_AA64ISAR0_EL1, x3 ; encoding: [0x03,0x06,0x18,0xd5]
+; CHECK: msr ID_AA64ISAR1_EL1, x3 ; encoding: [0x23,0x06,0x18,0xd5]
+; CHECK: msr ID_AA64MMFR0_EL1, x3 ; encoding: [0x03,0x07,0x18,0xd5]
+; CHECK: msr ID_AA64MMFR1_EL1, x3 ; encoding: [0x23,0x07,0x18,0xd5]
+; CHECK: msr ID_AA64PFR0_EL1, x3 ; encoding: [0x03,0x04,0x18,0xd5]
+; CHECK: msr ID_AA64PFR1_EL1, x3 ; encoding: [0x23,0x04,0x18,0xd5]
+; CHECK: msr IFSR32_EL2, x3 ; encoding: [0x23,0x50,0x1c,0xd5]
+; CHECK: msr ISR_EL1, x3 ; encoding: [0x03,0xc1,0x18,0xd5]
+; CHECK: msr MAIR_EL1, x3 ; encoding: [0x03,0xa2,0x18,0xd5]
+; CHECK: msr MAIR_EL2, x3 ; encoding: [0x03,0xa2,0x1c,0xd5]
+; CHECK: msr MAIR_EL3, x3 ; encoding: [0x03,0xa2,0x1e,0xd5]
+; CHECK: msr MDCR_EL2, x3 ; encoding: [0x23,0x11,0x1c,0xd5]
+; CHECK: msr MDCR_EL3, x3 ; encoding: [0x23,0x13,0x1e,0xd5]
+; CHECK: msr MIDR_EL1, x3 ; encoding: [0x03,0x00,0x18,0xd5]
+; CHECK: msr MPIDR_EL1, x3 ; encoding: [0xa3,0x00,0x18,0xd5]
+; CHECK: msr MVFR0_EL1, x3 ; encoding: [0x03,0x03,0x18,0xd5]
+; CHECK: msr MVFR1_EL1, x3 ; encoding: [0x23,0x03,0x18,0xd5]
+; CHECK: msr PAR_EL1, x3 ; encoding: [0x03,0x74,0x18,0xd5]
+; CHECK: msr RVBAR_EL1, x3 ; encoding: [0x23,0xc0,0x18,0xd5]
+; CHECK: msr RVBAR_EL2, x3 ; encoding: [0x23,0xc0,0x1c,0xd5]
+; CHECK: msr RVBAR_EL3, x3 ; encoding: [0x23,0xc0,0x1e,0xd5]
+; CHECK: msr SCR_EL3, x3 ; encoding: [0x03,0x11,0x1e,0xd5]
+; CHECK: msr SCTLR_EL1, x3 ; encoding: [0x03,0x10,0x18,0xd5]
+; CHECK: msr SCTLR_EL2, x3 ; encoding: [0x03,0x10,0x1c,0xd5]
+; CHECK: msr SCTLR_EL3, x3 ; encoding: [0x03,0x10,0x1e,0xd5]
+; CHECK: msr SDER32_EL3, x3 ; encoding: [0x23,0x11,0x1e,0xd5]
+; CHECK: msr TCR_EL1, x3 ; encoding: [0x43,0x20,0x18,0xd5]
+; CHECK: msr TCR_EL2, x3 ; encoding: [0x43,0x20,0x1c,0xd5]
+; CHECK: msr TCR_EL3, x3 ; encoding: [0x43,0x20,0x1e,0xd5]
+; CHECK: msr TEECR32_EL1, x3 ; encoding: [0x03,0x00,0x12,0xd5]
+; CHECK: msr TEEHBR32_EL1, x3 ; encoding: [0x03,0x10,0x12,0xd5]
+; CHECK: msr TPIDRRO_EL0, x3 ; encoding: [0x63,0xd0,0x1b,0xd5]
+; CHECK: msr TPIDR_EL0, x3 ; encoding: [0x43,0xd0,0x1b,0xd5]
+; CHECK: msr TPIDR_EL1, x3 ; encoding: [0x83,0xd0,0x18,0xd5]
+; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5]
+; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5]
+; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5]
+; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5]
+; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5]
+; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5]
+; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5]
+; CHECK: msr VBAR_EL2, x3 ; encoding: [0x03,0xc0,0x1c,0xd5]
+; CHECK: msr VBAR_EL3, x3 ; encoding: [0x03,0xc0,0x1e,0xd5]
+; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5]
+; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5]
+; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5]
+; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5]
+; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5]
+; CHECK: msr S2_2_C4_C6_4, x1 ; encoding: [0x81,0x46,0x12,0xd5]
+
+ mrs x3, ACTLR_EL1
+ mrs x3, ACTLR_EL2
+ mrs x3, ACTLR_EL3
+ mrs x3, ADFSR_EL1
+ mrs x3, ADFSR_EL2
+ mrs x3, ADFSR_EL3
+ mrs x3, AIDR_EL1
+ mrs x3, AIFSR_EL1
+ mrs x3, AIFSR_EL2
+ mrs x3, AIFSR_EL3
+ mrs x3, AMAIR_EL1
+ mrs x3, AMAIR_EL2
+ mrs x3, AMAIR_EL3
+ mrs x3, CCSIDR_EL1
+ mrs x3, CLIDR_EL1
+ mrs x3, CNTFRQ_EL0
+ mrs x3, CNTHCTL_EL2
+ mrs x3, CNTHP_CTL_EL2
+ mrs x3, CNTHP_CVAL_EL2
+ mrs x3, CNTHP_TVAL_EL2
+ mrs x3, CNTKCTL_EL1
+ mrs x3, CNTPCT_EL0
+ mrs x3, CNTP_CTL_EL0
+ mrs x3, CNTP_CVAL_EL0
+ mrs x3, CNTP_TVAL_EL0
+ mrs x3, CNTVCT_EL0
+ mrs x3, CNTVOFF_EL2
+ mrs x3, CNTV_CTL_EL0
+ mrs x3, CNTV_CVAL_EL0
+ mrs x3, CNTV_TVAL_EL0
+ mrs x3, CONTEXTIDR_EL1
+ mrs x3, CPACR_EL1
+ mrs x3, CPTR_EL2
+ mrs x3, CPTR_EL3
+ mrs x3, CSSELR_EL1
+ mrs x3, CTR_EL0
+ mrs x3, CURRENT_EL
+ mrs x3, DACR32_EL2
+ mrs x3, DCZID_EL0
+ mrs x3, ECOIDR_EL1
+ mrs x3, ESR_EL1
+ mrs x3, ESR_EL2
+ mrs x3, ESR_EL3
+ mrs x3, FAR_EL1
+ mrs x3, FAR_EL2
+ mrs x3, FAR_EL3
+ mrs x3, FPEXC32_EL2
+ mrs x3, HACR_EL2
+ mrs x3, HCR_EL2
+ mrs x3, HPFAR_EL2
+ mrs x3, HSTR_EL2
+ mrs x3, ID_AA64DFR0_EL1
+ mrs x3, ID_AA64DFR1_EL1
+ mrs x3, ID_AA64ISAR0_EL1
+ mrs x3, ID_AA64ISAR1_EL1
+ mrs x3, ID_AA64MMFR0_EL1
+ mrs x3, ID_AA64MMFR1_EL1
+ mrs x3, ID_AA64PFR0_EL1
+ mrs x3, ID_AA64PFR1_EL1
+ mrs x3, IFSR32_EL2
+ mrs x3, ISR_EL1
+ mrs x3, MAIR_EL1
+ mrs x3, MAIR_EL2
+ mrs x3, MAIR_EL3
+ mrs x3, MDCR_EL2
+ mrs x3, MDCR_EL3
+ mrs x3, MIDR_EL1
+ mrs x3, MPIDR_EL1
+ mrs x3, MVFR0_EL1
+ mrs x3, MVFR1_EL1
+ mrs x3, PAR_EL1
+ mrs x3, RVBAR_EL1
+ mrs x3, RVBAR_EL2
+ mrs x3, RVBAR_EL3
+ mrs x3, SCR_EL3
+ mrs x3, SCTLR_EL1
+ mrs x3, SCTLR_EL2
+ mrs x3, SCTLR_EL3
+ mrs x3, SDER32_EL3
+ mrs x3, TCR_EL1
+ mrs x3, TCR_EL2
+ mrs x3, TCR_EL3
+ mrs x3, TEECR32_EL1
+ mrs x3, TEEHBR32_EL1
+ mrs x3, TPIDRRO_EL0
+ mrs x3, TPIDR_EL0
+ mrs x3, TPIDR_EL1
+ mrs x3, TPIDR_EL2
+ mrs x3, TPIDR_EL3
+ mrs x3, TTBR0_EL1
+ mrs x3, TTBR0_EL2
+ mrs x3, TTBR0_EL3
+ mrs x3, TTBR1_EL1
+ mrs x3, VBAR_EL1
+ mrs x3, VBAR_EL2
+ mrs x3, VBAR_EL3
+ mrs x3, VMPIDR_EL2
+ mrs x3, VPIDR_EL2
+ mrs x3, VTCR_EL2
+ mrs x3, VTTBR_EL2
+
+ mrs x3, MDCCSR_EL0
+ mrs x3, MDCCINT_EL1
+ mrs x3, DBGDTR_EL0
+ mrs x3, DBGDTRRX_EL0
+ mrs x3, DBGDTRTX_EL0
+ mrs x3, DBGVCR32_EL2
+ mrs x3, OSDTRRX_EL1
+ mrs x3, MDSCR_EL1
+ mrs x3, OSDTRTX_EL1
+ mrs x3, OSECCR_EL11
+ mrs x3, DBGBVR0_EL1
+ mrs x3, DBGBVR1_EL1
+ mrs x3, DBGBVR2_EL1
+ mrs x3, DBGBVR3_EL1
+ mrs x3, DBGBVR4_EL1
+ mrs x3, DBGBVR5_EL1
+ mrs x3, DBGBVR6_EL1
+ mrs x3, DBGBVR7_EL1
+ mrs x3, DBGBVR8_EL1
+ mrs x3, DBGBVR9_EL1
+ mrs x3, DBGBVR10_EL1
+ mrs x3, DBGBVR11_EL1
+ mrs x3, DBGBVR12_EL1
+ mrs x3, DBGBVR13_EL1
+ mrs x3, DBGBVR14_EL1
+ mrs x3, DBGBVR15_EL1
+ mrs x3, DBGBCR0_EL1
+ mrs x3, DBGBCR1_EL1
+ mrs x3, DBGBCR2_EL1
+ mrs x3, DBGBCR3_EL1
+ mrs x3, DBGBCR4_EL1
+ mrs x3, DBGBCR5_EL1
+ mrs x3, DBGBCR6_EL1
+ mrs x3, DBGBCR7_EL1
+ mrs x3, DBGBCR8_EL1
+ mrs x3, DBGBCR9_EL1
+ mrs x3, DBGBCR10_EL1
+ mrs x3, DBGBCR11_EL1
+ mrs x3, DBGBCR12_EL1
+ mrs x3, DBGBCR13_EL1
+ mrs x3, DBGBCR14_EL1
+ mrs x3, DBGBCR15_EL1
+ mrs x3, DBGWVR0_EL1
+ mrs x3, DBGWVR1_EL1
+ mrs x3, DBGWVR2_EL1
+ mrs x3, DBGWVR3_EL1
+ mrs x3, DBGWVR4_EL1
+ mrs x3, DBGWVR5_EL1
+ mrs x3, DBGWVR6_EL1
+ mrs x3, DBGWVR7_EL1
+ mrs x3, DBGWVR8_EL1
+ mrs x3, DBGWVR9_EL1
+ mrs x3, DBGWVR10_EL1
+ mrs x3, DBGWVR11_EL1
+ mrs x3, DBGWVR12_EL1
+ mrs x3, DBGWVR13_EL1
+ mrs x3, DBGWVR14_EL1
+ mrs x3, DBGWVR15_EL1
+ mrs x3, DBGWCR0_EL1
+ mrs x3, DBGWCR1_EL1
+ mrs x3, DBGWCR2_EL1
+ mrs x3, DBGWCR3_EL1
+ mrs x3, DBGWCR4_EL1
+ mrs x3, DBGWCR5_EL1
+ mrs x3, DBGWCR6_EL1
+ mrs x3, DBGWCR7_EL1
+ mrs x3, DBGWCR8_EL1
+ mrs x3, DBGWCR9_EL1
+ mrs x3, DBGWCR10_EL1
+ mrs x3, DBGWCR11_EL1
+ mrs x3, DBGWCR12_EL1
+ mrs x3, DBGWCR13_EL1
+ mrs x3, DBGWCR14_EL1
+ mrs x3, DBGWCR15_EL1
+ mrs x3, MDRAR_EL1
+ mrs x3, OSLAR_EL1
+ mrs x3, OSLSR_EL1
+ mrs x3, OSDLR_EL1
+ mrs x3, DBGPRCR_EL1
+ mrs x3, DBGCLAIMSET_EL1
+ mrs x3, DBGCLAIMCLR_EL1
+ mrs x3, DBGAUTHSTATUS_EL1
+ mrs x3, DBGDEVID2
+ mrs x3, DBGDEVID1
+ mrs x3, DBGDEVID0
+ mrs x1, S2_2_C4_C6_4
+ mrs x3, s2_3_c2_c1_4
+ mrs x3, S2_3_c2_c1_4
+
+; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5]
+; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5]
+; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5]
+; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5]
+; CHECK: mrs x3, ADFSR_EL2 ; encoding: [0x03,0x51,0x3c,0xd5]
+; CHECK: mrs x3, ADFSR_EL3 ; encoding: [0x03,0x51,0x3e,0xd5]
+; CHECK: mrs x3, AIDR_EL1 ; encoding: [0xe3,0x00,0x39,0xd5]
+; CHECK: mrs x3, AFSR1_EL1 ; encoding: [0x23,0x51,0x38,0xd5]
+; CHECK: mrs x3, AIFSR_EL2 ; encoding: [0x23,0x51,0x3c,0xd5]
+; CHECK: mrs x3, AIFSR_EL3 ; encoding: [0x23,0x51,0x3e,0xd5]
+; CHECK: mrs x3, AMAIR_EL1 ; encoding: [0x03,0xa3,0x38,0xd5]
+; CHECK: mrs x3, AMAIR_EL2 ; encoding: [0x03,0xa3,0x3c,0xd5]
+; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5]
+; CHECK: mrs x3, CCSIDR_EL1 ; encoding: [0x03,0x00,0x39,0xd5]
+; CHECK: mrs x3, CLIDR_EL1 ; encoding: [0x23,0x00,0x39,0xd5]
+; CHECK: mrs x3, CNTFRQ_EL0 ; encoding: [0x03,0xe0,0x3b,0xd5]
+; CHECK: mrs x3, CNTHCTL_EL2 ; encoding: [0x03,0xe1,0x3c,0xd5]
+; CHECK: mrs x3, CNTHP_CTL_EL2 ; encoding: [0x23,0xe2,0x3c,0xd5]
+; CHECK: mrs x3, CNTHP_CVAL_EL2 ; encoding: [0x43,0xe2,0x3c,0xd5]
+; CHECK: mrs x3, CNTHP_TVAL_EL2 ; encoding: [0x03,0xe2,0x3c,0xd5]
+; CHECK: mrs x3, CNTKCTL_EL1 ; encoding: [0x03,0xe1,0x38,0xd5]
+; CHECK: mrs x3, CNTPCT_EL0 ; encoding: [0x23,0xe0,0x3b,0xd5]
+; CHECK: mrs x3, CNTP_CTL_EL0 ; encoding: [0x23,0xe2,0x3b,0xd5]
+; CHECK: mrs x3, CNTP_CVAL_EL0 ; encoding: [0x43,0xe2,0x3b,0xd5]
+; CHECK: mrs x3, CNTP_TVAL_EL0 ; encoding: [0x03,0xe2,0x3b,0xd5]
+; CHECK: mrs x3, CNTVCT_EL0 ; encoding: [0x43,0xe0,0x3b,0xd5]
+; CHECK: mrs x3, CNTVOFF_EL2 ; encoding: [0x63,0xe0,0x3c,0xd5]
+; CHECK: mrs x3, CNTV_CTL_EL0 ; encoding: [0x23,0xe3,0x3b,0xd5]
+; CHECK: mrs x3, CNTV_CVAL_EL0 ; encoding: [0x43,0xe3,0x3b,0xd5]
+; CHECK: mrs x3, CNTV_TVAL_EL0 ; encoding: [0x03,0xe3,0x3b,0xd5]
+; CHECK: mrs x3, CONTEXTIDR_EL1 ; encoding: [0x23,0xd0,0x38,0xd5]
+; CHECK: mrs x3, CPACR_EL1 ; encoding: [0x43,0x10,0x38,0xd5]
+; CHECK: mrs x3, CPTR_EL2 ; encoding: [0x43,0x11,0x3c,0xd5]
+; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5]
+; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5]
+; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5]
+; CHECK: mrs x3, CurrentEL ; encoding: [0x43,0x42,0x38,0xd5]
+; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5]
+; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5]
+; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5]
+; CHECK: mrs x3, ESR_EL1 ; encoding: [0x03,0x52,0x38,0xd5]
+; CHECK: mrs x3, ESR_EL2 ; encoding: [0x03,0x52,0x3c,0xd5]
+; CHECK: mrs x3, ESR_EL3 ; encoding: [0x03,0x52,0x3e,0xd5]
+; CHECK: mrs x3, FAR_EL1 ; encoding: [0x03,0x60,0x38,0xd5]
+; CHECK: mrs x3, FAR_EL2 ; encoding: [0x03,0x60,0x3c,0xd5]
+; CHECK: mrs x3, FAR_EL3 ; encoding: [0x03,0x60,0x3e,0xd5]
+; CHECK: mrs x3, FPEXC32_EL2 ; encoding: [0x03,0x53,0x3c,0xd5]
+; CHECK: mrs x3, HACR_EL2 ; encoding: [0xe3,0x11,0x3c,0xd5]
+; CHECK: mrs x3, HCR_EL2 ; encoding: [0x03,0x11,0x3c,0xd5]
+; CHECK: mrs x3, HPFAR_EL2 ; encoding: [0x83,0x60,0x3c,0xd5]
+; CHECK: mrs x3, HSTR_EL2 ; encoding: [0x63,0x11,0x3c,0xd5]
+; CHECK: mrs x3, ID_AA64DFR0_EL1 ; encoding: [0x03,0x05,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64DFR1_EL1 ; encoding: [0x23,0x05,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64ISAR0_EL1 ; encoding: [0x03,0x06,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64ISAR1_EL1 ; encoding: [0x23,0x06,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR0_EL1 ; encoding: [0x03,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64MMFR1_EL1 ; encoding: [0x23,0x07,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64PFR0_EL1 ; encoding: [0x03,0x04,0x38,0xd5]
+; CHECK: mrs x3, ID_AA64PFR1_EL1 ; encoding: [0x23,0x04,0x38,0xd5]
+; CHECK: mrs x3, IFSR32_EL2 ; encoding: [0x23,0x50,0x3c,0xd5]
+; CHECK: mrs x3, ISR_EL1 ; encoding: [0x03,0xc1,0x38,0xd5]
+; CHECK: mrs x3, MAIR_EL1 ; encoding: [0x03,0xa2,0x38,0xd5]
+; CHECK: mrs x3, MAIR_EL2 ; encoding: [0x03,0xa2,0x3c,0xd5]
+; CHECK: mrs x3, MAIR_EL3 ; encoding: [0x03,0xa2,0x3e,0xd5]
+; CHECK: mrs x3, MDCR_EL2 ; encoding: [0x23,0x11,0x3c,0xd5]
+; CHECK: mrs x3, MDCR_EL3 ; encoding: [0x23,0x13,0x3e,0xd5]
+; CHECK: mrs x3, MIDR_EL1 ; encoding: [0x03,0x00,0x38,0xd5]
+; CHECK: mrs x3, MPIDR_EL1 ; encoding: [0xa3,0x00,0x38,0xd5]
+; CHECK: mrs x3, MVFR0_EL1 ; encoding: [0x03,0x03,0x38,0xd5]
+; CHECK: mrs x3, MVFR1_EL1 ; encoding: [0x23,0x03,0x38,0xd5]
+; CHECK: mrs x3, PAR_EL1 ; encoding: [0x03,0x74,0x38,0xd5]
+; CHECK: mrs x3, RVBAR_EL1 ; encoding: [0x23,0xc0,0x38,0xd5]
+; CHECK: mrs x3, RVBAR_EL2 ; encoding: [0x23,0xc0,0x3c,0xd5]
+; CHECK: mrs x3, RVBAR_EL3 ; encoding: [0x23,0xc0,0x3e,0xd5]
+; CHECK: mrs x3, SCR_EL3 ; encoding: [0x03,0x11,0x3e,0xd5]
+; CHECK: mrs x3, SCTLR_EL1 ; encoding: [0x03,0x10,0x38,0xd5]
+; CHECK: mrs x3, SCTLR_EL2 ; encoding: [0x03,0x10,0x3c,0xd5]
+; CHECK: mrs x3, SCTLR_EL3 ; encoding: [0x03,0x10,0x3e,0xd5]
+; CHECK: mrs x3, SDER32_EL3 ; encoding: [0x23,0x11,0x3e,0xd5]
+; CHECK: mrs x3, TCR_EL1 ; encoding: [0x43,0x20,0x38,0xd5]
+; CHECK: mrs x3, TCR_EL2 ; encoding: [0x43,0x20,0x3c,0xd5]
+; CHECK: mrs x3, TCR_EL3 ; encoding: [0x43,0x20,0x3e,0xd5]
+; CHECK: mrs x3, TEECR32_EL1 ; encoding: [0x03,0x00,0x32,0xd5]
+; CHECK: mrs x3, TEEHBR32_EL1 ; encoding: [0x03,0x10,0x32,0xd5]
+; CHECK: mrs x3, TPIDRRO_EL0 ; encoding: [0x63,0xd0,0x3b,0xd5]
+; CHECK: mrs x3, TPIDR_EL0 ; encoding: [0x43,0xd0,0x3b,0xd5]
+; CHECK: mrs x3, TPIDR_EL1 ; encoding: [0x83,0xd0,0x38,0xd5]
+; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5]
+; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5]
+; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5]
+; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5]
+; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5]
+; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5]
+; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5]
+; CHECK: mrs x3, VBAR_EL2 ; encoding: [0x03,0xc0,0x3c,0xd5]
+; CHECK: mrs x3, VBAR_EL3 ; encoding: [0x03,0xc0,0x3e,0xd5]
+; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5]
+; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5]
+; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5]
+; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5]
+; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5]
+; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5]
+; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5]
+; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5]
+; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5]
+; CHECK: mrs x3, DBGVCR32_EL2 ; encoding: [0x03,0x07,0x34,0xd5]
+; CHECK: mrs x3, OSDTRRX_EL1 ; encoding: [0x43,0x00,0x30,0xd5]
+; CHECK: mrs x3, MDSCR_EL1 ; encoding: [0x43,0x02,0x30,0xd5]
+; CHECK: mrs x3, OSDTRTX_EL1 ; encoding: [0x43,0x03,0x30,0xd5]
+; CHECK: mrs x3, OSECCR_EL11 ; encoding: [0x43,0x06,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR0_EL1 ; encoding: [0x83,0x00,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR1_EL1 ; encoding: [0x83,0x01,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR2_EL1 ; encoding: [0x83,0x02,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR3_EL1 ; encoding: [0x83,0x03,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR4_EL1 ; encoding: [0x83,0x04,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR5_EL1 ; encoding: [0x83,0x05,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR6_EL1 ; encoding: [0x83,0x06,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR7_EL1 ; encoding: [0x83,0x07,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR8_EL1 ; encoding: [0x83,0x08,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR9_EL1 ; encoding: [0x83,0x09,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR10_EL1 ; encoding: [0x83,0x0a,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR11_EL1 ; encoding: [0x83,0x0b,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR12_EL1 ; encoding: [0x83,0x0c,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR13_EL1 ; encoding: [0x83,0x0d,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR14_EL1 ; encoding: [0x83,0x0e,0x30,0xd5]
+; CHECK: mrs x3, DBGBVR15_EL1 ; encoding: [0x83,0x0f,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR0_EL1 ; encoding: [0xa3,0x00,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR1_EL1 ; encoding: [0xa3,0x01,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR2_EL1 ; encoding: [0xa3,0x02,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR3_EL1 ; encoding: [0xa3,0x03,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR4_EL1 ; encoding: [0xa3,0x04,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR5_EL1 ; encoding: [0xa3,0x05,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR6_EL1 ; encoding: [0xa3,0x06,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR7_EL1 ; encoding: [0xa3,0x07,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR8_EL1 ; encoding: [0xa3,0x08,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR9_EL1 ; encoding: [0xa3,0x09,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR10_EL1 ; encoding: [0xa3,0x0a,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR11_EL1 ; encoding: [0xa3,0x0b,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR12_EL1 ; encoding: [0xa3,0x0c,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR13_EL1 ; encoding: [0xa3,0x0d,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR14_EL1 ; encoding: [0xa3,0x0e,0x30,0xd5]
+; CHECK: mrs x3, DBGBCR15_EL1 ; encoding: [0xa3,0x0f,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR0_EL1 ; encoding: [0xc3,0x00,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR1_EL1 ; encoding: [0xc3,0x01,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR2_EL1 ; encoding: [0xc3,0x02,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR3_EL1 ; encoding: [0xc3,0x03,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR4_EL1 ; encoding: [0xc3,0x04,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR5_EL1 ; encoding: [0xc3,0x05,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR6_EL1 ; encoding: [0xc3,0x06,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR7_EL1 ; encoding: [0xc3,0x07,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR8_EL1 ; encoding: [0xc3,0x08,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR9_EL1 ; encoding: [0xc3,0x09,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR10_EL1 ; encoding: [0xc3,0x0a,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR11_EL1 ; encoding: [0xc3,0x0b,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR12_EL1 ; encoding: [0xc3,0x0c,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR13_EL1 ; encoding: [0xc3,0x0d,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR14_EL1 ; encoding: [0xc3,0x0e,0x30,0xd5]
+; CHECK: mrs x3, DBGWVR15_EL1 ; encoding: [0xc3,0x0f,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR0_EL1 ; encoding: [0xe3,0x00,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR1_EL1 ; encoding: [0xe3,0x01,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR2_EL1 ; encoding: [0xe3,0x02,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR3_EL1 ; encoding: [0xe3,0x03,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR4_EL1 ; encoding: [0xe3,0x04,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR5_EL1 ; encoding: [0xe3,0x05,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR6_EL1 ; encoding: [0xe3,0x06,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR7_EL1 ; encoding: [0xe3,0x07,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR8_EL1 ; encoding: [0xe3,0x08,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR9_EL1 ; encoding: [0xe3,0x09,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR10_EL1 ; encoding: [0xe3,0x0a,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR11_EL1 ; encoding: [0xe3,0x0b,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR12_EL1 ; encoding: [0xe3,0x0c,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR13_EL1 ; encoding: [0xe3,0x0d,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR14_EL1 ; encoding: [0xe3,0x0e,0x30,0xd5]
+; CHECK: mrs x3, DBGWCR15_EL1 ; encoding: [0xe3,0x0f,0x30,0xd5]
+; CHECK: mrs x3, MDRAR_EL1 ; encoding: [0x03,0x10,0x30,0xd5]
+; CHECK: mrs x3, OSLAR_EL1 ; encoding: [0x83,0x10,0x30,0xd5]
+; CHECK: mrs x3, OSLSR_EL1 ; encoding: [0x83,0x11,0x30,0xd5]
+; CHECK: mrs x3, OSDLR_EL1 ; encoding: [0x83,0x13,0x30,0xd5]
+; CHECK: mrs x3, DBGPRCR_EL1 ; encoding: [0x83,0x14,0x30,0xd5]
+; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5]
+; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5]
+; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5]
+; CHECK: mrs x3, DBGDEVID2 ; encoding: [0xe3,0x70,0x30,0xd5]
+; CHECK: mrs x3, DBGDEVID1 ; encoding: [0xe3,0x71,0x30,0xd5]
+; CHECK: mrs x3, DBGDEVID0 ; encoding: [0xe3,0x72,0x30,0xd5]
+; CHECK: mrs x1, S2_2_C4_C6_4 ; encoding: [0x81,0x46,0x32,0xd5]
+; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5]
+; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5]
+
+ msr RMR_EL3, x0
+ msr RMR_EL2, x0
+ msr RMR_EL1, x0
+ msr CPM_IOACC_CTL_EL3, x0
+
+; CHECK: msr RMR_EL3, x0 ; encoding: [0x40,0xc0,0x1e,0xd5]
+; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1a,0xd5]
+; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x19,0xd5]
+; CHECK: msr CPM_IOACC_CTL_EL3, x0 ; encoding: [0x00,0xf2,0x1f,0xd5]
+
+ mrs x0, ID_PFR0_EL1
+ mrs x0, ID_PFR1_EL1
+ mrs x0, ID_DFR0_EL1
+ mrs x0, ID_AFR0_EL1
+ mrs x0, ID_ISAR0_EL1
+ mrs x0, ID_ISAR1_EL1
+ mrs x0, ID_ISAR2_EL1
+ mrs x0, ID_ISAR3_EL1
+ mrs x0, ID_ISAR4_EL1
+ mrs x0, ID_ISAR5_EL1
+ mrs x0, AFSR1_EL1
+ mrs x0, AFSR0_EL1
+ mrs x0, REVIDR_EL1
+; CHECK: mrs x0, ID_PFR0_EL1 ; encoding: [0x00,0x01,0x38,0xd5]
+; CHECK: mrs x0, ID_PFR1_EL1 ; encoding: [0x20,0x01,0x38,0xd5]
+; CHECK: mrs x0, ID_DFR0_EL1 ; encoding: [0x40,0x01,0x38,0xd5]
+; CHECK: mrs x0, ID_AFR0_EL1 ; encoding: [0x60,0x01,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR0_EL1 ; encoding: [0x00,0x02,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR1_EL1 ; encoding: [0x20,0x02,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR2_EL1 ; encoding: [0x40,0x02,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR3_EL1 ; encoding: [0x60,0x02,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR4_EL1 ; encoding: [0x80,0x02,0x38,0xd5]
+; CHECK: mrs x0, ID_ISAR5_EL1 ; encoding: [0xa0,0x02,0x38,0xd5]
+; CHECK: mrs x0, AFSR1_EL1 ; encoding: [0x20,0x51,0x38,0xd5]
+; CHECK: mrs x0, AFSR0_EL1 ; encoding: [0x00,0x51,0x38,0xd5]
+; CHECK: mrs x0, REVIDR_EL1 ; encoding: [0xc0,0x00,0x38,0xd5]
Added: llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s (added)
+++ llvm/trunk/test/MC/ARM64/tls-modifiers-darwin.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,13 @@
+; RUN: llvm-mc -triple=arm64-apple-ios7.0 %s -o - | FileCheck %s
+; RUN: llvm-mc -triple=arm64-apple-ios7.0 -filetype=obj %s -o - | llvm-objdump -r - | FileCheck %s --check-prefix=CHECK-OBJ
+
+ adrp x2, _var at TLVPPAGE
+ ldr x0, [x15, _var at TLVPPAGEOFF]
+ add lr, x0, _var at TLVPPAGEOFF
+; CHECK: adrp x2, _var at TLVPPAG
+; CHECK: ldr x0, [x15, _var at TLVPPAGEOFF]
+; CHECK: add lr, x0, _var at TLVPPAGEOFF
+
+; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
+; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var
+; CHECK-OBJ: 0 ARM64_RELOC_TLVP_LOAD_PAGE21 _var
Added: llvm/trunk/test/MC/ARM64/tls-relocs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/tls-relocs.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/tls-relocs.s (added)
+++ llvm/trunk/test/MC/ARM64/tls-relocs.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,320 @@
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s
+
+
+////////////////////////////////////////////////////////////////////////////////
+// TLS initial-exec forms
+////////////////////////////////////////////////////////////////////////////////
+
+ movz x15, #:gottprel_g1:var
+// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw
+
+// CHECK-ELF: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM:[^ ]+]]
+
+
+ movk x13, #:gottprel_g0_nc:var
+// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw
+
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]]
+
+ adrp x11, :gottprel:var
+ ldr x10, [x0, #:gottprel_lo12:var]
+ ldr x9, :gottprel:var
+// CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58]
+// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_imm19
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]]
+
+
+////////////////////////////////////////////////////////////////////////////////
+// TLS local-exec forms
+////////////////////////////////////////////////////////////////////////////////
+
+ movz x3, #:tprel_g2:var
+ movn x4, #:tprel_g2:var
+// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]]
+
+
+ movz x5, #:tprel_g1:var
+ movn x6, #:tprel_g1:var
+ movz w7, #:tprel_g1:var
+// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]]
+
+
+ movk x9, #:tprel_g1_nc:var
+ movk w10, #:tprel_g1_nc:var
+// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]]
+
+
+ movz x11, #:tprel_g0:var
+ movn x12, #:tprel_g0:var
+ movz w13, #:tprel_g0:var
+// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]]
+
+
+ movk x15, #:tprel_g0_nc:var
+ movk w16, #:tprel_g0_nc:var
+// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]]
+
+
+ add x21, x22, #:tprel_lo12:var
+// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]]
+
+
+ add x25, x26, #:tprel_lo12_nc:var
+// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]]
+
+
+ ldrb w29, [x30, #:tprel_lo12:var]
+ ldrsb x29, [x28, #:tprel_lo12_nc:var]
+// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK: ldrsb fp, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]]
+
+
+ strh w27, [x26, #:tprel_lo12:var]
+ ldrsh x25, [x24, #:tprel_lo12_nc:var]
+// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]]
+
+
+ ldr w23, [x22, #:tprel_lo12:var]
+ ldrsw x21, [x20, #:tprel_lo12_nc:var]
+// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]]
+
+ ldr x19, [x18, #:tprel_lo12:var]
+ str x17, [x16, #:tprel_lo12_nc:var]
+// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]]
+
+
+////////////////////////////////////////////////////////////////////////////////
+// TLS local-dynamic forms
+////////////////////////////////////////////////////////////////////////////////
+
+ movz x3, #:dtprel_g2:var
+ movn x4, #:dtprel_g2:var
+// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]]
+
+
+ movz x5, #:dtprel_g1:var
+ movn x6, #:dtprel_g1:var
+ movz w7, #:dtprel_g1:var
+// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
+
+
+ movk x9, #:dtprel_g1_nc:var
+ movk w10, #:dtprel_g1_nc:var
+// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]]
+
+
+ movz x11, #:dtprel_g0:var
+ movn x12, #:dtprel_g0:var
+ movz w13, #:dtprel_g0:var
+// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]]
+
+
+ movk x15, #:dtprel_g0_nc:var
+ movk w16, #:dtprel_g0_nc:var
+// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]]
+
+
+ add x21, x22, #:dtprel_lo12:var
+// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]]
+
+
+ add x25, x26, #:dtprel_lo12_nc:var
+// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]]
+
+
+ ldrb w29, [x30, #:dtprel_lo12:var]
+ ldrsb x29, [x28, #:dtprel_lo12_nc:var]
+// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
+// CHECK: ldrsb fp, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]]
+
+
+ strh w27, [x26, #:dtprel_lo12:var]
+ ldrsh x25, [x24, #:dtprel_lo12_nc:var]
+// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2
+// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]]
+
+
+ ldr w23, [x22, #:dtprel_lo12:var]
+ ldrsw x21, [x20, #:dtprel_lo12_nc:var]
+// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4
+// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]]
+
+ ldr x19, [x18, #:dtprel_lo12:var]
+ str x17, [x16, #:dtprel_lo12_nc:var]
+// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]]
+
+////////////////////////////////////////////////////////////////////////////////
+// TLS descriptor forms
+////////////////////////////////////////////////////////////////////////////////
+
+ adrp x8, :tlsdesc:var
+ ldr x7, [x6, #:tlsdesc_lo12:var]
+ add x5, x4, #:tlsdesc_lo12:var
+ .tlsdesccall var
+ blr x3
+
+// CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A']
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21
+// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8
+// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91]
+// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12
+// CHECK: .tlsdesccall var // encoding: []
+// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call
+// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6]
+
+
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]]
+// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSDESC_CALL [[VARSYM]]
+
+ // Make sure symbol 5 has type STT_TLS:
+
+// CHECK-ELF: Symbols [
+// CHECK-ELF: Symbol {
+// CHECK-ELF: Name: var (6)
+// CHECK-ELF-NEXT: Value:
+// CHECK-ELF-NEXT: Size:
+// CHECK-ELF-NEXT: Binding: Global
+// CHECK-ELF-NEXT: Type: TLS
Added: llvm/trunk/test/MC/ARM64/variable-exprs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM64/variable-exprs.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM64/variable-exprs.s (added)
+++ llvm/trunk/test/MC/ARM64/variable-exprs.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,40 @@
+// RUN: llvm-mc -triple arm64-apple-darwin10 %s -filetype=obj -o %t.o
+
+.data
+
+ .long 0
+a:
+ .long 0
+b = a
+
+c: .long b
+
+d2 = d
+.globl d2
+d3 = d + 4
+.globl d3
+
+e = a + 4
+
+g:
+f = g
+ .long 0
+
+ .long b
+ .long e
+ .long a + 4
+ .long d
+ .long d2
+ .long d3
+ .long f
+ .long g
+
+///
+ .text
+t0:
+Lt0_a:
+ .long 0
+
+ .section __DWARF,__debug_frame,regular,debug
+Lt1 = Lt0_a
+ .long Lt1
Added: llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/advsimd.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,2282 @@
+# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s
+
+0x00 0xb8 0x20 0x0e
+0x00 0xb8 0x20 0x4e
+0x00 0xb8 0x60 0x0e
+0x00 0xb8 0x60 0x4e
+0x00 0xb8 0xa0 0x0e
+0x00 0xb8 0xa0 0x4e
+
+# CHECK: abs.8b v0, v0
+# CHECK: abs.16b v0, v0
+# CHECK: abs.4h v0, v0
+# CHECK: abs.8h v0, v0
+# CHECK: abs.2s v0, v0
+# CHECK: abs.4s v0, v0
+
+0x00 0x84 0x20 0x0e
+0x00 0x84 0x20 0x4e
+0x00 0x84 0x60 0x0e
+0x00 0x84 0x60 0x4e
+0x00 0x84 0xa0 0x0e
+0x00 0x84 0xa0 0x4e
+0x00 0x84 0xe0 0x4e
+
+# CHECK: add.8b v0, v0, v0
+# CHECK: add.16b v0, v0, v0
+# CHECK: add.4h v0, v0, v0
+# CHECK: add.8h v0, v0, v0
+# CHECK: add.2s v0, v0, v0
+# CHECK: add.4s v0, v0, v0
+# CHECK: add.2d v0, v0, v0
+
+0x41 0x84 0xe3 0x5e
+
+# CHECK: add d1, d2, d3
+
+0x00 0x40 0x20 0x0e
+0x00 0x40 0x20 0x4e
+0x00 0x40 0x60 0x0e
+0x00 0x40 0x60 0x4e
+0x00 0x40 0xa0 0x0e
+0x00 0x40 0xa0 0x4e
+
+# CHECK: addhn.8b v0, v0, v0
+# CHECK: addhn2.16b v0, v0, v0
+# CHECK: addhn.4h v0, v0, v0
+# CHECK: addhn2.8h v0, v0, v0
+# CHECK: addhn.2s v0, v0, v0
+# CHECK: addhn2.4s v0, v0, v0
+
+0x00 0xbc 0x20 0x0e
+0x00 0xbc 0x20 0x4e
+0x00 0xbc 0x60 0x0e
+0x00 0xbc 0x60 0x4e
+0x00 0xbc 0xa0 0x0e
+0x00 0xbc 0xa0 0x4e
+0x00 0xbc 0xe0 0x4e
+
+# CHECK: addp.8b v0, v0, v0
+# CHECK: addp.16b v0, v0, v0
+# CHECK: addp.4h v0, v0, v0
+# CHECK: addp.8h v0, v0, v0
+# CHECK: addp.2s v0, v0, v0
+# CHECK: addp.4s v0, v0, v0
+# CHECK: addp.2d v0, v0, v0
+
+0x00 0xb8 0xf1 0x5e
+
+# CHECK: addp.2d d0, v0
+
+0x00 0xb8 0x31 0x0e
+0x00 0xb8 0x31 0x4e
+0x00 0xb8 0x71 0x0e
+0x00 0xb8 0x71 0x4e
+0x00 0xb8 0xb1 0x4e
+
+# CHECK: addv.8b b0, v0
+# CHECK: addv.16b b0, v0
+# CHECK: addv.4h h0, v0
+# CHECK: addv.8h h0, v0
+# CHECK: addv.4s s0, v0
+
+
+# INS/DUP
+0x60 0x0c 0x08 0x4e
+0x60 0x0c 0x04 0x4e
+0x60 0x0c 0x04 0x0e
+0x60 0x0c 0x02 0x4e
+0x60 0x0c 0x02 0x0e
+0x60 0x0c 0x01 0x4e
+0x60 0x0c 0x01 0x0e
+
+# CHECK: dup.2d v0, x3
+# CHECK: dup.4s v0, w3
+# CHECK: dup.2s v0, w3
+# CHECK: dup.8h v0, w3
+# CHECK: dup.4h v0, w3
+# CHECK: dup.16b v0, w3
+# CHECK: dup.8b v0, w3
+
+0x60 0x04 0x18 0x4e
+0x60 0x04 0x0c 0x0e
+0x60 0x04 0x0c 0x4e
+0x60 0x04 0x06 0x0e
+0x60 0x04 0x06 0x4e
+0x60 0x04 0x03 0x0e
+0x60 0x04 0x03 0x4e
+
+# CHECK: dup.2d v0, v3[1]
+# CHECK: dup.2s v0, v3[1]
+# CHECK: dup.4s v0, v3[1]
+# CHECK: dup.4h v0, v3[1]
+# CHECK: dup.8h v0, v3[1]
+# CHECK: dup.8b v0, v3[1]
+# CHECK: dup.16b v0, v3[1]
+
+
+0x43 0x2c 0x14 0x4e
+0x43 0x2c 0x14 0x4e
+0x43 0x3c 0x14 0x0e
+0x43 0x3c 0x14 0x0e
+0x43 0x3c 0x18 0x4e
+0x43 0x3c 0x18 0x4e
+
+# CHECK: smov.s x3, v2[2]
+# CHECK: smov.s x3, v2[2]
+# CHECK: umov.s w3, v2[2]
+# CHECK: umov.s w3, v2[2]
+# CHECK: umov.d x3, v2[1]
+# CHECK: umov.d x3, v2[1]
+
+0xa2 0x1c 0x18 0x4e
+0xa2 0x1c 0x0c 0x4e
+0xa2 0x1c 0x06 0x4e
+0xa2 0x1c 0x03 0x4e
+
+0xa2 0x1c 0x18 0x4e
+0xa2 0x1c 0x0c 0x4e
+0xa2 0x1c 0x06 0x4e
+0xa2 0x1c 0x03 0x4e
+
+# CHECK: ins.d v2[1], x5
+# CHECK: ins.s v2[1], w5
+# CHECK: ins.h v2[1], w5
+# CHECK: ins.b v2[1], w5
+
+# CHECK: ins.d v2[1], x5
+# CHECK: ins.s v2[1], w5
+# CHECK: ins.h v2[1], w5
+# CHECK: ins.b v2[1], w5
+
+0xe2 0x45 0x18 0x6e
+0xe2 0x25 0x0c 0x6e
+0xe2 0x15 0x06 0x6e
+0xe2 0x0d 0x03 0x6e
+
+0xe2 0x05 0x18 0x6e
+0xe2 0x45 0x1c 0x6e
+0xe2 0x35 0x1e 0x6e
+0xe2 0x2d 0x15 0x6e
+
+# CHECK: ins.d v2[1], v15[1]
+# CHECK: ins.s v2[1], v15[1]
+# CHECK: ins.h v2[1], v15[1]
+# CHECK: ins.b v2[1], v15[1]
+
+# CHECK: ins.d v2[1], v15[0]
+# CHECK: ins.s v2[3], v15[2]
+# CHECK: ins.h v2[7], v15[3]
+# CHECK: ins.b v2[10], v15[5]
+
+0x00 0x1c 0x20 0x0e
+0x00 0x1c 0x20 0x4e
+
+# CHECK: and.8b v0, v0, v0
+# CHECK: and.16b v0, v0, v0
+
+0x00 0x1c 0x60 0x0e
+
+# CHECK: bic.8b v0, v0, v0
+
+0x00 0x8c 0x20 0x2e
+0x00 0x3c 0x20 0x0e
+0x00 0x34 0x20 0x0e
+0x00 0x34 0x20 0x2e
+0x00 0x3c 0x20 0x2e
+0x00 0x8c 0x20 0x0e
+0x00 0xd4 0xa0 0x2e
+0x00 0xec 0x20 0x2e
+0x00 0xec 0xa0 0x2e
+0x00 0xd4 0x20 0x2e
+0x00 0xd4 0x20 0x0e
+0x00 0xe4 0x20 0x0e
+0x00 0xe4 0x20 0x2e
+0x00 0xe4 0xa0 0x2e
+0x00 0xfc 0x20 0x2e
+0x00 0xc4 0x20 0x2e
+0x00 0xc4 0x20 0x0e
+0x00 0xf4 0x20 0x2e
+0x00 0xf4 0x20 0x0e
+0x00 0xc4 0xa0 0x2e
+0x00 0xc4 0xa0 0x0e
+0x00 0xf4 0xa0 0x2e
+0x00 0xf4 0xa0 0x0e
+0x00 0xcc 0x20 0x0e
+0x00 0xcc 0xa0 0x0e
+0x00 0xdc 0x20 0x0e
+0x00 0xdc 0x20 0x2e
+0x00 0xfc 0x20 0x0e
+0x00 0xfc 0xa0 0x0e
+0x00 0xd4 0xa0 0x0e
+0x00 0x94 0x20 0x0e
+0x00 0x94 0x20 0x2e
+0x00 0x9c 0x20 0x0e
+0x00 0x9c 0x20 0x2e
+0x00 0x7c 0x20 0x0e
+0x00 0x74 0x20 0x0e
+0x00 0x04 0x20 0x0e
+0x00 0x24 0x20 0x0e
+0x00 0xa4 0x20 0x0e
+0x00 0x64 0x20 0x0e
+0x00 0xac 0x20 0x0e
+0x00 0x6c 0x20 0x0e
+0x00 0x0c 0x20 0x0e
+0x00 0xb4 0x60 0x0e
+0x00 0xb4 0x60 0x2e
+0x00 0x5c 0x20 0x0e
+0x00 0x4c 0x20 0x0e
+0x00 0x2c 0x20 0x0e
+0x00 0x14 0x20 0x0e
+0x00 0x54 0x20 0x0e
+0x00 0x44 0x20 0x0e
+0x00 0x84 0x20 0x2e
+0x00 0x7c 0x20 0x2e
+0x00 0x74 0x20 0x2e
+0x00 0x04 0x20 0x2e
+0x00 0x24 0x20 0x2e
+0x00 0xa4 0x20 0x2e
+0x00 0x64 0x20 0x2e
+0x00 0xac 0x20 0x2e
+0x00 0x6c 0x20 0x2e
+0x00 0x0c 0x20 0x2e
+0x00 0x5c 0x20 0x2e
+0x00 0x4c 0x20 0x2e
+0x00 0x2c 0x20 0x2e
+0x00 0x14 0x20 0x2e
+0x00 0x54 0x20 0x2e
+0x00 0x44 0x20 0x2e
+
+# CHECK: cmeq.8b v0, v0, v0
+# CHECK: cmge.8b v0, v0, v0
+# CHECK: cmgt.8b v0, v0, v0
+# CHECK: cmhi.8b v0, v0, v0
+# CHECK: cmhs.8b v0, v0, v0
+# CHECK: cmtst.8b v0, v0, v0
+# CHECK: fabd.2s v0, v0, v0
+# CHECK: facge.2s v0, v0, v0
+# CHECK: facgt.2s v0, v0, v0
+# CHECK: faddp.2s v0, v0, v0
+# CHECK: fadd.2s v0, v0, v0
+# CHECK: fcmeq.2s v0, v0, v0
+# CHECK: fcmge.2s v0, v0, v0
+# CHECK: fcmgt.2s v0, v0, v0
+# CHECK: fdiv.2s v0, v0, v0
+# CHECK: fmaxnmp.2s v0, v0, v0
+# CHECK: fmaxnm.2s v0, v0, v0
+# CHECK: fmaxp.2s v0, v0, v0
+# CHECK: fmax.2s v0, v0, v0
+# CHECK: fminnmp.2s v0, v0, v0
+# CHECK: fminnm.2s v0, v0, v0
+# CHECK: fminp.2s v0, v0, v0
+# CHECK: fmin.2s v0, v0, v0
+# CHECK: fmla.2s v0, v0, v0
+# CHECK: fmls.2s v0, v0, v0
+# CHECK: fmulx.2s v0, v0, v0
+# CHECK: fmul.2s v0, v0, v0
+# CHECK: frecps.2s v0, v0, v0
+# CHECK: frsqrts.2s v0, v0, v0
+# CHECK: fsub.2s v0, v0, v0
+# CHECK: mla.8b v0, v0, v0
+# CHECK: mls.8b v0, v0, v0
+# CHECK: mul.8b v0, v0, v0
+# CHECK: pmul.8b v0, v0, v0
+# CHECK: saba.8b v0, v0, v0
+# CHECK: sabd.8b v0, v0, v0
+# CHECK: shadd.8b v0, v0, v0
+# CHECK: shsub.8b v0, v0, v0
+# CHECK: smaxp.8b v0, v0, v0
+# CHECK: smax.8b v0, v0, v0
+# CHECK: sminp.8b v0, v0, v0
+# CHECK: smin.8b v0, v0, v0
+# CHECK: sqadd.8b v0, v0, v0
+# CHECK: sqdmulh.4h v0, v0, v0
+# CHECK: sqrdmulh.4h v0, v0, v0
+# CHECK: sqrshl.8b v0, v0, v0
+# CHECK: sqshl.8b v0, v0, v0
+# CHECK: sqsub.8b v0, v0, v0
+# CHECK: srhadd.8b v0, v0, v0
+# CHECK: srshl.8b v0, v0, v0
+# CHECK: sshl.8b v0, v0, v0
+# CHECK: sub.8b v0, v0, v0
+# CHECK: uaba.8b v0, v0, v0
+# CHECK: uabd.8b v0, v0, v0
+# CHECK: uhadd.8b v0, v0, v0
+# CHECK: uhsub.8b v0, v0, v0
+# CHECK: umaxp.8b v0, v0, v0
+# CHECK: umax.8b v0, v0, v0
+# CHECK: uminp.8b v0, v0, v0
+# CHECK: umin.8b v0, v0, v0
+# CHECK: uqadd.8b v0, v0, v0
+# CHECK: uqrshl.8b v0, v0, v0
+# CHECK: uqshl.8b v0, v0, v0
+# CHECK: uqsub.8b v0, v0, v0
+# CHECK: urhadd.8b v0, v0, v0
+# CHECK: urshl.8b v0, v0, v0
+# CHECK: ushl.8b v0, v0, v0
+
+0x00 0x1c 0xe0 0x2e
+0x00 0x1c 0xa0 0x2e
+0x00 0x1c 0x60 0x2e
+0x00 0x1c 0x20 0x2e
+0x00 0x1c 0xe0 0x0e
+0x00 0x1c 0xa0 0x0e
+
+# CHECK: bif.8b v0, v0, v0
+# CHECK: bit.8b v0, v0, v0
+# CHECK: bsl.8b v0, v0, v0
+# CHECK: eor.8b v0, v0, v0
+# CHECK: orn.8b v0, v0, v0
+# CHECK: orr.8b v0, v0, v0
+
+0x00 0x68 0x20 0x0e
+0x00 0x68 0x20 0x4e
+0x00 0x68 0x60 0x0e
+0x00 0x68 0x60 0x4e
+0x00 0x68 0xa0 0x0e
+0x00 0x68 0xa0 0x4e
+
+# CHECK: sadalp.4h v0, v0
+# CHECK: sadalp.8h v0, v0
+# CHECK: sadalp.2s v0, v0
+# CHECK: sadalp.4s v0, v0
+# CHECK: sadalp.1d v0, v0
+# CHECK: sadalp.2d v0, v0
+
+0x00 0x48 0x20 0x0e
+0x00 0x48 0x20 0x2e
+0x00 0x58 0x20 0x0e
+0x00 0xf8 0xa0 0x0e
+0x00 0xc8 0x21 0x0e
+0x00 0xc8 0x21 0x2e
+0x00 0xb8 0x21 0x0e
+0x00 0xb8 0x21 0x2e
+0x00 0xa8 0x21 0x0e
+0x00 0xa8 0x21 0x2e
+0x00 0xa8 0xa1 0x0e
+0x00 0xa8 0xa1 0x2e
+0x00 0xb8 0xa1 0x0e
+0x00 0xb8 0xa1 0x2e
+0x00 0xf8 0xa0 0x2e
+0x00 0xd8 0xa1 0x0e
+0x00 0xd8 0xa1 0x2e
+0x00 0xf8 0xa1 0x2e
+0x00 0xb8 0x20 0x2e
+0x00 0x58 0x20 0x2e
+0x00 0x58 0x60 0x2e
+0x00 0x18 0x20 0x0e
+0x00 0x08 0x20 0x2e
+0x00 0x08 0x20 0x0e
+0x00 0x68 0x20 0x0e
+0x00 0x28 0x20 0x0e
+0x00 0xd8 0x21 0x0e
+0x00 0x38 0x21 0x2e
+0x00 0x78 0x20 0x0e
+0x00 0x78 0x20 0x2e
+0x00 0x48 0x21 0x0e
+0x00 0x28 0x21 0x2e
+0x00 0x38 0x20 0x0e
+0x00 0x68 0x20 0x2e
+0x00 0x28 0x20 0x2e
+0x00 0xd8 0x21 0x2e
+0x00 0x48 0x21 0x2e
+0x00 0xc8 0xa1 0x0e
+0x00 0xc8 0xa1 0x2e
+0x00 0x38 0x20 0x2e
+0x00 0x28 0x21 0x0e
+0x00 0x48 0x20 0x0e
+0x00 0x48 0x20 0x2e
+0x00 0x58 0x20 0x0e
+0x00 0xf8 0xa0 0x0e
+0x00 0xc8 0x21 0x0e
+0x00 0xc8 0x21 0x2e
+0x00 0xb8 0x21 0x0e
+0x00 0xb8 0x21 0x2e
+0x00 0xa8 0x21 0x0e
+0x00 0xa8 0x21 0x2e
+0x00 0xa8 0xa1 0x0e
+0x00 0xa8 0xa1 0x2e
+0x00 0xb8 0xa1 0x0e
+0x00 0xb8 0xa1 0x2e
+0x00 0xf8 0xa0 0x2e
+0x00 0xd8 0xa1 0x0e
+0x00 0xd8 0xa1 0x2e
+0x00 0xf8 0xa1 0x2e
+0x00 0xb8 0x20 0x2e
+0x00 0x58 0x20 0x2e
+0x00 0x58 0x60 0x2e
+0x00 0x18 0x20 0x0e
+0x00 0x08 0x20 0x2e
+0x00 0x08 0x20 0x0e
+0x00 0x68 0x20 0x0e
+0x00 0x28 0x20 0x0e
+0x00 0xd8 0x21 0x0e
+0x00 0x38 0x21 0x2e
+0x00 0x78 0x20 0x0e
+0x00 0x78 0x20 0x2e
+0x00 0x48 0x21 0x0e
+0x00 0x28 0x21 0x2e
+0x00 0x38 0x20 0x0e
+0x00 0x68 0x20 0x2e
+0x00 0x28 0x20 0x2e
+0x00 0xd8 0x21 0x2e
+0x00 0x48 0x21 0x2e
+0x00 0xc8 0xa1 0x0e
+0x00 0xc8 0xa1 0x2e
+0x00 0x38 0x20 0x2e
+0x00 0x28 0x21 0x0e
+
+# CHECK: cls.8b v0, v0
+# CHECK: clz.8b v0, v0
+# CHECK: cnt.8b v0, v0
+# CHECK: fabs.2s v0, v0
+# CHECK: fcvtas.2s v0, v0
+# CHECK: fcvtau.2s v0, v0
+# CHECK: fcvtms.2s v0, v0
+# CHECK: fcvtmu.2s v0, v0
+# CHECK: fcvtns.2s v0, v0
+# CHECK: fcvtnu.2s v0, v0
+# CHECK: fcvtps.2s v0, v0
+# CHECK: fcvtpu.2s v0, v0
+# CHECK: fcvtzs.2s v0, v0
+# CHECK: fcvtzu.2s v0, v0
+# CHECK: fneg.2s v0, v0
+# CHECK: frecpe.2s v0, v0
+# CHECK: frsqrte.2s v0, v0
+# CHECK: fsqrt.2s v0, v0
+# CHECK: neg.8b v0, v0
+# CHECK: not.8b v0, v0
+# CHECK: rbit.8b v0, v0
+# CHECK: rev16.8b v0, v0
+# CHECK: rev32.8b v0, v0
+# CHECK: rev64.8b v0, v0
+# CHECK: sadalp.4h v0, v0
+# CHECK: saddlp.4h v0, v0
+# CHECK: scvtf.2s v0, v0
+# CHECK: shll.8h v0, v0, #8
+# CHECK: sqabs.8b v0, v0
+# CHECK: sqneg.8b v0, v0
+# CHECK: sqxtn.8b v0, v0
+# CHECK: sqxtun.8b v0, v0
+# CHECK: suqadd.8b v0, v0
+# CHECK: uadalp.4h v0, v0
+# CHECK: uaddlp.4h v0, v0
+# CHECK: ucvtf.2s v0, v0
+# CHECK: uqxtn.8b v0, v0
+# CHECK: urecpe.2s v0, v0
+# CHECK: ursqrte.2s v0, v0
+# CHECK: usqadd.8b v0, v0
+# CHECK: xtn.8b v0, v0
+
+0x00 0x98 0x20 0x0e
+0x00 0x98 0x20 0x4e
+0x00 0x98 0x60 0x0e
+0x00 0x98 0x60 0x4e
+0x00 0x98 0xa0 0x0e
+0x00 0x98 0xa0 0x4e
+0x00 0x98 0xe0 0x4e
+
+# CHECK: cmeq.8b v0, v0, #0
+# CHECK: cmeq.16b v0, v0, #0
+# CHECK: cmeq.4h v0, v0, #0
+# CHECK: cmeq.8h v0, v0, #0
+# CHECK: cmeq.2s v0, v0, #0
+# CHECK: cmeq.4s v0, v0, #0
+# CHECK: cmeq.2d v0, v0, #0
+
+0x00 0x88 0x20 0x2e
+0x00 0x88 0x20 0x0e
+0x00 0x98 0x20 0x2e
+0x00 0xa8 0x20 0x0e
+0x00 0xd8 0xa0 0x0e
+0x00 0xc8 0xa0 0x2e
+0x00 0xc8 0xa0 0x0e
+0x00 0xd8 0xa0 0x2e
+0x00 0xe8 0xa0 0x0e
+
+# CHECK: cmge.8b v0, v0, #0
+# CHECK: cmgt.8b v0, v0, #0
+# CHECK: cmle.8b v0, v0, #0
+# CHECK: cmlt.8b v0, v0, #0
+# CHECK: fcmeq.2s v0, v0, #0
+# CHECK: fcmge.2s v0, v0, #0
+# CHECK: fcmgt.2s v0, v0, #0
+# CHECK: fcmle.2s v0, v0, #0
+# CHECK: fcmlt.2s v0, v0, #0
+
+0x00 0x78 0x21 0x0e
+0x00 0x78 0x21 0x4e
+0x00 0x78 0x61 0x0e
+0x00 0x78 0x61 0x4e
+0x00 0x68 0x21 0x0e
+0x00 0x68 0x21 0x4e
+0x00 0x68 0x61 0x0e
+0x00 0x68 0x61 0x4e
+0x00 0x68 0x61 0x2e
+0x00 0x68 0x61 0x6e
+
+# CHECK: fcvtl v0.4s, v0.4h
+# CHECK: fcvtl2 v0.4s, v0.8h
+# CHECK: fcvtl v0.2d, v0.2s
+# CHECK: fcvtl2 v0.2d, v0.4s
+# CHECK: fcvtn v0.4h, v0.4s
+# CHECK: fcvtn2 v0.8h, v0.4s
+# CHECK: fcvtn v0.2s, v0.2d
+# CHECK: fcvtn2 v0.4s, v0.2d
+# CHECK: fcvtxn v0.2s, v0.2d
+# CHECK: fcvtxn2 v0.4s, v0.2d
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD modified immediate instructions
+#===-------------------------------------------------------------------------===
+
+0x20 0x14 0x00 0x2f
+0x20 0x34 0x00 0x2f
+0x20 0x54 0x00 0x2f
+0x20 0x74 0x00 0x2f
+
+# CHECK: bic.2s v0, #1
+# CHECK: bic.2s v0, #1, lsl #8
+# CHECK: bic.2s v0, #1, lsl #16
+# CHECK: bic.2s v0, #1, lsl #24
+
+0x20 0x94 0x00 0x2f
+0x20 0x94 0x00 0x2f
+0x20 0xb4 0x00 0x2f
+
+# CHECK: bic.4h v0, #1
+# CHECK: bic.4h v0, #1
+# FIXME: bic.4h v0, #1, lsl #8
+# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
+
+0x20 0x14 0x00 0x6f
+0x20 0x34 0x00 0x6f
+0x20 0x54 0x00 0x6f
+0x20 0x74 0x00 0x6f
+
+# CHECK: bic.4s v0, #1
+# CHECK: bic.4s v0, #1, lsl #8
+# CHECK: bic.4s v0, #1, lsl #16
+# CHECK: bic.4s v0, #1, lsl #24
+
+0x20 0x94 0x00 0x6f
+0x20 0xb4 0x00 0x6f
+
+# CHECK: bic.8h v0, #1
+# FIXME: bic.8h v0, #1, lsl #8
+# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
+
+0x00 0xf4 0x02 0x6f
+
+# CHECK: fmov.2d v0, #1.250000e-01
+
+0x00 0xf4 0x02 0x0f
+0x00 0xf4 0x02 0x4f
+
+# CHECK: fmov.2s v0, #1.250000e-01
+# CHECK: fmov.4s v0, #1.250000e-01
+
+0x20 0x14 0x00 0x0f
+0x20 0x34 0x00 0x0f
+0x20 0x54 0x00 0x0f
+0x20 0x74 0x00 0x0f
+
+# CHECK: orr.2s v0, #1
+# CHECK: orr.2s v0, #1, lsl #8
+# CHECK: orr.2s v0, #1, lsl #16
+# CHECK: orr.2s v0, #1, lsl #24
+
+0x20 0x94 0x00 0x0f
+0x20 0xb4 0x00 0x0f
+
+# CHECK: orr.4h v0, #1
+# FIXME: orr.4h v0, #1, lsl #8
+# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
+
+0x20 0x14 0x00 0x4f
+0x20 0x34 0x00 0x4f
+0x20 0x54 0x00 0x4f
+0x20 0x74 0x00 0x4f
+
+# CHECK: orr.4s v0, #1
+# CHECK: orr.4s v0, #1, lsl #8
+# CHECK: orr.4s v0, #1, lsl #16
+# CHECK: orr.4s v0, #1, lsl #24
+
+0x20 0x94 0x00 0x4f
+0x20 0xb4 0x00 0x4f
+
+# CHECK: orr.8h v0, #1
+# FIXME: orr.8h v0, #1, lsl #8
+# "orr.8h" should be selected over "fcvtns.4s v0, v1, #0"
+
+0x21 0x70 0x40 0x0c
+0x42 0xa0 0x40 0x4c
+0x64 0x64 0x40 0x0c
+0x87 0x24 0x40 0x4c
+0x0c 0xa8 0x40 0x0c
+0x0a 0x68 0x40 0x4c
+0x2d 0xac 0x40 0x0c
+0x4f 0x7c 0x40 0x4c
+
+# CHECK: ld1.8b { v1 }, [x1]
+# CHECK: ld1.16b { v2, v3 }, [x2]
+# CHECK: ld1.4h { v4, v5, v6 }, [x3]
+# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4]
+# CHECK: ld1.2s { v12, v13 }, [x0]
+# CHECK: ld1.4s { v10, v11, v12 }, [x0]
+# CHECK: ld1.1d { v13, v14 }, [x1]
+# CHECK: ld1.2d { v15 }, [x2]
+
+0x41 0x70 0xdf 0x0c
+0x41 0xa0 0xdf 0x0c
+0x41 0x60 0xdf 0x0c
+0x41 0x20 0xdf 0x0c
+0x42 0x70 0xdf 0x4c
+0x42 0xa0 0xdf 0x4c
+0x42 0x60 0xdf 0x4c
+0x42 0x20 0xdf 0x4c
+0x64 0x74 0xdf 0x0c
+0x64 0xa4 0xdf 0x0c
+0x64 0x64 0xdf 0x0c
+0x64 0x24 0xdf 0x0c
+0x87 0x74 0xdf 0x4c
+0x87 0xa4 0xdf 0x4c
+0x87 0x64 0xdf 0x4c
+0x87 0x24 0xdf 0x4c
+0x0c 0x78 0xdf 0x0c
+0x0c 0xa8 0xdf 0x0c
+0x0c 0x68 0xdf 0x0c
+0x0c 0x28 0xdf 0x0c
+0x0a 0x78 0xdf 0x4c
+0x0a 0xa8 0xdf 0x4c
+0x0a 0x68 0xdf 0x4c
+0x0a 0x28 0xdf 0x4c
+0x2d 0x7c 0xdf 0x0c
+0x2d 0xac 0xdf 0x0c
+0x2d 0x6c 0xdf 0x0c
+0x2d 0x2c 0xdf 0x0c
+0x4f 0x7c 0xdf 0x4c
+0x4f 0xac 0xdf 0x4c
+0x4f 0x6c 0xdf 0x4c
+0x4f 0x2c 0xdf 0x4c
+
+# CHECK: ld1.8b { v1 }, [x2], #8
+# CHECK: ld1.8b { v1, v2 }, [x2], #16
+# CHECK: ld1.8b { v1, v2, v3 }, [x2], #24
+# CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32
+# CHECK: ld1.16b { v2 }, [x2], #16
+# CHECK: ld1.16b { v2, v3 }, [x2], #32
+# CHECK: ld1.16b { v2, v3, v4 }, [x2], #48
+# CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64
+# CHECK: ld1.4h { v4 }, [x3], #8
+# CHECK: ld1.4h { v4, v5 }, [x3], #16
+# CHECK: ld1.4h { v4, v5, v6 }, [x3], #24
+# CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32
+# CHECK: ld1.8h { v7 }, [x4], #16
+# CHECK: ld1.8h { v7, v8 }, [x4], #32
+# CHECK: ld1.8h { v7, v8, v9 }, [x4], #48
+# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64
+# CHECK: ld1.2s { v12 }, [x0], #8
+# CHECK: ld1.2s { v12, v13 }, [x0], #16
+# CHECK: ld1.2s { v12, v13, v14 }, [x0], #24
+# CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32
+# CHECK: ld1.4s { v10 }, [x0], #16
+# CHECK: ld1.4s { v10, v11 }, [x0], #32
+# CHECK: ld1.4s { v10, v11, v12 }, [x0], #48
+# CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64
+# CHECK: ld1.1d { v13 }, [x1], #8
+# CHECK: ld1.1d { v13, v14 }, [x1], #16
+# CHECK: ld1.1d { v13, v14, v15 }, [x1], #24
+# CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32
+# CHECK: ld1.2d { v15 }, [x2], #16
+# CHECK: ld1.2d { v15, v16 }, [x2], #32
+# CHECK: ld1.2d { v15, v16, v17 }, [x2], #48
+# CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64
+
+0x21 0x70 0x00 0x0c
+0x42 0xa0 0x00 0x4c
+0x64 0x64 0x00 0x0c
+0x87 0x24 0x00 0x4c
+0x0c 0xa8 0x00 0x0c
+0x0a 0x68 0x00 0x4c
+0x2d 0xac 0x00 0x0c
+0x4f 0x7c 0x00 0x4c
+
+# CHECK: st1.8b { v1 }, [x1]
+# CHECK: st1.16b { v2, v3 }, [x2]
+# CHECK: st1.4h { v4, v5, v6 }, [x3]
+# CHECK: st1.8h { v7, v8, v9, v10 }, [x4]
+# CHECK: st1.2s { v12, v13 }, [x0]
+# CHECK: st1.4s { v10, v11, v12 }, [x0]
+# CHECK: st1.1d { v13, v14 }, [x1]
+# CHECK: st1.2d { v15 }, [x2]
+
+0x61 0x08 0x40 0x0d
+0x82 0x84 0x40 0x4d
+0xa3 0x58 0x40 0x0d
+0xc4 0x80 0x40 0x4d
+
+# CHECK: ld1.b { v1 }[2], [x3]
+# CHECK: ld1.d { v2 }[1], [x4]
+# CHECK: ld1.h { v3 }[3], [x5]
+# CHECK: ld1.s { v4 }[2], [x6]
+
+0x61 0x08 0xdf 0x0d
+0x82 0x84 0xdf 0x4d
+0xa3 0x58 0xdf 0x0d
+0xc4 0x80 0xdf 0x4d
+
+# CHECK: ld1.b { v1 }[2], [x3], #1
+# CHECK: ld1.d { v2 }[1], [x4], #8
+# CHECK: ld1.h { v3 }[3], [x5], #2
+# CHECK: ld1.s { v4 }[2], [x6], #4
+
+0x61 0x08 0x00 0x0d
+0x82 0x84 0x00 0x4d
+0xa3 0x58 0x00 0x0d
+0xc4 0x80 0x00 0x4d
+
+# CHECK: st1.b { v1 }[2], [x3]
+# CHECK: st1.d { v2 }[1], [x4]
+# CHECK: st1.h { v3 }[3], [x5]
+# CHECK: st1.s { v4 }[2], [x6]
+
+0x61 0x08 0x9f 0x0d
+0x82 0x84 0x9f 0x4d
+0xa3 0x58 0x9f 0x0d
+0xc4 0x80 0x9f 0x4d
+
+# CHECK: st1.b { v1 }[2], [x3], #1
+# CHECK: st1.d { v2 }[1], [x4], #8
+# CHECK: st1.h { v3 }[3], [x5], #2
+# CHECK: st1.s { v4 }[2], [x6], #4
+
+0x61 0x08 0xc4 0x0d
+0x82 0x84 0xc5 0x4d
+0xa3 0x58 0xc6 0x0d
+0xc4 0x80 0xc7 0x4d
+
+# CHECK: ld1.b { v1 }[2], [x3], x4
+# CHECK: ld1.d { v2 }[1], [x4], x5
+# CHECK: ld1.h { v3 }[3], [x5], x6
+# CHECK: ld1.s { v4 }[2], [x6], x7
+
+0x61 0x08 0x84 0x0d
+0x82 0x84 0x85 0x4d
+0xa3 0x58 0x86 0x0d
+0xc4 0x80 0x87 0x4d
+
+# CHECK: st1.b { v1 }[2], [x3], x4
+# CHECK: st1.d { v2 }[1], [x4], x5
+# CHECK: st1.h { v3 }[3], [x5], x6
+# CHECK: st1.s { v4 }[2], [x6], x7
+
+0x41 0x70 0xc3 0x0c
+0x42 0xa0 0xc4 0x4c
+0x64 0x64 0xc5 0x0c
+0x87 0x24 0xc6 0x4c
+0x0c 0xa8 0xc7 0x0c
+0x0a 0x68 0xc8 0x4c
+0x2d 0xac 0xc9 0x0c
+0x4f 0x7c 0xca 0x4c
+
+# CHECK: ld1.8b { v1 }, [x2], x3
+# CHECK: ld1.16b { v2, v3 }, [x2], x4
+# CHECK: ld1.4h { v4, v5, v6 }, [x3], x5
+# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6
+# CHECK: ld1.2s { v12, v13 }, [x0], x7
+# CHECK: ld1.4s { v10, v11, v12 }, [x0], x8
+# CHECK: ld1.1d { v13, v14 }, [x1], x9
+# CHECK: ld1.2d { v15 }, [x2], x10
+
+0x41 0x70 0x83 0x0c
+0x42 0xa0 0x84 0x4c
+0x64 0x64 0x85 0x0c
+0x87 0x24 0x86 0x4c
+0x0c 0xa8 0x87 0x0c
+0x0a 0x68 0x88 0x4c
+0x2d 0xac 0x89 0x0c
+0x4f 0x7c 0x8a 0x4c
+
+# CHECK: st1.8b { v1 }, [x2], x3
+# CHECK: st1.16b { v2, v3 }, [x2], x4
+# CHECK: st1.4h { v4, v5, v6 }, [x3], x5
+# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6
+# CHECK: st1.2s { v12, v13 }, [x0], x7
+# CHECK: st1.4s { v10, v11, v12 }, [x0], x8
+# CHECK: st1.1d { v13, v14 }, [x1], x9
+# CHECK: st1.2d { v15 }, [x2], x10
+
+0x41 0x70 0x9f 0x0c
+0x41 0xa0 0x9f 0x0c
+0x41 0x60 0x9f 0x0c
+0x41 0x20 0x9f 0x0c
+0x42 0x70 0x9f 0x4c
+0x42 0xa0 0x9f 0x4c
+0x42 0x60 0x9f 0x4c
+0x42 0x20 0x9f 0x4c
+0x64 0x74 0x9f 0x0c
+0x64 0xa4 0x9f 0x0c
+0x64 0x64 0x9f 0x0c
+0x64 0x24 0x9f 0x0c
+0x87 0x74 0x9f 0x4c
+0x87 0xa4 0x9f 0x4c
+0x87 0x64 0x9f 0x4c
+0x87 0x24 0x9f 0x4c
+0x0c 0x78 0x9f 0x0c
+0x0c 0xa8 0x9f 0x0c
+0x0c 0x68 0x9f 0x0c
+0x0c 0x28 0x9f 0x0c
+0x0a 0x78 0x9f 0x4c
+0x0a 0xa8 0x9f 0x4c
+0x0a 0x68 0x9f 0x4c
+0x0a 0x28 0x9f 0x4c
+0x2d 0x7c 0x9f 0x0c
+0x2d 0xac 0x9f 0x0c
+0x2d 0x6c 0x9f 0x0c
+0x2d 0x2c 0x9f 0x0c
+0x4f 0x7c 0x9f 0x4c
+0x4f 0xac 0x9f 0x4c
+0x4f 0x6c 0x9f 0x4c
+0x4f 0x2c 0x9f 0x4c
+
+# CHECK: st1.8b { v1 }, [x2], #8
+# CHECK: st1.8b { v1, v2 }, [x2], #16
+# CHECK: st1.8b { v1, v2, v3 }, [x2], #24
+# CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32
+# CHECK: st1.16b { v2 }, [x2], #16
+# CHECK: st1.16b { v2, v3 }, [x2], #32
+# CHECK: st1.16b { v2, v3, v4 }, [x2], #48
+# CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64
+# CHECK: st1.4h { v4 }, [x3], #8
+# CHECK: st1.4h { v4, v5 }, [x3], #16
+# CHECK: st1.4h { v4, v5, v6 }, [x3], #24
+# CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32
+# CHECK: st1.8h { v7 }, [x4], #16
+# CHECK: st1.8h { v7, v8 }, [x4], #32
+# CHECK: st1.8h { v7, v8, v9 }, [x4], #48
+# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64
+# CHECK: st1.2s { v12 }, [x0], #8
+# CHECK: st1.2s { v12, v13 }, [x0], #16
+# CHECK: st1.2s { v12, v13, v14 }, [x0], #24
+# CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32
+# CHECK: st1.4s { v10 }, [x0], #16
+# CHECK: st1.4s { v10, v11 }, [x0], #32
+# CHECK: st1.4s { v10, v11, v12 }, [x0], #48
+# CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64
+# CHECK: st1.1d { v13 }, [x1], #8
+# CHECK: st1.1d { v13, v14 }, [x1], #16
+# CHECK: st1.1d { v13, v14, v15 }, [x1], #24
+# CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32
+# CHECK: st1.2d { v15 }, [x2], #16
+# CHECK: st1.2d { v15, v16 }, [x2], #32
+# CHECK: st1.2d { v15, v16, v17 }, [x2], #48
+# CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64
+
+0x21 0xc0 0x40 0x0d
+0x21 0xc0 0xc2 0x0d
+0x64 0xc4 0x40 0x0d
+0x64 0xc4 0xc5 0x0d
+0xa9 0xc8 0x40 0x0d
+0xa9 0xc8 0xc6 0x0d
+0xec 0xcc 0x40 0x0d
+0xec 0xcc 0xc8 0x0d
+
+# CHECK: ld1r.8b { v1 }, [x1]
+# CHECK: ld1r.8b { v1 }, [x1], x2
+# CHECK: ld1r.4h { v4 }, [x3]
+# CHECK: ld1r.4h { v4 }, [x3], x5
+# CHECK: ld1r.2s { v9 }, [x5]
+# CHECK: ld1r.2s { v9 }, [x5], x6
+# CHECK: ld1r.1d { v12 }, [x7]
+# CHECK: ld1r.1d { v12 }, [x7], x8
+
+0x21 0xc0 0xdf 0x0d
+0x21 0xc4 0xdf 0x0d
+0x21 0xc8 0xdf 0x0d
+0x21 0xcc 0xdf 0x0d
+
+# CHECK: ld1r.8b { v1 }, [x1], #1
+# CHECK: ld1r.4h { v1 }, [x1], #2
+# CHECK: ld1r.2s { v1 }, [x1], #4
+# CHECK: ld1r.1d { v1 }, [x1], #8
+
+0x45 0x80 0x40 0x4c
+0x0a 0x88 0x40 0x0c
+
+# CHECK: ld2.16b { v5, v6 }, [x2]
+# CHECK: ld2.2s { v10, v11 }, [x0]
+
+0x45 0x80 0x00 0x4c
+0x0a 0x88 0x00 0x0c
+
+# CHECK: st2.16b { v5, v6 }, [x2]
+# CHECK: st2.2s { v10, v11 }, [x0]
+
+0x61 0x08 0x20 0x0d
+0x82 0x84 0x20 0x4d
+0xc3 0x50 0x20 0x0d
+0xe4 0x90 0x20 0x4d
+
+# CHECK: st2.b { v1, v2 }[2], [x3]
+# CHECK: st2.d { v2, v3 }[1], [x4]
+# CHECK: st2.h { v3, v4 }[2], [x6]
+# CHECK: st2.s { v4, v5 }[3], [x7]
+
+0x61 0x08 0xbf 0x0d
+0x82 0x84 0xbf 0x4d
+0xa3 0x58 0xbf 0x0d
+0xc4 0x80 0xbf 0x4d
+
+# CHECK: st2.b { v1, v2 }[2], [x3], #2
+# CHECK: st2.d { v2, v3 }[1], [x4], #16
+# CHECK: st2.h { v3, v4 }[3], [x5], #4
+# CHECK: st2.s { v4, v5 }[2], [x6], #8
+
+0x61 0x08 0x60 0x0d
+0x82 0x84 0x60 0x4d
+0xc3 0x50 0x60 0x0d
+0xe4 0x90 0x60 0x4d
+
+# CHECK: ld2.b { v1, v2 }[2], [x3]
+# CHECK: ld2.d { v2, v3 }[1], [x4]
+# CHECK: ld2.h { v3, v4 }[2], [x6]
+# CHECK: ld2.s { v4, v5 }[3], [x7]
+
+0x61 0x08 0xff 0x0d
+0x82 0x84 0xff 0x4d
+0xa3 0x58 0xff 0x0d
+0xc4 0x80 0xff 0x4d
+
+# CHECK: ld2.b { v1, v2 }[2], [x3], #2
+# CHECK: ld2.d { v2, v3 }[1], [x4], #16
+# CHECK: ld2.h { v3, v4 }[3], [x5], #4
+# CHECK: ld2.s { v4, v5 }[2], [x6], #8
+
+0x61 0x08 0xe4 0x0d
+0x82 0x84 0xe6 0x4d
+0xa3 0x58 0xe8 0x0d
+0xc4 0x80 0xea 0x4d
+
+# CHECK: ld2.b { v1, v2 }[2], [x3], x4
+# CHECK: ld2.d { v2, v3 }[1], [x4], x6
+# CHECK: ld2.h { v3, v4 }[3], [x5], x8
+# CHECK: ld2.s { v4, v5 }[2], [x6], x10
+
+0x61 0x08 0xa4 0x0d
+0x82 0x84 0xa6 0x4d
+0xa3 0x58 0xa8 0x0d
+0xc4 0x80 0xaa 0x4d
+
+# CHECK: st2.b { v1, v2 }[2], [x3], x4
+# CHECK: st2.d { v2, v3 }[1], [x4], x6
+# CHECK: st2.h { v3, v4 }[3], [x5], x8
+# CHECK: st2.s { v4, v5 }[2], [x6], x10
+
+0x64 0x84 0xc5 0x0c
+0x0c 0x88 0xc7 0x0c
+
+# CHECK: ld2.4h { v4, v5 }, [x3], x5
+# CHECK: ld2.2s { v12, v13 }, [x0], x7
+
+0x00 0x80 0xdf 0x0c
+0x00 0x80 0xdf 0x4c
+0x00 0x84 0xdf 0x0c
+0x00 0x84 0xdf 0x4c
+0x00 0x88 0xdf 0x0c
+0x00 0x88 0xdf 0x4c
+0x00 0x8c 0xdf 0x4c
+
+# CHECK: ld2.8b { v0, v1 }, [x0], #16
+# CHECK: ld2.16b { v0, v1 }, [x0], #32
+# CHECK: ld2.4h { v0, v1 }, [x0], #16
+# CHECK: ld2.8h { v0, v1 }, [x0], #32
+# CHECK: ld2.2s { v0, v1 }, [x0], #16
+# CHECK: ld2.4s { v0, v1 }, [x0], #32
+# CHECK: ld2.2d { v0, v1 }, [x0], #32
+
+0x64 0x84 0x85 0x0c
+0x0c 0x88 0x87 0x0c
+
+# CHECK: st2.4h { v4, v5 }, [x3], x5
+# CHECK: st2.2s { v12, v13 }, [x0], x7
+
+0x00 0x80 0x9f 0x0c
+0x00 0x80 0x9f 0x4c
+0x00 0x84 0x9f 0x0c
+0x00 0x84 0x9f 0x4c
+0x00 0x88 0x9f 0x0c
+0x00 0x88 0x9f 0x4c
+0x00 0x8c 0x9f 0x4c
+
+# CHECK: st2.8b { v0, v1 }, [x0], #16
+# CHECK: st2.16b { v0, v1 }, [x0], #32
+# CHECK: st2.4h { v0, v1 }, [x0], #16
+# CHECK: st2.8h { v0, v1 }, [x0], #32
+# CHECK: st2.2s { v0, v1 }, [x0], #16
+# CHECK: st2.4s { v0, v1 }, [x0], #32
+# CHECK: st2.2d { v0, v1 }, [x0], #32
+
+0x21 0xc0 0x60 0x0d
+0x21 0xc0 0xe2 0x0d
+0x21 0xc0 0x60 0x4d
+0x21 0xc0 0xe2 0x4d
+0x21 0xc4 0x60 0x0d
+0x21 0xc4 0xe2 0x0d
+0x21 0xc4 0x60 0x4d
+0x21 0xc4 0xe2 0x4d
+0x21 0xc8 0x60 0x0d
+0x21 0xc8 0xe2 0x0d
+0x21 0xcc 0x60 0x4d
+0x21 0xcc 0xe2 0x4d
+0x21 0xcc 0x60 0x0d
+0x21 0xcc 0xe2 0x0d
+
+# CHECK: ld2r.8b { v1, v2 }, [x1]
+# CHECK: ld2r.8b { v1, v2 }, [x1], x2
+# CHECK: ld2r.16b { v1, v2 }, [x1]
+# CHECK: ld2r.16b { v1, v2 }, [x1], x2
+# CHECK: ld2r.4h { v1, v2 }, [x1]
+# CHECK: ld2r.4h { v1, v2 }, [x1], x2
+# CHECK: ld2r.8h { v1, v2 }, [x1]
+# CHECK: ld2r.8h { v1, v2 }, [x1], x2
+# CHECK: ld2r.2s { v1, v2 }, [x1]
+# CHECK: ld2r.2s { v1, v2 }, [x1], x2
+# CHECK: ld2r.2d { v1, v2 }, [x1]
+# CHECK: ld2r.2d { v1, v2 }, [x1], x2
+# CHECK: ld2r.1d { v1, v2 }, [x1]
+# CHECK: ld2r.1d { v1, v2 }, [x1], x2
+
+0x21 0xc0 0xff 0x0d
+0x21 0xc0 0xff 0x4d
+0x21 0xc4 0xff 0x0d
+0x21 0xc4 0xff 0x4d
+0x21 0xc8 0xff 0x0d
+0x21 0xcc 0xff 0x4d
+0x21 0xcc 0xff 0x0d
+
+# CHECK: ld2r.8b { v1, v2 }, [x1], #2
+# CHECK: ld2r.16b { v1, v2 }, [x1], #2
+# CHECK: ld2r.4h { v1, v2 }, [x1], #4
+# CHECK: ld2r.8h { v1, v2 }, [x1], #4
+# CHECK: ld2r.2s { v1, v2 }, [x1], #8
+# CHECK: ld2r.2d { v1, v2 }, [x1], #16
+# CHECK: ld2r.1d { v1, v2 }, [x1], #16
+
+0x21 0x40 0x40 0x0c
+0x45 0x40 0x40 0x4c
+0x0a 0x48 0x40 0x0c
+
+# CHECK: ld3.8b { v1, v2, v3 }, [x1]
+# CHECK: ld3.16b { v5, v6, v7 }, [x2]
+# CHECK: ld3.2s { v10, v11, v12 }, [x0]
+
+0x21 0x40 0x00 0x0c
+0x45 0x40 0x00 0x4c
+0x0a 0x48 0x00 0x0c
+
+# CHECK: st3.8b { v1, v2, v3 }, [x1]
+# CHECK: st3.16b { v5, v6, v7 }, [x2]
+# CHECK: st3.2s { v10, v11, v12 }, [x0]
+
+0x61 0x28 0xc4 0x0d
+0x82 0xa4 0xc5 0x4d
+0xa3 0x78 0xc6 0x0d
+0xc4 0xa0 0xc7 0x4d
+
+# CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4
+# CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5
+# CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6
+# CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7
+
+0x61 0x28 0x84 0x0d
+0x82 0xa4 0x85 0x4d
+0xa3 0x78 0x86 0x0d
+0xc4 0xa0 0x87 0x4d
+
+# CHECK: st3.b { v1, v2, v3 }[2], [x3], x4
+# CHECK: st3.d { v2, v3, v4 }[1], [x4], x5
+# CHECK: st3.h { v3, v4, v5 }[3], [x5], x6
+# CHECK: st3.s { v4, v5, v6 }[2], [x6], x7
+
+0x61 0x28 0x9f 0x0d
+0x82 0xa4 0x9f 0x4d
+0xa3 0x78 0x9f 0x0d
+0xc4 0xa0 0x9f 0x4d
+
+# CHECK: st3.b { v1, v2, v3 }[2], [x3], #3
+# CHECK: st3.d { v2, v3, v4 }[1], [x4], #24
+# CHECK: st3.h { v3, v4, v5 }[3], [x5], #6
+# CHECK: st3.s { v4, v5, v6 }[2], [x6], #12
+
+0x41 0x40 0xc3 0x0c
+0x42 0x40 0xc4 0x4c
+0x64 0x44 0xc5 0x0c
+0x87 0x44 0xc6 0x4c
+0x0c 0x48 0xc7 0x0c
+0x0a 0x48 0xc8 0x4c
+0x4f 0x4c 0xca 0x4c
+
+# CHECK: ld3.8b { v1, v2, v3 }, [x2], x3
+# CHECK: ld3.16b { v2, v3, v4 }, [x2], x4
+# CHECK: ld3.4h { v4, v5, v6 }, [x3], x5
+# CHECK: ld3.8h { v7, v8, v9 }, [x4], x6
+# CHECK: ld3.2s { v12, v13, v14 }, [x0], x7
+# CHECK: ld3.4s { v10, v11, v12 }, [x0], x8
+# CHECK: ld3.2d { v15, v16, v17 }, [x2], x10
+
+0x00 0x40 0xdf 0x0c
+0x00 0x40 0xdf 0x4c
+0x00 0x44 0xdf 0x0c
+0x00 0x44 0xdf 0x4c
+0x00 0x48 0xdf 0x0c
+0x00 0x48 0xdf 0x4c
+0x00 0x4c 0xdf 0x4c
+
+# CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
+# CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
+# CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
+# CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
+# CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
+# CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
+# CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
+
+0x41 0x40 0x83 0x0c
+0x42 0x40 0x84 0x4c
+0x64 0x44 0x85 0x0c
+0x87 0x44 0x86 0x4c
+0x0c 0x48 0x87 0x0c
+0x0a 0x48 0x88 0x4c
+0x4f 0x4c 0x8a 0x4c
+
+# CHECK: st3.8b { v1, v2, v3 }, [x2], x3
+# CHECK: st3.16b { v2, v3, v4 }, [x2], x4
+# CHECK: st3.4h { v4, v5, v6 }, [x3], x5
+# CHECK: st3.8h { v7, v8, v9 }, [x4], x6
+# CHECK: st3.2s { v12, v13, v14 }, [x0], x7
+# CHECK: st3.4s { v10, v11, v12 }, [x0], x8
+# CHECK: st3.2d { v15, v16, v17 }, [x2], x10
+
+0x00 0x40 0x9f 0x0c
+0x00 0x40 0x9f 0x4c
+0x00 0x44 0x9f 0x0c
+0x00 0x44 0x9f 0x4c
+0x00 0x48 0x9f 0x0c
+0x00 0x48 0x9f 0x4c
+0x00 0x4c 0x9f 0x4c
+
+# CHECK: st3.8b { v0, v1, v2 }, [x0], #24
+# CHECK: st3.16b { v0, v1, v2 }, [x0], #48
+# CHECK: st3.4h { v0, v1, v2 }, [x0], #24
+# CHECK: st3.8h { v0, v1, v2 }, [x0], #48
+# CHECK: st3.2s { v0, v1, v2 }, [x0], #24
+# CHECK: st3.4s { v0, v1, v2 }, [x0], #48
+# CHECK: st3.2d { v0, v1, v2 }, [x0], #48
+
+0x61 0x28 0x40 0x0d
+0x82 0xa4 0x40 0x4d
+0xc3 0x70 0x40 0x0d
+0xe4 0xb0 0x40 0x4d
+
+# CHECK: ld3.b { v1, v2, v3 }[2], [x3]
+# CHECK: ld3.d { v2, v3, v4 }[1], [x4]
+# CHECK: ld3.h { v3, v4, v5 }[2], [x6]
+# CHECK: ld3.s { v4, v5, v6 }[3], [x7]
+
+0x61 0x28 0xdf 0x0d
+0x82 0xa4 0xdf 0x4d
+0xa3 0x78 0xdf 0x0d
+0xc4 0xa0 0xdf 0x4d
+
+# CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3
+# CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24
+# CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6
+# CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12
+
+0x61 0x28 0x00 0x0d
+0x82 0xa4 0x00 0x4d
+0xc3 0x70 0x00 0x0d
+0xe4 0xb0 0x00 0x4d
+
+# CHECK: st3.b { v1, v2, v3 }[2], [x3]
+# CHECK: st3.d { v2, v3, v4 }[1], [x4]
+# CHECK: st3.h { v3, v4, v5 }[2], [x6]
+# CHECK: st3.s { v4, v5, v6 }[3], [x7]
+
+0x21 0xe0 0x40 0x0d
+0x21 0xe0 0xc2 0x0d
+0x21 0xe0 0x40 0x4d
+0x21 0xe0 0xc2 0x4d
+0x21 0xe4 0x40 0x0d
+0x21 0xe4 0xc2 0x0d
+0x21 0xe4 0x40 0x4d
+0x21 0xe4 0xc2 0x4d
+0x21 0xe8 0x40 0x0d
+0x21 0xe8 0xc2 0x0d
+0x21 0xec 0x40 0x4d
+0x21 0xec 0xc2 0x4d
+0x21 0xec 0x40 0x0d
+0x21 0xec 0xc2 0x0d
+
+# CHECK: ld3r.8b { v1, v2, v3 }, [x1]
+# CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.16b { v1, v2, v3 }, [x1]
+# CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.4h { v1, v2, v3 }, [x1]
+# CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.8h { v1, v2, v3 }, [x1]
+# CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.2s { v1, v2, v3 }, [x1]
+# CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.2d { v1, v2, v3 }, [x1]
+# CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2
+# CHECK: ld3r.1d { v1, v2, v3 }, [x1]
+# CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2
+
+0x21 0xe0 0xdf 0x0d
+0x21 0xe0 0xdf 0x4d
+0x21 0xe4 0xdf 0x0d
+0x21 0xe4 0xdf 0x4d
+0x21 0xe8 0xdf 0x0d
+0x21 0xec 0xdf 0x4d
+0x21 0xec 0xdf 0x0d
+
+# CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3
+# CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3
+# CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6
+# CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6
+# CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12
+# CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24
+# CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24
+
+0x21 0x00 0x40 0x0c
+0x45 0x00 0x40 0x4c
+0x0a 0x08 0x40 0x0c
+
+# CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
+# CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
+
+0x21 0x00 0x00 0x0c
+0x45 0x00 0x00 0x4c
+0x0a 0x08 0x00 0x0c
+
+# CHECK: st4.8b { v1, v2, v3, v4 }, [x1]
+# CHECK: st4.16b { v5, v6, v7, v8 }, [x2]
+# CHECK: st4.2s { v10, v11, v12, v13 }, [x0]
+
+0x61 0x28 0xe4 0x0d
+0x82 0xa4 0xe5 0x4d
+0xa3 0x78 0xe6 0x0d
+0xc4 0xa0 0xe7 0x4d
+
+# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4
+# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5
+# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6
+# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7
+
+0x61 0x28 0xff 0x0d
+0x82 0xa4 0xff 0x4d
+0xa3 0x78 0xff 0x0d
+0xc4 0xa0 0xff 0x4d
+
+# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4
+# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32
+# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8
+# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16
+
+0x61 0x28 0xa4 0x0d
+0x82 0xa4 0xa5 0x4d
+0xa3 0x78 0xa6 0x0d
+0xc4 0xa0 0xa7 0x4d
+
+# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4
+# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5
+# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6
+# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7
+
+0x61 0x28 0xbf 0x0d
+0x82 0xa4 0xbf 0x4d
+0xa3 0x78 0xbf 0x0d
+0xc4 0xa0 0xbf 0x4d
+
+# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4
+# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32
+# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8
+# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16
+
+0x41 0x00 0xc3 0x0c
+0x42 0x00 0xc4 0x4c
+0x64 0x04 0xc5 0x0c
+0x87 0x04 0xc6 0x4c
+0x0c 0x08 0xc7 0x0c
+0x0a 0x08 0xc8 0x4c
+0x4f 0x0c 0xca 0x4c
+
+# CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3
+# CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4
+# CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5
+# CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6
+# CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7
+# CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8
+# CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10
+
+0x00 0x00 0xdf 0x0c
+0x00 0x00 0xdf 0x4c
+0x00 0x04 0xdf 0x0c
+0x00 0x04 0xdf 0x4c
+0x00 0x08 0xdf 0x0c
+0x00 0x08 0xdf 0x4c
+0x00 0x0c 0xdf 0x4c
+
+# CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
+# CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
+# CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
+# CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
+# CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
+# CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
+# CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
+
+0x00 0x00 0x9f 0x0c
+0x00 0x00 0x9f 0x4c
+0x00 0x04 0x9f 0x0c
+0x00 0x04 0x9f 0x4c
+0x00 0x08 0x9f 0x0c
+0x00 0x08 0x9f 0x4c
+0x00 0x0c 0x9f 0x4c
+
+# CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
+# CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
+# CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
+# CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
+# CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
+# CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
+# CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
+
+0x41 0x00 0x83 0x0c
+0x42 0x00 0x84 0x4c
+0x64 0x04 0x85 0x0c
+0x87 0x04 0x86 0x4c
+0x0c 0x08 0x87 0x0c
+0x0a 0x08 0x88 0x4c
+0x4f 0x0c 0x8a 0x4c
+
+# CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3
+# CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4
+# CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5
+# CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6
+# CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7
+# CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8
+# CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10
+
+0x61 0x28 0x60 0x0d
+0x82 0xa4 0x60 0x4d
+0xc3 0x70 0x60 0x0d
+0xe4 0xb0 0x60 0x4d
+
+# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3]
+# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4]
+# CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6]
+# CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7]
+
+0x61 0x28 0x20 0x0d
+0x82 0xa4 0x20 0x4d
+0xc3 0x70 0x20 0x0d
+0xe4 0xb0 0x20 0x4d
+
+# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3]
+# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4]
+# CHECK: st4.h { v3, v4, v5, v6 }[2], [x6]
+# CHECK: st4.s { v4, v5, v6, v7 }[3], [x7]
+
+0x21 0xe0 0x60 0x0d
+0x21 0xe0 0xe2 0x0d
+0x21 0xe0 0x60 0x4d
+0x21 0xe0 0xe2 0x4d
+0x21 0xe4 0x60 0x0d
+0x21 0xe4 0xe2 0x0d
+0x21 0xe4 0x60 0x4d
+0x21 0xe4 0xe2 0x4d
+0x21 0xe8 0x60 0x0d
+0x21 0xe8 0xe2 0x0d
+0x21 0xec 0x60 0x4d
+0x21 0xec 0xe2 0x4d
+0x21 0xec 0x60 0x0d
+0x21 0xec 0xe2 0x0d
+
+# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2
+# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1]
+# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2
+
+0x21 0xe0 0xff 0x0d
+0x21 0xe0 0xff 0x4d
+0x21 0xe4 0xff 0x0d
+0x21 0xe4 0xff 0x4d
+0x21 0xe8 0xff 0x0d
+0x21 0xec 0xff 0x4d
+0x21 0xec 0xff 0x0d
+
+# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4
+# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4
+# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8
+# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8
+# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16
+# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32
+# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32
+
+0x20 0xe4 0x00 0x2f
+0x20 0xe4 0x00 0x6f
+0x20 0xe4 0x00 0x0f
+0x20 0xe4 0x00 0x4f
+
+# CHECK: movi d0, #0x000000000000ff
+# CHECK: movi.2d v0, #0x000000000000ff
+# CHECK: movi.8b v0, #1
+# CHECK: movi.16b v0, #1
+
+0x20 0x04 0x00 0x0f
+0x20 0x24 0x00 0x0f
+0x20 0x44 0x00 0x0f
+0x20 0x64 0x00 0x0f
+
+# CHECK: movi.2s v0, #1
+# CHECK: movi.2s v0, #1, lsl #8
+# CHECK: movi.2s v0, #1, lsl #16
+# CHECK: movi.2s v0, #1, lsl #24
+
+0x20 0x04 0x00 0x4f
+0x20 0x24 0x00 0x4f
+0x20 0x44 0x00 0x4f
+0x20 0x64 0x00 0x4f
+
+# CHECK: movi.4s v0, #1
+# CHECK: movi.4s v0, #1, lsl #8
+# CHECK: movi.4s v0, #1, lsl #16
+# CHECK: movi.4s v0, #1, lsl #24
+
+0x20 0x84 0x00 0x0f
+0x20 0xa4 0x00 0x0f
+
+# CHECK: movi.4h v0, #1
+# CHECK: movi.4h v0, #1, lsl #8
+
+0x20 0x84 0x00 0x4f
+0x20 0xa4 0x00 0x4f
+
+# CHECK: movi.8h v0, #1
+# CHECK: movi.8h v0, #1, lsl #8
+
+0x20 0x04 0x00 0x2f
+0x20 0x24 0x00 0x2f
+0x20 0x44 0x00 0x2f
+0x20 0x64 0x00 0x2f
+
+# CHECK: mvni.2s v0, #1
+# CHECK: mvni.2s v0, #1, lsl #8
+# CHECK: mvni.2s v0, #1, lsl #16
+# CHECK: mvni.2s v0, #1, lsl #24
+
+0x20 0x04 0x00 0x6f
+0x20 0x24 0x00 0x6f
+0x20 0x44 0x00 0x6f
+0x20 0x64 0x00 0x6f
+
+# CHECK: mvni.4s v0, #1
+# CHECK: mvni.4s v0, #1, lsl #8
+# CHECK: mvni.4s v0, #1, lsl #16
+# CHECK: mvni.4s v0, #1, lsl #24
+
+0x20 0x84 0x00 0x2f
+0x20 0xa4 0x00 0x2f
+
+# CHECK: mvni.4h v0, #1
+# CHECK: mvni.4h v0, #1, lsl #8
+
+0x20 0x84 0x00 0x6f
+0x20 0xa4 0x00 0x6f
+
+# CHECK: mvni.8h v0, #1
+# CHECK: mvni.8h v0, #1, lsl #8
+
+0x20 0xc4 0x00 0x2f
+0x20 0xd4 0x00 0x2f
+0x20 0xc4 0x00 0x6f
+0x20 0xd4 0x00 0x6f
+
+# CHECK: mvni.2s v0, #1, msl #8
+# CHECK: mvni.2s v0, #1, msl #16
+# CHECK: mvni.4s v0, #1, msl #8
+# CHECK: mvni.4s v0, #1, msl #16
+
+0x00 0x88 0x21 0x2e
+0x00 0x98 0x21 0x2e
+0x00 0x98 0xa1 0x2e
+0x00 0x98 0x21 0x0e
+0x00 0x88 0x21 0x0e
+0x00 0x88 0xa1 0x0e
+0x00 0x98 0xa1 0x0e
+
+# CHECK: frinta.2s v0, v0
+# CHECK: frintx.2s v0, v0
+# CHECK: frinti.2s v0, v0
+# CHECK: frintm.2s v0, v0
+# CHECK: frintn.2s v0, v0
+# CHECK: frintp.2s v0, v0
+# CHECK: frintz.2s v0, v0
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD scalar x index instructions
+#===-------------------------------------------------------------------------===
+
+0x00 0x18 0xa0 0x5f
+0x00 0x18 0xc0 0x5f
+0x00 0x58 0xa0 0x5f
+0x00 0x58 0xc0 0x5f
+0x00 0x98 0xa0 0x7f
+0x00 0x98 0xc0 0x7f
+0x00 0x98 0xa0 0x5f
+0x00 0x98 0xc0 0x5f
+0x00 0x38 0x70 0x5f
+0x00 0x38 0xa0 0x5f
+0x00 0x78 0x70 0x5f
+0x00 0xc8 0x70 0x5f
+0x00 0xc8 0xa0 0x5f
+0x00 0xb8 0x70 0x5f
+0x00 0xb8 0xa0 0x5f
+0x00 0xd8 0x70 0x5f
+0x00 0xd8 0xa0 0x5f
+
+# CHECK: fmla.s s0, s0, v0[3]
+# CHECK: fmla.d d0, d0, v0[1]
+# CHECK: fmls.s s0, s0, v0[3]
+# CHECK: fmls.d d0, d0, v0[1]
+# CHECK: fmulx.s s0, s0, v0[3]
+# CHECK: fmulx.d d0, d0, v0[1]
+# CHECK: fmul.s s0, s0, v0[3]
+# CHECK: fmul.d d0, d0, v0[1]
+# CHECK: sqdmlal.h s0, h0, v0[7]
+# CHECK: sqdmlal.s d0, s0, v0[3]
+# CHECK: sqdmlsl.h s0, h0, v0[7]
+# CHECK: sqdmulh.h h0, h0, v0[7]
+# CHECK: sqdmulh.s s0, s0, v0[3]
+# CHECK: sqdmull.h s0, h0, v0[7]
+# CHECK: sqdmull.s d0, s0, v0[3]
+# CHECK: sqrdmulh.h h0, h0, v0[7]
+# CHECK: sqrdmulh.s s0, s0, v0[3]
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD vector x index instructions
+#===-------------------------------------------------------------------------===
+
+ 0x00 0x10 0x80 0x0f
+ 0x00 0x10 0xa0 0x4f
+ 0x00 0x18 0xc0 0x4f
+ 0x00 0x50 0x80 0x0f
+ 0x00 0x50 0xa0 0x4f
+ 0x00 0x58 0xc0 0x4f
+ 0x00 0x90 0x80 0x2f
+ 0x00 0x90 0xa0 0x6f
+ 0x00 0x98 0xc0 0x6f
+ 0x00 0x90 0x80 0x0f
+ 0x00 0x90 0xa0 0x4f
+ 0x00 0x98 0xc0 0x4f
+ 0x00 0x00 0x40 0x2f
+ 0x00 0x00 0x50 0x6f
+ 0x00 0x08 0x80 0x2f
+ 0x00 0x08 0xa0 0x6f
+ 0x00 0x40 0x40 0x2f
+ 0x00 0x40 0x50 0x6f
+ 0x00 0x48 0x80 0x2f
+ 0x00 0x48 0xa0 0x6f
+ 0x00 0x80 0x40 0x0f
+ 0x00 0x80 0x50 0x4f
+ 0x00 0x88 0x80 0x0f
+ 0x00 0x88 0xa0 0x4f
+ 0x00 0x20 0x40 0x0f
+ 0x00 0x20 0x50 0x4f
+ 0x00 0x28 0x80 0x0f
+ 0x00 0x28 0xa0 0x4f
+ 0x00 0x60 0x40 0x0f
+ 0x00 0x60 0x50 0x4f
+ 0x00 0x68 0x80 0x0f
+ 0x00 0x68 0xa0 0x4f
+ 0x00 0xa0 0x40 0x0f
+ 0x00 0xa0 0x50 0x4f
+ 0x00 0xa8 0x80 0x0f
+ 0x00 0xa8 0xa0 0x4f
+ 0x00 0x30 0x40 0x0f
+ 0x00 0x30 0x50 0x4f
+ 0x00 0x38 0x80 0x0f
+ 0x00 0x38 0xa0 0x4f
+ 0x00 0x70 0x40 0x0f
+ 0x00 0x70 0x50 0x4f
+ 0x00 0x78 0x80 0x0f
+ 0x00 0x78 0xa0 0x4f
+ 0x00 0xc0 0x40 0x0f
+ 0x00 0xc0 0x50 0x4f
+ 0x00 0xc8 0x80 0x0f
+ 0x00 0xc8 0xa0 0x4f
+ 0x00 0xb0 0x40 0x0f
+ 0x00 0xb0 0x50 0x4f
+ 0x00 0xb8 0x80 0x0f
+ 0x00 0xb8 0xa0 0x4f
+ 0x00 0xd0 0x40 0x0f
+ 0x00 0xd0 0x50 0x4f
+ 0x00 0xd8 0x80 0x0f
+ 0x00 0xd8 0xa0 0x4f
+ 0x00 0x20 0x40 0x2f
+ 0x00 0x20 0x50 0x6f
+ 0x00 0x28 0x80 0x2f
+ 0x00 0x28 0xa0 0x6f
+ 0x00 0x60 0x40 0x2f
+ 0x00 0x60 0x50 0x6f
+ 0x00 0x68 0x80 0x2f
+ 0x00 0x68 0xa0 0x6f
+ 0x00 0xa0 0x40 0x2f
+ 0x00 0xa0 0x50 0x6f
+ 0x00 0xa8 0x80 0x2f
+ 0x00 0xa8 0xa0 0x6f
+
+# CHECK: fmla.2s v0, v0, v0[0]
+# CHECK: fmla.4s v0, v0, v0[1]
+# CHECK: fmla.2d v0, v0, v0[1]
+# CHECK: fmls.2s v0, v0, v0[0]
+# CHECK: fmls.4s v0, v0, v0[1]
+# CHECK: fmls.2d v0, v0, v0[1]
+# CHECK: fmulx.2s v0, v0, v0[0]
+# CHECK: fmulx.4s v0, v0, v0[1]
+# CHECK: fmulx.2d v0, v0, v0[1]
+# CHECK: fmul.2s v0, v0, v0[0]
+# CHECK: fmul.4s v0, v0, v0[1]
+# CHECK: fmul.2d v0, v0, v0[1]
+# CHECK: mla.4h v0, v0, v0[0]
+# CHECK: mla.8h v0, v0, v0[1]
+# CHECK: mla.2s v0, v0, v0[2]
+# CHECK: mla.4s v0, v0, v0[3]
+# CHECK: mls.4h v0, v0, v0[0]
+# CHECK: mls.8h v0, v0, v0[1]
+# CHECK: mls.2s v0, v0, v0[2]
+# CHECK: mls.4s v0, v0, v0[3]
+# CHECK: mul.4h v0, v0, v0[0]
+# CHECK: mul.8h v0, v0, v0[1]
+# CHECK: mul.2s v0, v0, v0[2]
+# CHECK: mul.4s v0, v0, v0[3]
+# CHECK: smlal.4s v0, v0, v0[0]
+# CHECK: smlal2.4s v0, v0, v0[1]
+# CHECK: smlal.2d v0, v0, v0[2]
+# CHECK: smlal2.2d v0, v0, v0[3]
+# CHECK: smlsl.4s v0, v0, v0[0]
+# CHECK: smlsl2.4s v0, v0, v0[1]
+# CHECK: smlsl.2d v0, v0, v0[2]
+# CHECK: smlsl2.2d v0, v0, v0[3]
+# CHECK: smull.4s v0, v0, v0[0]
+# CHECK: smull2.4s v0, v0, v0[1]
+# CHECK: smull.2d v0, v0, v0[2]
+# CHECK: smull2.2d v0, v0, v0[3]
+# CHECK: sqdmlal.4s v0, v0, v0[0]
+# CHECK: sqdmlal2.4s v0, v0, v0[1]
+# CHECK: sqdmlal.2d v0, v0, v0[2]
+# CHECK: sqdmlal2.2d v0, v0, v0[3]
+# CHECK: sqdmlsl.4s v0, v0, v0[0]
+# CHECK: sqdmlsl2.4s v0, v0, v0[1]
+# CHECK: sqdmlsl.2d v0, v0, v0[2]
+# CHECK: sqdmlsl2.2d v0, v0, v0[3]
+# CHECK: sqdmulh.4h v0, v0, v0[0]
+# CHECK: sqdmulh.8h v0, v0, v0[1]
+# CHECK: sqdmulh.2s v0, v0, v0[2]
+# CHECK: sqdmulh.4s v0, v0, v0[3]
+# CHECK: sqdmull.4s v0, v0, v0[0]
+# CHECK: sqdmull2.4s v0, v0, v0[1]
+# CHECK: sqdmull.2d v0, v0, v0[2]
+# CHECK: sqdmull2.2d v0, v0, v0[3]
+# CHECK: sqrdmulh.4h v0, v0, v0[0]
+# CHECK: sqrdmulh.8h v0, v0, v0[1]
+# CHECK: sqrdmulh.2s v0, v0, v0[2]
+# CHECK: sqrdmulh.4s v0, v0, v0[3]
+# CHECK: umlal.4s v0, v0, v0[0]
+# CHECK: umlal2.4s v0, v0, v0[1]
+# CHECK: umlal.2d v0, v0, v0[2]
+# CHECK: umlal2.2d v0, v0, v0[3]
+# CHECK: umlsl.4s v0, v0, v0[0]
+# CHECK: umlsl2.4s v0, v0, v0[1]
+# CHECK: umlsl.2d v0, v0, v0[2]
+# CHECK: umlsl2.2d v0, v0, v0[3]
+# CHECK: umull.4s v0, v0, v0[0]
+# CHECK: umull2.4s v0, v0, v0[1]
+# CHECK: umull.2d v0, v0, v0[2]
+# CHECK: umull2.2d v0, v0, v0[3]
+
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD scalar + shift instructions
+#===-------------------------------------------------------------------------===
+
+ 0x00 0x54 0x41 0x5f
+ 0x00 0x54 0x41 0x7f
+ 0x00 0x9c 0x09 0x5f
+ 0x00 0x9c 0x12 0x5f
+ 0x00 0x9c 0x23 0x5f
+ 0x00 0x8c 0x09 0x7f
+ 0x00 0x8c 0x12 0x7f
+ 0x00 0x8c 0x23 0x7f
+ 0x00 0x64 0x09 0x7f
+ 0x00 0x64 0x12 0x7f
+ 0x00 0x64 0x23 0x7f
+ 0x00 0x64 0x44 0x7f
+ 0x00 0x74 0x09 0x5f
+ 0x00 0x74 0x12 0x5f
+ 0x00 0x74 0x23 0x5f
+ 0x00 0x74 0x44 0x5f
+ 0x00 0x94 0x09 0x5f
+ 0x00 0x94 0x12 0x5f
+ 0x00 0x94 0x23 0x5f
+ 0x00 0x84 0x09 0x7f
+ 0x00 0x84 0x12 0x7f
+ 0x00 0x84 0x23 0x7f
+ 0x00 0x44 0x41 0x7f
+ 0x00 0x24 0x41 0x5f
+ 0x00 0x34 0x41 0x5f
+ 0x00 0x04 0x41 0x5f
+ 0x00 0xe4 0x21 0x7f
+ 0x00 0xe4 0x42 0x7f
+ 0x00 0x9c 0x09 0x7f
+ 0x00 0x9c 0x12 0x7f
+ 0x00 0x9c 0x23 0x7f
+ 0x00 0x74 0x09 0x7f
+ 0x00 0x74 0x12 0x7f
+ 0x00 0x74 0x23 0x7f
+ 0x00 0x74 0x44 0x7f
+ 0x00 0x94 0x09 0x7f
+ 0x00 0x94 0x12 0x7f
+ 0x00 0x94 0x23 0x7f
+ 0x00 0x24 0x41 0x7f
+ 0x00 0x34 0x41 0x7f
+ 0x00 0x04 0x41 0x7f
+ 0x00 0x14 0x41 0x7f
+
+# CHECK: shl d0, d0, #1
+# CHECK: sli d0, d0, #1
+# CHECK: sqrshrn b0, h0, #7
+# CHECK: sqrshrn h0, s0, #14
+# CHECK: sqrshrn s0, d0, #29
+# CHECK: sqrshrun b0, h0, #7
+# CHECK: sqrshrun h0, s0, #14
+# CHECK: sqrshrun s0, d0, #29
+# CHECK: sqshlu b0, b0, #1
+# CHECK: sqshlu h0, h0, #2
+# CHECK: sqshlu s0, s0, #3
+# CHECK: sqshlu d0, d0, #4
+# CHECK: sqshl b0, b0, #1
+# CHECK: sqshl h0, h0, #2
+# CHECK: sqshl s0, s0, #3
+# CHECK: sqshl d0, d0, #4
+# CHECK: sqshrn b0, h0, #7
+# CHECK: sqshrn h0, s0, #14
+# CHECK: sqshrn s0, d0, #29
+# CHECK: sqshrun b0, h0, #7
+# CHECK: sqshrun h0, s0, #14
+# CHECK: sqshrun s0, d0, #29
+# CHECK: sri d0, d0, #63
+# CHECK: srshr d0, d0, #63
+# CHECK: srsra d0, d0, #63
+# CHECK: sshr d0, d0, #63
+# CHECK: ucvtf s0, s0, #31
+# CHECK: ucvtf d0, d0, #62
+# CHECK: uqrshrn b0, h0, #7
+# CHECK: uqrshrn h0, s0, #14
+# CHECK: uqrshrn s0, d0, #29
+# CHECK: uqshl b0, b0, #1
+# CHECK: uqshl h0, h0, #2
+# CHECK: uqshl s0, s0, #3
+# CHECK: uqshl d0, d0, #4
+# CHECK: uqshrn b0, h0, #7
+# CHECK: uqshrn h0, s0, #14
+# CHECK: uqshrn s0, d0, #29
+# CHECK: urshr d0, d0, #63
+# CHECK: ursra d0, d0, #63
+# CHECK: ushr d0, d0, #63
+# CHECK: usra d0, d0, #63
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD vector + shift instructions
+#===-------------------------------------------------------------------------===
+
+ 0x00 0xfc 0x21 0x0f
+ 0x00 0xfc 0x22 0x4f
+ 0x00 0xfc 0x43 0x4f
+ 0x00 0xfc 0x21 0x2f
+ 0x00 0xfc 0x22 0x6f
+ 0x00 0xfc 0x43 0x6f
+ 0x00 0x8c 0x09 0x0f
+ 0x00 0x8c 0x0a 0x4f
+ 0x00 0x8c 0x13 0x0f
+ 0x00 0x8c 0x14 0x4f
+ 0x00 0x8c 0x25 0x0f
+ 0x00 0x8c 0x26 0x4f
+ 0x00 0xe4 0x21 0x0f
+ 0x00 0xe4 0x22 0x4f
+ 0x00 0xe4 0x43 0x4f
+ 0x00 0x54 0x09 0x0f
+ 0x00 0x54 0x0a 0x4f
+ 0x00 0x54 0x13 0x0f
+ 0x00 0x54 0x14 0x4f
+ 0x00 0x54 0x25 0x0f
+ 0x00 0x54 0x26 0x4f
+ 0x00 0x54 0x47 0x4f
+ 0x00 0x84 0x09 0x0f
+ 0x00 0x84 0x0a 0x4f
+ 0x00 0x84 0x13 0x0f
+ 0x00 0x84 0x14 0x4f
+ 0x00 0x84 0x25 0x0f
+ 0x00 0x84 0x26 0x4f
+ 0x00 0x54 0x09 0x2f
+ 0x00 0x54 0x0a 0x6f
+ 0x00 0x54 0x13 0x2f
+ 0x00 0x54 0x14 0x6f
+ 0x00 0x54 0x25 0x2f
+ 0x00 0x54 0x26 0x6f
+ 0x00 0x54 0x47 0x6f
+ 0x00 0x9c 0x09 0x0f
+ 0x00 0x9c 0x0a 0x4f
+ 0x00 0x9c 0x13 0x0f
+ 0x00 0x9c 0x14 0x4f
+ 0x00 0x9c 0x25 0x0f
+ 0x00 0x9c 0x26 0x4f
+ 0x00 0x8c 0x09 0x2f
+ 0x00 0x8c 0x0a 0x6f
+ 0x00 0x8c 0x13 0x2f
+ 0x00 0x8c 0x14 0x6f
+ 0x00 0x8c 0x25 0x2f
+ 0x00 0x8c 0x26 0x6f
+ 0x00 0x64 0x09 0x2f
+ 0x00 0x64 0x0a 0x6f
+ 0x00 0x64 0x13 0x2f
+ 0x00 0x64 0x14 0x6f
+ 0x00 0x64 0x25 0x2f
+ 0x00 0x64 0x26 0x6f
+ 0x00 0x64 0x47 0x6f
+ 0x00 0x74 0x09 0x0f
+ 0x00 0x74 0x0a 0x4f
+ 0x00 0x74 0x13 0x0f
+ 0x00 0x74 0x14 0x4f
+ 0x00 0x74 0x25 0x0f
+ 0x00 0x74 0x26 0x4f
+ 0x00 0x74 0x47 0x4f
+ 0x00 0x94 0x09 0x0f
+ 0x00 0x94 0x0a 0x4f
+ 0x00 0x94 0x13 0x0f
+ 0x00 0x94 0x14 0x4f
+ 0x00 0x94 0x25 0x0f
+ 0x00 0x94 0x26 0x4f
+ 0x00 0x84 0x09 0x2f
+ 0x00 0x84 0x0a 0x6f
+ 0x00 0x84 0x13 0x2f
+ 0x00 0x84 0x14 0x6f
+ 0x00 0x84 0x25 0x2f
+ 0x00 0x84 0x26 0x6f
+ 0x00 0x44 0x09 0x2f
+ 0x00 0x44 0x0a 0x6f
+ 0x00 0x44 0x13 0x2f
+ 0x00 0x44 0x14 0x6f
+ 0x00 0x44 0x25 0x2f
+ 0x00 0x44 0x26 0x6f
+ 0x00 0x44 0x47 0x6f
+ 0x00 0x24 0x09 0x0f
+ 0x00 0x24 0x0a 0x4f
+ 0x00 0x24 0x13 0x0f
+ 0x00 0x24 0x14 0x4f
+ 0x00 0x24 0x25 0x0f
+ 0x00 0x24 0x26 0x4f
+ 0x00 0x24 0x47 0x4f
+ 0x00 0x34 0x09 0x0f
+ 0x00 0x34 0x0a 0x4f
+ 0x00 0x34 0x13 0x0f
+ 0x00 0x34 0x14 0x4f
+ 0x00 0x34 0x25 0x0f
+ 0x00 0x34 0x26 0x4f
+ 0x00 0x34 0x47 0x4f
+ 0x00 0xa4 0x09 0x0f
+ 0x00 0xa4 0x0a 0x4f
+ 0x00 0xa4 0x13 0x0f
+ 0x00 0xa4 0x14 0x4f
+ 0x00 0xa4 0x25 0x0f
+ 0x00 0xa4 0x26 0x4f
+ 0x00 0x04 0x09 0x0f
+ 0x00 0x04 0x0a 0x4f
+ 0x00 0x04 0x13 0x0f
+ 0x00 0x04 0x14 0x4f
+ 0x00 0x04 0x25 0x0f
+ 0x00 0x04 0x26 0x4f
+ 0x00 0x04 0x47 0x4f
+ 0x00 0x04 0x09 0x0f
+ 0x00 0x14 0x0a 0x4f
+ 0x00 0x14 0x13 0x0f
+ 0x00 0x14 0x14 0x4f
+ 0x00 0x14 0x25 0x0f
+ 0x00 0x14 0x26 0x4f
+ 0x00 0x14 0x47 0x4f
+ 0x00 0x14 0x40 0x5f
+ 0x00 0xe4 0x21 0x2f
+ 0x00 0xe4 0x22 0x6f
+ 0x00 0xe4 0x43 0x6f
+ 0x00 0x9c 0x09 0x2f
+ 0x00 0x9c 0x0a 0x6f
+ 0x00 0x9c 0x13 0x2f
+ 0x00 0x9c 0x14 0x6f
+ 0x00 0x9c 0x25 0x2f
+ 0x00 0x9c 0x26 0x6f
+ 0x00 0x74 0x09 0x2f
+ 0x00 0x74 0x0a 0x6f
+ 0x00 0x74 0x13 0x2f
+ 0x00 0x74 0x14 0x6f
+ 0x00 0x74 0x25 0x2f
+ 0x00 0x74 0x26 0x6f
+ 0x00 0x74 0x47 0x6f
+ 0x00 0x94 0x09 0x2f
+ 0x00 0x94 0x0a 0x6f
+ 0x00 0x94 0x13 0x2f
+ 0x00 0x94 0x14 0x6f
+ 0x00 0x94 0x25 0x2f
+ 0x00 0x94 0x26 0x6f
+ 0x00 0x24 0x09 0x2f
+ 0x00 0x24 0x0a 0x6f
+ 0x00 0x24 0x13 0x2f
+ 0x00 0x24 0x14 0x6f
+ 0x00 0x24 0x25 0x2f
+ 0x00 0x24 0x26 0x6f
+ 0x00 0x24 0x47 0x6f
+ 0x00 0x34 0x09 0x2f
+ 0x00 0x34 0x0a 0x6f
+ 0x00 0x34 0x13 0x2f
+ 0x00 0x34 0x14 0x6f
+ 0x00 0x34 0x25 0x2f
+ 0x00 0x34 0x26 0x6f
+ 0x00 0x34 0x47 0x6f
+ 0x00 0xa4 0x09 0x2f
+ 0x00 0xa4 0x0a 0x6f
+ 0x00 0xa4 0x13 0x2f
+ 0x00 0xa4 0x14 0x6f
+ 0x00 0xa4 0x25 0x2f
+ 0x00 0xa4 0x26 0x6f
+ 0x00 0x04 0x09 0x2f
+ 0x00 0x04 0x0a 0x6f
+ 0x00 0x04 0x13 0x2f
+ 0x00 0x04 0x14 0x6f
+ 0x00 0x04 0x25 0x2f
+ 0x00 0x04 0x26 0x6f
+ 0x00 0x04 0x47 0x6f
+ 0x00 0x14 0x09 0x2f
+ 0x00 0x14 0x0a 0x6f
+ 0x00 0x14 0x13 0x2f
+ 0x00 0x14 0x14 0x6f
+ 0x00 0x14 0x25 0x2f
+ 0x00 0x14 0x26 0x6f
+ 0x00 0x14 0x47 0x6f
+
+# CHECK: fcvtzs.2s v0, v0, #31
+# CHECK: fcvtzs.4s v0, v0, #30
+# CHECK: fcvtzs.2d v0, v0, #61
+# CHECK: fcvtzu.2s v0, v0, #31
+# CHECK: fcvtzu.4s v0, v0, #30
+# CHECK: fcvtzu.2d v0, v0, #61
+# CHECK: rshrn.8b v0, v0, #7
+# CHECK: rshrn2.16b v0, v0, #6
+# CHECK: rshrn.4h v0, v0, #13
+# CHECK: rshrn2.8h v0, v0, #12
+# CHECK: rshrn.2s v0, v0, #27
+# CHECK: rshrn2.4s v0, v0, #26
+# CHECK: scvtf.2s v0, v0, #31
+# CHECK: scvtf.4s v0, v0, #30
+# CHECK: scvtf.2d v0, v0, #61
+# CHECK: shl.8b v0, v0, #1
+# CHECK: shl.16b v0, v0, #2
+# CHECK: shl.4h v0, v0, #3
+# CHECK: shl.8h v0, v0, #4
+# CHECK: shl.2s v0, v0, #5
+# CHECK: shl.4s v0, v0, #6
+# CHECK: shl.2d v0, v0, #7
+# CHECK: shrn.8b v0, v0, #7
+# CHECK: shrn2.16b v0, v0, #6
+# CHECK: shrn.4h v0, v0, #13
+# CHECK: shrn2.8h v0, v0, #12
+# CHECK: shrn.2s v0, v0, #27
+# CHECK: shrn2.4s v0, v0, #26
+# CHECK: sli.8b v0, v0, #1
+# CHECK: sli.16b v0, v0, #2
+# CHECK: sli.4h v0, v0, #3
+# CHECK: sli.8h v0, v0, #4
+# CHECK: sli.2s v0, v0, #5
+# CHECK: sli.4s v0, v0, #6
+# CHECK: sli.2d v0, v0, #7
+# CHECK: sqrshrn.8b v0, v0, #7
+# CHECK: sqrshrn2.16b v0, v0, #6
+# CHECK: sqrshrn.4h v0, v0, #13
+# CHECK: sqrshrn2.8h v0, v0, #12
+# CHECK: sqrshrn.2s v0, v0, #27
+# CHECK: sqrshrn2.4s v0, v0, #26
+# CHECK: sqrshrun.8b v0, v0, #7
+# CHECK: sqrshrun2.16b v0, v0, #6
+# CHECK: sqrshrun.4h v0, v0, #13
+# CHECK: sqrshrun2.8h v0, v0, #12
+# CHECK: sqrshrun.2s v0, v0, #27
+# CHECK: sqrshrun2.4s v0, v0, #26
+# CHECK: sqshlu.8b v0, v0, #1
+# CHECK: sqshlu.16b v0, v0, #2
+# CHECK: sqshlu.4h v0, v0, #3
+# CHECK: sqshlu.8h v0, v0, #4
+# CHECK: sqshlu.2s v0, v0, #5
+# CHECK: sqshlu.4s v0, v0, #6
+# CHECK: sqshlu.2d v0, v0, #7
+# CHECK: sqshl.8b v0, v0, #1
+# CHECK: sqshl.16b v0, v0, #2
+# CHECK: sqshl.4h v0, v0, #3
+# CHECK: sqshl.8h v0, v0, #4
+# CHECK: sqshl.2s v0, v0, #5
+# CHECK: sqshl.4s v0, v0, #6
+# CHECK: sqshl.2d v0, v0, #7
+# CHECK: sqshrn.8b v0, v0, #7
+# CHECK: sqshrn2.16b v0, v0, #6
+# CHECK: sqshrn.4h v0, v0, #13
+# CHECK: sqshrn2.8h v0, v0, #12
+# CHECK: sqshrn.2s v0, v0, #27
+# CHECK: sqshrn2.4s v0, v0, #26
+# CHECK: sqshrun.8b v0, v0, #7
+# CHECK: sqshrun2.16b v0, v0, #6
+# CHECK: sqshrun.4h v0, v0, #13
+# CHECK: sqshrun2.8h v0, v0, #12
+# CHECK: sqshrun.2s v0, v0, #27
+# CHECK: sqshrun2.4s v0, v0, #26
+# CHECK: sri.8b v0, v0, #7
+# CHECK: sri.16b v0, v0, #6
+# CHECK: sri.4h v0, v0, #13
+# CHECK: sri.8h v0, v0, #12
+# CHECK: sri.2s v0, v0, #27
+# CHECK: sri.4s v0, v0, #26
+# CHECK: sri.2d v0, v0, #57
+# CHECK: srshr.8b v0, v0, #7
+# CHECK: srshr.16b v0, v0, #6
+# CHECK: srshr.4h v0, v0, #13
+# CHECK: srshr.8h v0, v0, #12
+# CHECK: srshr.2s v0, v0, #27
+# CHECK: srshr.4s v0, v0, #26
+# CHECK: srshr.2d v0, v0, #57
+# CHECK: srsra.8b v0, v0, #7
+# CHECK: srsra.16b v0, v0, #6
+# CHECK: srsra.4h v0, v0, #13
+# CHECK: srsra.8h v0, v0, #12
+# CHECK: srsra.2s v0, v0, #27
+# CHECK: srsra.4s v0, v0, #26
+# CHECK: srsra.2d v0, v0, #57
+# CHECK: sshll.8h v0, v0, #1
+# CHECK: sshll2.8h v0, v0, #2
+# CHECK: sshll.4s v0, v0, #3
+# CHECK: sshll2.4s v0, v0, #4
+# CHECK: sshll.2d v0, v0, #5
+# CHECK: sshll2.2d v0, v0, #6
+# CHECK: sshr.8b v0, v0, #7
+# CHECK: sshr.16b v0, v0, #6
+# CHECK: sshr.4h v0, v0, #13
+# CHECK: sshr.8h v0, v0, #12
+# CHECK: sshr.2s v0, v0, #27
+# CHECK: sshr.4s v0, v0, #26
+# CHECK: sshr.2d v0, v0, #57
+# CHECK: sshr.8b v0, v0, #7
+# CHECK: ssra.16b v0, v0, #6
+# CHECK: ssra.4h v0, v0, #13
+# CHECK: ssra.8h v0, v0, #12
+# CHECK: ssra.2s v0, v0, #27
+# CHECK: ssra.4s v0, v0, #26
+# CHECK: ssra.2d v0, v0, #57
+# CHECK: ssra d0, d0, #64
+# CHECK: ucvtf.2s v0, v0, #31
+# CHECK: ucvtf.4s v0, v0, #30
+# CHECK: ucvtf.2d v0, v0, #61
+# CHECK: uqrshrn.8b v0, v0, #7
+# CHECK: uqrshrn2.16b v0, v0, #6
+# CHECK: uqrshrn.4h v0, v0, #13
+# CHECK: uqrshrn2.8h v0, v0, #12
+# CHECK: uqrshrn.2s v0, v0, #27
+# CHECK: uqrshrn2.4s v0, v0, #26
+# CHECK: uqshl.8b v0, v0, #1
+# CHECK: uqshl.16b v0, v0, #2
+# CHECK: uqshl.4h v0, v0, #3
+# CHECK: uqshl.8h v0, v0, #4
+# CHECK: uqshl.2s v0, v0, #5
+# CHECK: uqshl.4s v0, v0, #6
+# CHECK: uqshl.2d v0, v0, #7
+# CHECK: uqshrn.8b v0, v0, #7
+# CHECK: uqshrn2.16b v0, v0, #6
+# CHECK: uqshrn.4h v0, v0, #13
+# CHECK: uqshrn2.8h v0, v0, #12
+# CHECK: uqshrn.2s v0, v0, #27
+# CHECK: uqshrn2.4s v0, v0, #26
+# CHECK: urshr.8b v0, v0, #7
+# CHECK: urshr.16b v0, v0, #6
+# CHECK: urshr.4h v0, v0, #13
+# CHECK: urshr.8h v0, v0, #12
+# CHECK: urshr.2s v0, v0, #27
+# CHECK: urshr.4s v0, v0, #26
+# CHECK: urshr.2d v0, v0, #57
+# CHECK: ursra.8b v0, v0, #7
+# CHECK: ursra.16b v0, v0, #6
+# CHECK: ursra.4h v0, v0, #13
+# CHECK: ursra.8h v0, v0, #12
+# CHECK: ursra.2s v0, v0, #27
+# CHECK: ursra.4s v0, v0, #26
+# CHECK: ursra.2d v0, v0, #57
+# CHECK: ushll.8h v0, v0, #1
+# CHECK: ushll2.8h v0, v0, #2
+# CHECK: ushll.4s v0, v0, #3
+# CHECK: ushll2.4s v0, v0, #4
+# CHECK: ushll.2d v0, v0, #5
+# CHECK: ushll2.2d v0, v0, #6
+# CHECK: ushr.8b v0, v0, #7
+# CHECK: ushr.16b v0, v0, #6
+# CHECK: ushr.4h v0, v0, #13
+# CHECK: ushr.8h v0, v0, #12
+# CHECK: ushr.2s v0, v0, #27
+# CHECK: ushr.4s v0, v0, #26
+# CHECK: ushr.2d v0, v0, #57
+# CHECK: usra.8b v0, v0, #7
+# CHECK: usra.16b v0, v0, #6
+# CHECK: usra.4h v0, v0, #13
+# CHECK: usra.8h v0, v0, #12
+# CHECK: usra.2s v0, v0, #27
+# CHECK: usra.4s v0, v0, #26
+# CHECK: usra.2d v0, v0, #57
+
+
+ 0x00 0xe0 0x20 0x0e
+ 0x00 0xe0 0x20 0x4e
+ 0x00 0xe0 0xe0 0x0e
+ 0x00 0xe0 0xe0 0x4e
+
+# CHECK: pmull.8h v0, v0, v0
+# CHECK: pmull2.8h v0, v0, v0
+# CHECK: pmull.1q v0, v0, v0
+# CHECK: pmull2.1q v0, v0, v0
+
+ 0x41 0xd8 0x70 0x7e
+ 0x83 0xd8 0x30 0x7e
+# CHECK: faddp.2d d1, v2
+# CHECK: faddp.2s s3, v4
+
+ 0x82 0x60 0x01 0x4e
+ 0x80 0x60 0x01 0x0e
+ 0xa2 0x00 0x01 0x4e
+ 0xa0 0x00 0x01 0x0e
+ 0xa2 0x40 0x01 0x4e
+ 0xa0 0x40 0x01 0x0e
+ 0xc2 0x20 0x01 0x4e
+ 0xc0 0x20 0x01 0x0e
+
+# CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1
+# CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1
+# CHECK: tbl.16b v2, { v5 }, v1
+# CHECK: tbl.8b v0, { v5 }, v1
+# CHECK: tbl.16b v2, { v5, v6, v7 }, v1
+# CHECK: tbl.8b v0, { v5, v6, v7 }, v1
+# CHECK: tbl.16b v2, { v6, v7 }, v1
+# CHECK: tbl.8b v0, { v6, v7 }, v1
+#
+ 0x82 0x70 0x01 0x4e
+ 0x80 0x70 0x01 0x0e
+ 0xa2 0x10 0x01 0x4e
+ 0xa0 0x10 0x01 0x0e
+ 0xa2 0x50 0x01 0x4e
+ 0xa0 0x50 0x01 0x0e
+ 0xc2 0x30 0x01 0x4e
+ 0xc0 0x30 0x01 0x0e
+
+# CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1
+# CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1
+# CHECK: tbx.16b v2, { v5 }, v1
+# CHECK: tbx.8b v0, { v5 }, v1
+# CHECK: tbx.16b v2, { v5, v6, v7 }, v1
+# CHECK: tbx.8b v0, { v5, v6, v7 }, v1
+# CHECK: tbx.16b v2, { v6, v7 }, v1
+# CHECK: tbx.8b v0, { v6, v7 }, v1
+#
+
+0x00 0x80 0x20 0x0e
+0x00 0x80 0x20 0x4e
+0x00 0x80 0xa0 0x0e
+0x00 0x80 0xa0 0x4e
+
+# CHECK: smlal.8h v0, v0, v0
+# CHECK: smlal2.8h v0, v0, v0
+# CHECK: smlal.2d v0, v0, v0
+# CHECK: smlal2.2d v0, v0, v0
+
+0x00 0x80 0x20 0x2e
+0x00 0x80 0x20 0x6e
+0x00 0x80 0xa0 0x2e
+0x00 0x80 0xa0 0x6e
+
+# CHECK: umlal.8h v0, v0, v0
+# CHECK: umlal2.8h v0, v0, v0
+# CHECK: umlal.2d v0, v0, v0
+# CHECK: umlal2.2d v0, v0, v0
+
+0x00 0x90 0x60 0x5e
+0x00 0x90 0xa0 0x5e
+0x00 0xb0 0x60 0x5e
+0x00 0xb0 0xa0 0x5e
+
+# CHECK: sqdmlal s0, h0, h0
+# CHECK: sqdmlal d0, s0, s0
+# CHECK: sqdmlsl s0, h0, h0
+# CHECK: sqdmlsl d0, s0, s0
+
+0xaa 0xc5 0xc7 0x4d
+0xaa 0xc9 0xc7 0x4d
+0xaa 0xc1 0xc7 0x4d
+
+# CHECK: ld1r.8h { v10 }, [x13], x7
+# CHECK: ld1r.4s { v10 }, [x13], x7
+# CHECK: ld1r.16b { v10 }, [x13], x7
+
+0x00 0xd0 0x60 0x5e
+0x00 0xd0 0xa0 0x5e
+# CHECK: sqdmull s0, h0, h0
+# CHECK: sqdmull d0, s0, s0
+
+0x00 0xd8 0xa1 0x7e
+0x00 0xd8 0xe1 0x7e
+
+# CHECK: frsqrte s0, s0
+# CHECK: frsqrte d0, d0
+
+0xca 0xcd 0xc7 0x4d
+0xea 0xc9 0xe7 0x4d
+0xea 0xe9 0xc7 0x4d
+0xea 0xe9 0xe7 0x4d
+# CHECK: ld1r.2d { v10 }, [x14], x7
+# CHECK: ld2r.4s { v10, v11 }, [x15], x7
+# CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7
+# CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7
+
+#===-------------------------------------------------------------------------===
+# AdvSIMD scalar three same
+#===-------------------------------------------------------------------------===
+0x62 0xdc 0x21 0x5e
+# CHECK: fmulx s2, s3, s1
+0x62 0xdc 0x61 0x5e
+# CHECK: fmulx d2, d3, d1
+
+
+# rdar://12511369
+0xe8 0x6b 0xdf 0x4c
+# CHECK: ld1.4s { v8, v9, v10 }, [sp], #48
Added: llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/arithmetic.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,522 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+#==---------------------------------------------------------------------------==
+# Add/Subtract with carry/borrow
+#==---------------------------------------------------------------------------==
+
+0x41 0x00 0x03 0x1a
+0x41 0x00 0x03 0x9a
+0x85 0x00 0x03 0x3a
+0x85 0x00 0x03 0xba
+
+# CHECK: adc w1, w2, w3
+# CHECK: adc x1, x2, x3
+# CHECK: adcs w5, w4, w3
+# CHECK: adcs x5, x4, x3
+
+0x41 0x00 0x03 0x5a
+0x41 0x00 0x03 0xda
+0x41 0x00 0x03 0x7a
+0x41 0x00 0x03 0xfa
+
+# CHECK: sbc w1, w2, w3
+# CHECK: sbc x1, x2, x3
+# CHECK: sbcs w1, w2, w3
+# CHECK: sbcs x1, x2, x3
+
+#==---------------------------------------------------------------------------==
+# Add/Subtract with (optionally shifted) immediate
+#==---------------------------------------------------------------------------==
+
+0x83 0x00 0x10 0x11
+0x83 0x00 0x10 0x91
+
+# CHECK: add w3, w4, #1024
+# CHECK: add x3, x4, #1024
+
+0x83 0x00 0x50 0x11
+0x83 0x00 0x40 0x11
+0x83 0x00 0x50 0x91
+0x83 0x00 0x40 0x91
+0xff 0x83 0x00 0x91
+
+# CHECK: add w3, w4, #4194304
+# CHECK: add x3, x4, #4194304
+# CHECK: add x3, x4, #0, lsl #12
+# CHECK: add sp, sp, #32
+
+0x83 0x00 0x10 0x31
+0x83 0x00 0x50 0x31
+0x83 0x00 0x10 0xb1
+0x83 0x00 0x50 0xb1
+
+# CHECK: adds w3, w4, #1024
+# CHECK: adds w3, w4, #4194304
+# CHECK: adds x3, x4, #1024
+# CHECK: adds x3, x4, #4194304
+
+0x83 0x00 0x10 0x51
+0x83 0x00 0x50 0x51
+0x83 0x00 0x10 0xd1
+0x83 0x00 0x50 0xd1
+0xff 0x83 0x00 0xd1
+
+# CHECK: sub w3, w4, #1024
+# CHECK: sub w3, w4, #4194304
+# CHECK: sub x3, x4, #1024
+# CHECK: sub x3, x4, #4194304
+# CHECK: sub sp, sp, #32
+
+0x83 0x00 0x10 0x71
+0x83 0x00 0x50 0x71
+0x83 0x00 0x10 0xf1
+0x83 0x00 0x50 0xf1
+
+# CHECK: subs w3, w4, #1024
+# CHECK: subs w3, w4, #4194304
+# CHECK: subs x3, x4, #1024
+# CHECK: subs x3, x4, #4194304
+
+#==---------------------------------------------------------------------------==
+# Add/Subtract register with (optional) shift
+#==---------------------------------------------------------------------------==
+
+0xac 0x01 0x0e 0x0b
+0xac 0x01 0x0e 0x8b
+0xac 0x31 0x0e 0x0b
+0xac 0x31 0x0e 0x8b
+0xac 0xa9 0x4e 0x0b
+0xac 0xa9 0x4e 0x8b
+0xac 0x9d 0x8e 0x0b
+0xac 0x9d 0x8e 0x8b
+
+# CHECK: add w12, w13, w14
+# CHECK: add x12, x13, x14
+# CHECK: add w12, w13, w14, lsl #12
+# CHECK: add x12, x13, x14, lsl #12
+# CHECK: add w12, w13, w14, lsr #42
+# CHECK: add x12, x13, x14, lsr #42
+# CHECK: add w12, w13, w14, asr #39
+# CHECK: add x12, x13, x14, asr #39
+
+0xac 0x01 0x0e 0x4b
+0xac 0x01 0x0e 0xcb
+0xac 0x31 0x0e 0x4b
+0xac 0x31 0x0e 0xcb
+0xac 0xa9 0x4e 0x4b
+0xac 0xa9 0x4e 0xcb
+0xac 0x9d 0x8e 0x4b
+0xac 0x9d 0x8e 0xcb
+
+# CHECK: sub w12, w13, w14
+# CHECK: sub x12, x13, x14
+# CHECK: sub w12, w13, w14, lsl #12
+# CHECK: sub x12, x13, x14, lsl #12
+# CHECK: sub w12, w13, w14, lsr #42
+# CHECK: sub x12, x13, x14, lsr #42
+# CHECK: sub w12, w13, w14, asr #39
+# CHECK: sub x12, x13, x14, asr #39
+
+0xac 0x01 0x0e 0x2b
+0xac 0x01 0x0e 0xab
+0xac 0x31 0x0e 0x2b
+0xac 0x31 0x0e 0xab
+0xac 0xa9 0x4e 0x2b
+0xac 0xa9 0x4e 0xab
+0xac 0x9d 0x8e 0x2b
+0xac 0x9d 0x8e 0xab
+
+# CHECK: adds w12, w13, w14
+# CHECK: adds x12, x13, x14
+# CHECK: adds w12, w13, w14, lsl #12
+# CHECK: adds x12, x13, x14, lsl #12
+# CHECK: adds w12, w13, w14, lsr #42
+# CHECK: adds x12, x13, x14, lsr #42
+# CHECK: adds w12, w13, w14, asr #39
+# CHECK: adds x12, x13, x14, asr #39
+
+0xac 0x01 0x0e 0x6b
+0xac 0x01 0x0e 0xeb
+0xac 0x31 0x0e 0x6b
+0xac 0x31 0x0e 0xeb
+0xac 0xa9 0x4e 0x6b
+0xac 0xa9 0x4e 0xeb
+0xac 0x9d 0x8e 0x6b
+0xac 0x9d 0x8e 0xeb
+
+# CHECK: subs w12, w13, w14
+# CHECK: subs x12, x13, x14
+# CHECK: subs w12, w13, w14, lsl #12
+# CHECK: subs x12, x13, x14, lsl #12
+# CHECK: subs w12, w13, w14, lsr #42
+# CHECK: subs x12, x13, x14, lsr #42
+# CHECK: subs w12, w13, w14, asr #39
+# CHECK: subs x12, x13, x14, asr #39
+
+#==---------------------------------------------------------------------------==
+# Add/Subtract with (optional) extend
+#==---------------------------------------------------------------------------==
+
+0x41 0x00 0x23 0x0b
+0x41 0x20 0x23 0x0b
+0x41 0x40 0x23 0x0b
+0x41 0x60 0x23 0x0b
+0x41 0x80 0x23 0x0b
+0x41 0xa0 0x23 0x0b
+0x41 0xc0 0x23 0x0b
+0x41 0xe0 0x23 0x0b
+
+# CHECK: add w1, w2, w3, uxtb
+# CHECK: add w1, w2, w3, uxth
+# CHECK: add w1, w2, w3, uxtw
+# CHECK: add w1, w2, w3, uxtx
+# CHECK: add w1, w2, w3, sxtb
+# CHECK: add w1, w2, w3, sxth
+# CHECK: add w1, w2, w3, sxtw
+# CHECK: add w1, w2, w3, sxtx
+
+0x41 0x00 0x23 0x8b
+0x41 0x20 0x23 0x8b
+0x41 0x40 0x23 0x8b
+0x41 0x80 0x23 0x8b
+0x41 0xa0 0x23 0x8b
+0x41 0xc0 0x23 0x8b
+
+# CHECK: add x1, x2, w3, uxtb
+# CHECK: add x1, x2, w3, uxth
+# CHECK: add x1, x2, w3, uxtw
+# CHECK: add x1, x2, w3, sxtb
+# CHECK: add x1, x2, w3, sxth
+# CHECK: add x1, x2, w3, sxtw
+
+0xe1 0x43 0x23 0x0b
+0xe1 0x43 0x23 0x0b
+0x5f 0x60 0x23 0x8b
+0x5f 0x60 0x23 0x8b
+
+# CHECK: add w1, wsp, w3
+# CHECK: add w1, wsp, w3
+# CHECK: add sp, x2, x3
+# CHECK: add sp, x2, x3
+
+0x41 0x00 0x23 0x4b
+0x41 0x20 0x23 0x4b
+0x41 0x40 0x23 0x4b
+0x41 0x60 0x23 0x4b
+0x41 0x80 0x23 0x4b
+0x41 0xa0 0x23 0x4b
+0x41 0xc0 0x23 0x4b
+0x41 0xe0 0x23 0x4b
+
+# CHECK: sub w1, w2, w3, uxtb
+# CHECK: sub w1, w2, w3, uxth
+# CHECK: sub w1, w2, w3, uxtw
+# CHECK: sub w1, w2, w3, uxtx
+# CHECK: sub w1, w2, w3, sxtb
+# CHECK: sub w1, w2, w3, sxth
+# CHECK: sub w1, w2, w3, sxtw
+# CHECK: sub w1, w2, w3, sxtx
+
+0x41 0x00 0x23 0xcb
+0x41 0x20 0x23 0xcb
+0x41 0x40 0x23 0xcb
+0x41 0x80 0x23 0xcb
+0x41 0xa0 0x23 0xcb
+0x41 0xc0 0x23 0xcb
+
+# CHECK: sub x1, x2, w3, uxtb
+# CHECK: sub x1, x2, w3, uxth
+# CHECK: sub x1, x2, w3, uxtw
+# CHECK: sub x1, x2, w3, sxtb
+# CHECK: sub x1, x2, w3, sxth
+# CHECK: sub x1, x2, w3, sxtw
+
+0xe1 0x43 0x23 0x4b
+0xe1 0x43 0x23 0x4b
+0x5f 0x60 0x23 0xcb
+0x5f 0x60 0x23 0xcb
+
+# CHECK: sub w1, wsp, w3
+# CHECK: sub w1, wsp, w3
+# CHECK: sub sp, x2, x3
+# CHECK: sub sp, x2, x3
+
+0x41 0x00 0x23 0x2b
+0x41 0x20 0x23 0x2b
+0x41 0x40 0x23 0x2b
+0x41 0x60 0x23 0x2b
+0x41 0x80 0x23 0x2b
+0x41 0xa0 0x23 0x2b
+0x41 0xc0 0x23 0x2b
+0x41 0xe0 0x23 0x2b
+
+# CHECK: adds w1, w2, w3, uxtb
+# CHECK: adds w1, w2, w3, uxth
+# CHECK: adds w1, w2, w3, uxtw
+# CHECK: adds w1, w2, w3, uxtx
+# CHECK: adds w1, w2, w3, sxtb
+# CHECK: adds w1, w2, w3, sxth
+# CHECK: adds w1, w2, w3, sxtw
+# CHECK: adds w1, w2, w3, sxtx
+
+0x41 0x00 0x23 0xab
+0x41 0x20 0x23 0xab
+0x41 0x40 0x23 0xab
+0x41 0x80 0x23 0xab
+0x41 0xa0 0x23 0xab
+0x41 0xc0 0x23 0xab
+
+# CHECK: adds x1, x2, w3, uxtb
+# CHECK: adds x1, x2, w3, uxth
+# CHECK: adds x1, x2, w3, uxtw
+# CHECK: adds x1, x2, w3, sxtb
+# CHECK: adds x1, x2, w3, sxth
+# CHECK: adds x1, x2, w3, sxtw
+
+0xe1 0x43 0x23 0x2b
+0xe1 0x43 0x23 0x2b
+
+# CHECK: adds w1, wsp, w3
+# CHECK: adds w1, wsp, w3
+
+0x41 0x00 0x23 0x6b
+0x41 0x20 0x23 0x6b
+0x41 0x40 0x23 0x6b
+0x41 0x60 0x23 0x6b
+0x41 0x80 0x23 0x6b
+0x41 0xa0 0x23 0x6b
+0x41 0xc0 0x23 0x6b
+0x41 0xe0 0x23 0x6b
+
+# CHECK: subs w1, w2, w3, uxtb
+# CHECK: subs w1, w2, w3, uxth
+# CHECK: subs w1, w2, w3, uxtw
+# CHECK: subs w1, w2, w3, uxtx
+# CHECK: subs w1, w2, w3, sxtb
+# CHECK: subs w1, w2, w3, sxth
+# CHECK: subs w1, w2, w3, sxtw
+# CHECK: subs w1, w2, w3, sxtx
+
+0x41 0x00 0x23 0xeb
+0x41 0x20 0x23 0xeb
+0x41 0x40 0x23 0xeb
+0x41 0x80 0x23 0xeb
+0x41 0xa0 0x23 0xeb
+0x41 0xc0 0x23 0xeb
+
+# CHECK: subs x1, x2, w3, uxtb
+# CHECK: subs x1, x2, w3, uxth
+# CHECK: subs x1, x2, w3, uxtw
+# CHECK: subs x1, x2, w3, sxtb
+# CHECK: subs x1, x2, w3, sxth
+# CHECK: subs x1, x2, w3, sxtw
+
+0xe1 0x43 0x23 0x6b
+0xe1 0x43 0x23 0x6b
+
+# CHECK: subs w1, wsp, w3
+# CHECK: subs w1, wsp, w3
+
+0x1f 0x41 0x28 0xeb
+0x3f 0x41 0x28 0x6b
+0xff 0x43 0x28 0x6b
+0xff 0x43 0x28 0xeb
+
+# CHECK: cmp x8, w8, uxtw
+# CHECK: cmp w9, w8, uxtw
+# CHECK: cmp wsp, w8
+# CHECK: cmp sp, w8
+
+0x3f 0x41 0x28 0x4b
+0xe1 0x43 0x28 0x4b
+0xff 0x43 0x28 0x4b
+0x3f 0x41 0x28 0xcb
+0xe1 0x43 0x28 0xcb
+0xff 0x43 0x28 0xcb
+0xe1 0x43 0x28 0x6b
+0xe1 0x43 0x28 0xeb
+
+# CHECK: sub wsp, w9, w8
+# CHECK: sub w1, wsp, w8
+# CHECK: sub wsp, wsp, w8
+# CHECK: sub sp, x9, w8
+# CHECK: sub x1, sp, w8
+# CHECK: sub sp, sp, w8
+# CHECK: subs w1, wsp, w8
+# CHECK: subs x1, sp, w8
+
+#==---------------------------------------------------------------------------==
+# Signed/Unsigned divide
+#==---------------------------------------------------------------------------==
+
+0x41 0x0c 0xc3 0x1a
+0x41 0x0c 0xc3 0x9a
+0x41 0x08 0xc3 0x1a
+0x41 0x08 0xc3 0x9a
+
+# CHECK: sdiv w1, w2, w3
+# CHECK: sdiv x1, x2, x3
+# CHECK: udiv w1, w2, w3
+# CHECK: udiv x1, x2, x3
+
+#==---------------------------------------------------------------------------==
+# Variable shifts
+#==---------------------------------------------------------------------------==
+
+ 0x41 0x28 0xc3 0x1a
+# CHECK: asrv w1, w2, w3
+ 0x41 0x28 0xc3 0x9a
+# CHECK: asrv x1, x2, x3
+ 0x41 0x20 0xc3 0x1a
+# CHECK: lslv w1, w2, w3
+ 0x41 0x20 0xc3 0x9a
+# CHECK: lslv x1, x2, x3
+ 0x41 0x24 0xc3 0x1a
+# CHECK: lsrv w1, w2, w3
+ 0x41 0x24 0xc3 0x9a
+# CHECK: lsrv x1, x2, x3
+ 0x41 0x2c 0xc3 0x1a
+# CHECK: rorv w1, w2, w3
+ 0x41 0x2c 0xc3 0x9a
+# CHECK: rorv x1, x2, x3
+
+#==---------------------------------------------------------------------------==
+# One operand instructions
+#==---------------------------------------------------------------------------==
+
+ 0x41 0x14 0xc0 0x5a
+# CHECK: cls w1, w2
+ 0x41 0x14 0xc0 0xda
+# CHECK: cls x1, x2
+ 0x41 0x10 0xc0 0x5a
+# CHECK: clz w1, w2
+ 0x41 0x10 0xc0 0xda
+# CHECK: clz x1, x2
+ 0x41 0x00 0xc0 0x5a
+# CHECK: rbit w1, w2
+ 0x41 0x00 0xc0 0xda
+# CHECK: rbit x1, x2
+ 0x41 0x08 0xc0 0x5a
+# CHECK: rev w1, w2
+ 0x41 0x0c 0xc0 0xda
+# CHECK: rev x1, x2
+ 0x41 0x04 0xc0 0x5a
+# CHECK: rev16 w1, w2
+ 0x41 0x04 0xc0 0xda
+# CHECK: rev16 x1, x2
+ 0x41 0x08 0xc0 0xda
+# CHECK: rev32 x1, x2
+
+#==---------------------------------------------------------------------------==
+# 6.6.1 Multiply-add instructions
+#==---------------------------------------------------------------------------==
+
+0x41 0x10 0x03 0x1b
+0x41 0x10 0x03 0x9b
+0x41 0x90 0x03 0x1b
+0x41 0x90 0x03 0x9b
+0x41 0x10 0x23 0x9b
+0x41 0x90 0x23 0x9b
+0x41 0x10 0xa3 0x9b
+0x41 0x90 0xa3 0x9b
+
+# CHECK: madd w1, w2, w3, w4
+# CHECK: madd x1, x2, x3, x4
+# CHECK: msub w1, w2, w3, w4
+# CHECK: msub x1, x2, x3, x4
+# CHECK: smaddl x1, w2, w3, x4
+# CHECK: smsubl x1, w2, w3, x4
+# CHECK: umaddl x1, w2, w3, x4
+# CHECK: umsubl x1, w2, w3, x4
+
+#==---------------------------------------------------------------------------==
+# Multiply-high instructions
+#==---------------------------------------------------------------------------==
+
+0x41 0x7c 0x43 0x9b
+0x41 0x7c 0xc3 0x9b
+
+# CHECK: smulh x1, x2, x3
+# CHECK: umulh x1, x2, x3
+
+#==---------------------------------------------------------------------------==
+# Move immediate instructions
+#==---------------------------------------------------------------------------==
+
+0x20 0x00 0x80 0x52
+0x20 0x00 0x80 0xd2
+0x20 0x00 0xa0 0x52
+0x20 0x00 0xa0 0xd2
+
+# CHECK: movz w0, #1
+# CHECK: movz x0, #1
+# CHECK: movz w0, #1, lsl #16
+# CHECK: movz x0, #1, lsl #16
+
+0x40 0x00 0x80 0x12
+0x40 0x00 0x80 0x92
+0x40 0x00 0xa0 0x12
+0x40 0x00 0xa0 0x92
+
+# CHECK: movn w0, #2
+# CHECK: movn x0, #2
+# CHECK: movn w0, #2, lsl #16
+# CHECK: movn x0, #2, lsl #16
+
+0x20 0x00 0x80 0x72
+0x20 0x00 0x80 0xf2
+0x20 0x00 0xa0 0x72
+0x20 0x00 0xa0 0xf2
+
+# CHECK: movk w0, #1
+# CHECK: movk x0, #1
+# CHECK: movk w0, #1, lsl #16
+# CHECK: movk x0, #1, lsl #16
+
+#==---------------------------------------------------------------------------==
+# Conditionally set flags instructions
+#==---------------------------------------------------------------------------==
+
+ 0x1f 0x00 0x00 0x31
+# CHECK: cmn w0, #0
+ 0x1f 0xfc 0x03 0xb1
+# CHECK: x0, #255
+
+ 0x23 0x08 0x42 0x3a
+# CHECK: ccmn w1, #2, #3, eq
+ 0x23 0x08 0x42 0xba
+# CHECK: ccmn x1, #2, #3, eq
+ 0x23 0x08 0x42 0x7a
+# CHECK: ccmp w1, #2, #3, eq
+ 0x23 0x08 0x42 0xfa
+# CHECK: ccmp x1, #2, #3, eq
+
+ 0x23 0x00 0x42 0x3a
+# CHECK: ccmn w1, w2, #3, eq
+ 0x23 0x00 0x42 0xba
+# CHECK: ccmn x1, x2, #3, eq
+ 0x23 0x00 0x42 0x7a
+# CHECK: ccmp w1, w2, #3, eq
+ 0x23 0x00 0x42 0xfa
+# CHECK: ccmp x1, x2, #3, eq
+
+#==---------------------------------------------------------------------------==
+# Conditional select instructions
+#==---------------------------------------------------------------------------==
+
+ 0x41 0x00 0x83 0x1a
+# CHECK: csel w1, w2, w3, eq
+ 0x41 0x00 0x83 0x9a
+# CHECK: csel x1, x2, x3, eq
+ 0x41 0x04 0x83 0x1a
+# CHECK: csinc w1, w2, w3, eq
+ 0x41 0x04 0x83 0x9a
+# CHECK: csinc x1, x2, x3, eq
+ 0x41 0x00 0x83 0x5a
+# CHECK: csinv w1, w2, w3, eq
+ 0x41 0x00 0x83 0xda
+# CHECK: csinv x1, x2, x3, eq
+ 0x41 0x04 0x83 0x5a
+# CHECK: csneg w1, w2, w3, eq
+ 0x41 0x04 0x83 0xda
+# CHECK: csneg x1, x2, x3, eq
Added: llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/bitfield.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,29 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+#==---------------------------------------------------------------------------==
+# 5.4.4 Bitfield Operations
+#==---------------------------------------------------------------------------==
+
+0x41 0x3c 0x01 0x33
+0x41 0x3c 0x41 0xb3
+0x41 0x3c 0x01 0x13
+0x41 0x3c 0x41 0x93
+0x41 0x3c 0x01 0x53
+0x41 0x3c 0x41 0xd3
+
+# CHECK: bfm w1, w2, #1, #15
+# CHECK: bfm x1, x2, #1, #15
+# CHECK: sbfm w1, w2, #1, #15
+# CHECK: sbfm x1, x2, #1, #15
+# CHECK: ubfm w1, w2, #1, #15
+# CHECK: ubfm x1, x2, #1, #15
+
+#==---------------------------------------------------------------------------==
+# 5.4.5 Extract (immediate)
+#==---------------------------------------------------------------------------==
+
+0x41 0x3c 0x83 0x13
+0x62 0x04 0xc4 0x93
+
+# CHECK: extr w1, w2, w3, #15
+# CHECK: extr x2, x3, x4, #1
Added: llvm/trunk/test/MC/Disassembler/ARM64/branch.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/branch.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/branch.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/branch.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+#-----------------------------------------------------------------------------
+# Unconditional branch (register) instructions.
+#-----------------------------------------------------------------------------
+
+ 0xc0 0x03 0x5f 0xd6
+# CHECK: ret
+ 0x20 0x00 0x5f 0xd6
+# CHECK: ret x1
+ 0xe0 0x03 0xbf 0xd6
+# CHECK: drps
+ 0xe0 0x03 0x9f 0xd6
+# CHECK: eret
+ 0xa0 0x00 0x1f 0xd6
+# CHECK: br x5
+ 0x20 0x01 0x3f 0xd6
+# CHECK: blr x9
+ 0x0B 0x00 0x18 0x37
+# CHECK: tbnz w11, #3, #0
+
+#-----------------------------------------------------------------------------
+# Exception generation instructions.
+#-----------------------------------------------------------------------------
+
+ 0x20 0x00 0x20 0xd4
+# CHECK: brk #1
+ 0x41 0x00 0xa0 0xd4
+# CHECK: dcps1 #2
+ 0x62 0x00 0xa0 0xd4
+# CHECK: dcps2 #3
+ 0x83 0x00 0xa0 0xd4
+# CHECK: dcps3 #4
+ 0xa0 0x00 0x40 0xd4
+# CHECK: hlt #5
+ 0xc2 0x00 0x00 0xd4
+# CHECK: hvc #6
+ 0xe3 0x00 0x00 0xd4
+# CHECK: smc #7
+ 0x01 0x01 0x00 0xd4
+# CHECK: svc #8
+
+#-----------------------------------------------------------------------------
+# PC-relative branches (both positive and negative displacement)
+#-----------------------------------------------------------------------------
+
+ 0x07 0x00 0x00 0x14
+# CHECK: b #28
+ 0x06 0x00 0x00 0x94
+# CHECK: bl #24
+ 0xa1 0x00 0x00 0x54
+# CHECK: b.ne #20
+ 0x80 0x00 0x08 0x36
+# CHECK: tbz w0, #1, #16
+ 0xe1 0xff 0xf7 0x36
+# CHECK: tbz w1, #30, #-4
+ 0x60 0x00 0x08 0x37
+# CHECK: tbnz w0, #1, #12
+ 0x40 0x00 0x00 0xb4
+# CHECK: cbz x0, #8
+ 0x20 0x00 0x00 0xb5
+# CHECK: cbnz x0, #4
+ 0x1f 0x20 0x03 0xd5
+# CHECK: nop
+ 0xff 0xff 0xff 0x17
+# CHECK: b #-4
+ 0xc1 0xff 0xff 0x54
+# CHECK: b.ne #-8
+ 0xa0 0xff 0x0f 0x36
+# CHECK: tbz w0, #1, #-12
+ 0x80 0xff 0xff 0xb4
+# CHECK: cbz x0, #-16
+ 0x1f 0x20 0x03 0xd5
+# CHECK: nop
+
Added: llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/crc32.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,18 @@
+# RUN: llvm-mc -triple=arm64 -disassemble < %s | FileCheck %s
+
+# CHECK: crc32b w5, w7, w20
+# CHECK: crc32h w28, wzr, w30
+# CHECK: crc32w w0, w1, w2
+# CHECK: crc32x w7, w9, x20
+# CHECK: crc32cb w9, w5, w4
+# CHECK: crc32ch w13, w17, w25
+# CHECK: crc32cw wzr, w3, w5
+# CHECK: crc32cx w18, w16, xzr
+0xe5 0x40 0xd4 0x1a
+0xfc 0x47 0xde 0x1a
+0x20 0x48 0xc2 0x1a
+0x27 0x4d 0xd4 0x9a
+0xa9 0x50 0xc4 0x1a
+0x2d 0x56 0xd9 0x1a
+0x7f 0x58 0xc5 0x1a
+0x12 0x5e 0xdf 0x9a
Added: llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/crypto.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,47 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE
+
+ 0x20 0x48 0x28 0x4e
+ 0x20 0x58 0x28 0x4e
+ 0x20 0x68 0x28 0x4e
+ 0x20 0x78 0x28 0x4e
+ 0x20 0x00 0x02 0x5e
+ 0x20 0x10 0x02 0x5e
+ 0x20 0x20 0x02 0x5e
+ 0x20 0x30 0x02 0x5e
+ 0x20 0x40 0x02 0x5e
+ 0x20 0x50 0x02 0x5e
+ 0x20 0x60 0x02 0x5e
+ 0x20 0x08 0x28 0x5e
+ 0x20 0x18 0x28 0x5e
+ 0x20 0x28 0x28 0x5e
+
+# CHECK: aese v0.16b, v1.16b
+# CHECK: aesd v0.16b, v1.16b
+# CHECK: aesmc v0.16b, v1.16b
+# CHECK: aesimc v0.16b, v1.16b
+# CHECK: sha1c q0, s1, v2.4s
+# CHECK: sha1p q0, s1, v2.4s
+# CHECK: sha1m q0, s1, v2.4s
+# CHECK: sha1su0 v0.4s, v1.4s, v2
+# CHECK: sha256h q0, q1, v2.4s
+# CHECK: sha256h2 q0, q1, v2.4s
+# CHECK: sha256su1 v0.4s, v1.4s, v2.4s
+# CHECK: sha1h s0, s1
+# CHECK: sha1su1 v0.4s, v1.4s
+# CHECK: sha256su0 v0.4s, v1.4s
+
+# CHECK-APPLE: aese.16b v0, v1
+# CHECK-APPLE: aesd.16b v0, v1
+# CHECK-APPLE: aesmc.16b v0, v1
+# CHECK-APPLE: aesimc.16b v0, v1
+# CHECK-APPLE: sha1c.4s q0, s1, v2
+# CHECK-APPLE: sha1p.4s q0, s1, v2
+# CHECK-APPLE: sha1m.4s q0, s1, v2
+# CHECK-APPLE: sha1su0.4s v0, v1, v2
+# CHECK-APPLE: sha256h.4s q0, q1, v2
+# CHECK-APPLE: sha256h2.4s q0, q1, v2
+# CHECK-APPLE: sha256su1.4s v0, v1, v2
+# CHECK-APPLE: sha1h s0, s1
+# CHECK-APPLE: sha1su1.4s v0, v1
+# CHECK-APPLE: sha256su0.4s v0, v1
Added: llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/invalid-logical.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,6 @@
+# RUN: llvm-mc -triple arm64-apple-darwin -disassemble < %s 2>&1 | FileCheck %s
+
+# rdar://15226511
+0x7b 0xbf 0x25 0x72
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: 0x7b 0xbf 0x25 0x72
Added: llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,5 @@
+config.suffixes = ['.txt']
+
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
Added: llvm/trunk/test/MC/Disassembler/ARM64/logical.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/logical.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/logical.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/logical.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,217 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+#==---------------------------------------------------------------------------==
+# 5.4.2 Logical (immediate)
+#==---------------------------------------------------------------------------==
+
+0x00 0x00 0x00 0x12
+0x00 0x00 0x40 0x92
+0x41 0x0c 0x00 0x12
+0x41 0x0c 0x40 0x92
+0xbf 0xec 0x7c 0x92
+0x00 0x00 0x00 0x72
+0x00 0x00 0x40 0xf2
+0x41 0x0c 0x00 0x72
+0x41 0x0c 0x40 0xf2
+
+# CHECK: and w0, w0, #0x1
+# CHECK: and x0, x0, #0x1
+# CHECK: and w1, w2, #0xf
+# CHECK: and x1, x2, #0xf
+# CHECK: and sp, x5, #0xfffffffffffffff0
+# CHECK: ands w0, w0, #0x1
+# CHECK: ands x0, x0, #0x1
+# CHECK: ands w1, w2, #0xf
+# CHECK: ands x1, x2, #0xf
+
+0x41 0x00 0x12 0x52
+0x41 0x00 0x71 0xd2
+
+# CHECK: eor w1, w2, #0x4000
+# CHECK: eor x1, x2, #0x8000
+
+0x41 0x00 0x12 0x32
+0x41 0x00 0x71 0xb2
+
+# CHECK: orr w1, w2, #0x4000
+# CHECK: orr x1, x2, #0x8000
+
+#==---------------------------------------------------------------------------==
+# 5.5.3 Logical (shifted register)
+#==---------------------------------------------------------------------------==
+
+0x41 0x00 0x03 0x0a
+0x41 0x00 0x03 0x8a
+0x41 0x08 0x03 0x0a
+0x41 0x08 0x03 0x8a
+0x41 0x08 0x43 0x0a
+0x41 0x08 0x43 0x8a
+0x41 0x08 0x83 0x0a
+0x41 0x08 0x83 0x8a
+0x41 0x08 0xc3 0x0a
+0x41 0x08 0xc3 0x8a
+
+# CHECK: and w1, w2, w3
+# CHECK: and x1, x2, x3
+# CHECK: and w1, w2, w3, lsl #2
+# CHECK: and x1, x2, x3, lsl #2
+# CHECK: and w1, w2, w3, lsr #2
+# CHECK: and x1, x2, x3, lsr #2
+# CHECK: and w1, w2, w3, asr #2
+# CHECK: and x1, x2, x3, asr #2
+# CHECK: and w1, w2, w3, ror #2
+# CHECK: and x1, x2, x3, ror #2
+
+0x41 0x00 0x03 0x6a
+0x41 0x00 0x03 0xea
+0x41 0x08 0x03 0x6a
+0x41 0x08 0x03 0xea
+0x41 0x08 0x43 0x6a
+0x41 0x08 0x43 0xea
+0x41 0x08 0x83 0x6a
+0x41 0x08 0x83 0xea
+0x41 0x08 0xc3 0x6a
+0x41 0x08 0xc3 0xea
+
+# CHECK: ands w1, w2, w3
+# CHECK: ands x1, x2, x3
+# CHECK: ands w1, w2, w3, lsl #2
+# CHECK: ands x1, x2, x3, lsl #2
+# CHECK: ands w1, w2, w3, lsr #2
+# CHECK: ands x1, x2, x3, lsr #2
+# CHECK: ands w1, w2, w3, asr #2
+# CHECK: ands x1, x2, x3, asr #2
+# CHECK: ands w1, w2, w3, ror #2
+# CHECK: ands x1, x2, x3, ror #2
+
+0x41 0x00 0x23 0x0a
+0x41 0x00 0x23 0x8a
+0x41 0x0c 0x23 0x0a
+0x41 0x0c 0x23 0x8a
+0x41 0x0c 0x63 0x0a
+0x41 0x0c 0x63 0x8a
+0x41 0x0c 0xa3 0x0a
+0x41 0x0c 0xa3 0x8a
+0x41 0x0c 0xe3 0x0a
+0x41 0x0c 0xe3 0x8a
+
+# CHECK: bic w1, w2, w3
+# CHECK: bic x1, x2, x3
+# CHECK: bic w1, w2, w3, lsl #3
+# CHECK: bic x1, x2, x3, lsl #3
+# CHECK: bic w1, w2, w3, lsr #3
+# CHECK: bic x1, x2, x3, lsr #3
+# CHECK: bic w1, w2, w3, asr #3
+# CHECK: bic x1, x2, x3, asr #3
+# CHECK: bic w1, w2, w3, ror #3
+# CHECK: bic x1, x2, x3, ror #3
+
+0x41 0x00 0x23 0x6a
+0x41 0x00 0x23 0xea
+0x41 0x0c 0x23 0x6a
+0x41 0x0c 0x23 0xea
+0x41 0x0c 0x63 0x6a
+0x41 0x0c 0x63 0xea
+0x41 0x0c 0xa3 0x6a
+0x41 0x0c 0xa3 0xea
+0x41 0x0c 0xe3 0x6a
+0x41 0x0c 0xe3 0xea
+
+# CHECK: bics w1, w2, w3
+# CHECK: bics x1, x2, x3
+# CHECK: bics w1, w2, w3, lsl #3
+# CHECK: bics x1, x2, x3, lsl #3
+# CHECK: bics w1, w2, w3, lsr #3
+# CHECK: bics x1, x2, x3, lsr #3
+# CHECK: bics w1, w2, w3, asr #3
+# CHECK: bics x1, x2, x3, asr #3
+# CHECK: bics w1, w2, w3, ror #3
+# CHECK: bics x1, x2, x3, ror #3
+
+0x41 0x00 0x23 0x4a
+0x41 0x00 0x23 0xca
+0x41 0x10 0x23 0x4a
+0x41 0x10 0x23 0xca
+0x41 0x10 0x63 0x4a
+0x41 0x10 0x63 0xca
+0x41 0x10 0xa3 0x4a
+0x41 0x10 0xa3 0xca
+0x41 0x10 0xe3 0x4a
+0x41 0x10 0xe3 0xca
+
+# CHECK: eon w1, w2, w3
+# CHECK: eon x1, x2, x3
+# CHECK: eon w1, w2, w3, lsl #4
+# CHECK: eon x1, x2, x3, lsl #4
+# CHECK: eon w1, w2, w3, lsr #4
+# CHECK: eon x1, x2, x3, lsr #4
+# CHECK: eon w1, w2, w3, asr #4
+# CHECK: eon x1, x2, x3, asr #4
+# CHECK: eon w1, w2, w3, ror #4
+# CHECK: eon x1, x2, x3, ror #4
+
+0x41 0x00 0x03 0x4a
+0x41 0x00 0x03 0xca
+0x41 0x14 0x03 0x4a
+0x41 0x14 0x03 0xca
+0x41 0x14 0x43 0x4a
+0x41 0x14 0x43 0xca
+0x41 0x14 0x83 0x4a
+0x41 0x14 0x83 0xca
+0x41 0x14 0xc3 0x4a
+0x41 0x14 0xc3 0xca
+
+# CHECK: eor w1, w2, w3
+# CHECK: eor x1, x2, x3
+# CHECK: eor w1, w2, w3, lsl #5
+# CHECK: eor x1, x2, x3, lsl #5
+# CHECK: eor w1, w2, w3, lsr #5
+# CHECK: eor x1, x2, x3, lsr #5
+# CHECK: eor w1, w2, w3, asr #5
+# CHECK: eor x1, x2, x3, asr #5
+# CHECK: eor w1, w2, w3, ror #5
+# CHECK: eor x1, x2, x3, ror #5
+
+0x41 0x00 0x03 0x2a
+0x41 0x00 0x03 0xaa
+0x41 0x18 0x03 0x2a
+0x41 0x18 0x03 0xaa
+0x41 0x18 0x43 0x2a
+0x41 0x18 0x43 0xaa
+0x41 0x18 0x83 0x2a
+0x41 0x18 0x83 0xaa
+0x41 0x18 0xc3 0x2a
+0x41 0x18 0xc3 0xaa
+
+# CHECK: orr w1, w2, w3
+# CHECK: orr x1, x2, x3
+# CHECK: orr w1, w2, w3, lsl #6
+# CHECK: orr x1, x2, x3, lsl #6
+# CHECK: orr w1, w2, w3, lsr #6
+# CHECK: orr x1, x2, x3, lsr #6
+# CHECK: orr w1, w2, w3, asr #6
+# CHECK: orr x1, x2, x3, asr #6
+# CHECK: orr w1, w2, w3, ror #6
+# CHECK: orr x1, x2, x3, ror #6
+
+0x41 0x00 0x23 0x2a
+0x41 0x00 0x23 0xaa
+0x41 0x1c 0x23 0x2a
+0x41 0x1c 0x23 0xaa
+0x41 0x1c 0x63 0x2a
+0x41 0x1c 0x63 0xaa
+0x41 0x1c 0xa3 0x2a
+0x41 0x1c 0xa3 0xaa
+0x41 0x1c 0xe3 0x2a
+0x41 0x1c 0xe3 0xaa
+
+# CHECK: orn w1, w2, w3
+# CHECK: orn x1, x2, x3
+# CHECK: orn w1, w2, w3, lsl #7
+# CHECK: orn x1, x2, x3, lsl #7
+# CHECK: orn w1, w2, w3, lsr #7
+# CHECK: orn x1, x2, x3, lsr #7
+# CHECK: orn w1, w2, w3, asr #7
+# CHECK: orn x1, x2, x3, asr #7
+# CHECK: orn w1, w2, w3, ror #7
+# CHECK: orn x1, x2, x3, ror #7
Added: llvm/trunk/test/MC/Disassembler/ARM64/memory.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/memory.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/memory.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/memory.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,558 @@
+# RUN: llvm-mc --disassemble -triple arm64-apple-darwin < %s | FileCheck %s
+
+#-----------------------------------------------------------------------------
+# Indexed loads
+#-----------------------------------------------------------------------------
+
+ 0x85 0x14 0x40 0xb9
+ 0x64 0x00 0x40 0xf9
+ 0xe2 0x13 0x40 0xf9
+ 0xe5 0x07 0x40 0x3d
+ 0xe6 0x07 0x40 0x7d
+ 0xe7 0x07 0x40 0xbd
+ 0xe8 0x07 0x40 0xfd
+ 0xe9 0x07 0xc0 0x3d
+ 0x64 0x00 0x40 0x39
+ 0x20 0x78 0xa0 0xb8
+ 0x85 0x50 0x40 0x39
+
+# CHECK: ldr w5, [x4, #20]
+# CHECK: ldr x4, [x3]
+# CHECK: ldr x2, [sp, #32]
+# CHECK: ldr b5, [sp, #1]
+# CHECK: ldr h6, [sp, #2]
+# CHECK: ldr s7, [sp, #4]
+# CHECK: ldr d8, [sp, #8]
+# CHECK: ldr q9, [sp, #16]
+# CHECK: ldrb w4, [x3]
+# CHECK: ldrsw x0, [x1, x0, lsl #2]
+# CHECK: ldrb w5, [x4, #20]
+# CHECK: ldrsb w9, [x3]
+# CHECK: ldrsb x2, [sp, #128]
+# CHECK: ldrh w2, [sp, #32]
+# CHECK: ldrsh w3, [sp, #32]
+# CHECK: ldrsh x5, [x9, #24]
+# CHECK: ldrsw x9, [sp, #512]
+# CHECK: prfm pldl3strm, [sp, #32]
+
+ 0x69 0x00 0xc0 0x39
+ 0xe2 0x03 0x82 0x39
+ 0xe2 0x43 0x40 0x79
+ 0xe3 0x43 0xc0 0x79
+ 0x25 0x31 0x80 0x79
+ 0xe9 0x03 0x82 0xb9
+ 0xe5 0x13 0x80 0xf9
+ 0x40 0x00 0x80 0xf9
+ 0x41 0x00 0x80 0xf9
+ 0x42 0x00 0x80 0xf9
+ 0x43 0x00 0x80 0xf9
+ 0x44 0x00 0x80 0xf9
+ 0x45 0x00 0x80 0xf9
+ 0x50 0x00 0x80 0xf9
+ 0x51 0x00 0x80 0xf9
+ 0x52 0x00 0x80 0xf9
+ 0x53 0x00 0x80 0xf9
+ 0x54 0x00 0x80 0xf9
+ 0x55 0x00 0x80 0xf9
+
+# CHECK: prfm pldl1keep, [x2]
+# CHECK: prfm pldl1strm, [x2]
+# CHECK: prfm pldl2keep, [x2]
+# CHECK: prfm pldl2strm, [x2]
+# CHECK: prfm pldl3keep, [x2]
+# CHECK: prfm pldl3strm, [x2]
+# CHECK: prfm pstl1keep, [x2]
+# CHECK: prfm pstl1strm, [x2]
+# CHECK: prfm pstl2keep, [x2]
+# CHECK: prfm pstl2strm, [x2]
+# CHECK: prfm pstl3keep, [x2]
+# CHECK: prfm pstl3strm, [x2]
+
+#-----------------------------------------------------------------------------
+# Indexed stores
+#-----------------------------------------------------------------------------
+
+ 0x64 0x00 0x00 0xf9
+ 0xe2 0x13 0x00 0xf9
+ 0x85 0x14 0x00 0xb9
+ 0xe5 0x07 0x00 0x3d
+ 0xe6 0x07 0x00 0x7d
+ 0xe7 0x07 0x00 0xbd
+ 0xe8 0x07 0x00 0xfd
+ 0xe9 0x07 0x80 0x3d
+ 0x64 0x00 0x00 0x39
+ 0x85 0x50 0x00 0x39
+ 0xe2 0x43 0x00 0x79
+
+# CHECK: str x4, [x3]
+# CHECK: str x2, [sp, #32]
+# CHECK: str w5, [x4, #20]
+# CHECK: str b5, [sp, #1]
+# CHECK: str h6, [sp, #2]
+# CHECK: str s7, [sp, #4]
+# CHECK: str d8, [sp, #8]
+# CHECK: str q9, [sp, #16]
+# CHECK: strb w4, [x3]
+# CHECK: strb w5, [x4, #20]
+# CHECK: strh w2, [sp, #32]
+
+#-----------------------------------------------------------------------------
+# Unscaled immediate loads and stores
+#-----------------------------------------------------------------------------
+
+ 0x62 0x00 0x40 0xb8
+ 0xe2 0x83 0x41 0xb8
+ 0x62 0x00 0x40 0xf8
+ 0xe2 0x83 0x41 0xf8
+ 0xe5 0x13 0x40 0x3c
+ 0xe6 0x23 0x40 0x7c
+ 0xe7 0x43 0x40 0xbc
+ 0xe8 0x83 0x40 0xfc
+ 0xe9 0x03 0xc1 0x3c
+ 0x69 0x00 0xc0 0x38
+ 0xe2 0x03 0x88 0x38
+ 0xe3 0x03 0xc2 0x78
+ 0x25 0x81 0x81 0x78
+ 0xe9 0x03 0x98 0xb8
+
+# CHECK: ldur w2, [x3]
+# CHECK: ldur w2, [sp, #24]
+# CHECK: ldur x2, [x3]
+# CHECK: ldur x2, [sp, #24]
+# CHECK: ldur b5, [sp, #1]
+# CHECK: ldur h6, [sp, #2]
+# CHECK: ldur s7, [sp, #4]
+# CHECK: ldur d8, [sp, #8]
+# CHECK: ldur q9, [sp, #16]
+# CHECK: ldursb w9, [x3]
+# CHECK: ldursb x2, [sp, #128]
+# CHECK: ldursh w3, [sp, #32]
+# CHECK: ldursh x5, [x9, #24]
+# CHECK: ldursw x9, [sp, #-128]
+
+ 0x64 0x00 0x00 0xb8
+ 0xe2 0x03 0x02 0xb8
+ 0x64 0x00 0x00 0xf8
+ 0xe2 0x03 0x02 0xf8
+ 0x85 0x40 0x01 0xb8
+ 0xe5 0x13 0x00 0x3c
+ 0xe6 0x23 0x00 0x7c
+ 0xe7 0x43 0x00 0xbc
+ 0xe8 0x83 0x00 0xfc
+ 0xe9 0x03 0x81 0x3c
+ 0x64 0x00 0x00 0x38
+ 0x85 0x40 0x01 0x38
+ 0xe2 0x03 0x02 0x78
+ 0xe5 0x03 0x82 0xf8
+
+# CHECK: stur w4, [x3]
+# CHECK: stur w2, [sp, #32]
+# CHECK: stur x4, [x3]
+# CHECK: stur x2, [sp, #32]
+# CHECK: stur w5, [x4, #20]
+# CHECK: stur b5, [sp, #1]
+# CHECK: stur h6, [sp, #2]
+# CHECK: stur s7, [sp, #4]
+# CHECK: stur d8, [sp, #8]
+# CHECK: stur q9, [sp, #16]
+# CHECK: sturb w4, [x3]
+# CHECK: sturb w5, [x4, #20]
+# CHECK: sturh w2, [sp, #32]
+# CHECK: prfum pldl3strm, [sp, #32]
+
+#-----------------------------------------------------------------------------
+# Unprivileged loads and stores
+#-----------------------------------------------------------------------------
+
+ 0x83 0x08 0x41 0xb8
+ 0x83 0x08 0x41 0xf8
+ 0x83 0x08 0x41 0x38
+ 0x69 0x08 0xc0 0x38
+ 0xe2 0x0b 0x88 0x38
+ 0x83 0x08 0x41 0x78
+ 0xe3 0x0b 0xc2 0x78
+ 0x25 0x89 0x81 0x78
+ 0xe9 0x0b 0x98 0xb8
+
+# CHECK: ldtr w3, [x4, #16]
+# CHECK: ldtr x3, [x4, #16]
+# CHECK: ldtrb w3, [x4, #16]
+# CHECK: ldtrsb w9, [x3]
+# CHECK: ldtrsb x2, [sp, #128]
+# CHECK: ldtrh w3, [x4, #16]
+# CHECK: ldtrsh w3, [sp, #32]
+# CHECK: ldtrsh x5, [x9, #24]
+# CHECK: ldtrsw x9, [sp, #-128]
+
+ 0x85 0x48 0x01 0xb8
+ 0x64 0x08 0x00 0xf8
+ 0xe2 0x0b 0x02 0xf8
+ 0x64 0x08 0x00 0x38
+ 0x85 0x48 0x01 0x38
+ 0xe2 0x0b 0x02 0x78
+
+# CHECK: sttr w5, [x4, #20]
+# CHECK: sttr x4, [x3]
+# CHECK: sttr x2, [sp, #32]
+# CHECK: sttrb w4, [x3]
+# CHECK: sttrb w5, [x4, #20]
+# CHECK: sttrh w2, [sp, #32]
+
+#-----------------------------------------------------------------------------
+# Pre-indexed loads and stores
+#-----------------------------------------------------------------------------
+
+ 0xfd 0x8c 0x40 0xf8
+ 0xfe 0x8c 0x40 0xf8
+ 0x05 0x1c 0x40 0x3c
+ 0x06 0x2c 0x40 0x7c
+ 0x07 0x4c 0x40 0xbc
+ 0x08 0x8c 0x40 0xfc
+ 0x09 0x0c 0xc1 0x3c
+
+# CHECK: ldr fp, [x7, #8]!
+# CHECK: ldr lr, [x7, #8]!
+# CHECK: ldr b5, [x0, #1]!
+# CHECK: ldr h6, [x0, #2]!
+# CHECK: ldr s7, [x0, #4]!
+# CHECK: ldr d8, [x0, #8]!
+# CHECK: ldr q9, [x0, #16]!
+
+ 0xfe 0x8c 0x1f 0xf8
+ 0xfd 0x8c 0x1f 0xf8
+ 0x05 0xfc 0x1f 0x3c
+ 0x06 0xec 0x1f 0x7c
+ 0x07 0xcc 0x1f 0xbc
+ 0x08 0x8c 0x1f 0xfc
+ 0x09 0x0c 0x9f 0x3c
+
+# CHECK: str lr, [x7, #-8]!
+# CHECK: str fp, [x7, #-8]!
+# CHECK: str b5, [x0, #-1]!
+# CHECK: str h6, [x0, #-2]!
+# CHECK: str s7, [x0, #-4]!
+# CHECK: str d8, [x0, #-8]!
+# CHECK: str q9, [x0, #-16]!
+
+#-----------------------------------------------------------------------------
+# post-indexed loads and stores
+#-----------------------------------------------------------------------------
+
+ 0xfe 0x84 0x1f 0xf8
+ 0xfd 0x84 0x1f 0xf8
+ 0x05 0xf4 0x1f 0x3c
+ 0x06 0xe4 0x1f 0x7c
+ 0x07 0xc4 0x1f 0xbc
+ 0x08 0x84 0x1f 0xfc
+ 0x09 0x04 0x9f 0x3c
+
+# CHECK: str lr, [x7], #-8
+# CHECK: str fp, [x7], #-8
+# CHECK: str b5, [x0], #-1
+# CHECK: str h6, [x0], #-2
+# CHECK: str s7, [x0], #-4
+# CHECK: str d8, [x0], #-8
+# CHECK: str q9, [x0], #-16
+
+ 0xfd 0x84 0x40 0xf8
+ 0xfe 0x84 0x40 0xf8
+ 0x05 0x14 0x40 0x3c
+ 0x06 0x24 0x40 0x7c
+ 0x07 0x44 0x40 0xbc
+ 0x08 0x84 0x40 0xfc
+ 0x09 0x04 0xc1 0x3c
+
+# CHECK: ldr fp, [x7], #8
+# CHECK: ldr lr, [x7], #8
+# CHECK: ldr b5, [x0], #1
+# CHECK: ldr h6, [x0], #2
+# CHECK: ldr s7, [x0], #4
+# CHECK: ldr d8, [x0], #8
+# CHECK: ldr q9, [x0], #16
+
+#-----------------------------------------------------------------------------
+# Load/Store pair (indexed offset)
+#-----------------------------------------------------------------------------
+
+ 0xe3 0x09 0x42 0x29
+ 0xe4 0x27 0x7f 0xa9
+ 0xc2 0x0d 0x42 0x69
+ 0xe2 0x0f 0x7e 0x69
+ 0x4a 0x04 0x48 0x2d
+ 0x4a 0x04 0x40 0x6d
+
+# CHECK: ldp w3, w2, [x15, #16]
+# CHECK: ldp x4, x9, [sp, #-16]
+# CHECK: ldpsw x2, x3, [x14, #16]
+# CHECK: ldpsw x2, x3, [sp, #-16]
+# CHECK: ldp s10, s1, [x2, #64]
+# CHECK: ldp d10, d1, [x2]
+
+ 0xe3 0x09 0x02 0x29
+ 0xe4 0x27 0x3f 0xa9
+ 0x4a 0x04 0x08 0x2d
+ 0x4a 0x04 0x00 0x6d
+
+# CHECK: stp w3, w2, [x15, #16]
+# CHECK: stp x4, x9, [sp, #-16]
+# CHECK: stp s10, s1, [x2, #64]
+# CHECK: stp d10, d1, [x2]
+
+#-----------------------------------------------------------------------------
+# Load/Store pair (pre-indexed)
+#-----------------------------------------------------------------------------
+
+ 0xe3 0x09 0xc2 0x29
+ 0xe4 0x27 0xff 0xa9
+ 0xc2 0x0d 0xc2 0x69
+ 0xe2 0x0f 0xfe 0x69
+ 0x4a 0x04 0xc8 0x2d
+ 0x4a 0x04 0xc1 0x6d
+
+# CHECK: ldp w3, w2, [x15, #16]!
+# CHECK: ldp x4, x9, [sp, #-16]!
+# CHECK: ldpsw x2, x3, [x14, #16]!
+# CHECK: ldpsw x2, x3, [sp, #-16]!
+# CHECK: ldp s10, s1, [x2, #64]!
+# CHECK: ldp d10, d1, [x2, #16]!
+
+ 0xe3 0x09 0x82 0x29
+ 0xe4 0x27 0xbf 0xa9
+ 0x4a 0x04 0x88 0x2d
+ 0x4a 0x04 0x81 0x6d
+
+# CHECK: stp w3, w2, [x15, #16]!
+# CHECK: stp x4, x9, [sp, #-16]!
+# CHECK: stp s10, s1, [x2, #64]!
+# CHECK: stp d10, d1, [x2, #16]!
+
+#-----------------------------------------------------------------------------
+# Load/Store pair (post-indexed)
+#-----------------------------------------------------------------------------
+
+ 0xe3 0x09 0xc2 0x28
+ 0xe4 0x27 0xff 0xa8
+ 0xc2 0x0d 0xc2 0x68
+ 0xe2 0x0f 0xfe 0x68
+ 0x4a 0x04 0xc8 0x2c
+ 0x4a 0x04 0xc1 0x6c
+
+# CHECK: ldp w3, w2, [x15], #16
+# CHECK: ldp x4, x9, [sp], #-16
+# CHECK: ldpsw x2, x3, [x14], #16
+# CHECK: ldpsw x2, x3, [sp], #-16
+# CHECK: ldp s10, s1, [x2], #64
+# CHECK: ldp d10, d1, [x2], #16
+
+ 0xe3 0x09 0x82 0x28
+ 0xe4 0x27 0xbf 0xa8
+ 0x4a 0x04 0x88 0x2c
+ 0x4a 0x04 0x81 0x6c
+
+# CHECK: stp w3, w2, [x15], #16
+# CHECK: stp x4, x9, [sp], #-16
+# CHECK: stp s10, s1, [x2], #64
+# CHECK: stp d10, d1, [x2], #16
+
+#-----------------------------------------------------------------------------
+# Load/Store pair (no-allocate)
+#-----------------------------------------------------------------------------
+
+ 0xe3 0x09 0x42 0x28
+ 0xe4 0x27 0x7f 0xa8
+ 0x4a 0x04 0x48 0x2c
+ 0x4a 0x04 0x40 0x6c
+
+# CHECK: ldnp w3, w2, [x15, #16]
+# CHECK: ldnp x4, x9, [sp, #-16]
+# CHECK: ldnp s10, s1, [x2, #64]
+# CHECK: ldnp d10, d1, [x2]
+
+ 0xe3 0x09 0x02 0x28
+ 0xe4 0x27 0x3f 0xa8
+ 0x4a 0x04 0x08 0x2c
+ 0x4a 0x04 0x00 0x6c
+
+# CHECK: stnp w3, w2, [x15, #16]
+# CHECK: stnp x4, x9, [sp, #-16]
+# CHECK: stnp s10, s1, [x2, #64]
+# CHECK: stnp d10, d1, [x2]
+
+#-----------------------------------------------------------------------------
+# Load/Store register offset
+#-----------------------------------------------------------------------------
+
+ 0x00 0x68 0x60 0xb8
+ 0x00 0x78 0x60 0xb8
+ 0x00 0x68 0x60 0xf8
+ 0x00 0x78 0x60 0xf8
+ 0x00 0xe8 0x60 0xf8
+
+# CHECK: ldr w0, [x0, x0]
+# CHECK: ldr w0, [x0, x0, lsl #2]
+# CHECK: ldr x0, [x0, x0]
+# CHECK: ldr x0, [x0, x0, lsl #3]
+# CHECK: ldr x0, [x0, x0, sxtx]
+
+ 0x21 0x68 0x62 0x3c
+ 0x21 0x78 0x62 0x3c
+ 0x21 0x68 0x62 0x7c
+ 0x21 0x78 0x62 0x7c
+ 0x21 0x68 0x62 0xbc
+ 0x21 0x78 0x62 0xbc
+ 0x21 0x68 0x62 0xfc
+ 0x21 0x78 0x62 0xfc
+ 0x21 0x68 0xe2 0x3c
+ 0x21 0x78 0xe2 0x3c
+
+# CHECK: ldr b1, [x1, x2]
+# CHECK: ldr b1, [x1, x2, lsl #0]
+# CHECK: ldr h1, [x1, x2]
+# CHECK: ldr h1, [x1, x2, lsl #1]
+# CHECK: ldr s1, [x1, x2]
+# CHECK: ldr s1, [x1, x2, lsl #2]
+# CHECK: ldr d1, [x1, x2]
+# CHECK: ldr d1, [x1, x2, lsl #3]
+# CHECK: ldr q1, [x1, x2]
+# CHECK: ldr q1, [x1, x2, lsl #4]
+
+ 0xe1 0x6b 0x23 0xfc
+ 0xe1 0x5b 0x23 0xfc
+ 0xe1 0x6b 0xa3 0x3c
+ 0xe1 0x5b 0xa3 0x3c
+
+# CHECK: str d1, [sp, x3]
+# CHECK: str d1, [sp, x3, uxtw #3]
+# CHECK: str q1, [sp, x3]
+# CHECK: str q1, [sp, x3, uxtw #4]
+
+#-----------------------------------------------------------------------------
+# Load/Store exclusive
+#-----------------------------------------------------------------------------
+
+ 0x26 0x7c 0x5f 0x08
+ 0x26 0x7c 0x5f 0x48
+ 0x27 0x0d 0x7f 0x88
+ 0x27 0x0d 0x7f 0xc8
+
+# CHECK: ldxrb w6, [x1]
+# CHECK: ldxrh w6, [x1]
+# CHECK: ldxp w7, w3, [x9]
+# CHECK: ldxp x7, x3, [x9]
+
+ 0x64 0x7c 0x01 0xc8
+ 0x64 0x7c 0x01 0x88
+ 0x64 0x7c 0x01 0x08
+ 0x64 0x7c 0x01 0x48
+ 0x22 0x18 0x21 0xc8
+ 0x22 0x18 0x21 0x88
+
+# CHECK: stxr w1, x4, [x3]
+# CHECK: stxr w1, w4, [x3]
+# CHECK: stxrb w1, w4, [x3]
+# CHECK: stxrh w1, w4, [x3]
+# CHECK: stxp w1, x2, x6, [x1]
+# CHECK: stxp w1, w2, w6, [x1]
+
+#-----------------------------------------------------------------------------
+# Load-acquire/Store-release non-exclusive
+#-----------------------------------------------------------------------------
+
+ 0xe4 0xff 0xdf 0x88
+ 0xe4 0xff 0xdf 0xc8
+ 0xe4 0xff 0xdf 0x08
+ 0xe4 0xff 0xdf 0x48
+
+# CHECK: ldar w4, [sp]
+# CHECK: ldar x4, [sp]
+# CHECK: ldarb w4, [sp]
+# CHECK: ldarh w4, [sp]
+
+ 0xc3 0xfc 0x9f 0x88
+ 0xc3 0xfc 0x9f 0xc8
+ 0xc3 0xfc 0x9f 0x08
+ 0xc3 0xfc 0x9f 0x48
+
+# CHECK: stlr w3, [x6]
+# CHECK: stlr x3, [x6]
+# CHECK: stlrb w3, [x6]
+# CHECK: stlrh w3, [x6]
+
+#-----------------------------------------------------------------------------
+# Load-acquire/Store-release exclusive
+#-----------------------------------------------------------------------------
+
+ 0x82 0xfc 0x5f 0x88
+ 0x82 0xfc 0x5f 0xc8
+ 0x82 0xfc 0x5f 0x08
+ 0x82 0xfc 0x5f 0x48
+ 0x22 0x98 0x7f 0x88
+ 0x22 0x98 0x7f 0xc8
+
+# CHECK: ldaxr w2, [x4]
+# CHECK: ldaxr x2, [x4]
+# CHECK: ldaxrb w2, [x4]
+# CHECK: ldaxrh w2, [x4]
+# CHECK: ldaxp w2, w6, [x1]
+# CHECK: ldaxp x2, x6, [x1]
+
+ 0x27 0xfc 0x08 0xc8
+ 0x27 0xfc 0x08 0x88
+ 0x27 0xfc 0x08 0x08
+ 0x27 0xfc 0x08 0x48
+ 0x22 0x98 0x21 0xc8
+ 0x22 0x98 0x21 0x88
+
+# CHECK: stlxr w8, x7, [x1]
+# CHECK: stlxr w8, w7, [x1]
+# CHECK: stlxrb w8, w7, [x1]
+# CHECK: stlxrh w8, w7, [x1]
+# CHECK: stlxp w1, x2, x6, [x1]
+# CHECK: stlxp w1, w2, w6, [x1]
+
+#-----------------------------------------------------------------------------
+# Load/Store with explicit LSL values
+#-----------------------------------------------------------------------------
+ 0x20 0x78 0xa0 0xb8
+ 0x20 0x78 0x60 0xf8
+ 0x20 0x78 0x20 0xf8
+ 0x20 0x78 0x60 0xb8
+ 0x20 0x78 0x20 0xb8
+ 0x20 0x78 0xe0 0x3c
+ 0x20 0x78 0xa0 0x3c
+ 0x20 0x78 0x60 0xfc
+ 0x20 0x78 0x20 0xfc
+ 0x20 0x78 0x60 0xbc
+ 0x20 0x78 0x20 0xbc
+ 0x20 0x78 0x60 0x7c
+ 0x20 0x78 0x60 0x3c
+ 0x20 0x78 0x60 0x38
+ 0x20 0x78 0x20 0x38
+ 0x20 0x78 0xe0 0x38
+ 0x20 0x78 0x60 0x78
+ 0x20 0x78 0x20 0x78
+ 0x20 0x78 0xe0 0x78
+ 0x20 0x78 0xa0 0x38
+ 0x20 0x78 0xa0 0x78
+
+# CHECK: ldrsw x0, [x1, x0, lsl #2]
+# CHECK: ldr x0, [x1, x0, lsl #3]
+# CHECK: str x0, [x1, x0, lsl #3]
+# CHECK: ldr w0, [x1, x0, lsl #2]
+# CHECK: str w0, [x1, x0, lsl #2]
+# CHECK: ldr q0, [x1, x0, lsl #4]
+# CHECK: str q0, [x1, x0, lsl #4]
+# CHECK: ldr d0, [x1, x0, lsl #3]
+# CHECK: str d0, [x1, x0, lsl #3]
+# CHECK: ldr s0, [x1, x0, lsl #2]
+# CHECK: str s0, [x1, x0, lsl #2]
+# CHECK: ldr h0, [x1, x0, lsl #1]
+# CHECK: ldr b0, [x1, x0, lsl #0]
+# CHECK: ldrb w0, [x1, x0, lsl #0]
+# CHECK: strb w0, [x1, x0, lsl #0]
+# CHECK: ldrsb w0, [x1, x0, lsl #0]
+# CHECK: ldrh w0, [x1, x0, lsl #1]
+# CHECK: strh w0, [x1, x0, lsl #1]
+# CHECK: ldrsh w0, [x1, x0, lsl #1]
+# CHECK: ldrsb x0, [x1, x0, lsl #0]
+# CHECK: ldrsh x0, [x1, x0, lsl #1]
Added: llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/scalar-fp.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,255 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+#-----------------------------------------------------------------------------
+# Floating-point arithmetic
+#-----------------------------------------------------------------------------
+
+0x41 0xc0 0x20 0x1e
+0x41 0xc0 0x60 0x1e
+
+# CHECK: fabs s1, s2
+# CHECK: fabs d1, d2
+
+0x41 0x28 0x23 0x1e
+0x41 0x28 0x63 0x1e
+
+# CHECK: fadd s1, s2, s3
+# CHECK: fadd d1, d2, d3
+
+0x41 0x18 0x23 0x1e
+0x41 0x18 0x63 0x1e
+
+# CHECK: fdiv s1, s2, s3
+# CHECK: fdiv d1, d2, d3
+
+0x41 0x10 0x03 0x1f
+0x41 0x10 0x43 0x1f
+
+# CHECK: fmadd s1, s2, s3, s4
+# CHECK: fmadd d1, d2, d3, d4
+
+0x41 0x48 0x23 0x1e
+0x41 0x48 0x63 0x1e
+0x41 0x68 0x23 0x1e
+0x41 0x68 0x63 0x1e
+
+# CHECK: fmax s1, s2, s3
+# CHECK: fmax d1, d2, d3
+# CHECK: fmaxnm s1, s2, s3
+# CHECK: fmaxnm d1, d2, d3
+
+0x41 0x58 0x23 0x1e
+0x41 0x58 0x63 0x1e
+0x41 0x78 0x23 0x1e
+0x41 0x78 0x63 0x1e
+
+# CHECK: fmin s1, s2, s3
+# CHECK: fmin d1, d2, d3
+# CHECK: fminnm s1, s2, s3
+# CHECK: fminnm d1, d2, d3
+
+0x41 0x90 0x03 0x1f
+0x41 0x90 0x43 0x1f
+
+# CHECK: fmsub s1, s2, s3, s4
+# CHECK: fmsub d1, d2, d3, d4
+
+0x41 0x08 0x23 0x1e
+0x41 0x08 0x63 0x1e
+
+# CHECK: fmul s1, s2, s3
+# CHECK: fmul d1, d2, d3
+
+0x41 0x40 0x21 0x1e
+0x41 0x40 0x61 0x1e
+
+# CHECK: fneg s1, s2
+# CHECK: fneg d1, d2
+
+0x41 0x10 0x23 0x1f
+0x41 0x10 0x63 0x1f
+
+# CHECK: fnmadd s1, s2, s3, s4
+# CHECK: fnmadd d1, d2, d3, d4
+
+0x41 0x90 0x23 0x1f
+0x41 0x90 0x63 0x1f
+
+# CHECK: fnmsub s1, s2, s3, s4
+# CHECK: fnmsub d1, d2, d3, d4
+
+0x41 0x88 0x23 0x1e
+0x41 0x88 0x63 0x1e
+
+# CHECK: fnmul s1, s2, s3
+# CHECK: fnmul d1, d2, d3
+
+0x41 0xc0 0x21 0x1e
+0x41 0xc0 0x61 0x1e
+
+# CHECK: fsqrt s1, s2
+# CHECK: fsqrt d1, d2
+
+0x41 0x38 0x23 0x1e
+0x41 0x38 0x63 0x1e
+
+# CHECK: fsub s1, s2, s3
+# CHECK: fsub d1, d2, d3
+
+#-----------------------------------------------------------------------------
+# Floating-point comparison
+#-----------------------------------------------------------------------------
+
+0x20 0x04 0x22 0x1e
+0x20 0x04 0x62 0x1e
+0x30 0x04 0x22 0x1e
+0x30 0x04 0x62 0x1e
+
+# CHECK: fccmp s1, s2, #0, eq
+# CHECK: fccmp d1, d2, #0, eq
+# CHECK: fccmpe s1, s2, #0, eq
+# CHECK: fccmpe d1, d2, #0, eq
+
+0x20 0x20 0x22 0x1e
+0x20 0x20 0x62 0x1e
+0x28 0x20 0x20 0x1e
+0x28 0x20 0x60 0x1e
+0x30 0x20 0x22 0x1e
+0x30 0x20 0x62 0x1e
+0x38 0x20 0x20 0x1e
+0x38 0x20 0x60 0x1e
+
+# CHECK: fcmp s1, s2
+# CHECK: fcmp d1, d2
+# CHECK: fcmp s1, #0.0
+# CHECK: fcmp d1, #0.0
+# CHECK: fcmpe s1, s2
+# CHECK: fcmpe d1, d2
+# CHECK: fcmpe s1, #0.0
+# CHECK: fcmpe d1, #0.0
+
+#-----------------------------------------------------------------------------
+# Floating-point conditional select
+#-----------------------------------------------------------------------------
+
+0x41 0x0c 0x23 0x1e
+0x41 0x0c 0x63 0x1e
+
+# CHECK: fcsel s1, s2, s3, eq
+# CHECK: fcsel d1, d2, d3, eq
+
+#-----------------------------------------------------------------------------
+# Floating-point convert
+#-----------------------------------------------------------------------------
+
+0x41 0xc0 0x63 0x1e
+0x41 0x40 0x62 0x1e
+0x41 0xc0 0xe2 0x1e
+0x41 0x40 0xe2 0x1e
+0x41 0xc0 0x22 0x1e
+0x41 0xc0 0x23 0x1e
+
+# CHECK: fcvt h1, d2
+# CHECK: fcvt s1, d2
+# CHECK: fcvt d1, h2
+# CHECK: fcvt s1, h2
+# CHECK: fcvt d1, s2
+# CHECK: fcvt h1, s2
+
+0x41 0x00 0x44 0x1e
+0x41 0x04 0x44 0x1e
+0x41 0x00 0x44 0x9e
+0x41 0x04 0x44 0x9e
+0x41 0x00 0x04 0x1e
+0x41 0x04 0x04 0x1e
+0x41 0x00 0x04 0x9e
+0x41 0x04 0x04 0x9e
+
+#-----------------------------------------------------------------------------
+# Floating-point move
+#-----------------------------------------------------------------------------
+
+0x41 0x00 0x27 0x1e
+0x41 0x00 0x26 0x1e
+0x41 0x00 0x67 0x9e
+0x41 0x00 0x66 0x9e
+
+# CHECK: fmov s1, w2
+# CHECK: fmov w1, s2
+# CHECK: fmov d1, x2
+# CHECK: fmov x1, d2
+
+0x01 0x10 0x28 0x1e
+0x01 0x10 0x68 0x1e
+0x01 0xf0 0x7b 0x1e
+0x01 0xf0 0x6b 0x1e
+
+# CHECK: fmov s1, #1.250000e-01
+# CHECK: fmov d1, #1.250000e-01
+# CHECK: fmov d1, #-4.843750e-01
+# CHECK: fmov d1, #4.843750e-01
+
+0x41 0x40 0x20 0x1e
+0x41 0x40 0x60 0x1e
+
+# CHECK: fmov s1, s2
+# CHECK: fmov d1, d2
+
+#-----------------------------------------------------------------------------
+# Floating-point round to integral
+#-----------------------------------------------------------------------------
+
+0x41 0x40 0x26 0x1e
+0x41 0x40 0x66 0x1e
+
+# CHECK: frinta s1, s2
+# CHECK: frinta d1, d2
+
+0x41 0xc0 0x27 0x1e
+0x41 0xc0 0x67 0x1e
+
+# CHECK: frinti s1, s2
+# CHECK: frinti d1, d2
+
+0x41 0x40 0x25 0x1e
+0x41 0x40 0x65 0x1e
+
+# CHECK: frintm s1, s2
+# CHECK: frintm d1, d2
+
+0x41 0x40 0x24 0x1e
+0x41 0x40 0x64 0x1e
+
+# CHECK: frintn s1, s2
+# CHECK: frintn d1, d2
+
+0x41 0xc0 0x24 0x1e
+0x41 0xc0 0x64 0x1e
+
+# CHECK: frintp s1, s2
+# CHECK: frintp d1, d2
+
+0x41 0x40 0x27 0x1e
+0x41 0x40 0x67 0x1e
+
+# CHECK: frintx s1, s2
+# CHECK: frintx d1, d2
+
+0x41 0xc0 0x25 0x1e
+0x41 0xc0 0x65 0x1e
+
+# CHECK: frintz s1, s2
+# CHECK: frintz d1, d2
+
+ 0x00 0x3c 0xe0 0x7e
+ 0x00 0x8c 0xe0 0x5e
+
+# CHECK: cmhs d0, d0, d0
+# CHECK: cmtst d0, d0, d0
+
+0x00 0x00 0xaf 0x9e
+0x00 0x00 0xae 0x9e
+
+# CHECK: fmov.d v0[1], x0
+# CHECK: fmov.d x0, v0[1]
+
Added: llvm/trunk/test/MC/Disassembler/ARM64/system.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM64/system.txt?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM64/system.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM64/system.txt Sat Mar 29 05:18:08 2014
@@ -0,0 +1,58 @@
+# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
+
+
+#-----------------------------------------------------------------------------
+# Hint encodings
+#-----------------------------------------------------------------------------
+
+ 0x1f 0x20 0x03 0xd5
+# CHECK: nop
+ 0x9f 0x20 0x03 0xd5
+# CHECK: sev
+ 0xbf 0x20 0x03 0xd5
+# CHECK: sevl
+ 0x5f 0x20 0x03 0xd5
+# CHECK: wfe
+ 0x7f 0x20 0x03 0xd5
+# CHECK: wfi
+ 0x3f 0x20 0x03 0xd5
+# CHECK: yield
+
+#-----------------------------------------------------------------------------
+# Single-immediate operand instructions
+#-----------------------------------------------------------------------------
+
+ 0x5f 0x3a 0x03 0xd5
+# CHECK: clrex #10
+ 0xdf 0x3f 0x03 0xd5
+# CHECK: isb{{$}}
+ 0xbf 0x33 0x03 0xd5
+# CHECK: dmb osh
+ 0x9f 0x37 0x03 0xd5
+# CHECK: dsb nsh
+
+#-----------------------------------------------------------------------------
+# Generic system instructions
+#-----------------------------------------------------------------------------
+ 0xff 0x05 0x0a 0xd5
+ 0xe7 0x6a 0x0f 0xd5
+ 0xf4 0x3f 0x2e 0xd5
+ 0xbf 0x40 0x00 0xd5
+ 0x00 0x00 0x10 0xd5
+ 0x00 0x00 0x30 0xd5
+
+# CHECK: sys #2, c0, c5, #7
+# CHECK: sys #7, c6, c10, #7, x7
+# CHECK: sysl x20, #6, c3, c15, #7
+# CHECK: msr SPSel, #0
+# CHECK: msr S2_0_C0_C0_0, x0
+# CHECK: mrs x0, S2_0_C0_C0_0
+
+ 0x40 0xc0 0x1e 0xd5
+ 0x40 0xc0 0x1a 0xd5
+ 0x40 0xc0 0x19 0xd5
+
+# CHECK: msr RMR_EL3, x0
+# CHECK: msr RMR_EL2, x0
+# CHECK: msr RMR_EL1, x0
+
Added: llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s (added)
+++ llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,21 @@
+; RUN: llvm-mc -triple arm64-apple-darwin -filetype=obj -o - < %s | macho-dump -dump-section-data | FileCheck %s
+; rdar://13028719
+
+ .globl context_save0
+ .align 6
+Lcontext_save0:
+context_save0:
+ .fill 2, 8, 5
+Lcontext_save0_end:
+Lcontext_save0_size: .quad (Lcontext_save0_end - Lcontext_save0)
+
+ .align 6
+Lcontext_save1:
+ .fill 2, 8, 0
+Lcontext_save1_end:
+Lcontext_save1_size: .quad (Lcontext_save1_end - Lcontext_save1)
+
+Llockup_release:
+ .quad 0
+
+; CHECK: ('_section_data', '05000000 00000000 05000000 00000000 10000000 00000000 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 1f2003d5 00000000 00000000 00000000 00000000 10000000 00000000 00000000 00000000')
Added: llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s (added)
+++ llvm/trunk/test/MC/MachO/ARM64/darwin-ARM64-reloc.s Sat Mar 29 05:18:08 2014
@@ -0,0 +1,157 @@
+; RUN: llvm-mc -n -triple arm64-apple-darwin10 %s -filetype=obj -o - | macho-dump --dump-section-data | FileCheck %s
+
+ .text
+_fred:
+ bl _func
+ bl _func + 20
+
+ adrp x3, _data at page
+ ldr w2, [x3, _data at pageoff]
+
+ add x3, x3, _data at pageoff + 4
+
+ adrp x3, _data at page+1
+ ldr w2, [x3, _data at pageoff + 4]
+
+ adrp x3, _data_ext at gotpage
+ ldr w2, [x3, _data_ext at gotpageoff]
+
+ .data
+_data:
+ .quad _foo
+ .quad _foo + 4
+ .quad _foo - _bar
+ .quad _foo - _bar + 4
+
+ .long _foo - _bar
+
+ .quad _foo at got
+ .long _foo at got - .
+
+
+; CHECK: ('cputype', 16777228)
+; CHECK: ('cpusubtype', 0)
+; CHECK: ('filetype', 1)
+; CHECK: ('num_load_commands', 3)
+; CHECK: ('load_commands_size', 336)
+; CHECK: ('flag', 0)
+; CHECK: ('reserved', 0)
+; CHECK: ('load_commands', [
+; CHECK: # Load Command 0
+; CHECK: (('command', 25)
+; CHECK: ('size', 232)
+; CHECK: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+; CHECK: ('vm_addr', 0)
+; CHECK: ('vm_size', 84)
+; CHECK: ('file_offset', 368)
+; CHECK: ('file_size', 84)
+; CHECK: ('maxprot', 7)
+; CHECK: ('initprot', 7)
+; CHECK: ('num_sections', 2)
+; CHECK: ('flags', 0)
+; CHECK: ('sections', [
+; CHECK: # Section 0
+; CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+; CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+; CHECK: ('address', 0)
+; CHECK: ('size', 36)
+; CHECK: ('offset', 368)
+; CHECK: ('alignment', 0)
+; CHECK: ('reloc_offset', 452)
+; CHECK: ('num_reloc', 13)
+; CHECK: ('flags', 0x80000400)
+; CHECK: ('reserved1', 0)
+; CHECK: ('reserved2', 0)
+; CHECK: ('reserved3', 0)
+; CHECK: ),
+; CHECK: ('_relocations', [
+; CHECK: # Relocation 0
+; CHECK: (('word-0', 0x20),
+; CHECK: ('word-1', 0x6c000005)),
+; CHECK: # Relocation 1
+; CHECK: (('word-0', 0x1c),
+; CHECK: ('word-1', 0x5d000005)),
+; CHECK: # Relocation 2
+; CHECK: (('word-0', 0x18),
+; CHECK: ('word-1', 0xa4000004)),
+; CHECK: # Relocation 3
+; CHECK: (('word-0', 0x18),
+; CHECK: ('word-1', 0x4c000002)),
+; CHECK: # Relocation 4
+; CHECK: (('word-0', 0x14),
+; CHECK: ('word-1', 0xa4000001)),
+; CHECK: # Relocation 5
+; CHECK: (('word-0', 0x14),
+; CHECK: ('word-1', 0x3d000002)),
+; CHECK: # Relocation 6
+; CHECK: (('word-0', 0x10),
+; CHECK: ('word-1', 0xa4000004)),
+; CHECK: # Relocation 7
+; CHECK: (('word-0', 0x10),
+; CHECK: ('word-1', 0x4c000002)),
+; CHECK: # Relocation 8
+; CHECK: (('word-0', 0xc),
+; CHECK: ('word-1', 0x4c000002)),
+; CHECK: # Relocation 9
+; CHECK: (('word-0', 0x8),
+; CHECK: ('word-1', 0x3d000002)),
+; CHECK: # Relocation 10
+; CHECK: (('word-0', 0x4),
+; CHECK: ('word-1', 0xa4000014)),
+; CHECK: # Relocation 11
+; CHECK: (('word-0', 0x4),
+; CHECK: ('word-1', 0x2d000007)),
+; CHECK: # Relocation 12
+; CHECK: (('word-0', 0x0),
+; CHECK: ('word-1', 0x2d000007)),
+; CHECK: ])
+; CHECK: ('_section_data', '00000094 00000094 03000090 620040b9 63000091 03000090 620040b9 03000090 620040b9')
+; CHECK: # Section 1
+; CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+; CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+; CHECK: ('address', 36)
+; CHECK: ('size', 48)
+; CHECK: ('offset', 404)
+; CHECK: ('alignment', 0)
+; CHECK: ('reloc_offset', 556)
+; CHECK: ('num_reloc', 10)
+; CHECK: ('flags', 0x0)
+; CHECK: ('reserved1', 0)
+; CHECK: ('reserved2', 0)
+; CHECK: ('reserved3', 0)
+; CHECK: ),
+; CHECK: ('_relocations', [
+; CHECK: # Relocation 0
+; CHECK: (('word-0', 0x2c),
+; CHECK: ('word-1', 0x7d000006)),
+; CHECK: # Relocation 1
+; CHECK: (('word-0', 0x24),
+; CHECK: ('word-1', 0x7e000006)),
+; CHECK: # Relocation 2
+; CHECK: (('word-0', 0x20),
+; CHECK: ('word-1', 0x1c000004)),
+; CHECK: # Relocation 3
+; CHECK: (('word-0', 0x20),
+; CHECK: ('word-1', 0xc000006)),
+; CHECK: # Relocation 4
+; CHECK: (('word-0', 0x18),
+; CHECK: ('word-1', 0x1e000004)),
+; CHECK: # Relocation 5
+; CHECK: (('word-0', 0x18),
+; CHECK: ('word-1', 0xe000006)),
+; CHECK: # Relocation 6
+; CHECK: (('word-0', 0x10),
+; CHECK: ('word-1', 0x1e000004)),
+; CHECK: # Relocation 7
+; CHECK: (('word-0', 0x10),
+; CHECK: ('word-1', 0xe000006)),
+; CHECK: # Relocation 8
+; CHECK: (('word-0', 0x8),
+; CHECK: ('word-1', 0xe000006)),
+; CHECK: # Relocation 9
+; CHECK: (('word-0', 0x0),
+; CHECK: ('word-1', 0xe000006)),
+; CHECK: ])
+; CHECK: ('_section_data', '00000000 00000000 04000000 00000000 00000000 00000000 04000000 00000000 00000000 00000000 00000000 d4ffffff')
+; CHECK: ])
+; CHECK: ),
Added: llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/MC/MachO/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,4 @@
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
+
Added: llvm/trunk/test/Transforms/GlobalMerge/ARM/arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM/arm.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM/arm.ll (added)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM/arm.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,85 @@
+; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O0 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O0 -o - -global-merge=true | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O1 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - -global-merge=true | FileCheck -check-prefix=MERGE %s
+
+; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
+; MERGE: .zerofill __DATA,__bss,__MergedGlobals,60,4
+; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
+
+; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
+; NO-MERGE: .zerofill __DATA,__bss,_bar,20,2
+; NO-MERGE: .zerofill __DATA,__bss,_baz,20,2
+; NO-MERGE: .zerofill __DATA,__bss,_foo,20,2
+; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-ios3.0.0"
+
+ at bar = internal global [5 x i32] zeroinitializer, align 4
+ at baz = internal global [5 x i32] zeroinitializer, align 4
+ at foo = internal global [5 x i32] zeroinitializer, align 4
+
+; Function Attrs: nounwind ssp
+define internal void @initialize() #0 {
+ %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 0), align 4, !tbaa !1
+ %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 0), align 4, !tbaa !1
+ %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 1), align 4, !tbaa !1
+ %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 1), align 4, !tbaa !1
+ %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 2), align 4, !tbaa !1
+ %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 2), align 4, !tbaa !1
+ %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 3), align 4, !tbaa !1
+ %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 3), align 4, !tbaa !1
+ %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
+ %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #3
+ store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+ ret void
+}
+
+declare i32 @calc(...) #1
+
+; Function Attrs: nounwind ssp
+define internal void @calculate() #0 {
+ %1 = load <4 x i32>* bitcast ([5 x i32]* @bar to <4 x i32>*), align 4
+ %2 = load <4 x i32>* bitcast ([5 x i32]* @baz to <4 x i32>*), align 4
+ %3 = mul <4 x i32> %2, %1
+ store <4 x i32> %3, <4 x i32>* bitcast ([5 x i32]* @foo to <4 x i32>*), align 4
+ %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i32 0, i32 4), align 4, !tbaa !1
+ %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i32 0, i32 4), align 4, !tbaa !1
+ %6 = mul nsw i32 %5, %4
+ store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 4), align 4, !tbaa !1
+ ret void
+}
+
+; Function Attrs: nounwind readnone ssp
+define internal i32* @returnFoo() #2 {
+ ret i32* getelementptr inbounds ([5 x i32]* @foo, i32 0, i32 0)
+}
+
+attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #3 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = metadata !{metadata !"LLVM version 3.4 "}
+!1 = metadata !{metadata !2, metadata !2, i64 0}
+!2 = metadata !{metadata !"int", metadata !3, i64 0}
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}
Added: llvm/trunk/test/Transforms/GlobalMerge/ARM/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM/lit.local.cfg (added)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,4 @@
+targets = set(config.root.targets_to_build.split())
+if not 'ARM' in targets:
+ config.unsupported = True
+
Added: llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll (added)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM64/arm64.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,88 @@
+; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O0 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O0 -o - -global-merge=true | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - | FileCheck -check-prefix=MERGE %s
+; RUN: llc %s -O1 -o - -global-merge=false | FileCheck -check-prefix=NO-MERGE %s
+; RUN: llc %s -O1 -o - -global-merge=true | FileCheck -check-prefix=MERGE %s
+
+; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
+; MERGE: .zerofill __DATA,__bss,__MergedGlobals,60,4
+; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2
+; MERGE-NOT: .zerofill __DATA,__bss,_foo,20,2
+
+; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
+; NO-MERGE: .zerofill __DATA,__bss,_bar,20,2
+; NO-MERGE: .zerofill __DATA,__bss,_baz,20,2
+; NO-MERGE: .zerofill __DATA,__bss,_foo,20,2
+; NO-MERGE-NOT: .zerofill __DATA,__bss,__MergedGlobals,60,4
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
+target triple = "arm64-apple-ios7.0.0"
+
+ at bar = internal global [5 x i32] zeroinitializer, align 4
+ at baz = internal global [5 x i32] zeroinitializer, align 4
+ at foo = internal global [5 x i32] zeroinitializer, align 4
+
+; Function Attrs: nounwind ssp
+define internal void @initialize() #0 {
+ %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
+ %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
+ %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
+ %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
+ %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
+ %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
+ %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
+ %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
+ %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
+ %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2
+ store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
+ ret void
+}
+
+declare i32 @calc(...)
+
+; Function Attrs: nounwind ssp
+define internal void @calculate() #0 {
+ %1 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4
+ %2 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4
+ %3 = mul nsw i32 %2, %1
+ store i32 %3, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0), align 4
+ %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4
+ %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4
+ %6 = mul nsw i32 %5, %4
+ store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 1), align 4
+ %7 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4
+ %8 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4
+ %9 = mul nsw i32 %8, %7
+ store i32 %9, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 2), align 4
+ %10 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4
+ %11 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4
+ %12 = mul nsw i32 %11, %10
+ store i32 %12, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 3), align 4
+ %13 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4
+ %14 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4
+ %15 = mul nsw i32 %14, %13
+ store i32 %15, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 4), align 4
+ ret void
+}
+
+; Function Attrs: nounwind readnone ssp
+define internal i32* @returnFoo() #1 {
+ ret i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0)
+}
+
+attributes #0 = { nounwind ssp }
+attributes #1 = { nounwind readnone ssp }
+attributes #2 = { nounwind }
Added: llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/Transforms/GlobalMerge/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,4 @@
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
+
Modified: llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll?rev=205090&r1=205089&r2=205090&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll Sat Mar 29 05:18:08 2014
@@ -1,6 +1,3 @@
-target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
-target triple = "thumbv7-apple-ios0"
-
; RUN: opt -S -instcombine < %s | FileCheck %s
define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp {
@@ -67,6 +64,72 @@ entry:
declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+; ARM64 variants - <rdar://problem/12349617>
+
+define <4 x i32> @mulByZeroARM64(<4 x i16> %x) nounwind readnone ssp {
+entry:
+ %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
+ ret <4 x i32> %a
+; CHECK: entry:
+; CHECK-NEXT: ret <4 x i32> zeroinitializer
+}
+
+define <4 x i32> @mulByOneARM64(<4 x i16> %x) nounwind readnone ssp {
+entry:
+ %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ ret <4 x i32> %a
+; CHECK: entry:
+; CHECK-NEXT: %a = sext <4 x i16> %x to <4 x i32>
+; CHECK-NEXT: ret <4 x i32> %a
+}
+
+define <4 x i32> @constantMulARM64() nounwind readnone ssp {
+entry:
+ %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+ ret <4 x i32> %a
+; CHECK: entry:
+; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
+}
+
+define <4 x i32> @constantMulSARM64() nounwind readnone ssp {
+entry:
+ %b = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ ret <4 x i32> %b
+; CHECK: entry:
+; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
+}
+
+define <4 x i32> @constantMulUARM64() nounwind readnone ssp {
+entry:
+ %b = tail call <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
+ ret <4 x i32> %b
+; CHECK: entry:
+; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
+}
+
+define <4 x i32> @complex1ARM64(<4 x i16> %x) nounwind readnone ssp {
+entry:
+ %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
+ %b = add <4 x i32> zeroinitializer, %a
+ ret <4 x i32> %b
+; CHECK: entry:
+; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) [[NUW:#[0-9]+]]
+; CHECK-NEXT: ret <4 x i32> %a
+}
+
+define <4 x i32> @complex2ARM64(<4 x i32> %x) nounwind readnone ssp {
+entry:
+ %a = tail call <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
+ %b = add <4 x i32> %x, %a
+ ret <4 x i32> %b
+; CHECK: entry:
+; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6>
+; CHECK-NEXT: ret <4 x i32> %b
+}
+
+declare <4 x i32> @llvm.arm64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+declare <4 x i32> @llvm.arm64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+
; CHECK: attributes #0 = { nounwind readnone ssp }
; CHECK: attributes #1 = { nounwind readnone }
; CHECK: attributes [[NUW]] = { nounwind }
Modified: llvm/trunk/test/Transforms/InstCombine/sincospi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sincospi.ll?rev=205090&r1=205089&r2=205090&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sincospi.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/sincospi.ll Sat Mar 29 05:18:08 2014
@@ -1,5 +1,6 @@
; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios7.0 | FileCheck %s
+; RUN: opt -instcombine -S < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
; RUN: opt -instcombine -S < %s -mtriple=x86_64-apple-macosx10.8 | FileCheck %s --check-prefix=CHECK-NO-SINCOS
; RUN: opt -instcombine -S < %s -mtriple=arm-apple-ios6.0 | FileCheck %s --check-prefix=CHECK-NO-SINCOS
; RUN: opt -instcombine -S < %s -mtriple=x86_64-none-linux-gnu | FileCheck %s --check-prefix=CHECK-NO-SINCOS
Added: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,5 @@
+config.suffixes = ['.ll']
+
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
Added: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memcpy.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,33 @@
+; RUN: llc -march=arm64 -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
+; rdar://10232252
+; Prevent LSR of doing poor choice that cannot be folded in addressing mode
+
+; Remove the -pre-RA-sched=list-hybrid option after fixing:
+; <rdar://problem/12702735> [ARM64][coalescer] need better register
+; coalescing for simple unit tests.
+
+; CHECK: testCase
+; CHECK: %while.body{{$}}
+; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8
+; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8
+; CHECK: %while.end
+define i32 @testCase() nounwind ssp {
+entry:
+ br label %while.body
+
+while.body: ; preds = %while.body, %entry
+ %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
+ %pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
+ %pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
+ %incdec.ptr = getelementptr inbounds i64* %pSrc.04, i64 1
+ %tmp = load volatile i64* %pSrc.04, align 8
+ %incdec.ptr1 = getelementptr inbounds i64* %pDst.05, i64 1
+ store volatile i64 %tmp, i64* %pDst.05, align 8
+ %sub = add i64 %len.06, -8
+ %cmp = icmp sgt i64 %sub, -1
+ br i1 %cmp, label %while.body, label %while.end
+
+while.end: ; preds = %while.body
+ tail call void inttoptr (i64 6442450944 to void ()*)() nounwind
+ ret i32 0
+}
Added: llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll (added)
+++ llvm/trunk/test/Transforms/LoopStrengthReduce/ARM64/lsr-memset.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,101 @@
+; RUN: llc < %s -O3 -march=arm64 -mcpu=cyclone -pre-RA-sched=list-hybrid | FileCheck %s
+; <rdar://problem/11635990> [arm64] [lsr] Inefficient EA/loop-exit calc in bzero_phys
+;
+; LSR on loop %while.cond should reassociate non-address mode
+; expressions at use %cmp16 to avoid sinking computation into %while.body18.
+;
+; Remove the -pre-RA-sched=list-hybrid option after fixing:
+; <rdar://problem/12702735> [ARM64][coalescer] need better register
+; coalescing for simple unit tests.
+
+; CHECK: @memset
+; CHECK: %while.body18{{$}}
+; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #8
+; First set the IVREG variable, then use it
+; CHECK-NEXT: sub [[IVREG:x[0-9]+]],
+; CHECK: [[IVREG]], #8
+; CHECK-NEXT: cmp [[IVREG]], #7
+; CHECK-NEXT: b.hi
+define i8* @memset(i8* %dest, i32 %val, i64 %len) nounwind ssp noimplicitfloat {
+entry:
+ %cmp = icmp eq i64 %len, 0
+ br i1 %cmp, label %done, label %while.cond.preheader
+
+while.cond.preheader: ; preds = %entry
+ %conv = trunc i32 %val to i8
+ br label %while.cond
+
+while.cond: ; preds = %while.body, %while.cond.preheader
+ %ptr.0 = phi i8* [ %incdec.ptr, %while.body ], [ %dest, %while.cond.preheader ]
+ %len.addr.0 = phi i64 [ %dec, %while.body ], [ %len, %while.cond.preheader ]
+ %cond = icmp eq i64 %len.addr.0, 0
+ br i1 %cond, label %done, label %land.rhs
+
+land.rhs: ; preds = %while.cond
+ %0 = ptrtoint i8* %ptr.0 to i64
+ %and = and i64 %0, 7
+ %cmp5 = icmp eq i64 %and, 0
+ br i1 %cmp5, label %if.end9, label %while.body
+
+while.body: ; preds = %land.rhs
+ %incdec.ptr = getelementptr inbounds i8* %ptr.0, i64 1
+ store i8 %conv, i8* %ptr.0, align 1, !tbaa !0
+ %dec = add i64 %len.addr.0, -1
+ br label %while.cond
+
+if.end9: ; preds = %land.rhs
+ %conv.mask = and i32 %val, 255
+ %1 = zext i32 %conv.mask to i64
+ %2 = shl nuw nsw i64 %1, 8
+ %ins18 = or i64 %2, %1
+ %3 = shl nuw nsw i64 %1, 16
+ %ins15 = or i64 %ins18, %3
+ %4 = shl nuw nsw i64 %1, 24
+ %5 = shl nuw nsw i64 %1, 32
+ %mask8 = or i64 %ins15, %4
+ %6 = shl nuw nsw i64 %1, 40
+ %mask5 = or i64 %mask8, %5
+ %7 = shl nuw nsw i64 %1, 48
+ %8 = shl nuw i64 %1, 56
+ %mask2.masked = or i64 %mask5, %6
+ %mask = or i64 %mask2.masked, %7
+ %ins = or i64 %mask, %8
+ %9 = bitcast i8* %ptr.0 to i64*
+ %cmp1636 = icmp ugt i64 %len.addr.0, 7
+ br i1 %cmp1636, label %while.body18, label %while.body29.lr.ph
+
+while.body18: ; preds = %if.end9, %while.body18
+ %wideptr.038 = phi i64* [ %incdec.ptr19, %while.body18 ], [ %9, %if.end9 ]
+ %len.addr.137 = phi i64 [ %sub, %while.body18 ], [ %len.addr.0, %if.end9 ]
+ %incdec.ptr19 = getelementptr inbounds i64* %wideptr.038, i64 1
+ store i64 %ins, i64* %wideptr.038, align 8, !tbaa !2
+ %sub = add i64 %len.addr.137, -8
+ %cmp16 = icmp ugt i64 %sub, 7
+ br i1 %cmp16, label %while.body18, label %while.end20
+
+while.end20: ; preds = %while.body18
+ %cmp21 = icmp eq i64 %sub, 0
+ br i1 %cmp21, label %done, label %while.body29.lr.ph
+
+while.body29.lr.ph: ; preds = %while.end20, %if.end9
+ %len.addr.1.lcssa49 = phi i64 [ %sub, %while.end20 ], [ %len.addr.0, %if.end9 ]
+ %wideptr.0.lcssa48 = phi i64* [ %incdec.ptr19, %while.end20 ], [ %9, %if.end9 ]
+ %10 = bitcast i64* %wideptr.0.lcssa48 to i8*
+ br label %while.body29
+
+while.body29: ; preds = %while.body29, %while.body29.lr.ph
+ %len.addr.235 = phi i64 [ %len.addr.1.lcssa49, %while.body29.lr.ph ], [ %dec26, %while.body29 ]
+ %ptr.134 = phi i8* [ %10, %while.body29.lr.ph ], [ %incdec.ptr31, %while.body29 ]
+ %dec26 = add i64 %len.addr.235, -1
+ %incdec.ptr31 = getelementptr inbounds i8* %ptr.134, i64 1
+ store i8 %conv, i8* %ptr.134, align 1, !tbaa !0
+ %cmp27 = icmp eq i64 %dec26, 0
+ br i1 %cmp27, label %done, label %while.body29
+
+done: ; preds = %while.cond, %while.body29, %while.end20, %entry
+ ret i8* %dest
+}
+
+!0 = metadata !{metadata !"omnipotent char", metadata !1}
+!1 = metadata !{metadata !"Simple C/C++ TBAA"}
+!2 = metadata !{metadata !"long long", metadata !0}
Added: llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll (added)
+++ llvm/trunk/test/Transforms/LoopVectorize/ARM64/gather-cost.ll Sat Mar 29 05:18:08 2014
@@ -0,0 +1,85 @@
+; RUN: opt -loop-vectorize -mtriple=arm64-apple-ios -S -mcpu=cyclone < %s | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
+
+ at kernel = global [512 x float] zeroinitializer, align 16
+ at kernel2 = global [512 x float] zeroinitializer, align 16
+ at kernel3 = global [512 x float] zeroinitializer, align 16
+ at kernel4 = global [512 x float] zeroinitializer, align 16
+ at src_data = global [1536 x float] zeroinitializer, align 16
+ at r_ = global i8 0, align 1
+ at g_ = global i8 0, align 1
+ at b_ = global i8 0, align 1
+
+; We don't want to vectorize most loops containing gathers because they are
+; expensive.
+; Make sure we don't vectorize it.
+; CHECK-NOT: x float>
+
+define void @_Z4testmm(i64 %size, i64 %offset) {
+entry:
+ %cmp53 = icmp eq i64 %size, 0
+ br i1 %cmp53, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+ br label %for.body
+
+for.body:
+ %r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ]
+ %g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ]
+ %v.055 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+ %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
+ %add = add i64 %v.055, %offset
+ %mul = mul i64 %add, 3
+ %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul
+ %0 = load float* %arrayidx, align 4
+ %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055
+ %1 = load float* %arrayidx2, align 4
+ %mul3 = fmul fast float %0, %1
+ %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055
+ %2 = load float* %arrayidx4, align 4
+ %mul5 = fmul fast float %mul3, %2
+ %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055
+ %3 = load float* %arrayidx6, align 4
+ %mul7 = fmul fast float %mul5, %3
+ %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055
+ %4 = load float* %arrayidx8, align 4
+ %mul9 = fmul fast float %mul7, %4
+ %add10 = fadd fast float %r.057, %mul9
+ %arrayidx.sum = add i64 %mul, 1
+ %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
+ %5 = load float* %arrayidx11, align 4
+ %mul13 = fmul fast float %1, %5
+ %mul15 = fmul fast float %2, %mul13
+ %mul17 = fmul fast float %3, %mul15
+ %mul19 = fmul fast float %4, %mul17
+ %add20 = fadd fast float %g.056, %mul19
+ %arrayidx.sum52 = add i64 %mul, 2
+ %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
+ %6 = load float* %arrayidx21, align 4
+ %mul23 = fmul fast float %1, %6
+ %mul25 = fmul fast float %2, %mul23
+ %mul27 = fmul fast float %3, %mul25
+ %mul29 = fmul fast float %4, %mul27
+ %add30 = fadd fast float %b.054, %mul29
+ %inc = add i64 %v.055, 1
+ %exitcond = icmp ne i64 %inc, %size
+ br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:
+ %add30.lcssa = phi float [ %add30, %for.body ]
+ %add20.lcssa = phi float [ %add20, %for.body ]
+ %add10.lcssa = phi float [ %add10, %for.body ]
+ %phitmp = fptoui float %add10.lcssa to i8
+ %phitmp60 = fptoui float %add20.lcssa to i8
+ %phitmp61 = fptoui float %add30.lcssa to i8
+ br label %for.end
+
+for.end:
+ %r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+ %g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+ %b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+ store i8 %r.0.lcssa, i8* @r_, align 1
+ store i8 %g.0.lcssa, i8* @g_, align 1
+ store i8 %b.0.lcssa, i8* @b_, align 1
+ ret void
+}
Added: llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg?rev=205090&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg (added)
+++ llvm/trunk/test/Transforms/LoopVectorize/ARM64/lit.local.cfg Sat Mar 29 05:18:08 2014
@@ -0,0 +1,6 @@
+config.suffixes = ['.ll', '.c', '.cpp']
+
+targets = set(config.root.targets_to_build.split())
+if not 'ARM64' in targets:
+ config.unsupported = True
+
Modified: llvm/trunk/unittests/ADT/TripleTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/TripleTest.cpp?rev=205090&r1=205089&r2=205090&view=diff
==============================================================================
--- llvm/trunk/unittests/ADT/TripleTest.cpp (original)
+++ llvm/trunk/unittests/ADT/TripleTest.cpp Sat Mar 29 05:18:08 2014
@@ -354,7 +354,7 @@ TEST(TripleTest, BitWidthArchVariants) {
T.setArch(Triple::arm);
EXPECT_EQ(Triple::arm, T.get32BitArchVariant().getArch());
- EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch());
+ EXPECT_EQ(Triple::arm64, T.get64BitArchVariant().getArch());
T.setArch(Triple::mips);
EXPECT_EQ(Triple::mips, T.get32BitArchVariant().getArch());
Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=205090&r1=205089&r2=205090&view=diff
==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Sat Mar 29 05:18:08 2014
@@ -151,7 +151,7 @@ if [ "$ARM_HOSTED_BUILD" = yes ]; then
unset SDKROOT && \
$SRC_DIR/configure $COMMON_CONFIGURE_OPTS \
- --enable-targets=arm \
+ --enable-targets=arm,arm64 \
--host=arm-apple-darwin10 \
--target=arm-apple-darwin10 \
--build=i686-apple-darwin10 \
@@ -188,7 +188,7 @@ else
export CC=`xcrun -sdk macosx -find clang`
export CXX=`xcrun -sdk macosx -find clang++`
- configure_opts="--enable-targets=arm,x86"
+ configure_opts="--enable-targets=arm,arm64,x86"
if [ -n "$MACOSX_DEPLOYMENT_TARGET" ]; then
COMMON_MAKEFLAGS="$COMMON_MAKEFLAGS \
DEPLOYMENT_TARGET=-mmacosx-version-min=$MACOSX_DEPLOYMENT_TARGET"
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