[llvm] r204616 - SelectionDAG: Allow promotion of SELECT nodes from float to int types

[Tom Stellard]

Author: tstellar
Date: Mon Mar 24 11:07:28 2014
New Revision: 204616

URL: http://llvm.org/viewvc/llvm-project?rev=204616&view=rev
Log:
SelectionDAG: Allow promotion of SELECT nodes from float to int types

And vice-versa, as long as the types are the same width.

There are a few R600 tests that will cover this.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=204616&r1=204615&r2=204616&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Mar 24 11:07:28 2014
@@ -3990,7 +3990,8 @@ void SelectionDAGLegalize::PromoteNode(S
   }
   case ISD::SELECT: {
     unsigned ExtOp, TruncOp;
-    if (Node->getValueType(0).isVector()) {
+    if (Node->getValueType(0).isVector() ||
+        Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
       ExtOp   = ISD::BITCAST;
       TruncOp = ISD::BITCAST;
     } else if (Node->getValueType(0).isInteger()) {