[llvm] r204479 - Add overall description, file comments, some structure

Renato Golin renato.golin at linaro.org
Fri Mar 21 09:49:44 PDT 2014

Author: rengolin
Date: Fri Mar 21 11:49:43 2014
New Revision: 204479

URL: http://llvm.org/viewvc/llvm-project?rev=204479&view=rev
Add overall description, file comments, some structure


Modified: llvm/trunk/docs/TableGen/BackEnds.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TableGen/BackEnds.rst?rev=204479&r1=204478&r2=204479&view=diff
--- llvm/trunk/docs/TableGen/BackEnds.rst (original)
+++ llvm/trunk/docs/TableGen/BackEnds.rst Fri Mar 21 11:49:43 2014
@@ -32,86 +32,201 @@ LLVM BackEnds
    of its purpose with a list of users, output generated from generic input, and
    finally why it needed a new backend (in case there's something similar).
+Overall, each backend will take the same TableGen file type and transform into
+similar output for different targets/uses. There is an implicit contract between
+the TableGen files, the back-ends and their users.
+For instance, a global contract is that each back-end produces macro-guarded
+sections. Based on whether the file is included by a header or a source file,
+or even in which context of each file the include is being used, you have
+todefine a macro just before including it, to get the right output:
+.. code-block:: c++
+  #include "ARMGenRegisterInfo.inc"
+And just part of the generated file would be included. This is useful if
+you need the same information in multiple formats (instantiation, initialization,
+getter/setter functions, etc) from the same source TableGen file without having
+to re-compile the TableGen file multiple times.
-Generate machine code emitter.
+Sometimes, multiple macros might be defined before the same include file to
+output multiple blocks:
+.. code-block:: c++
+  #include "ARMGenAsmMatcher.inc"
+The macros will be undef'd automatically as they're used, in the include file.
+On all LLVM back-ends, the ``llvm-tblgen`` binary will be executed on the root
+TableGen file ``<Target>.td``, which should include all others. This guarantees
+that all information needed is accessible, and that no duplication is needed
+in the TbleGen files.
+**Purpose**: CodeEmitterGen uses the descriptions of instructions and their fields to
+construct an automated code emitter: a function that, given a MachineInstr,
+returns the (currently, 32-bit unsigned) value of the instruction.
+**Output**: C++ code, implementing the target's CodeEmitter
+class by overriding the virtual functions as ``<Target>CodeEmitter::function()``.
+**Usage**: Used to include directly at the end of ``<Target>CodeEmitter.cpp``, and
+with option `-mc-emitter` to be included in ``<Target>MCCodeEmitter.cpp``.
-Generate registers and register classes info.
+**Purpose**: This tablegen backend is responsible for emitting a description of a target
+register file for a code generator.  It uses instances of the Register,
+RegisterAliases, and RegisterClass classes to gather this information.
+**Output**: C++ code with enums and structures representing the register mappings,
+properties, masks, etc.
+**Usage**: Both on ``<Target>BaseRegisterInfo`` and ``<Target>MCTargetDesc`` (headers
+and source files) with macros defining in which they are for declaration vs.
+initialization issues.
-Generate instruction descriptions.
+**Purpose**: This tablegen backend is responsible for emitting a description of the target
+instruction set for the code generator. (what are the differences from CodeEmitter?)
+**Output**: C++ code with enums and structures representing the register mappings,
+properties, masks, etc.
+**Usage**: Both on ``<Target>BaseInstrInfo`` and ``<Target>MCTargetDesc`` (headers
+and source files) with macros defining in which they are for declaration vs.
-Generate calling convention descriptions.
+**Purpose**: Emits an assembly printer for the current target.
+**Output**: Implementation of ``<Target>InstPrinter::printInstruction()``, among
+other things.
+**Usage**: Included directly into ``InstPrinter/<Target>InstPrinter.cpp``.
-Generate assembly writer.
+**Purpose**: Emits a target specifier matcher for
+converting parsed assembly operands in the MCInst structures. It also
+emits a matcher for custom operand parsing. Extensive documentation is
+written on the ``AsmMatcherEmitter.cpp`` file.
+**Output**: Assembler parsers' matcher functions, declarations, etc.
+**Usage**: Used in back-ends' ``AsmParser/<Target>AsmParser.cpp`` for
+building the AsmParser class.
-Generate disassembler.
+**Purpose**: Contains disassembler table emitters for various
+architectures. Extensive documentation is written on the
+``DisassemblerEmitter.cpp`` file.
+**Output**: Decoding tables, static decoding functions, etc.
+**Usage**: Directly included in ``Disassembler/<Target>Disassembler.cpp``
+to cater for all default decodings, after all hand-made ones.
-Generate pseudo instruction lowering.
+**Purpose**: Generate pseudo instruction lowering.
+**Output**: Implements ``ARMAsmPrinter::emitPseudoExpansionLowering()``.
+**Usage**: Included directly into ``<Target>AsmPrinter.cpp``.
-Generate assembly instruction matcher.
+**Purpose**: Responsible for emitting descriptions of the calling
+conventions supported by this target.
+**Output**: Implement static functions to deal with calling conventions
+chained by matching styles, returning false on no match.
+**Usage**: Used in ISelLowering and FastIsel as function pointers to
+implementation returned by a CC sellection function.
-Generate a DAG instruction selector.
+**Purpose**: Generate a DAG instruction selector.
+**Output**: Creates huge functions for automating DAG selection.
+**Usage**: Included in ``<Target>ISelDAGToDAG.cpp`` inside the target's
+implementation of ``SelectionDAGISel``.
-Generate DFA Packetizer for VLIW targets.
+**Purpose**: This class parses the Schedule.td file and produces an API that
+can be used to reason about whether an instruction can be added to a packet
+on a VLIW architecture. The class internally generates a deterministic finite
+automaton (DFA) that models all possible mappings of machine instructions
+to functional units as instructions are added to a packet.
+**Output**: Scheduling tables for GPU back-ends (Hexagon, AMD).
+**Usage**: Included directly on ``<Target>InstrInfo.cpp``.
-Generate a "fast" instruction selector.
+**Purpose**: This tablegen backend emits code for use by the "fast"
+instruction selection algorithm. See the comments at the top of
+lib/CodeGen/SelectionDAG/FastISel.cpp for background. This file
+scans through the target's tablegen instruction-info files
+and extracts instructions with obvious-looking patterns, and it emits
+code to look up these instructions by type and operator.
+**Output**: Generates ``Predicate`` and ``FastEmit`` methods.
+**Usage**: Implements private methods of the targets' implementation
+of ``FastISel`` class.
-Generate subtarget enumerations.
+**Purpose**: Generate subtarget enumerations.
+**Output**: Enums, globals, local tables for sub-target information.
-Generate intrinsic information.
+**Usage**: Populates ``<Target>Subtarget`` and
+``MCTargetDesc/<Target>MCTargetDesc`` files (both headers and source).
-Generate target intrinsic information.
+**Purpose**: Generate (target) intrinsic information.
-Print enum values for a class.
+**Purpose**: Print enum values for a class.
-Generate ctags-compatible index.
+**Purpose**: This tablegen backend emits an index of definitions in ctags(1)
+format. A helper script, utils/TableGen/tdtags, provides an easier-to-use
+interface; run 'tdtags -H' for documentation.
 Clang BackEnds

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