[PATCH] R600: Fix truncstore from i64 to i1

Tom Stellard tom at stellard.net
Wed Mar 12 07:12:39 PDT 2014


LGTM.

-Tom

On Tue, Mar 11, 2014 at 10:22:06AM -0700, Matt Arsenault wrote:
> http://llvm-reviews.chandlerc.com/D3047
> 
> Files:
>   lib/Target/R600/AMDGPUISelLowering.cpp
>   test/CodeGen/R600/trunc-store-i1.ll
> 
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -123,6 +123,11 @@
>    setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand);
>    setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
>  
> +  setTruncStoreAction(MVT::i64, MVT::i1, Expand);
> +  setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
> +  setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
> +
> +
>    // XXX: This can be change to always be Custom, once the non-BFI path of
>    // MergeVectorStores can handle 64-bit stores.
>    setTruncStoreAction(MVT::v4i32, MVT::v4i16,
> Index: test/CodeGen/R600/trunc-store-i1.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/trunc-store-i1.ll
> @@ -0,0 +1,30 @@
> +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
> +
> +
> +; SI-LABEL: @global_truncstore_i32_to_i1
> +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]],
> +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0
> +; SI: BUFFER_STORE_BYTE [[VREG]],
> +define void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwind {
> +  %trunc = trunc i32 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}
> +
> +; SI-LABEL: @global_truncstore_i64_to_i1
> +; SI: BUFFER_STORE_BYTE
> +define void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwind {
> +  %trunc = trunc i64 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}
> +
> +; SI-LABEL: @global_truncstore_i16_to_i1
> +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]],
> +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0
> +; SI: BUFFER_STORE_BYTE [[VREG]],
> +define void @global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val) nounwind {
> +  %trunc = trunc i16 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}

> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -123,6 +123,11 @@
>    setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand);
>    setTruncStoreAction(MVT::v4i32, MVT::v4i1, Expand);
>  
> +  setTruncStoreAction(MVT::i64, MVT::i1, Expand);
> +  setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
> +  setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
> +
> +
>    // XXX: This can be change to always be Custom, once the non-BFI path of
>    // MergeVectorStores can handle 64-bit stores.
>    setTruncStoreAction(MVT::v4i32, MVT::v4i16,
> Index: test/CodeGen/R600/trunc-store-i1.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/trunc-store-i1.ll
> @@ -0,0 +1,30 @@
> +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
> +
> +
> +; SI-LABEL: @global_truncstore_i32_to_i1
> +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]],
> +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0
> +; SI: BUFFER_STORE_BYTE [[VREG]],
> +define void @global_truncstore_i32_to_i1(i1 addrspace(1)* %out, i32 %val) nounwind {
> +  %trunc = trunc i32 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}
> +
> +; SI-LABEL: @global_truncstore_i64_to_i1
> +; SI: BUFFER_STORE_BYTE
> +define void @global_truncstore_i64_to_i1(i1 addrspace(1)* %out, i64 %val) nounwind {
> +  %trunc = trunc i64 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}
> +
> +; SI-LABEL: @global_truncstore_i16_to_i1
> +; SI: S_LOAD_DWORD [[LOAD:s[0-9]+]],
> +; SI: V_AND_B32_e64 [[VREG:v[0-9]+]], 1, [[LOAD]], 0, 0, 0, 0
> +; SI: BUFFER_STORE_BYTE [[VREG]],
> +define void @global_truncstore_i16_to_i1(i1 addrspace(1)* %out, i16 %val) nounwind {
> +  %trunc = trunc i16 %val to i1
> +  store i1 %trunc, i1 addrspace(1)* %out, align 1
> +  ret void
> +}

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