[PATCH] Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059)
hans at chromium.org
Mon Mar 10 14:56:34 PDT 2014
Comment at: lib/Target/X86/X86ISelLowering.cpp:18070
@@ -18062,1 +18069,3 @@
SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
Jim Grosbach wrote:
> This seems very strange. Why do we not want to perform the operations in 64-bits here? It's still 64-bit data whether we're in 64-bit mode or not, right?
> Can you elaborate a bit on what's actually going wrong here?
(I'm new to this so please correct me if I seem confused here..)
> This seems very strange. Why do we not want to perform the operations in 64-bits
> here? It's still 64-bit data whether we're in 64-bit mode or not, right?
This runs after the DAG has been legalized. If we generate a 64-bit ISD::BITCAST node, we'll select an instruction that moves to a 64-bit integer register, e.g. "movd %xmm1, %rax", which obviously doesn't work well when targeting 32-bit.
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