[PATCH] R600/SI: Expand selects on vectors.
Tom Stellard
tom at stellard.net
Thu Mar 6 03:49:14 PST 2014
On Wed, Mar 05, 2014 at 06:50:01PM -0800, Matt Arsenault wrote:
> Move to AMDGPUISelLowering. Add a few more tests, but does not test the evergreen part since there seem to be problems with load / store of double vectors.
>
LGTM.
-Tom
> http://llvm-reviews.chandlerc.com/D2906
>
> CHANGE SINCE LAST DIFF
> http://llvm-reviews.chandlerc.com/D2906?vs=7443&id=7573#toc
>
> Files:
> lib/Target/R600/AMDGPUISelLowering.cpp
> test/CodeGen/R600/select-vectors.ll
>
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -181,6 +181,7 @@
> setOperationAction(ISD::UDIV, VT, Expand);
> setOperationAction(ISD::UINT_TO_FP, VT, Expand);
> setOperationAction(ISD::UREM, VT, Expand);
> + setOperationAction(ISD::SELECT, VT, Expand);
> setOperationAction(ISD::VSELECT, VT, Expand);
> setOperationAction(ISD::XOR, VT, Expand);
> }
> @@ -202,6 +203,7 @@
> setOperationAction(ISD::FRINT, VT, Expand);
> setOperationAction(ISD::FSQRT, VT, Expand);
> setOperationAction(ISD::FSUB, VT, Expand);
> + setOperationAction(ISD::SELECT, VT, Expand);
> }
> }
>
> Index: test/CodeGen/R600/select-vectors.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/select-vectors.ll
> @@ -0,0 +1,155 @@
> +; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +
> +; Test expansion of scalar selects on vectors.
> +; Evergreen not enabled since it seems to be having problems with doubles.
> +
> +
> +; FUNC-LABEL: @select_v4i8
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind {
> + %cmp = icmp eq i8 %c, 0
> + %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b
> + store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4i16
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b
> + store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: BUFFER_STORE_DWORDX2
> +define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
> + store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: BUFFER_STORE_DWORDX4
> +define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
> + store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b
> + store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2f32
> +; SI: BUFFER_STORE_DWORDX2
> +define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
> + store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4f32
> +; SI: BUFFER_STORE_DWORDX4
> +define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x float> %a, <4 x float> %b
> + store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8f32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x float> %a, <8 x float> %b
> + store <8 x float> %select, <8 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x double> %a, <2 x double> %b
> + store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x double> %a, <4 x double> %b
> + store <4 x double> %select, <4 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x double> %a, <8 x double> %b
> + store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> Index: lib/Target/R600/AMDGPUISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/AMDGPUISelLowering.cpp
> +++ lib/Target/R600/AMDGPUISelLowering.cpp
> @@ -181,6 +181,7 @@
> setOperationAction(ISD::UDIV, VT, Expand);
> setOperationAction(ISD::UINT_TO_FP, VT, Expand);
> setOperationAction(ISD::UREM, VT, Expand);
> + setOperationAction(ISD::SELECT, VT, Expand);
> setOperationAction(ISD::VSELECT, VT, Expand);
> setOperationAction(ISD::XOR, VT, Expand);
> }
> @@ -202,6 +203,7 @@
> setOperationAction(ISD::FRINT, VT, Expand);
> setOperationAction(ISD::FSQRT, VT, Expand);
> setOperationAction(ISD::FSUB, VT, Expand);
> + setOperationAction(ISD::SELECT, VT, Expand);
> }
> }
>
> Index: test/CodeGen/R600/select-vectors.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/select-vectors.ll
> @@ -0,0 +1,155 @@
> +; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
> +
> +; Test expansion of scalar selects on vectors.
> +; Evergreen not enabled since it seems to be having problems with doubles.
> +
> +
> +; FUNC-LABEL: @select_v4i8
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind {
> + %cmp = icmp eq i8 %c, 0
> + %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b
> + store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4i16
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b
> + store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: BUFFER_STORE_DWORDX2
> +define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
> + store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: BUFFER_STORE_DWORDX4
> +define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
> + store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8i32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x i32> %a, <8 x i32> %b
> + store <8 x i32> %select, <8 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2f32
> +; SI: BUFFER_STORE_DWORDX2
> +define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
> + store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4f32
> +; SI: BUFFER_STORE_DWORDX4
> +define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x float> %a, <4 x float> %b
> + store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8f32
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x float> %a, <8 x float> %b
> + store <8 x float> %select, <8 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v2f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x double> %a, <2 x double> %b
> + store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v4f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x double> %a, <4 x double> %b
> + store <4 x double> %select, <4 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; FUNC-LABEL: @select_v8f64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +; SI: V_CNDMASK_B32_e64
> +define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <8 x double> %a, <8 x double> %b
> + store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16
> + ret void
> +}
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