[PATCH] R600/SI: Expand selects on vectors.
Tom Stellard
tom at stellard.net
Tue Mar 4 07:48:22 PST 2014
On Fri, Feb 28, 2014 at 07:03:46PM -0800, Matt Arsenault wrote:
> Only need one loop
>
> http://llvm-reviews.chandlerc.com/D2906
>
> CHANGE SINCE LAST DIFF
> http://llvm-reviews.chandlerc.com/D2906?vs=7442&id=7443#toc
>
> Files:
> lib/Target/R600/SIISelLowering.cpp
> test/CodeGen/R600/select-vectors.ll
>
> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -104,6 +104,11 @@
> setOperationAction(ISD::STORE, MVT::v2i32, Custom);
> setOperationAction(ISD::STORE, MVT::v4i32, Custom);
>
> + for (int I = MVT::VECTOR_VALUETYPE; I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
> + MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
> + setOperationAction(ISD::SELECT, VT, Expand);
> + }
> +
Can you add this to the v*i32 and v*f32 loops in AMDGPUISelLowering.cpp
instead, so we cover all targets. There is already a loop in
SIISelLowering.cpp that handles vectors with greater than four elements.
Thanks,
Tom
> setOperationAction(ISD::SELECT, MVT::i64, Custom);
>
> setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
> Index: test/CodeGen/R600/select-vectors.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/select-vectors.ll
> @@ -0,0 +1,80 @@
> +; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck %s
> +; Test expansion of scalar selects on vectors.
> +
> +; CHECK-LABEL: @select_v4i8
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind {
> + %cmp = icmp eq i8 %c, 0
> + %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b
> + store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4i16
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b
> + store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2i32
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: BUFFER_STORE_DWORDX2
> +define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
> + store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4i32
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: BUFFER_STORE_DWORDX4
> +define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
> + store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2f32
> +; CHECK: BUFFER_STORE_DWORDX2
> +define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
> + store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4f32
> +; CHECK: BUFFER_STORE_DWORDX4
> +define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x float> %a, <4 x float> %b
> + store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2f64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x double> %a, <2 x double> %b
> + store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> Index: lib/Target/R600/SIISelLowering.cpp
> ===================================================================
> --- lib/Target/R600/SIISelLowering.cpp
> +++ lib/Target/R600/SIISelLowering.cpp
> @@ -104,6 +104,11 @@
> setOperationAction(ISD::STORE, MVT::v2i32, Custom);
> setOperationAction(ISD::STORE, MVT::v4i32, Custom);
>
> + for (int I = MVT::VECTOR_VALUETYPE; I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
> + MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
> + setOperationAction(ISD::SELECT, VT, Expand);
> + }
> +
> setOperationAction(ISD::SELECT, MVT::i64, Custom);
>
> setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
> Index: test/CodeGen/R600/select-vectors.ll
> ===================================================================
> --- /dev/null
> +++ test/CodeGen/R600/select-vectors.ll
> @@ -0,0 +1,80 @@
> +; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck %s
> +; Test expansion of scalar selects on vectors.
> +
> +; CHECK-LABEL: @select_v4i8
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b, i8 %c) nounwind {
> + %cmp = icmp eq i8 %c, 0
> + %select = select i1 %cmp, <4 x i8> %a, <4 x i8> %b
> + store <4 x i8> %select, <4 x i8> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4i16
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i16> %a, <4 x i16> %b
> + store <4 x i16> %select, <4 x i16> addrspace(1)* %out, align 4
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2i32
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: BUFFER_STORE_DWORDX2
> +define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
> + store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4i32
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: BUFFER_STORE_DWORDX4
> +define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b
> + store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2f32
> +; CHECK: BUFFER_STORE_DWORDX2
> +define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x float> %a, <2 x float> %b
> + store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v4f32
> +; CHECK: BUFFER_STORE_DWORDX4
> +define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <4 x float> %a, <4 x float> %b
> + store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16
> + ret void
> +}
> +
> +; CHECK-LABEL: @select_v2f64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +; CHECK: V_CNDMASK_B32_e64
> +define void @select_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b, i32 %c) nounwind {
> + %cmp = icmp eq i32 %c, 0
> + %select = select i1 %cmp, <2 x double> %a, <2 x double> %b
> + store <2 x double> %select, <2 x double> addrspace(1)* %out, align 16
> + ret void
> +}
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
More information about the llvm-commits
mailing list