[PATCH] AARCH64_BE load/store rules fix for ARM ABI
t.p.northover at gmail.com
Mon Mar 3 06:54:25 PST 2014
> Does the user expect different behaviour in LE & BE ?
> probably not.
> Suppose the user stores a vector - and then tries to load that to a lane.
> Results in different layout in LE & BE.
Can you give a code example for this? The load lane instructions are
for loading scalars or structs, both of which seem to have the correct
layout for equivalent semantics, to me. I *suspect* that when you
write out the C code, we'll find it actually should behave differently
(either that or it wouldn't anyway ;-)).
> Only had to fix all respective LE unit tests :-(
> Good thing is: they're also BE tests now.
Excellent! Thanks, I'm quite looking forward to that change.
> Removing LD1 without adding LDR leaves vector register loads unmatchable.
Ah yes, that makes sense.
Cheers (and thanks for keeping on with the work!).
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