[llvm] r202666 - [Sparc] Add return/rett instruction to Sparc backend.
Venkatraman Govindaraju
venkatra at cs.wisc.edu
Sun Mar 2 14:55:53 PST 2014
Author: venkatra
Date: Sun Mar 2 16:55:53 2014
New Revision: 202666
URL: http://llvm.org/viewvc/llvm-project?rev=202666&view=rev
Log:
[Sparc] Add return/rett instruction to Sparc backend.
Modified:
llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt
llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s
llvm/trunk/test/MC/Sparc/sparc64-ctrl-instructions.s
Modified: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp Sun Mar 2 16:55:53 2014
@@ -446,6 +446,9 @@ ParseRegister(unsigned &RegNo, SMLoc &St
return Error(StartLoc, "invalid register name");
}
+static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
+ unsigned VariantID);
+
bool SparcAsmParser::
ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc,
@@ -455,6 +458,9 @@ ParseInstruction(ParseInstructionInfo &I
// First operand in MCInst is instruction mnemonic.
Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
+ // apply mnemonic aliases, if any, so that we can parse operands correctly.
+ applyMnemonicAliases(Name, getAvailableFeatures(), 0);
+
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
if (getLexer().is(AsmToken::Comma)) {
Modified: llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp Sun Mar 2 16:55:53 2014
@@ -209,6 +209,8 @@ static DecodeStatus DecodeSIMM13(MCInst
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
+ const void *Decoder);
#include "SparcGenDisassemblerTables.inc"
@@ -409,6 +411,34 @@ static DecodeStatus DecodeJMPL(MCInst &M
if (isImm)
MI.addOperand(MCOperand::CreateImm(simm13));
else {
+ status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+ }
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
+ const void *Decoder) {
+
+ unsigned rs1 = fieldFromInstruction(insn, 14, 5);
+ unsigned isImm = fieldFromInstruction(insn, 13, 1);
+ unsigned rs2 = 0;
+ unsigned simm13 = 0;
+ if (isImm)
+ simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
+ else
+ rs2 = fieldFromInstruction(insn, 0, 5);
+
+ // Decode RS1.
+ DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+ if (status != MCDisassembler::Success)
+ return status;
+
+ // Decode RS2 | SIMM13.
+ if (isImm)
+ MI.addOperand(MCOperand::CreateImm(simm13));
+ else {
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
if (status != MCDisassembler::Success)
return status;
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrAliases.td Sun Mar 2 16:55:53 2014
@@ -249,6 +249,8 @@ def : InstAlias<"mov $simm13, $rd", (ORr
// restore -> restore %g0, %g0, %g0
def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
+def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
+
def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Sun Mar 2 16:55:53 2014
@@ -406,6 +406,14 @@ let isReturn = 1, isTerminator = 1, hasD
"jmp %i7+$val", []>;
}
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
+ isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
+ def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
+ "rett $addr", []>;
+ def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
+ "rett $addr", []>;
+}
+
// Section B.1 - Load Integer Instructions, p. 90
let DecoderMethod = "DecodeLoadInt" in {
defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
Modified: llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Sparc/sparc.txt Sun Mar 2 16:55:53 2014
@@ -197,3 +197,6 @@
# CHECK: ret
0x81,0xc7,0xe0,0x08
+
+# CHECK: rett %i7+8
+0x81 0xcf 0xe0 0x08
Modified: llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s (original)
+++ llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s Sun Mar 2 16:55:53 2014
@@ -274,3 +274,5 @@
! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22
fbo,a .BB0
+ ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08]
+ rett %i7 + 8
Modified: llvm/trunk/test/MC/Sparc/sparc64-ctrl-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Sparc/sparc64-ctrl-instructions.s?rev=202666&r1=202665&r2=202666&view=diff
==============================================================================
--- llvm/trunk/test/MC/Sparc/sparc64-ctrl-instructions.s (original)
+++ llvm/trunk/test/MC/Sparc/sparc64-ctrl-instructions.s Sun Mar 2 16:55:53 2014
@@ -1214,3 +1214,6 @@
fmovrsnz %g1, %f2, %f3
fmovrsgz %g1, %f2, %f3
fmovrsgez %g1, %f2, %f3
+
+ ! CHECK: rett %i7+8 ! encoding: [0x81,0xcf,0xe0,0x08]
+ return %i7 + 8
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