[PATCH] Adds Cortex-A53 and Cortex-A57 subtargets.

[Andrew Trick]

On Feb 28, 2014, at 2:00 PM, Dave Estes <cestes at codeaurora.org> wrote:

>  Removes reference to limited availability documentation. Models hazard for FP DIV and FP SQRT correctly. Adds unit test case.

+// Modeling each pipeline as an "Issue-port" (BufferSize = -1). This means that
+// each resource can be issued instructions from the common "reservation
+// station". Cortex-A53 is in-order and thus doesn't have reservations stations
+// within its pipes but you can think of the incoming instruction stream as one
+// massive reservation station for all of the pipes.
+//

If this is already working for you, that's cool. But I should point out that typical in-order machines would set BufferSize=0 on the resources. That would prevent two instructions that need to be issued on the same pipe from being scheduled back-to-back in the same "cycle".

This comment just looks stale:

+// A53UnitFPMDS is the only exception, wheras is has BufferSize = 1 since it is
+// not pipelined for most of its instructions.

Otherwise looks good.

-Andy

> 
> Hi apazos, mcrosier, atrick,
> 
> http://llvm-reviews.chandlerc.com/D2829
> 
> CHANGE SINCE LAST DIFF
>  http://llvm-reviews.chandlerc.com/D2829?vs=7210&id=7436#toc
> 
> Files:
>  lib/Target/AArch64/AArch64.td
>  lib/Target/AArch64/AArch64InstrInfo.td
>  lib/Target/AArch64/AArch64Schedule.td
>  lib/Target/AArch64/AArch64ScheduleA53.td
>  lib/Target/AArch64/AArch64Subtarget.h
>  test/CodeGen/AArch64/misched-basic-A53.ll
> <D2829.2.patch>