[PATCH] Adds Cortex-A53 and Cortex-A57 subtargets.

[Andrew Trick]

On Feb 24, 2014, at 1:34 PM, Dave Estes <cestes at codeaurora.org> wrote:

>> Thanks for working on this. LGTM.
>> 
>> Tim and Jiangning, are you ok with this change?
> 
> Thanks a bunch for the feedback, Ana.
> 
> I would really appreciate some additional feedback from Andy, Tim, or anyone else with experience in the new Machine Model. Cortex-A53 is mostly in-order, so the model I developed is somewhat trivial. However, I feel like I need confirmation of my approach of this rudimentary first implementation before I start modeling any of the more sophisticated aspects of the processor: forwarding, issue-width restrictions, mid-pipe hazards in the Neon/FP Mult/Div/MAC/Sqrt pipeline, etc.

First off, in case it isn't clear, the machine model will only be used by the MachineScheduler. To enable the MachineScheduler pass your target must implement TargetSubtargetInfo::enableMachineScheduler.

I can't comment on these processors at all, so I'll just give some general advice.

The default is MicroOpBufferSize=0, which is suitable for in-order execution in that it prioritizes latency hiding. Setting it to 1 makes it less strict by allowing latency to be balanced with other heuristics:

def CortexA53Model {
...
  let MicroOpBufferSize = 1
}

To model in-order resource conflicts, if you care about that, you actually need to explicitly set BufferSize=0 in the processor resource def:

def A53UnitXX  : ProcResource<1> { let BufferSize = 0; }

That prevents multiple instructions sharing the same resource from being scheduled in the same cycle.

-Andy

> 
> -- 
> Employee of Qualcomm Innovation Center, Inc.
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