[llvm] r201287 - [AArch64]Add support for spilling FPR8/FPR16.

Hao Liu Hao.Liu at arm.com
Wed Feb 12 18:36:58 PST 2014


Author: haoliu
Date: Wed Feb 12 20:36:58 2014
New Revision: 201287

URL: http://llvm.org/viewvc/llvm-project?rev=201287&view=rev
Log:
[AArch64]Add support for spilling FPR8/FPR16.

Added:
    llvm/trunk/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=201287&r1=201286&r2=201287&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed Feb 12 20:36:58 2014
@@ -487,6 +487,10 @@ AArch64InstrInfo::storeRegToStackSlot(Ma
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP8_STR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    StoreOp = AArch64::LSFP16_STR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {
@@ -553,6 +557,10 @@ AArch64InstrInfo::loadRegFromStackSlot(M
     default:
       llvm_unreachable("Unknown size for regclass");
     }
+  } else if (AArch64::FPR8RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP8_LDR;
+  } else if (AArch64::FPR16RegClass.hasSubClassEq(RC)) {
+    LoadOp = AArch64::LSFP16_LDR;
   } else if (RC->hasType(MVT::f32) || RC->hasType(MVT::f64) ||
              RC->hasType(MVT::f128)) {
     switch (RC->getSize()) {

Added: llvm/trunk/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll?rev=201287&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/neon-spill-fpr8-fpr16.ll Wed Feb 12 20:36:58 2014
@@ -0,0 +1,30 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+; This file tests the spill of FPR8/FPR16. The volatile loads/stores force the
+; allocator to keep the value live until it's needed.
+
+%bigtype_v1i8 = type [20 x <1 x i8>]
+
+define void @spill_fpr8(%bigtype_v1i8* %addr) {
+; CHECK-LABEL: spill_fpr8:
+; CHECK: 1-byte Folded Spill
+; CHECK: 1-byte Folded Reload
+  %val1 = load volatile %bigtype_v1i8* %addr
+  %val2 = load volatile %bigtype_v1i8* %addr
+  store volatile %bigtype_v1i8 %val1, %bigtype_v1i8* %addr
+  store volatile %bigtype_v1i8 %val2, %bigtype_v1i8* %addr
+  ret void
+}
+
+%bigtype_v1i16 = type [20 x <1 x i16>]
+
+define void @spill_fpr16(%bigtype_v1i16* %addr) {
+; CHECK-LABEL: spill_fpr16:
+; CHECK: 2-byte Folded Spill
+; CHECK: 2-byte Folded Reload
+  %val1 = load volatile %bigtype_v1i16* %addr
+  %val2 = load volatile %bigtype_v1i16* %addr
+  store volatile %bigtype_v1i16 %val1, %bigtype_v1i16* %addr
+  store volatile %bigtype_v1i16 %val2, %bigtype_v1i16* %addr
+  ret void
+}
\ No newline at end of file





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