[llvm] r201059 - Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
Bob Wilson
bob.wilson at apple.com
Sun Feb 9 20:12:30 PST 2014
Craig,
This appears to cause a crash building compiler-rt with a bootstrapped build. I’ll send you a test case separately.
On Feb 9, 2014, at 4:50 PM, Craig Topper <craig.topper at gmail.com> wrote:
> Author: ctopper
> Date: Sun Feb 9 18:50:34 2014
> New Revision: 201059
>
> URL: http://llvm.org/viewvc/llvm-project?rev=201059&view=rev
> Log:
> Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.
>
> Modified:
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
> llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td
> llvm/trunk/lib/Target/X86/X86InstrFormats.td
> llvm/trunk/lib/Target/X86/X86InstrInfo.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
> llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86BaseInfo.h Sun Feb 9 18:50:34 2014
> @@ -272,6 +272,10 @@ namespace X86II {
> /// destination index register DI/ESI/RDI.
> RawFrmDstSrc = 10,
>
> + /// MRMX[rm] - The forms are used to represent instructions that use a
> + /// Mod/RM byte, and don't use the middle field for anything.
> + MRMXr = 14, MRMXm = 15,
> +
> /// MRM[0-7][rm] - These forms are used to represent instructions that use
> /// a Mod/RM byte, and use the middle field to hold extended opcode
> /// information. In the intel manual these are represented as /0, /1, ...
> @@ -674,11 +678,13 @@ namespace X86II {
> // Opcode == X86::LEA16r || Opcode == X86::LEA32r)
> return FirstMemOp;
> }
> + case X86II::MRMXr:
> case X86II::MRM0r: case X86II::MRM1r:
> case X86II::MRM2r: case X86II::MRM3r:
> case X86II::MRM4r: case X86II::MRM5r:
> case X86II::MRM6r: case X86II::MRM7r:
> return -1;
> + case X86II::MRMXm:
> case X86II::MRM0m: case X86II::MRM1m:
> case X86II::MRM2m: case X86II::MRM3m:
> case X86II::MRM4m: case X86II::MRM5m:
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Sun Feb 9 18:50:34 2014
> @@ -1426,28 +1426,35 @@ EncodeInstruction(const MCInst &MI, raw_
> break;
> }
>
> + case X86II::MRMXr:
> case X86II::MRM0r: case X86II::MRM1r:
> case X86II::MRM2r: case X86II::MRM3r:
> case X86II::MRM4r: case X86II::MRM5r:
> - case X86II::MRM6r: case X86II::MRM7r:
> + case X86II::MRM6r: case X86II::MRM7r: {
> if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
> ++CurOp;
> EmitByte(BaseOpcode, CurByte, OS);
> + uint64_t Form = TSFlags & X86II::FormMask;
> EmitRegModRMByte(MI.getOperand(CurOp++),
> - (TSFlags & X86II::FormMask)-X86II::MRM0r,
> + (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r,
> CurByte, OS);
> break;
> + }
> +
> + case X86II::MRMXm:
> case X86II::MRM0m: case X86II::MRM1m:
> case X86II::MRM2m: case X86II::MRM3m:
> case X86II::MRM4m: case X86II::MRM5m:
> - case X86II::MRM6m: case X86II::MRM7m:
> + case X86II::MRM6m: case X86II::MRM7m: {
> if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
> ++CurOp;
> EmitByte(BaseOpcode, CurByte, OS);
> - EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
> + uint64_t Form = TSFlags & X86II::FormMask;
> + EmitMemModRMByte(MI, CurOp, (Form == X86II::MRMXm) ? 0 : Form-X86II::MRM0m,
> TSFlags, CurByte, OS, Fixups, STI);
> CurOp += X86::AddrNumOperands;
> break;
> + }
> case X86II::MRM_C1: case X86II::MRM_C2: case X86II::MRM_C3:
> case X86II::MRM_C4: case X86II::MRM_C8: case X86II::MRM_C9:
> case X86II::MRM_CA: case X86II::MRM_CB: case X86II::MRM_D0:
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Sun Feb 9 18:50:34 2014
> @@ -1295,6 +1295,7 @@ void Emitter<CodeEmitter>::emitInstructi
> break;
> }
>
> + case X86II::MRMXr:
> case X86II::MRM0r: case X86II::MRM1r:
> case X86II::MRM2r: case X86II::MRM3r:
> case X86II::MRM4r: case X86II::MRM5r:
> @@ -1302,8 +1303,9 @@ void Emitter<CodeEmitter>::emitInstructi
> if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
> ++CurOp;
> MCE.emitByte(BaseOpcode);
> + uint64_t Form = (Desc->TSFlags & X86II::FormMask);
> emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
> - (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
> + (Form == X86II::MRMXr) ? 0 : Form-X86II::MRM0r);
>
> if (CurOp == NumOps)
> break;
> @@ -1332,6 +1334,7 @@ void Emitter<CodeEmitter>::emitInstructi
> break;
> }
>
> + case X86II::MRMXm:
> case X86II::MRM0m: case X86II::MRM1m:
> case X86II::MRM2m: case X86II::MRM3m:
> case X86II::MRM4m: case X86II::MRM5m:
> @@ -1343,7 +1346,8 @@ void Emitter<CodeEmitter>::emitInstructi
> X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0;
>
> MCE.emitByte(BaseOpcode);
> - emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
> + uint64_t Form = (Desc->TSFlags & X86II::FormMask);
> + emitMemModRMByte(MI, CurOp, (Form==X86II::MRMXm) ? 0 : Form - X86II::MRM0m,
> PCAdj);
> CurOp += X86::AddrNumOperands;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrCMovSetCC.td Sun Feb 9 18:50:34 2014
> @@ -82,11 +82,11 @@ defm CMOVG : CMOV<0x4F, "cmovg" , X86_C
> // SetCC instructions.
> multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
> let Uses = [EFLAGS] in {
> - def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
> + def r : I<opc, MRMXr, (outs GR8:$dst), (ins),
> !strconcat(Mnemonic, "\t$dst"),
> [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
> IIC_SET_R>, TB, Sched<[WriteALU]>;
> - def m : I<opc, MRM0m, (outs), (ins i8mem:$dst),
> + def m : I<opc, MRMXm, (outs), (ins i8mem:$dst),
> !strconcat(Mnemonic, "\t$dst"),
> [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
> IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Sun Feb 9 18:50:34 2014
> @@ -24,6 +24,7 @@ def MRMDestMem : Format<4>; def MRMSrcRe
> def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
> def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
> def RawFrmDstSrc: Format<10>;
> +def MRMXr : Format<14>; def MRMXm : Format<15>;
> def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
> def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
> def MRM6r : Format<22>; def MRM7r : Format<23>;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Feb 9 18:50:34 2014
> @@ -928,9 +928,9 @@ def trunc_su : PatFrag<(ops node:$src),
> // Nop
> let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
> def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
> - def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
> + def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
> "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
> - def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
> + def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
> "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Feb 9 18:50:34 2014
> @@ -7677,7 +7677,7 @@ defm : pclmul_alias<"lqlq", 0x00>;
> let Predicates = [HasSSE4A] in {
>
> let Constraints = "$src = $dst" in {
> -def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
> +def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
> (ins VR128:$src, i8imm:$len, i8imm:$idx),
> "extrq\t{$idx, $len, $src|$src, $len, $idx}",
> [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
>
> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=201059&r1=201058&r2=201059&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Feb 9 18:50:34 2014
> @@ -63,6 +63,7 @@ namespace X86Local {
> RawFrmSrc = 8,
> RawFrmDst = 9,
> RawFrmDstSrc = 10,
> + MRMXr = 14, MRMXm = 15,
> MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
> MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
> MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
> @@ -165,6 +166,8 @@ static bool needsModRMForDecode(uint8_t
> form == X86Local::MRMDestMem ||
> form == X86Local::MRMSrcReg ||
> form == X86Local::MRMSrcMem ||
> + form == X86Local::MRMXr ||
> + form == X86Local::MRMXm ||
> (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
> (form >= X86Local::MRM0m && form <= X86Local::MRM7m));
> }
> @@ -178,6 +181,7 @@ static bool needsModRMForDecode(uint8_t
> static bool isRegFormat(uint8_t form) {
> return (form == X86Local::MRMDestReg ||
> form == X86Local::MRMSrcReg ||
> + form == X86Local::MRMXr ||
> (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
> }
>
> @@ -741,6 +745,7 @@ void RecognizableInstr::emitInstructionS
> HANDLE_OPTIONAL(immediate)
> HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
> break;
> + case X86Local::MRMXr:
> case X86Local::MRM0r:
> case X86Local::MRM1r:
> case X86Local::MRM2r:
> @@ -767,6 +772,7 @@ void RecognizableInstr::emitInstructionS
> HANDLE_OPTIONAL(relocation)
> HANDLE_OPTIONAL(immediate)
> break;
> + case X86Local::MRMXm:
> case X86Local::MRM0m:
> case X86Local::MRM1m:
> case X86Local::MRM2m:
>
>
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