[PATCH] Forbid the use of registers t6, t7 and t8 if the target is MIPS NaCl.

Sasa Stankovic Sasa.Stankovic at imgtec.com
Wed Feb 5 10:56:51 PST 2014



================
Comment at: test/CodeGen/Mips/nacl-reserved-regs.ll:42
@@ +41,3 @@
+  %16 = load i32* @g16
+  %add = add i32 %1, %0
+  %add1 = add i32 %add, %2
----------------
Mark Seaborn wrote:
> If this is just calculating a running sum of all g0-g16, it seems like this isn't a robust way to force use of many registers, because the backend can move the adds between the loads so only a couple of registers are used.
> 
> Maybe do something like:
> %val1 = call i32 @get_val()
> ...
> %valN = call i32 @get_val()
> call void @use_val(i32 %val1)
> ...
> call void @use_val(i32 %valN)
> 
> Or just do:
> call fastcc void @foo(i32 1, ..., i32 16)
> to check handling of "fastcc"
> 
I tried this, but it doesn't seem to work. For the first 9 val's the generated code uses callee-save registers s0, ..., s8 with the following pattern:

jal     get_val
move    s0, v0
...
move    a0, s0
jal     use_val

For the next 9 val's, instead of using caller-save "t" register, the return value is put on stack:

jal     get_val
sw     v0, 44(sp)
...
lw     a0, 44(sp)
jal     use_val

"t" register is not used because the register would need to be saved on stack before the next call to get_val (it is caller-saved), and the resulting sequence would be one instruction longer:

jal     get_val
move    t0, v0
sw      t0, 44(sp)
jal     get_val
...
lw      a0, 44(sp)
jal     use_val


http://llvm-reviews.chandlerc.com/D2694



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