[PATCH] Forbid the use of registers t6, t7 and t8 if the target is MIPS NaCl.

[Sasa Stankovic]

sstankovic added you to the CC list for the revision "Forbid the use of registers t6, t7 and t8 if the target is MIPS NaCl.".

Hi mseaborn,

This patch forbids the use of registers t6, t7 and t8 if the target is MIPS NaCl.

http://llvm-reviews.chandlerc.com/D2694

Files:
  lib/Target/Mips/MipsCallingConv.td
  lib/Target/Mips/MipsRegisterInfo.cpp
  test/CodeGen/Mips/fastcc.ll
  test/CodeGen/Mips/nacl-reserved-regs.ll

Index: lib/Target/Mips/MipsCallingConv.td
===================================================================
--- lib/Target/Mips/MipsCallingConv.td
+++ lib/Target/Mips/MipsCallingConv.td
@@ -192,8 +192,13 @@
 
   // Integer arguments are passed in integer registers. All scratch registers,
   // except for AT, V0 and T9, are available to be used as argument registers.
-  CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6,
-                                 T7, T8, V1]>>,
+  CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()",
+      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
+
+  // In PNaCl, T6, T7 and T8 are reserved and not available as argument
+  // registers for fastcc.
+  CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
+      CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
 
   // f32 arguments are passed in single-precision floating pointer registers.
   CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
Index: lib/Target/Mips/MipsRegisterInfo.cpp
===================================================================
--- lib/Target/Mips/MipsRegisterInfo.cpp
+++ lib/Target/Mips/MipsRegisterInfo.cpp
@@ -134,6 +134,15 @@
   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
     Reserved.set(ReservedGPR32[I]);
 
+  // Reserved for PNaCl use
+  if (Subtarget.isTargetNaCl()) {
+    static const uint16_t PnaclReservedCPURegs[] = {
+      Mips::T6, Mips::T7, Mips::T8
+    };
+    for (unsigned I = 0; I < array_lengthof(PnaclReservedCPURegs); ++I)
+      Reserved.set(PnaclReservedCPURegs[I]);
+  }
+
   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
     Reserved.set(ReservedGPR64[I]);
 
Index: test/CodeGen/Mips/fastcc.ll
===================================================================
--- test/CodeGen/Mips/fastcc.ll
+++ test/CodeGen/Mips/fastcc.ll
@@ -1,4 +1,7 @@
 ; RUN: llc  < %s -march=mipsel | FileCheck %s 
+; RUN: llc  < %s -mtriple=mipsel-none-nacl-gnu \
+; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
+
 
 @gi0 = external global i32
 @gi1 = external global i32
@@ -95,6 +98,11 @@
 ; CHECK: lw  $5
 ; CHECK: lw  $4
 
+; t6, t7 and t8 are reserved in PNaCl and cannot be used for fastcc.
+; CHECK-NACL-NOT: $14
+; CHECK-NACL-NOT: $15
+; CHECK-NACL-NOT: $24
+
   %0 = load i32* @gi0, align 4
   %1 = load i32* @gi1, align 4
   %2 = load i32* @gi2, align 4
@@ -134,6 +142,11 @@
 ; CHECK: sw  $24
 ; CHECK: sw  $3
 
+; t6, t7 and t8 are reserved in PNaCl and cannot be used for fastcc.
+; CHECK-NACL-NOT: $14
+; CHECK-NACL-NOT: $15
+; CHECK-NACL-NOT: $24
+
   store i32 %a0, i32* @g0, align 4
   store i32 %a1, i32* @g1, align 4
   store i32 %a2, i32* @g2, align 4
Index: test/CodeGen/Mips/nacl-reserved-regs.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/nacl-reserved-regs.ll
@@ -0,0 +1,69 @@
+; RUN: llc -march=mipsel -O3 < %s | FileCheck %s
+; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
+; RUN:  | FileCheck %s -check-prefix=CHECK-NACL
+
+ at g0 = external global i32
+ at g1 = external global i32
+ at g2 = external global i32
+ at g3 = external global i32
+ at g4 = external global i32
+ at g5 = external global i32
+ at g6 = external global i32
+ at g7 = external global i32
+ at g8 = external global i32
+ at g9 = external global i32
+ at g10 = external global i32
+ at g11 = external global i32
+ at g12 = external global i32
+ at g13 = external global i32
+ at g14 = external global i32
+ at g15 = external global i32
+ at g16 = external global i32
+
+define i32 @f() {
+entry:
+  %0 = load i32* @g0
+  %1 = load i32* @g1
+  %2 = load i32* @g2
+  %3 = load i32* @g3
+  %4 = load i32* @g4
+  %5 = load i32* @g5
+  %6 = load i32* @g6
+  %7 = load i32* @g7
+  %8 = load i32* @g8
+  %9 = load i32* @g9
+  %10 = load i32* @g10
+  %11 = load i32* @g11
+  %12 = load i32* @g12
+  %13 = load i32* @g13
+  %14 = load i32* @g14
+  %15 = load i32* @g15
+  %16 = load i32* @g16
+  %add = add i32 %1, %0
+  %add1 = add i32 %add, %2
+  %add2 = add i32 %add1, %3
+  %add3 = add i32 %add2, %4
+  %add4 = add i32 %add3, %5
+  %add5 = add i32 %add4, %6
+  %add6 = add i32 %add5, %7
+  %add7 = add i32 %add6, %8
+  %add8 = add i32 %add7, %9
+  %add9 = add i32 %add8, %10
+  %add10 = add i32 %add9, %11
+  %add11 = add i32 %add10, %12
+  %add12 = add i32 %add11, %13
+  %add13 = add i32 %add12, %14
+  %add14 = add i32 %add13, %15
+  %add15 = add i32 %add14, %16
+  ret i32 %add15
+
+; Check that t6, t7 and t8 are used in non-PNaCl code.
+; CHECK: $14
+; CHECK: $15
+; CHECK: $24
+
+; t6, t7 and t8 are reserved in PNaCl.
+; CHECK-NACL-NOT: $14
+; CHECK-NACL-NOT: $15
+; CHECK-NACL-NOT: $24
+}
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